JP2008147268A - Mesa type semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor element that can be miniaturized without impairing a withstand voltage and a method of manufacturing the same are provided.
A first P-type semiconductor layer and a second P-type semiconductor layer are formed to extend from the surface of a low-concentration N-type semiconductor substrate into the layer, and the semiconductor layer is formed as a mesa portion. Accordingly, the metal electrode 104 is formed on one main surface of the semiconductor substrate 102, and the mesa portion 109 and the second P-type semiconductor layer 108a are provided with a withstand voltage without providing a withstand voltage structure outside the active region of these semiconductors. Therefore, it is possible to reduce the size.
[Selection] Figure 1

Description

  The present invention relates to a mesa type semiconductor device and a method for manufacturing the same, and relates to a technology of a chip type high voltage semiconductor device.

  As a conventional chip type high voltage semiconductor device, there is a device having an MPS (Merged PiN Diode and Schottky Barrier Diode) structure and a guard ring around it. This is, for example, as shown in FIG. 3, where (a) is a plan view and (b) is a cross-sectional view taken along the line XX in (a).

In FIG. 3, 1 is an n ⁺ cathode layer, 2 is an n intermediate layer, 3 is an n ⁻ drift layer, 4 is a trench groove, 5 is an oxide film, 6 is polysilicon, 7 is a p ⁻ anode layer, and 8 is p ^+. Layer, 9 is an insulating film, 10 is an anode electrode, 11 is a metal film, 12 is a cathode electrode, 13 is an active region, 14 is a breakdown voltage structure, 16 is a Schottky junction, A is a pn diode part, and B is a Schottky diode part Is shown.

A method for manufacturing this semiconductor rectifier will be described below. First, the n intermediate layer 2 is formed by epitaxial growth on the n ⁺ cathode layer 1, and the n ⁻ drift layer 3 is further epitaxially grown on the n intermediate layer 2 so as to be slightly lower than the concentration of the n intermediate layer 2. Form.

Next, a plurality of trench grooves 4 are formed at equal intervals in the n ⁻ drift layer 3, oxide films 5 are formed on the sidewalls and bottom surfaces of the trench grooves 4, and then the oxide films on the bottom surfaces are removed.
Thereafter, the trench 6 is filled with polysilicon 6, boron is implanted through the polysilicon 6 using an oxide film having an opening corresponding to the polysilicon 6 as a mask, and heat treatment is performed to form the p ⁻ anode layer 7. .

Next, anode electrode 10 is formed on the surfaces of n ⁻ drift layer 3 and polysilicon 6 that form one main surface of the semiconductor substrate. A Schottky junction is formed at the interface between the anode electrode 10 and the n ⁻ drift layer 3.

In this way, the pn diode part A formed by the p ⁻ anode layer 7 and the n ⁻ drift layer 3 and the Schottky diode part B formed by the anode electrode 10 and the n ⁻ drift layer 3 are arranged in parallel. The MPS structure semiconductor rectifier element is formed.

This semiconductor rectifier element is provided with a breakdown voltage structure 14 around an active region 13 including a pn diode portion A and a Schottky diode portion B, and the breakdown voltage structure 14 is composed of a plurality of p ⁺ layers 8 constituting a guard ring. .

In the positional relationship between the trench groove 4 and the p ⁺ layer 8 of the guard ring on one main surface of the semiconductor substrate, the trench groove 4 located on the outermost side in the arrangement direction of the trench grooves 4 and the guard ring are located on the innermost side. A favorable breakdown voltage can be ensured by satisfying the condition of W1 ≦ L1, where W1 is an interval between opposite ends of the p ⁺ layer 8 and L1 is an interval between trench grooves.

Patent Document 1 is a prior art document in the field to which the present invention belongs.
JP 2002-83976 A

  However, the above-described conventional configuration requires a region for forming a guard ring, which is a breakdown voltage structure, around the active region in addition to the active region that originally functions as a semiconductor device. It had a problem that hinders it.

  SUMMARY OF THE INVENTION The present invention solves the above-described problems, and an object of the present invention is to provide a mesa-type semiconductor element capable of reducing the size of the semiconductor element and increasing the breakdown voltage, and a manufacturing method thereof.

  In order to solve the above-described problem, the mesa semiconductor device of the present invention includes a low-concentration semiconductor layer having the same conductivity type as that of the material semiconductor substrate formed on a material semiconductor substrate forming a base layer of the semiconductor substrate, and the low-concentration semiconductor device. A plurality of first semiconductor layers formed at a plurality of scattered locations of the semiconductor layer and having a conductivity type different from that of the low concentration semiconductor layer extend from the surface of the low concentration semiconductor layer into the layer, and A plurality of second semiconductor layers formed at a plurality of scattered locations on the outer periphery of the low-concentration semiconductor layer so as to surround a range where the semiconductor layers are scattered, and having a conductivity type different from that of the low-concentration semiconductor layer Extending from the surface of the low-concentration semiconductor layer into the layer, a mesa portion reaching the material semiconductor substrate along the outer periphery of one main surface of the semiconductor substrate is formed, and the second mesa portion is applied to the mesa portion Cover the exposed surface of the semiconductor layer and cover the mesa Protective film is formed, the metal electrode is formed on one main surface of the semiconductor substrate, wherein the backside metallization layer on the other main surface of said semiconductor substrate is formed.

In addition, all the first semiconductor layers and the second semiconductor layers are equal in distance to each other and are arranged in a honeycomb structure.
According to the method for manufacturing a mesa semiconductor device of the present invention, a low-concentration semiconductor layer having the same conductivity type as that of the material semiconductor substrate is formed by epitaxial growth on the material semiconductor substrate forming the base layer of the semiconductor substrate, and the low-concentration semiconductor layer is formed. An initial oxidation step of forming an oxide film on the surface by a thermal oxidation method, a window opening step of selectively etching and removing the oxide film to open a window at a predetermined position, and exposing the low-concentration semiconductor layer in the window; By using the oxide film as a mask, a dopant having a conductivity type different from that of the low-concentration semiconductor layer is implanted into the exposed surface of the low-concentration semiconductor layer, and drive diffusion is performed by thermal diffusion, thereby interspersing the low-concentration semiconductor layer. Forming a first semiconductor layer extending from the surface of the low-concentration semiconductor layer into a plurality of locations, and surrounding a range where the first semiconductor layer is scattered A diffusion step of forming a second semiconductor layer extending from the surface of the low-concentration semiconductor layer into the layer at a plurality of locations scattered around the outer periphery of the low-concentration semiconductor layer, and vapor deposition and selective etching removal, Forming a metal electrode on one main surface of the semiconductor substrate to cover all the surfaces of the first semiconductor layer and a part of the surface of the second semiconductor layer; and one of the semiconductor substrates. A mesa portion is formed by mesa etching along the outer periphery of the main surface and from the periphery of the metal electrode to the material semiconductor substrate, and covers the exposed surface of the second semiconductor layer over the mesa portion. And a mesa forming step of forming a back metallization layer on the other main surface of the semiconductor substrate by vapor deposition.

  As described above, according to the present invention, the depletion layer generated in the low-concentration semiconductor layer when the reverse electric field is applied is extended toward the mesa portion to reduce the curvature of the depletion layer, and the curvature portion of the depletion layer is the mesa portion. Since the presence of the second semiconductor layer over the mesa portion further reduces the curvature of the depletion layer and relaxes the electric field concentration, it is possible to increase the breakdown voltage, and the active region that originally functions as a semiconductor element can be obtained. A mesa semiconductor element that can be miniaturized and can have a high breakdown voltage can be realized without requiring a region for forming a semiconductor layer having a breakdown voltage structure.

  Further, by arranging all the first semiconductor layers and the second semiconductor layers in the honeycomb structure so that their adjacent distances are equal, it is possible to prevent the electric field and current from being biased during energization.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a mesa semiconductor device according to an embodiment of the present invention. FIG. 1A is a top view of a semiconductor substrate with the electrode structure removed, and FIG. 1B is a top view of the semiconductor substrate. It is AA arrow sectional drawing in.

  In FIG. 1, 101 is a mesa diode, 102 is a semiconductor substrate, 103 is a protective layer, 104 is a metal electrode, 105 is a back metallization layer, 106 is an N-type semiconductor substrate, 107 is a low-concentration N-type semiconductor layer, and 108 is a first substrate. One P-type semiconductor layer, 108a is a second P-type semiconductor layer, and 109 is a mesa portion.

  In FIG. 1, a semiconductor substrate 102 has a low-concentration N-type semiconductor layer 107 formed by epitaxial growth on an N-type semiconductor substrate 106 that forms a base material semiconductor substrate. One P-type semiconductor layer 108 is dotted, and the first P-type semiconductor layer 108 extends from the surface of the low-concentration N-type semiconductor layer 107 into the layer.

  A plurality of second P-type semiconductor layers 108a are scattered around the periphery of the low-concentration N-type semiconductor layer 107 so as to surround a range where the plurality of first P-type semiconductor layers 108 are scattered. A second P-type semiconductor layer 108a extends from the surface of the low-concentration N-type semiconductor layer 107 into the layer.

  A metal electrode 104 as an anode is formed on one main surface of the semiconductor substrate 102, that is, on the surfaces of the low-concentration N-type semiconductor layer 107, the first P-type semiconductor layer 108, and the second P-type semiconductor layer 108a. The semiconductor substrate 102 has a back metallized layer 105 as a cathode formed on the other main surface which is opposite to the main surface.

  The semiconductor substrate 102 is formed with a mesa portion 109 having a concave inclined surface along the outer periphery of one main surface, and the mesa portion 109 extends from the periphery of the metal electrode 104 to the N-type semiconductor substrate 106. Therefore, each second P-type semiconductor layer 108 a is exposed in the mesa portion 109, and the protective film 103 made of glass is formed so as to cover the mesa portion 109.

  The mesa semiconductor device having the above-described configuration reduces the curvature of the depletion layer by extending the depletion layer generated in the low-concentration N-type semiconductor layer 107 toward the mesa portion when a reverse electric field is applied, and the curvature portion is the mesa portion 109. The presence of the second P-type semiconductor layer 108a in the mesa portion 109 further reduces the curvature of the depletion layer and relaxes the electric field concentration, so that a high breakdown voltage can be achieved.

  Therefore, a mesa semiconductor that can be miniaturized and can have a high breakdown voltage without requiring a region for forming a semiconductor layer having a breakdown voltage structure around an active region that originally functions as a semiconductor element. An element can be realized.

Here, as an example, when the thickness of the low-concentration N-type semiconductor layer 107 is 20 to 30 μm and the dopant concentration is 2 × 10 ¹⁴ , all the first P-type semiconductor layers 108 and the second P-type semiconductor layers are used. It is preferable that the semiconductor layers 108a have the same distance between adjacent layers (set to about 5 to 15 μm) and are geometrically arranged in a honeycomb structure.

  According to the preferable conditions of this example, it is possible to prevent a bias from occurring in the electric field distribution at the time of applying the reverse bias and the current distribution at the time of applying the forward bias, and to stably and reliably perform the operation as the semiconductor device. In the embodiment of the present invention, the protective film 103 is described as being made of glass. However, the present invention is not limited to this, and may be a resin or the like.

Below, the manufacturing method of the mesa type | mold semiconductor element of this invention is demonstrated. FIG. 2 shows a cross section at the end of the main steps of the process of manufacturing the mesa semiconductor device of the present invention.
In FIG. 2, 102 is a semiconductor substrate, 103 is a protective layer, 104 is a metal electrode, 105 is a back metallization layer, 106 is an N-type semiconductor substrate, 107 is a low-concentration N-type semiconductor layer, and 108 is a first P-type semiconductor layer. 108a denotes a second P-type semiconductor layer, 109 denotes a mesa portion, 110 denotes a silicon oxide film, and 110a denotes a window.

  FIG. 2A shows an initial oxidation step. A low concentration N-type semiconductor layer 107 is formed by epitaxial growth on an N-type semiconductor substrate 106 made of silicon, and heat is applied to the surface of the low concentration N-type semiconductor layer 107. A silicon oxide film 110 is formed by an oxidation method.

  FIG. 2B shows a window opening process. After the initial oxidation process, the silicon oxide film is selectively etched and removed, and a plurality of locations where the silicon oxide film 110 is scattered, that is, the first process is shown in FIG. A window 110a is opened at a position corresponding to a portion to be formed for forming the P-type semiconductor layer 108 and the second P-type semiconductor layer 108a, and the low-concentration N-type semiconductor layer 107 is exposed in the window 110a.

  FIG. 2C shows a diffusion process. After the previous window opening process, a P-type dopant such as boron is implanted into the exposed surface of the low-concentration N-type semiconductor layer 107 using the silicon oxide film 110 as a mask. By performing drive diffusion by thermal diffusion, the first P-type semiconductor layer 108 extending from the surface of the low-concentration N-type semiconductor layer 107 into the layer is provided at a plurality of locations where the low-concentration N-type semiconductor layer 107 is scattered. The surface of the low-concentration N-type semiconductor layer 107 is formed at a plurality of locations on the outer periphery of the low-concentration N-type semiconductor layer 107 so as to surround a range where the plurality of first P-type semiconductor layers are scattered. A second P-type semiconductor layer 108 a extending into the layer is formed to obtain the semiconductor substrate 102.

Note that the first P-type semiconductor layer 108 and the second P-type semiconductor layer 108a are again covered with the silicon oxide film 110 by heat during drive diffusion.
FIG. 2 (d) shows a metal electrode forming process. After the previous diffusion process, a metal electrode 104 made of aluminum or the like is formed on one main surface of the semiconductor substrate 102 by vapor deposition and selective etching removal. Form. The metal electrode 104 covers the surface of all the first P-type semiconductor layers 108 and a part of the surface of the second P-type semiconductor layer 108a.

  FIG. 2E shows a mesa formation process. After the previous metal electrode formation process, the N-type semiconductor substrate 106 extends along the outer periphery of one main surface of the semiconductor substrate 102 and from the outer periphery of the metal electrode 104. A mesa portion 109 reaching the top is formed by mesa etching, and a protective film 103 covering the exposed surface of each second P-type semiconductor layer 108a covering the mesa portion 109 and covering the mesa portion 109 is formed. The protective film 103 is made of glass, and is formed by heat-treating glass powder. Then, by forming the back metallized layer 105 as a cathode on the other main surface of the semiconductor substrate 102 by vapor deposition, the mesa diode shown in FIG. 1 is obtained.

  The present invention is a mesa type semiconductor element, and is particularly suitable for a small size and high withstand voltage.

BRIEF DESCRIPTION OF THE DRAWINGS The mesa diode in embodiment of this invention is shown, (a) is a top view, (b) is AA arrow sectional drawing in (a). Sectional drawing which shows the main manufacturing processes of the mesa type diode in embodiment of this invention 1 shows a conventional semiconductor device, where (a) is a top view and (b) is a cross-sectional view taken along line XX in (a).

Explanation of symbols

A pn diode part B Schottky diode part 1 n ⁺ cathode layer 2 n intermediate layer 3 n ^- drift layer 4 trench groove 5 oxide film 6 polysilicon 7 p ^- anode layer 8 p ⁺ layer 9 insulating film 10 anode electrode 11 metal film DESCRIPTION OF SYMBOLS 12 Cathode electrode 13 Active region 14 Withstand voltage structure 16 Schottky junction 101 Mesa type diode 102 Semiconductor substrate 103 Protective layer 104 Metal electrode 105 Back surface metallization layer 106 N type semiconductor substrate 107 Low concentration N type semiconductor layer 108 First P type semiconductor layer 108a Second P-type semiconductor layer 109 Mesa portion 110 Silicon oxide film 110a Window

Claims (3)

A low concentration semiconductor layer having the same conductivity type as that of the material semiconductor substrate is formed on the material semiconductor substrate forming the base layer of the semiconductor substrate, and the low concentration semiconductor layer is formed at a plurality of scattered locations of the low concentration semiconductor layer. A plurality of first semiconductor layers having different conductivity types extend from the surface of the low-concentration semiconductor layer into the layer and surround the range where the first semiconductor layers are scattered. A plurality of second semiconductor layers formed at a plurality of scattered locations on the outer periphery of the semiconductor layer and having a conductivity type different from that of the low-concentration semiconductor layer extend from the surface of the low-concentration semiconductor layer into the layer; A mesa portion that reaches the material semiconductor substrate along the outer periphery of one main surface of the substrate is formed, and a protective film that covers the exposed surface of the second semiconductor layer covering the mesa portion and covers the mesa portion Formed on one main surface of the semiconductor substrate. Electrodes are formed, a mesa type semiconductor device characterized by the other main surface to the back surface metallization layer of the semiconductor substrate is formed. 2. The mesa semiconductor element according to claim 1, wherein all of the first semiconductor layers and the second semiconductor layers have the same distance from each other and are arranged in a honeycomb structure. An initial stage in which a low-concentration semiconductor layer having the same conductivity type as that of the material semiconductor substrate is formed on the material semiconductor substrate forming the base layer of the semiconductor substrate by epitaxial growth, and an oxide film is formed on the surface of the low-concentration semiconductor layer by a thermal oxidation method An oxidation process;
A window opening step of performing selective etching removal on the oxide film to open a window at a predetermined position, and exposing the low-concentration semiconductor layer in the window;
By using the oxide film as a mask, a dopant having a conductivity type different from that of the low-concentration semiconductor layer is implanted into the exposed surface of the low-concentration semiconductor layer, and drive diffusion is performed by thermal diffusion, thereby interspersing the low-concentration semiconductor layer. Forming a first semiconductor layer extending from the surface of the low-concentration semiconductor layer into a plurality of locations, and surrounding the area where the first semiconductor layer is scattered, A diffusion step of forming a second semiconductor layer extending into the layer from the surface of the low-concentration semiconductor layer at a plurality of locations scattered around the outer periphery; and
Metal electrode formation for forming a metal electrode that covers all of the surface of the first semiconductor layer and a part of the surface of the second semiconductor layer on one main surface of the semiconductor substrate by vapor deposition and selective etching removal Process,
A mesa portion is formed by mesa etching along the outer periphery of one main surface of the semiconductor substrate and from the periphery of the metal electrode to the material semiconductor substrate, and the exposed surface of the second semiconductor layer over the mesa portion A mesa forming step of forming a protective film covering the mesa portion and forming a back metallization layer on the other main surface of the semiconductor substrate by vapor deposition. Production method.

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