JP2008141114A - Manufacturing method of semiconductor chip for stacked chip and manufacturing method of stacked chip - Google Patents

Abstract

Provided is a stacked chip in which a semiconductor chip is not easily damaged in a stacked chip formed by stacking a plurality of semiconductor chips even when the thickness of the semiconductor chip is reduced. A method of manufacturing a semiconductor chip for a stacked chip that enables this is obtained.
In obtaining a structure in which individual semiconductor chips 8 and 9 are cut out from a wafer 1 and an adhesive layer 10 or 11 for forming a stacked chip is provided on the semiconductor chips 8 or 9, a wafer is first obtained. 1 is cut by dicing to obtain individual semiconductor chips 8 and 9, and then adhesive layers 10 and 11 are formed on the upper surface of the semiconductor chips 8 and 9 on the dicing tape 6 except for the electrical conduction portion. The manufacturing method of the semiconductor chip for stacked chips which obtains the semiconductor chips 8 and 9 by which the adhesive layers 10 and 11 were laminated | stacked.
[Selection] Figure 2

Description

  The present invention relates to a method for manufacturing a semiconductor chip for obtaining a stacked chip having a structure in which a plurality of semiconductor chips are stacked, and a method for manufacturing the stacked chip, and in particular, the upper and lower semiconductor chips are interposed via an adhesive. Manufacturing method of stacked chip semiconductor chip used for stacked chip having a structure in which upper and lower semiconductor chips are electrically connected to each other, and stacked chip using the stacked chip semiconductor chip It relates to the manufacturing method.

  Various electronic devices such as mobile phones and personal computers are required to be smaller and lighter. Therefore, miniaturization and high density are also demanded in the semiconductor devices used. In order to achieve such a purpose, a stacked chip formed by stacking a plurality of semiconductor chips is used. By using the stacked chip, the mounting area of the semiconductor device can be reduced.

  In addition, when a stacked chip is formed using a plurality of semiconductor chips that are to be electrically connected to each other, it is possible to simplify wiring routing and the like. For this reason, various stacked chips are proposed in which not only the upper and lower semiconductor chips are simply stacked and integrated, but also electrically connected.

  For example, Patent Document 1 below discloses an example of a method for manufacturing this type of stacked chip. Here, a plurality of semiconductor chips are stacked on a substrate on which a semiconductor device is configured. Each semiconductor chip is formed with a penetrating electrode penetrating from the top surface to the top surface and projecting upward from the top surface and downward from the bottom surface. The upper end of the through electrode of the lower semiconductor chip and the lower end of the through electrode of the upper semiconductor chip are joined by solder, whereby the upper and lower semiconductor chips are stacked with a gap therebetween, and the upper and lower semiconductor chips are stacked. Electrical connections are made.

In the method of manufacturing a stacked chip described in Patent Document 1, a plurality of semiconductor chips are stacked on a substrate as described above, and after the electrical connection between the semiconductor chips is achieved, the exterior is applied with a sealing resin. ing. The sealing resin not only covers the periphery of the stacked body in which a plurality of semiconductor chips are stacked, but also fills and cures the gap between the upper and lower semiconductor chips.
JP 2004-273525 A

  In the manufacturing method described in Patent Document 1, a plurality of semiconductor chips that are electrically connected to each other are firmly integrated by the sealing resin. However, when the thickness of the semiconductor chip is reduced, stress may be applied to the semiconductor chip when the sealing resin is filled and cured in the gap in the semiconductor chip, and the semiconductor chip may be damaged. In recent years, in order to achieve further miniaturization and thinning, semiconductor chips used for stacked chips are also becoming thinner. When the semiconductor chip becomes thin, it may be easily damaged by an external force. Therefore, in the manufacturing method described in Patent Document 1, there is a possibility that the semiconductor chip is cracked or cracked even if the semiconductor chip is not broken or cracked due to the stress when the sealing resin is filled and cured.

  An object of the present invention is not only to reliably connect semiconductor chips to each other in view of the current state of the prior art described above, but also to stack and integrate even when the semiconductor chips are thinned. It is an object of the present invention to provide a stacked chip semiconductor chip manufacturing method and a stacked chip manufacturing method capable of providing a highly reliable stacked chip in which a semiconductor chip is hardly damaged.

  A first invention of the present application is a semiconductor chip for obtaining a stacked chip in which a plurality of semiconductor chips are stacked and electrically connected, and the upper and lower semiconductor chips are from the front surface to the back surface. A method of manufacturing a semiconductor chip for stacked chips having an electrically conductive portion used for electrically connecting a semiconductor chip, wherein the semiconductor wafer includes a plurality of semiconductor chips, and includes an electrically conductive portion on a surface thereof. A step of preparing a mother wafer in which a conductive pattern is formed and the electrically conductive portion is exposed on the surface; and a process of reducing the thickness from the back side of the wafer; A step of exposing the wafer to the back surface, a step of attaching the wafer to the dicing tape from the back surface side, and a wafer attached to the dicing tape to each stacked And a step of forming an adhesive layer in a region excluding the electrically conductive portion on the upper surface of each semiconductor chip divided on the dicing tape. .

  A second invention is a semiconductor chip for obtaining a stacked chip in which a plurality of semiconductor chips are stacked and electrically connected, and the upper and lower semiconductor chips are electrically connected to each other from the front surface to the back surface. A method for manufacturing a semiconductor chip for stacked chips having an electrically conductive portion used to connect electrically, wherein the semiconductor chip is a mother wafer in which a plurality of semiconductor chips are configured, and the conductive pattern including the electrically conductive portion on the surface And a step of preparing a mother wafer having the electrically conductive portion exposed on the surface, and a process of reducing the thickness from the back surface side of the wafer, and the electrically conductive portion on the back surface of the wafer. A step of exposing, a step of forming an adhesive layer on the back surface of the wafer in a region excluding the electrically conductive portion, and dicing the wafer through the adhesive layer. A step of sticking the-loop, characterized in that it comprises a step of dividing the wafer affixed to the dicing tape into individual semiconductor chips.

  A third invention is a semiconductor chip for obtaining a stacked chip in which a plurality of semiconductor chips are stacked and electrically connected, and the upper and lower semiconductor chips are electrically connected to each other from the front surface to the back surface. A method for manufacturing a semiconductor chip for stacked chips having an electrically conductive portion used to connect electrically, wherein the semiconductor chip is a mother wafer in which a plurality of semiconductor chips are configured, and the conductive pattern including the electrically conductive portion on the surface And a step of preparing a mother wafer having the electrically conductive portion exposed on the surface, and a process of reducing the thickness from the back surface side of the wafer, and the electrically conductive portion on the back surface of the wafer. Exposing the wafer to the dicing tape from the back side, and contacting the region on the front surface of the wafer excluding the electrically conductive portion. Forming an adhesive layer, a step of semi-curing the adhesive layer, characterized in that it comprises a step of dividing the semiconductor wafer into individual semiconductor chips.

  A fourth invention is a semiconductor chip for obtaining a stacked chip in which a plurality of semiconductor chips are stacked and electrically connected, and the upper and lower semiconductor chips are electrically connected to each other from the front surface to the back surface. A method for manufacturing a semiconductor chip for stacked chips having an electrically conductive portion used to connect electrically, wherein the semiconductor chip is a mother wafer in which a plurality of semiconductor chips are configured, and the conductive pattern including the electrically conductive portion on the surface And a step of preparing a mother wafer having the electrically conductive portion exposed on the surface, and applying an adhesive layer on the surface of the wafer except for the electrically conductive portion. Forming at the same time, processing from the back side of the wafer, reducing the thickness of the wafer, exposing the electrically conductive portion to the back side, and the wafer After the electrically conductive portion is exposed on the back side, the method includes a step of sticking the wafer to the dicing tape from the back side, and a step of dividing the wafer attached to the dicing tape into individual semiconductor chips. .

  In the third invention, preferably, the adhesive for forming the adhesive layer has a thermosetting compound, a curing agent for curing the thermosetting compound with heat, and a molecular weight of 600 or less. Contains a photocurable compound. Therefore, when semi-curing the adhesive layer, either one of light irradiation or heating is adopted, and finally a stacked chip semiconductor chip is laminated, and the adhesive layer is cured and integrated. In order to perform this, the other of light irradiation and heating may be employed. That is, an operation for semi-curing the adhesive layer and an operation for completely curing the adhesive layer can be selected from two methods of heating and light irradiation. Therefore, by adjusting the blending ratio of the thermosetting compound and the curing agent and the blending ratio of the photocurable compound, it becomes easy to reliably make the adhesive layer semi-cured or completely cure.

  The stacked chip manufacturing method according to the present invention includes a step of preparing a plurality of stacked chip semiconductor chips obtained by the stacked chip semiconductor chip manufacturing method according to the present invention, and the stacked chip semiconductor chip described above. A step of filling a conductive material into the opening of the adhesive layer, and laminating and bonding the plurality of stacked chip semiconductor chips via the adhesive layer, and upper and lower semiconductor chips by the conductive material The electrical conduction parts of the above are electrically connected to each other.

  According to the method for manufacturing a semiconductor chip for stacked chips according to the first invention, the adhesive layer is formed in a region excluding the electrically conductive portions reaching the upper and lower surfaces of the semiconductor chip after dividing the wafer into individual semiconductor chips. Is formed. Therefore, the individual semiconductor chips on which the adhesive layer is formed can be laminated and integrated using the adhesive layer. In the adhesive layer, electrical connection between the upper and lower semiconductor chips can be reliably achieved simply by applying a conductive material to the region where the electrically conductive portion is formed. Therefore, since the adhesive layer is used for stacking a plurality of semiconductor chips to achieve electrical connection and integration, even when the thickness of the semiconductor chip is thin, the sealing resin is injected. It is difficult to apply such a large stress. Therefore, even when the semiconductor chip is made thinner, the semiconductor chip is hardly damaged, and thus a stacked chip having excellent reliability can be obtained. In addition, since the adhesive layer is formed after dividing the wafer into the semiconductor chips, for example, even if a large amount of water is used during dicing, the adhesive layer is formed after dicing. There is no risk of the layer being degraded by water.

  Also in the second invention, an adhesive layer is formed on the back surface of the wafer excluding the electrically conductive portion, and the individual semiconductor chips together with the adhesive layer in a state where the wafer is adhered to the dicing tape through the adhesive layer. Therefore, the upper and lower semiconductor chips can be joined and integrated using the adhesive layer. Even in this case, the upper and lower semiconductor chips can be reliably electrically connected to each other by applying a conductive material to the region where the electrically conductive portion is exposed. Also in the second invention, since it is not necessary to inject a sealing resin when the upper and lower semiconductor chips are stacked and integrated, even if the semiconductor chip is thinned, the semiconductor chip is hardly damaged. In the second invention, the adhesive layer is formed on the back surface of the wafer, and the semiconductor wafer is divided into individual semiconductor chips with the adhesive layer attached to the dicing tape via the adhesive layer. At that time, even if a large amount of water is used, the adhesive layer on the back surface side is difficult to come into contact with water. Therefore, the adhesive layer is hardly deteriorated by water.

  In the third invention, after the wafer is affixed to the dicing tape from the back surface side, an adhesive layer is formed on the front surface side of the wafer except for the electrically conductive portion. At this stage, the wafer is divided into individual semiconductor chips. Therefore, by applying a conductive material to the region where the electrical conduction portion is exposed, laminating a plurality of semiconductor chips, and completely curing the adhesive layer, the upper and lower semiconductor chips are firmly bonded to each other, Can be integrated. Also, the upper and lower semiconductor chips are connected.

  In the third invention, since the adhesive layer is in a semi-cured state before dividing the wafer into semiconductor chips, even if water adheres to the adhesive layer during dicing or the like, it is in a semi-cured state. Deterioration of the adhesive layer hardly occurs.

  In the fourth invention, an adhesive layer is formed simultaneously with the application on the surface of the wafer except for the electrically conductive portion, and the wafer is divided into individual semiconductor chips in a state of being affixed to a dicing tape. The Accordingly, the semiconductor chips can be joined and integrated via the adhesive layer. Even in this case, by providing a conductive material in a region where the electrical conduction portion is represented, electrical connection between the electrical conduction portions of the upper and lower semiconductor chips can be achieved. Therefore, when a plurality of semiconductor chips are integrated with the adhesive layer, it is difficult to apply a large stress to the semiconductor chip. Therefore, it is possible to provide a stacked chip having excellent reliability even when the semiconductor chip is thinned. It becomes possible.

  That is, in any of the first to fourth inventions, since an adhesive layer is formed in an area excluding the electrical conduction portion on each semiconductor chip obtained by dividing the wafer, the adhesion is performed. A plurality of semiconductor chips can be joined and integrated using an agent layer, and a conductive material is applied to a region where the electrical conduction portion is disposed, so that upper and lower electrical conduction portions are Even in the case where the semiconductor chip is thinned compared to the conventional method in which the upper and lower semiconductor chips are integrated by a sealing resin, the semiconductor chip is common in that it can be electrically connected. This is common in that it has a unique effect that it is difficult to cause damage.

  Hereinafter, the present invention will be clarified by describing specific embodiments of the present invention with reference to the drawings.

(First embodiment)
With reference to FIGS. 1A to 1C and FIGS. 2A to 2D, a manufacturing method of a stacked chip semiconductor chip and a manufacturing method of a stacked chip according to the first embodiment of the present invention are described. Will be explained.

  First, as shown in FIG. 1A, a mother wafer 1 is prepared. The wafer 1 is made of an appropriate semiconductor material. By dividing the wafer 1 as described later, individual semiconductor chips are obtained. Therefore, the wafer 1 has a structure in which a plurality of semiconductor chips are connected.

  A conductive pattern 2 is formed on the surface 1 a of the wafer 1. The conductive pattern 2 is made of an appropriate metal or alloy such as Cu or Al. Although the conductive pattern 2 is schematically shown in FIG. 1A, the conductive pattern 2 includes a wiring pattern 3 and an electrically conductive portion 4 for connecting the semiconductor chips. Among these, the electric conduction part 4 has an upper end exposed at the front surface 1a of the wafer 1 and extends from the front surface 1a toward the back surface 1b. The lower end of the electrical conduction portion 4 ends above the lower surface 1b of the mother wafer 1. An internal electrode 5 is formed in the wafer 1 so as to be connected to the electrical conduction portion 4.

  The conductive pattern 2 and the internal electrode 5 are appropriately formed according to the function of each semiconductor chip, and the conductive pattern 2 formed on the upper surface is provided with bumps for electrically connecting to the outside in addition to the wiring pattern 3. May be included.

  In FIG. 1A, the wiring pattern 3 is formed by forming a groove on the surface 1a of the wafer 1 and filling the groove with a conductive material. It may be provided by forming a conductive film on the surface 1a.

  The electrical conduction portion 4 can be formed by providing a through hole from the surface 1a of the wafer 1 and filling it with a conductive material. But the formation method of the electrical conduction part 4 is not specifically limited. The electrical conduction portion 4 can also be formed of an appropriate metal or alloy such as Cu, Al, or Ag.

  Next, the wafer 1 is processed from the back surface 1b side by polishing and / or etching to reduce the thickness of the wafer 1. The process of reducing the thickness of the wafer 1 is to expose the lower end of the electrical conducting portion 4 to the back side of the wafer 1. That is, as shown in FIG. 1B, by reducing the thickness of the wafer 1, the lower end of the electrical conduction portion 4 is exposed to the back surface 1 c of the wafer 1.

  The processing method for thinning the wafer 1 is not limited, but a mechanical polishing method or an etching method can be used. As the mechanical polishing method, an appropriate polishing method such as a method using sand blasting can be used. As an etching method, an appropriate wet or dry etching method can be used. Further, the above polishing and etching may be used in combination.

  Next, as shown in FIG. 1B, the wafer 1 </ b> A having a reduced thickness is bonded onto the dicing tape 6. In this case, a dicing tape having an adhesive surface on the upper surface is used as the dicing tape 6. In this way, the wafer 1A is fixed on the dicing tape 6. The dicing tape 6 is fixed to the frame member 7.

  Next, as shown in FIG. 1C, dicing is performed from the surface 1a of the wafer 1A, and the wafer 1A is divided into individual semiconductor chips 8 and 9. In this case, the cutting with the dicing blade is performed so as to remove the portion below the upper surface of the dicing tape 6. That is, dicing is performed so that the grooves 6a to 6c in FIG.

  At the time of dicing, processing is performed so that a part of the wafer 1A is removed by a dicing blade. In this case, in order to suppress frictional heat by the rotary dicing blade, dicing is usually performed while ejecting a large amount of water. Is done.

  Thereafter, as shown in FIG. 2A, the adhesive layers 10 and 11 supported on the lower surface of the support film 13 are brought into pressure contact with the semiconductor chips 8 and 9 and transferred. As the support film 13, an appropriate synthetic resin film can be used. Adhesive layers 10 and 11 having openings 10a, 10b, 11a, and 11b are formed on the lower surface of the support film 13 so as to expose the portions where the electrical conduction portions 4 are provided.

  The adhesive layers 10 and 11 are transferred so that the openings 10a, 10b, 11a, and 11b are aligned with the portion where the lower electrical conduction portion 4 is provided. At the time of transfer, the adhesive layers 10 and 11 provided on the lower surface of the support film 13 are laminated on the upper surfaces of the semiconductor chips 8 and 9, and the roller 16 is moved from the back surface of the support film 13, thereby the adhesive layers 10 and 11. Press.

  Thereafter, the support film 13 is peeled off from the adhesive layers 10 and 11. Therefore, it is desirable that the support film 13 is made of a synthetic resin excellent in releasability from which the adhesive layers 10 and 11 can be easily peeled, or the surface is treated with a release agent. In this way, the adhesive layers 10 and 11 are laminated on the semiconductor chips 8 and 9 as shown in FIG. Thereafter, as shown in FIG. 2C, the openings 10a, 10b, 11a, and 11b are filled with the conductive material 12 shown in FIG. As the conductive material 12, an appropriate conductive material such as a solder paste can be used, and the filling method can also be performed by an appropriate method such as a printing method.

  Thereafter, the individual semiconductor chips 8 and 9 are peeled off from the dicing tape 6 together with the adhesive layers 10 and 11 and laminated as shown in FIG. That is, a plurality of semiconductor chips 8 and 9 are stacked on the stacking stage 17. Here, the upper and lower semiconductor chips 8 and 9 are bonded to each other via, for example, adhesive layers 10 and 11 on the upper surface of the lower semiconductor chips 8 and 9. In addition, the electrical connection is performed by connecting the upper and lower electrical conducting portions 4 with respect to the conductive material 12 provided on the adhesive layers 10 and 11. In this method, the semiconductor chips 8 and 9 are peeled off from the dicing tape 6 together with the adhesive layers 10 and 11 and laminated. In the laminated body, since a process for flowing the sealing resin is not required, even when the thickness of the semiconductor chips 8 and 9 is reduced, stress is not easily applied. Is unlikely to occur. Therefore, the stacked chip 14 having excellent reliability can be obtained.

  In the present invention, when stacking a plurality of stacked chip semiconductor chips, the plurality of semiconductor chips need not all be the same, and different types of semiconductor chips may be stacked.

  In the present embodiment, as shown in FIG. 2A, the adhesive layers 10 and 11 provided on the individual semiconductor chips 8 and 9 are provided on the lower surface of the support film 13 in advance. An adhesive layer having a pattern in which the agent layers 10 and 11 are connected may be formed on the lower surface of the support film 13. In this case, as shown in FIG. 2B, the continuous adhesive layer pattern 15 is laminated so as to straddle the upper surfaces of the semiconductor chips 8 and 9. Therefore, dicing is performed again from the state shown in FIG. 2B, and the excess adhesive layer portion may be removed so as to leave the adhesive layers 10 and 11 on the semiconductor chips 8 and 9.

  In the manufacturing method of the present embodiment, as described above, the wafer 1A is diced prior to the formation of the adhesive layers 10 and 11, and is divided into individual semiconductor chips 8 and 9. When cutting the semiconductor wafer 1A, as described above, it is common to use a large amount of water. Accordingly, when the uncured adhesive comes into contact with water, the adhesive may be deteriorated. However, in this embodiment, since the adhesive layers 10 and 11 are formed after the dicing, the adhesive layers 10 and 11 are hardly deteriorated.

(Second Embodiment)
With reference to FIGS. 3A to 3C and FIGS. 4A and 4B, a manufacturing method of a stacked chip semiconductor chip and a manufacturing method of a stacked chip according to the second embodiment will be described.

  As shown in FIG. 3A, a similar wafer 1 is prepared in the same manner as in the first embodiment. Then, as in the case of the first embodiment, the thickness of the wafer 1 is reduced to expose the pattern of the electrically conductive portion 4. Up to here, since it is performed in the same manner as in the first embodiment, the description of the first embodiment is incorporated.

  In the second embodiment, the adhesive layer 21 is formed on the back surface 1c of the wafer 1A having a reduced thickness by a screen printing method. The adhesive layer 21 is printed so as to have openings 10 a, 10 b, 11 a, 11 b that expose the lower ends of the electrical conduction portions 4. Thereafter, the adhesive layer 21 is semi-cured. In this case, an appropriate curable composition can be used as the adhesive constituting the adhesive layer 21, but a thermosetting adhesive or a photo-curing adhesive that is cured by UV irradiation is preferable. Used for. In this case, the adhesive layer 21 can be in a semi-cured state by adjusting the degree of heating, the light irradiation intensity, the irradiation time, and the like.

  More preferably, as the adhesive constituting the adhesive layer 21, a thermosetting compound that cures by heating, a curing agent that cures the thermosetting compound that cures by heating, and light irradiation. An adhesive composition containing a photocurable compound that cures is used. In this case, the semi-curing can be performed by heating or light irradiation, and the adhesive layer 21 to be described later can be completely cured by light irradiation or heating. Alternatively, semi-curing and complete curing may be achieved by adjusting the intensity of both heating and light irradiation. In any case, by using an adhesive that is cured by two types of curing methods, the adhesive layer 21 can be easily made into a semi-cured state, and can be completely cured easily at a later stage. A preferable example of such an adhesive will be described later.

  Next, the wafer 1A is bonded onto the dicing tape 6 from the adhesive layer 21 side. In this way, as shown in FIG. 3C, the wafer 1A is stuck on the dicing tape 6 from the adhesive layer 21 side.

  Thereafter, the wafer 1A is diced to form individual semiconductor chips 8A and 9A as shown in FIG. This dicing is performed in the same manner as the dicing step in the first embodiment, that is, so that the grooves 6a to 6c are formed. Therefore, the description of the dicing method of the semiconductor wafer 1A in the first embodiment is omitted by using the description. However, it is divided into individual semiconductor chips 8A and 9A, and the adhesive layer 21 is also divided by dicing, so that the adhesive layers 10A and 11A are formed. That is, the adhesive layers 10A and 11A are formed below the semiconductor chips 8A and 9A.

  Next, as shown in FIG. 4B, a conductive material 22 is printed on the electrical conduction portion 4 on the surface of the semiconductor chips 8A and 9A. As the conductive material 22, for example, an appropriate conductive paste such as a solder paste can be used. The conductive material 22 is raised upward from the upper surface of the electrical conduction portion 4.

  Then, the conductive material 22 is cured or semi-cured, and the individual semiconductor chips 8A and 9A are peeled off from the dicing tape 6 together with the adhesive layers 10A and 11A and laminated. In this case, the openings 10a, 10b, 11a, 11b of the adhesive layers 10A, 11A are not filled with a conductive material, but the conductive material 22 enters the openings 10a, 10b, 11a, 11b, and Electrical connection between the semiconductor chips is performed. More specifically, when the semiconductor chip 9A is stacked above the semiconductor chip 8A, the conductive material 22 provided on the surface of the lower semiconductor chip 8A is provided on the lower surface of the upper semiconductor chip 9A. It will enter into the openings 11a and 11b of the adhesive layer 11A. Therefore, the conductive material 22 joins the upper end of the electrical conduction part 4 of the semiconductor chip 8A and the lower end of the electrical conduction part 4 of the upper semiconductor chip 9A by the conductive material 22 to achieve electrical connection. Become.

  Therefore, the conductive material 22 needs to have an amount and a hardness sufficient to electrically connect the upper and lower electrical conducting portions 4.

  Thus, also in the second embodiment, a stacked chip formed by stacking a plurality of semiconductor chips 8A and 9A can be obtained. The specific structure of this stacked chip is almost the same as that of the stacked chip 14 shown in FIG. 2D, and the conductive material 12 in FIG.

  Also in this embodiment, since the upper and lower semiconductor chips 8A and 9A are bonded by the adhesive layer 10A or 11A, it is difficult to apply a large stress to the semiconductor chips 8A and 9A. Therefore, even if the semiconductor chips 8A and 9A are made thin, destruction hardly occurs.

  In the present embodiment, the adhesive layer 21 is formed prior to dicing the semiconductor wafer 1A, and the adhesive layer 21 is also cut during dicing. Therefore, at the time of dicing, there is a possibility that the water to be used may come into contact with the adhesive layer 21 or the cut adhesive layers 10A and 11A. However, in FIG. 3C, dicing is performed from the upper surface side of the wafer 1A, and thus water is sprayed from the upper surface side of the wafer 1A. In this case, since only a part, that is, the side surface of the adhesive layer 21 is exposed, the main part of the adhesive layer 21 does not come into contact with water. In addition, even after cutting, as shown in FIG. 4A, only a part of the side surfaces of the adhesive layers 10A and 11A are in contact with water. Therefore, the adhesive layers 10A and 11A are not significantly deteriorated by water.

(Third embodiment)
With reference to FIGS. 5A to 5D and FIGS. 6A and 6B, the manufacturing method of the third embodiment will be described.

  In the third embodiment, a wafer 1 is first prepared as shown in FIG. Thereafter, the thickness of the wafer 1 is reduced, and the lower end of the electrical conduction portion 4 is exposed. In this way, the wafer 1A shown in FIG. 5B is manufactured and bonded onto the dicing tape 6. Since it is performed in the same manner as the first embodiment so far, the description of the first embodiment is omitted by using the description of the first embodiment.

  Next, as shown in FIG. 5C, an adhesive layer 31 is formed on the wafer 1A bonded on the dicing tape 6 by screen printing. That is, the adhesive 31 </ b> A is screen-printed using a screen plate in which the screen 33 is attached to the support frame 32 and the squeegee 34. In this way, the adhesive layer 31 is formed. On the screen 33, the adhesive 31 </ b> A is printed so that the openings 10 a, 10 b, 11 a, and 11 b are formed in the portions where the electrically conductive portion 4 is exposed on the surface of the wafer 1. Accordingly, as shown in FIG. 5D, the adhesive layer 31 has the openings 10a, 10b, 11a, and 11b. Thereafter, preferably, the adhesive layer 31 is brought into a semi-cured state by heating or irradiation with light. The adhesive layer 31 is made semi-cured by heating, irradiating light, or using both, as in the case of the second embodiment.

  Next, as shown in FIG. 6A, the wafer 1A is divided into individual semiconductor chips 8 and 9 by dicing, and the adhesive layer 31 is divided to form adhesive layers 10 and 11. This dicing is performed in the same manner as the step of dicing the wafer 1A in the first embodiment. Therefore, as shown in FIG. 6A, a structure in which the adhesive layers 10 and 11 are formed on the individual semiconductor chips 8 and 9 on the dicing tape 6 can be obtained. Thereafter, as in the case of the first embodiment, the openings 10a, 10b, 11a, and 11b are filled with the conductive material 12. In this way, the structure shown in FIG. 6B is obtained. Therefore, the stacked chip can be obtained by peeling and laminating the semiconductor chips 8 and 9 together with the adhesive layers 10 and 11 in the same manner as in the first embodiment.

  Also in the third embodiment, since the plurality of semiconductor chips 8 and 9 are stacked via the adhesive layer 10 or the adhesive layer 11, a large stress is applied to the semiconductor chips 8 and 9 during the stacking. It ’s hard to join. Therefore, a stacked chip can be obtained by using the thin semiconductor chips 8 and 9, thereby realizing a reduction in height of the stacked chip without impairing reliability.

  In the third embodiment, the adhesive layer 31 is formed prior to the dicing, and water contacts the adhesive layer 31 during dicing. However, since the adhesive layer 31 is in a semi-cured state as described above prior to dicing, deterioration due to water is less likely to occur.

  In the present embodiment, the dicing is performed in a state where the adhesive layer 31 is in a semi-cured state, and the adhesive layers 10 and 11 are completely cured by heating and / or light irradiation during lamination. become.

(Fourth embodiment)
With reference to FIGS. 7A to 7C and FIGS. 8A to 8C, a manufacturing method according to the fourth embodiment will be described.

  In the fourth embodiment, first, as shown in FIG. 7A, a wafer 1 is prepared. The wafer 1 is prepared in the same manner as in the first embodiment.

  Next, as shown in FIG. 7B, an adhesive layer 41 is formed on the surface 1a of the wafer 1 by screen printing. Formation of the adhesive layer 41 by this screen printing is performed in the same manner as the screen printing shown in FIG. That is, the adhesive 41a may be screen-printed using a screen plate and a squeegee 34 in which a screen 33 is stretched on the support frame 32.

  After the screen printing, the adhesive layer 41 is cured by heating and / or light irradiation. Alternatively, the adhesive layer 41 is not cured and is simply dried. In this way, the adhesive layer 41 having the openings 10a, 10b, 11a, and 11b from which the electrical conduction portion 4 is exposed is formed. Here, the adhesive layer 41 is formed simultaneously with the application of the adhesive layer by screen printing.

  Next, as shown in FIG. 7C, a protective tape 42 is applied on the adhesive layer 41, and the thickness of the wafer 1 is reduced from the back surface 1 b side while the adhesive layer 41 is protected. . Since this processing is performed in the same manner as the processing performed to reduce the thickness in the first embodiment, the description in the first embodiment is omitted here.

  By reducing the thickness of the wafer 1 in this way, the electrically conductive portion 4 is exposed on the back side of the wafer. Next, as shown in FIG. 8A, the wafer 1 </ b> A thinned as described above is bonded to the dicing tape 6 together with the adhesive layer 41.

  Thereafter, dicing is performed to divide the wafer 1A into individual semiconductor chips. Next, as shown in FIG. 8B, the remaining portions of the protective tape 42 are removed from the individual semiconductor chips. At the time of dicing, the adhesive layer 41 is also divided at the same time, and the adhesive layers 10 and 11 are formed. Water is used for dicing. However, since the adhesive layer 41 is protected by the protective tape 42, the adhesive layer is hardly deteriorated during dicing with water.

  However, the protective tape 42 may not be used in the present embodiment. In that case, the adhesive layer 41 may be slightly deteriorated by water.

  Thereafter, as shown in FIG. 8C, the conductive material 12 is filled in the openings 10a, 10b, 11a, and 11b. The step of filling the conductive material 12 and the subsequent step of stacking the semiconductor chips 8 and 9 can be performed in the same manner as in the first embodiment.

  Also in the fourth embodiment, when manufacturing the stacked chip, the individual semiconductor chips 8 and 9 shown in FIG. 8C are peeled off from the dicing tape 6 together with the adhesive layers 10 and 11 and laminated. That's fine. Then, the upper and lower semiconductor chips 8 and 9 are joined by the adhesive layer 10 or the adhesive layer 11. Therefore, even when the thickness of the semiconductor chips 8 and 9 is reduced, stress is not easily applied, so that the semiconductor chips 8 and 9 are hardly damaged. Therefore, it is possible to reduce the height of the stacked chip without impairing the reliability.

(adhesive)
In each of the above-described embodiments, the opening 10a and the like are formed on the wafer surface on which the adhesive layer is formed in order to expose the electrical conduction portion 4. The formation pattern of such an adhesive layer is schematically shown in FIG. In FIG. 9, a plurality of electrically conductive portions 4 are aligned on the surface of the semiconductor chip 9, and openings 10 a and 10 b are formed in the adhesive layer 10 so as to surround each electrically conductive portion 4. However, as shown in a schematic plan view in FIG. 10, an adhesive layer 10 having no openings 10a and 10b may be formed. In FIG. 10, an adhesive layer is formed in a part of the region excluding the region where the electrically conductive portion 4 is exposed. Thus, when forming the adhesive layer in the region excluding the electrically conductive portion, it may be at least a part of the remaining region other than the region where the electrically conductive portion is exposed, and the openings 10a, 10b may not necessarily be formed.

  In the first to fourth embodiments described above, the upper and lower semiconductor chips are joined via the adhesive layers 10 and 11 and the like. However, the adhesive constituting these adhesive layers is not particularly limited. However, preferably, as the adhesive constituting the adhesive layer, a thermosetting adhesive, a photocurable adhesive, or an adhesive that is cured by both heat and light is suitably used. When a thermosetting adhesive is used, the adhesive layer can be easily cured only by heating. Such a thermosetting adhesive is not particularly limited, and an appropriate thermosetting resin composition including a thermosetting compound and a curing agent for curing the thermosetting compound with heat may be used. it can. However, in order to increase the reliability, mechanical strength, and dimensional stability of the stacked chip, an epoxy resin-based thermosetting adhesive using an epoxy resin is preferably used as the thermosetting compound. In this case, the mechanical strength, dimensional stability, heat resistance and moisture resistance of the stacked chip can be improved.

  The epoxy resin is not particularly limited, but a resin having a polycyclic hydrocarbon skeleton in the main chain is preferably used.

  The epoxy resin having the polycyclic hydrocarbon skeleton in the main chain is not particularly limited. For example, an epoxy resin having a dicyclopentadiene skeleton such as dicyclopentadiene dioxide and a phenol novolac epoxy resin having a dicyclopentadiene skeleton. (Hereinafter referred to as “dicyclopentadiene type epoxy resin”), 1-glycidylnaphthalene, 2-glycidylnaphthalene, 1,2-diglycidylnaphthalene, 1,5-diglycidylnaphthalene, 1,6-diglycidylnaphthalene, 1 , 7-diglycidylnaphthalene, 2,7-diglycidylnaphthalene, triglycidylnaphthalene, epoxy resin having a naphthalene skeleton such as 1,2,5,6-tetraglycidylnaphthalene (hereinafter referred to as “naphthalene type epoxy resin”) , Tetrahydroxy Eniruetan type epoxy resins, tetrakis (glycidyloxyphenyl) ethane, 3,4-epoxy-6-methylcyclohexyl-3,4-epoxy-6-methylcyclohexane carbonate, and the like. Of these, dicyclopentadiene type epoxy resins and naphthalene type epoxy resins are preferably used.

  These epoxy resins having a polycyclic hydrocarbon skeleton in the main chain may be used alone or in combination of two or more. Moreover, the said dicyclopentadiene type | mold epoxy resin and naphthalene type | mold epoxy resin may each be used independently, and both may be used together.

  Although the epoxy resin which has the said polycyclic hydrocarbon skeleton in a principal chain is not specifically limited, The minimum with a preferable weight average molecular weight is 500, and a preferable upper limit is 1000. When the weight average molecular weight of the epoxy resin having a polycyclic hydrocarbon skeleton in the main chain is less than 500, the mechanical strength, heat resistance, moisture resistance, etc. of the cured thermosetting resin composition are not sufficiently improved. If the weight average molecular weight exceeds 1000, the cured thermosetting resin composition may become too rigid and brittle.

  The curing agent is not particularly limited. For example, heat curing acid anhydride curing agents such as trialkyltetrahydrophthalic anhydride, phenolic curing agents, amine curing agents, latent curing agents such as dicyandiamide, cation Examples thereof include system catalyst type curing agents. These epoxy resin curing agents may be used alone or in combination of two or more.

  Among the above curing agents, a thermosetting curing agent that is liquid at normal temperature and a latent curing agent such as dicyandiamide that is polyfunctional and that can be added in a small amount equivalently are preferably used. By using such a curing agent, it is possible to form an adhesive layer that is flexible at room temperature and has good handleability before curing.

  Typical examples of the thermosetting curing agent that is liquid at room temperature include acid anhydrides such as methyltetrahydrophthalic anhydride, methylhexahydrophthalic anhydride, methylnadic anhydride, and trialkyltetrahydrophthalic anhydride. System curing agent. Of these, methylnadic acid anhydride and trialkyltetrahydrophthalic anhydride are preferably used because they are hydrophobized. These acid anhydride curing agents may be used alone or in combination of two or more.

  In the thermosetting resin composition, a curing accelerator may be used in combination with the curing agent in order to adjust the curing speed and the physical properties of the cured product.

  Although it does not specifically limit as said hardening accelerator, For example, an imidazole type hardening accelerator, a tertiary amine type hardening accelerator, etc. are mentioned. Among these, an imidazole-based curing accelerator is preferably used because it is easy to control the reaction system for adjusting the curing speed and the physical properties of the cured product. These curing accelerators may be used alone or in combination of two or more.

  Although it does not specifically limit as said imidazole series hardening accelerator, For example, the brand name "2MAOK-PW which protected the basicity with 1-cyanoethyl-2-phenylimidazole which protected 1st-position of imidazole with the cyanoethyl group, or isocyanuric acid. (Shikoku Kasei Kogyo Co., Ltd.). These imidazole type hardening accelerators may be used independently and 2 or more types may be used together.

  When using an acid anhydride curing agent in combination with a curing accelerator such as an imidazole curing accelerator, the addition amount of the acid anhydride curing agent should be less than or equal to the theoretically required equivalent to the epoxy group. Is preferred. If the addition amount of the acid anhydride curing agent is excessive more than necessary, chlorine ions may be easily eluted by moisture from the cured product of the thermosetting resin composition. For example, when an elution component is extracted with hot water from a cured thermosetting resin composition, the pH of the extracted water is lowered to about 4 to 5, and a large amount of chlorine ions extracted from the epoxy resin is eluted. It may end up.

In addition, when an amine curing agent and a curing accelerator such as an imidazole curing accelerator are used in combination, the addition amount of the amine curing agent may be less than or equal to the theoretically required equivalent to the epoxy group. preferable. If the addition amount of the amine-based curing agent is excessive more than necessary, chlorine ions may be easily eluted by moisture from the cured product of the thermosetting resin composition. For example, when an elution component is extracted with hot water from a cured thermosetting resin composition, the pH of the extracted water becomes basic and the chloride ions extracted from the epoxy resin may be eluted in large amounts. is there.
Moreover, it is preferable that the said thermosetting resin composition contains the solid polymer which has a functional group which reacts with an epoxy resin further. By containing the solid polymer having a functional group that reacts with the epoxy resin, the thermal reliability of the cured product is enhanced. Although it does not specifically limit as a solid polymer which has a functional group which reacts with the said epoxy group, For example, resin which has an amino group, a urethane group, an imide group, a hydroxyl group, a carboxyl group, an epoxy group etc. is mentioned. Among these, a polymer having an epoxy group is preferable. When the high molecular polymer which has an epoxy group is used, the flexibility of the thermosetting resin composition after hardening can be improved.

  Further, when an epoxy resin having a polycyclic hydrocarbon skeleton in the main chain and a polymer having an epoxy group are used, the cured thermosetting resin composition has the above polycyclic hydrocarbon skeleton as the main chain. The mechanical strength, heat resistance, and moisture resistance are increased due to the epoxy resin contained in the resin, and the flexibility is also enhanced due to the high molecular polymer having the epoxy group.

  The polymer having an epoxy group is not particularly limited as long as it is a polymer having an epoxy group at the terminal and / or side chain (pendant position). For example, an epoxy group-containing acrylic rubber, an epoxy group-containing Examples thereof include butadiene rubber, bisphenol type high molecular weight epoxy resin, epoxy group-containing phenoxy resin, epoxy group-containing acrylic resin, epoxy group-containing urethane resin, and epoxy group-containing polyester resin. Especially, since the mechanical strength and heat resistance of the thermosetting resin composition after hardening can be improved, an epoxy group containing acrylic resin is used suitably. These polymer polymers having an epoxy group may be used alone or in combination of two or more.

  Moreover, as said photocurable adhesive agent, the appropriate photocurable composition containing the suitable photocurable compound hardened | cured by irradiation of light, and the photocatalyst which accelerates | stimulates hardening of a photocurable compound by irradiation of light. Can be used. As such a photocurable composition, an appropriate compound that is cured by photoradical polymerization or photocationic polymerization when irradiated with light such as ultraviolet rays, such as an acrylic compound or an epoxy compound, can be used. . As the photocatalyst, an appropriate photopolymerization initiator that causes the photoradical polymerization or photocationic polymerization can be used.

  Also in the photocurable composition, since the cured product is excellent in mechanical strength and excellent in dimensional stability and moisture resistance, a photocurable adhesive mainly composed of an epoxy compound is preferably used.

  However, as described above, an adhesive that includes both a photocuring component and a thermosetting component and can be cured by both light irradiation and heating may be used as the adhesive constituting the adhesive layer.

(Semi-cured)
In the second embodiment and the third embodiment described above, the dicing process is performed after the adhesive layer is semi-cured. This is because, after the semi-curing stage, the contact with water during dicing is very difficult to cause deterioration of the adhesive layer. In this case, semi-curing refers to a state in which curing does not result in complete curing, but is cured to such a degree that deterioration due to dicing water contact does not easily occur. As for the semi-cured state, the degree to which deterioration due to dicing contact with water does not easily occur differs depending on the type of adhesive and the degree of contact with water. It shall be in a state where it has been hardened to such an extent that deterioration due to contact is unlikely to occur.

  In realizing the semi-cured state as described above and facilitating the operation of complete curing at a later stage, the adhesive constituting the adhesive layer is an adhesive that is cured by both heat and light. Preferably used. In this case, curing may be performed by either heating or light irradiation to obtain a semi-cured state, and finally complete curing by light irradiation or heating. That is, the semi-cured state and the complete curing can be easily and reliably realized by appropriately selecting both heating and light irradiation.

  Although it does not specifically limit as a photocurable compound, Especially, the (meth) acrylate compound which has two or more functional groups in 1 molecule is used suitably, In that case, while ensuring sufficient adhesive force, light It is possible to easily realize a semi-cured state while proceeding photopolymerization / crosslinking by irradiation.

  The (meth) acrylate compound having two or more functional groups in one molecule preferably has a molecular weight of 600 or less. When the molecular weight is as small as 600 or less, the adhesive is excellent in initial fluidity, and has excellent coating properties and printability without using other solvents, which is preferable.

  Although it does not specifically limit as a (meth) acrylate compound with a molecular weight of 600 or less, For example, bifunctional acrylate compounds, such as modified bisphenol A diacrylate and dimethylol dicyclopentadiene acrylate; Trimethylol propane triacrylate, trimethylol propane ethoxy acrylate A trifunctional acrylate compound such as dipentaerythritol hexaacrylate, a tetrafunctional or higher acrylate compound, a bifunctional methacrylate compound such as butanediol dimethacrylate, and the like can be preferably used.

  Examples of commercially available photocurable compounds include Ebecryl 150, Ebecryl 1150, IRR214, TMPTA, EB160, DPHA, BDDMA (all manufactured by Daicel).

  The blending amount of the photocurable compound is not particularly limited, but a preferable upper limit is 20 parts by weight with respect to 100 parts by weight of the total amount of the epoxy compound. If it exceeds 20 parts by weight, heat resistance may not be sufficiently obtained.

  Although it does not specifically limit as said photoinitiator, For example, Irgacure 651 etc. which are visible light polymerization initiators can be used.

  The blending amount of the photopolymerization initiator is not particularly limited, but a preferable lower limit is 0.1 parts by weight and a preferable upper limit is 5 parts by weight with respect to 100 parts by weight of the photocurable compound.

  The adhesive may further contain additives such as an adhesion promoter such as a thixotropic agent, a solvent, an antioxidant, a bleed inhibitor, and an imidazole silane coupling agent, if necessary. Moreover, when it contains the said photocurable compound, you may contain a sensitizer further.

(Adhesive application method)
In the above-described first to fourth embodiments, the transfer method and the printing method by screen printing are shown in forming the adhesive layer, but the method for forming the adhesive layer is not particularly limited. For example, in the first embodiment, the adhesive layer may be formed by a printing method such as screen printing instead of the transfer method. As a printing method, gravure printing or the like may be used in addition to screen printing. In general, in the manufacture of a semiconductor device, when applying an adhesive, the adhesive is generally applied to the entire surface by a spin coating method, and then patterning is often performed using a photolithography technique. However, when the adhesive layer is formed by spin coating, it is very difficult to make the film thickness uniform with high accuracy.

  On the other hand, according to the printing method and the transfer method described above, the thickness of the adhesive layer can be made uniform with high accuracy. Therefore, it is difficult for the stacked semiconductor chips to be inclined in the stacked chip, and it is possible to provide a stacked chip with excellent reliability.

(Example)
Hereinafter, although a concrete example is given and the effect of the present invention is clarified, the present invention is not limited to the following example.

(Examples 1-3)
According to the composition of Table 1, each material shown below was stirred and mixed using a homodisper to prepare an adhesive composition.

1. Thermosetting compound Dicyclopentadiene type epoxy resin (HP-7200HH, manufactured by Dainippon Ink & Chemicals, Inc.)
Naphthalene type epoxy resin (HP-4032D, manufactured by Dainippon Ink & Chemicals, Inc., liquid at normal temperature)
Epoxy group-containing acrylic resin (Blemmer CP-30, manufactured by Japan Epoxy Resin Co., Ltd.)
2. Curing agent Acid anhydride (YH-307, manufactured by Japan Epoxy Resin Co., Ltd.)
3. Curing accelerator Imidazole compound (2MA-OK, manufactured by Shikoku Kasei Kogyo Co., Ltd.)
4). Additives Epoxysilane coupling agent (KB43, manufactured by Shin-Etsu Chemical Co., Ltd.)
Thickener (MT-10, manufactured by Nippon Aerosil Co., Ltd.)
5. Photocurable compound Acrylic crosslinking agent (Aronix M402, manufactured by Toa Gosei Co., Ltd.) (molecular weight: 562)
6. Photopolymerization initiator Photoradical generator (Irgacure 651, manufactured by Ciba Specialty Chemicals)
7). Solvent Methyl ethyl ketone

(2) Manufacture of stacked chips (Example 1) Adhesive layer after dicing An 8-inch diameter notch wafer having a semiconductor circuit and copper vias in advance (thickness of silicon wafer is 0.7 mm, size of one chip is 10 mm) × 20 mm, and there are 20 copper vias with a diameter of 70 μm and a depth of 70 μm on each side.

  A back grind tape (Selfa BG, manufactured by Sekisui Chemical Co., Ltd.) is pasted on the upper surface of the semiconductor wafer, the back surface is ground to a thickness of 100 μm, and then etched with Wet Etch to expose the electrically conductive portion and form a through electrode. A semiconductor wafer was obtained.

  The back surface of the semiconductor wafer was attached to a dicing tape “PE tape # 6318-B” (manufactured by Sekisui Chemical Co., Ltd., thickness 70 μm, base polyethylene, adhesive rubber adhesive 10 μm), and the back grind tape was peeled off.

  Using a dicing apparatus DFD651 (manufactured by DISCO Corporation), the semiconductor wafer was divided into chip sizes of 10 mm × 10 mm at a feed rate of 50 mm / second.

  An adhesive having the composition shown in Table 1 was applied using a screen printing apparatus (MT320-TVC, Microtec) to form an adhesive layer in a pattern shape excluding the through electrode as shown in FIG. The thickness of the adhesive layer was 20 μm.

  After forming the above adhesive layer, using a die bonder best D-02 (made by Canon Machinery Co., Ltd.), the divided semiconductor chips are continuously picked up at a collet size of 8 mm square and a push-up speed of 5 mm / sec. A stacked chip semiconductor chip was obtained, aligned with a flip chip bonder DB100 (manufactured by Shibuya Kogyo Co., Ltd.), and the adhesive layer was cured at 180 ° C. for 30 minutes to obtain a stacked chip.

  The obtained stacked chip semiconductor chip is die-bonded on a 151 mm × 66 mm, 0.16 mm thick copper wiring board, and another stacked chip semiconductor chip is laminated via an adhesive layer formed on the upper surface thereof. did.

  After three layers were laminated, the adhesive layer was cured at 170 ° C. for 30 minutes to obtain a stacked chip.

(Example 2)
An adhesive layer was formed on the back surface of the semiconductor wafer whose back surface was ground in the same manner as in Example 1 using the same screen printing apparatus as in Example 1.

  A stacked chip semiconductor chip was obtained in the same manner as in Example 1 except that the semiconductor wafer was divided into semiconductor chips in a state of being bonded to a dicing tape via an adhesive layer.

  A stacked chip was obtained in the same manner as in Example 1 except that the chips were stacked via an adhesive layer formed on the back surface of the semiconductor chip.

(Example 3)
The back grind tape was peeled off from the upper surface of the semiconductor wafer whose back surface was ground in the same manner as in Example 1, and an adhesive layer was formed using the same screen printing apparatus as in Example 1.

  Thereafter, the adhesive layer was irradiated with light using a UV irradiation apparatus (ORC, JL4300) under the conditions of a high-pressure mercury lamp 30 mW / cm 2 and 20 seconds, and the adhesive layer was semi-cured.

  The back surface of the semiconductor wafer provided with the semi-cured adhesive layer was attached to a dicing tape in the same manner as in Example 1, and a stacked chip semiconductor chip was obtained in the same manner as in Example 1.

  The obtained stacked chip semiconductor chip is die-bonded on a 151 mm × 66 mm, 0.16 mm thick copper wiring board, and another stacked chip semiconductor chip is laminated via an adhesive layer formed on the upper surface thereof. did.

  After three layers were laminated, the adhesive layer was cured at 180 ° C. for 30 minutes to obtain a stacked chip.

(Comparative Example 1)
A semiconductor wafer whose back surface was ground in the same manner as in Example 1 was divided in the same manner as in Example 1 without forming an adhesive layer to obtain a semiconductor chip for stacked chips.

  A solder layer was formed on the tip of the through electrode protrusion of the obtained stacked chip semiconductor chip.

  The stacked chip semiconductor chip on which the solder layer was formed was aligned using a flip chip bonder DB100 (manufactured by Shibuya Kogyo Co., Ltd.), and three chips were stacked via the solder layer.

  An adhesive was injected into the periphery of the laminate, and an adhesive layer was also disposed between the semiconductor chips by the same phenomenon as underfill.

  Then, it heated for 30 minutes at 180 degreeC, the adhesive bond layer was hardened, and the stacked chip | tip was produced.

(Evaluation)
(1) Breakage of semiconductor chip For each of the 100 stacked chips obtained in Examples 1 to 3 and Comparative Example 1, the used adhesive was removed with a mixed acid, and cracks or cracks occurred on the surface of the semiconductor chip. Whether or not was observed using an electron microscope. Evaluation was performed based on the following criteria.

  (Double-circle): A crack and a crack were not observed.

  ○: Some small cracks or small cracks were observed.

  Δ: Cracks or cracks were observed.

  X: Cracks and cracks were observed.

(2) Heat resistance test About 100 obtained semiconductor chip laminates, after drying at 125 ° C for 6 hours and subsequently treating at 30 ° C under 80% wet conditions for 48 hours, the same 260 ° C as during solder reflow, Heat treatment was performed for 30 seconds. And it was observed whether the delamination had generate | occur | produced about the semiconductor chip laminated body after performing such heat processing 3 times. Observation of delamination was performed using an ultrasonic exploration imaging apparatus (mi-scope hyper II, manufactured by Hitachi Construction Machinery Finetech Co., Ltd.).

  Moreover, the adhesive for semiconductor components used for the semiconductor chip laminated body was removed with a mixed acid, and it was observed whether or not the silicon nitride protective film on the surface of the semiconductor chip was cracked.

  The heat resistance of the semiconductor chip laminate was evaluated by evaluating the delamination and cracking of the protective film according to the following criteria.

  (Double-circle): The delamination and the crack of the protective film were not observed.

  A: Some peeling between layers or small cracks in the protective film were observed.

  (Triangle | delta): The delamination or the crack of a protective film was observed.

  X: Conspicuous peeling between layers or conspicuous cracking of the protective film was observed.

(3) Temperature cycle test About the obtained semiconductor chip laminated body, about the semiconductor chip laminated body after performing a temperature cycle test which makes 9 cycles at -55 degreeC and 9 minutes at 125 degreeC, and performed 1000 cycles Whether or not delamination occurred was observed. Moreover, the adhesive for semiconductor components used for the semiconductor chip laminated body was removed with a mixed acid, and it was observed whether or not the silicon nitride protective film on the surface of the semiconductor chip was cracked.

  The delamination and the crack of the protective film were evaluated according to the following criteria.

  (Double-circle): The delamination and the crack of the protective film were not observed.

  ○: Some peeling between layers or small cracks in the protective film were observed.

  (Triangle | delta): The delamination or the crack of a protective film was observed.

  X: Conspicuous peeling between layers or conspicuous cracking of the protective film was observed.

(A)-(c) is typical front sectional drawing for demonstrating each process of the manufacturing method of the semiconductor chip for stacked chips which concerns on the 1st Embodiment of this invention. (A)-(d) is each partial notch front sectional drawing for demonstrating each process of the manufacturing method of 1st Embodiment. (A)-(c) is each typical front sectional drawing for demonstrating the manufacturing method of the 2nd Embodiment of this invention. (A), (b) is typical fragmentary front sectional drawing for demonstrating each process of the manufacturing method of 2nd Embodiment. (A)-(d) is each typical front sectional drawing for demonstrating each process of manufacture of the 3rd Embodiment of this invention. (A), (b) is a partial notch front sectional drawing for demonstrating each process of the manufacturing method of 3rd Embodiment. (A)-(c) is typical front sectional drawing for demonstrating each process of the manufacturing method of the semiconductor chip for stacked chips which concerns on the 4th Embodiment of this invention. (A)-(c) is each partial notch front sectional drawing for demonstrating each process of the manufacturing method of 4th Embodiment. The top view which shows typically the relationship between the adhesive bond layer formed in the surface of the semiconductor chip of this invention, an opening part, and an electrically-conductive part. In this invention, the typical top view which shows the other example of the positional relationship of the adhesive bond layer formed in the upper surface of a semiconductor chip, and an electrically-conductive part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Wafer 1a ... Front surface 1b ... Back surface 1A ... Wafer 1c ... Back surface 2 ... Conductive pattern 3 ... Wiring pattern 4 ... Electrical conduction part 5 ... Internal electrode 6 ... Dicing tape 7 ... Frame material 8, 9 ... Semiconductor chip 8A, 9A ... Semiconductor chip 10, 11 ... Adhesive layer 10A, 11A ... Adhesive layer 10a, 10b, 11a, 11b ... Opening 12 ... Conductive material 13 ... Support film 14 ... Stacked chip 15 ... Adhesive layer pattern 16 ... Roller 17 ... Lamination stage 21 ... Adhesive layer 22 ... Conductive material 31 ... Adhesive layer 31A ... Adhesive 32 ... Support frame 33 ... Screen 34 ... Squeegee 41 ... Adhesive layer 41a ... Adhesive

Claims (6)

A semiconductor chip for obtaining a stacked chip in which a plurality of semiconductor chips are stacked and electrically connected to each other, from the front surface to the back surface, and for electrically connecting the upper and lower semiconductor chips. A method of manufacturing a semiconductor chip for a stacked chip having an electrically conductive portion used,
A step of preparing a mother wafer in which a plurality of semiconductor chips are configured, a conductive pattern including an electrically conductive portion formed on the surface, and the electrically conductive portion exposed on the surface; ,
A process of reducing the thickness from the back side of the wafer, and exposing the electrically conductive portion to the back side of the wafer;
Attaching the wafer to the dicing tape from the back side;
Dividing the wafer affixed to the dicing tape into individual stacked chip semiconductor chips;
And a step of forming an adhesive layer in a region excluding the electrical conduction portion on the upper surface of each semiconductor chip divided on the dicing tape. A semiconductor chip for obtaining a stacked chip in which a plurality of semiconductor chips are stacked and electrically connected to each other, from the front surface to the back surface, and for electrically connecting the upper and lower semiconductor chips. A method of manufacturing a semiconductor chip for a stacked chip having an electrically conductive portion used,
A step of preparing a mother wafer in which a plurality of semiconductor chips are configured, a conductive pattern including an electrically conductive portion formed on the surface, and the electrically conductive portion exposed on the surface; ,
Applying a process of reducing the thickness from the back side of the wafer, exposing the electrically conductive portion on the back side of the wafer;
Forming an adhesive layer on the back surface of the wafer in a region excluding the electrically conductive portion;
Attaching the wafer to the dicing tape through the adhesive layer;
And a step of dividing the wafer affixed to the dicing tape into individual semiconductor chips. A semiconductor chip for obtaining a stacked chip in which a plurality of semiconductor chips are stacked and electrically connected to each other, from the front surface to the back surface, and for electrically connecting the upper and lower semiconductor chips. A method of manufacturing a semiconductor chip for a stacked chip having an electrically conductive portion used,
A step of preparing a mother wafer in which a plurality of semiconductor chips are configured, a conductive pattern including an electrically conductive portion formed on the surface, and the electrically conductive portion exposed on the surface; ,
Applying a process of reducing the thickness from the back side of the wafer, exposing the electrically conductive portion on the back side of the wafer;
Attaching the wafer to the dicing tape from the back side;
Forming an adhesive layer in a region excluding the electrically conductive portion on the surface of the wafer;
Semi-curing the adhesive layer;
Dividing the semiconductor wafer into individual semiconductor chips, and a method for manufacturing a semiconductor chip for stacked chips. A semiconductor chip for obtaining a stacked chip in which a plurality of semiconductor chips are stacked and electrically connected to each other, from the front surface to the back surface, and for electrically connecting the upper and lower semiconductor chips. A method of manufacturing a semiconductor chip for a stacked chip having an electrically conductive portion used,
A step of preparing a mother wafer in which a plurality of semiconductor chips are configured, a conductive pattern including an electrically conductive portion formed on the surface, and the electrically conductive portion exposed on the surface; ,
Forming an adhesive layer on the surface of the wafer at the same time as applying an adhesive to a region excluding the electrically conductive portion; and
Processing from the back side of the wafer, reducing the thickness of the wafer, and exposing the electrically conductive portion to the back side;
After the electrically conductive portion is exposed on the back side of the wafer, the step of attaching the wafer to the dicing tape from the back side;
A method of manufacturing a semiconductor chip for stacked chips, comprising the step of dividing a wafer affixed to a dicing tape into individual semiconductor chips.   The adhesive for forming the adhesive layer contains a thermosetting compound, a curing agent for curing the thermosetting compound by heat, and a photocurable compound having a molecular weight of 600 or less. The manufacturing method of the semiconductor chip for stacked chips of Claim 3 characterized by the above-mentioned. A step of preparing a plurality of stacked chip semiconductor chips obtained by the manufacturing method according to claim 1;
Filling the opening of the adhesive layer of the semiconductor chip for stacked chips with a conductive material;
The plurality of stacked chip semiconductor chips are stacked and bonded via the adhesive layer, and the electrically conductive portions of the upper and lower semiconductor chips are electrically connected by the conductive material. A method for manufacturing a stacked chip.

Images