JP2008140925A - Semiconductor device, manufacturing method thereof, and display device - Google Patents

Abstract

A semiconductor device having excellent reliability, a manufacturing method thereof, and a display device are provided.
A semiconductor device having a structure in which a semiconductor element having element bumps is mounted on a wiring board having a wiring pattern formed on the board, wherein the wiring board has terminal bumps on terminal portions of the wiring pattern. The semiconductor device is a semiconductor device having a structure in which terminal bumps and element bumps are electrically connected. Preferably, the element bumps and / or terminal bumps include gold and / or tin.
[Selection] Figure 1

Description

The present invention relates to a semiconductor device, a manufacturing method thereof, and a display device. More specifically, a semiconductor device in which a semiconductor element such as a semiconductor integrated circuit having a bump is flip-chip mounted on a wiring board by a mounting method such as a COF (Chip on Film) method or a COB (Chip on Board) method, and a manufacturing method thereof And a display device.

In recent years, flip chip mounting has been used as a method for mounting a semiconductor integrated circuit (hereinafter also referred to as an “IC chip”) on a substrate. According to flip chip mounting, the surface of the IC chip and the substrate are electrically connected by bumps (projecting electrodes) of the IC chip, so that the mounting area can be reduced as compared with wire bonding or the like. Therefore, the flip chip mounting technique is widely used for semiconductor devices provided in portable devices, thin display devices, and the like that are strongly demanded for miniaturization and thinning.

7A and 7B are schematic cross-sectional views showing a conventional semiconductor device, in which FIG. 7A is an enlarged view showing an IC chip mounting region and its vicinity, and FIG. 7B is an enlarged view showing the vicinity of a connection region of an IC chip and a wiring board. is there. In the conventional semiconductor device 120, as shown in FIG. 7A, an IC chip 131 is flip-chip mounted on a wiring substrate 140 in which a wiring pattern 142 and a resist 145 are formed on a substrate 141. The IC chip 131 and the wiring board 140 are fixed by the adhesive layer 122, and the element bumps 132 formed on the IC chip 131 and the terminal portions 143 from which the wiring patterns 142 are extended are electrically connected. Thus, the IC chip 131 and the wiring board 140 are electrically connected. However, in the conventional semiconductor device 120 in which the IC chip 131 is flip-chip mounted, a connection failure may occur between the IC chip 131 and the wiring board 140.

In addition, as an adhesion method when an IC chip having bumps is flip-chip mounted on a substrate, after applying an adhesive to the substrate, a pre-coating method in which the IC chip is crimped and the adhesive is cured, and the IC chip is mounted on the substrate. For example, an IC chip bump and a terminal portion provided on the substrate are metal-bonded to each other and then an adhesive is poured between the IC chip and the substrate. As the post-coating method, the bump electrode side of the bare chip IC is opposed to the mounting area of the wiring substrate, and the inner lead or wiring pattern corresponding to each bump electrode is metal-bonded, and a resin is applied between the bare chip IC and the mounting area. A method for manufacturing a semiconductor device including a resin sealing step for pouring and a step for curing a resin is disclosed (for example, see Patent Document 1).

Further, the structure of the IC chip mounting portion of the substrate is a structure having a terminal (flying lead) protruding from the opening of the substrate, such as a TAB (Tape Automated Bonding) method, a terminal portion such as the COF method and the COB method. Is supported by the substrate over the entire surface (structure in which the IC chip mounting portion has no substrate opening).

As a technology for flip-chip mounting an IC chip by the TAB method, a TAB type semiconductor in which a large number of electrodes provided in a semiconductor element and the vicinity of the tip of an inner lead formed on a flexible circuit board are connected by heating, pressurizing or the like. In the device, a TAB type semiconductor device having no protrusion (bump) on both the electrode of the semiconductor element and the inner lead is disclosed (for example, see Patent Document 2). According to this, it is described that a low-cost and highly reliable semiconductor device can be manufactured.

However, in this semiconductor device, an IC chip is flip-chip mounted by the TAB method, and Patent Document 1 does not describe the COF method and the COB method at all. Therefore, the semiconductor device in which the IC chip is flip-chip mounted on the wiring substrate having a structure in which the terminal portion is supported on the entire surface, like the COF method and the COB method, is devised in that excellent reliability is realized. There was room for.

On the other hand, a liquid crystal display device is disclosed in which a liquid crystal display panel and a flexible printed circuit board with fine irregularities formed on the surface of a terminal are bonded using an anisotropic conductive film not containing conductive particles ( For example, see Patent Document 3.)

Moreover, the technique which arrange | positions and arrange | positions the groove | channel which diagonally crosses a terminal in the terminal surface of each terminal in the connection part of a flexible substrate is disclosed (for example, refer patent document 4).

However, these technologies also have room for improvement in terms of realizing excellent reliability. These techniques are techniques for processing the terminals themselves provided on the substrate.
JP 2006-147934 A Japanese Patent Laid-Open No. 10-335376 JP 2003-156759 A JP 2004-47355 A

The present invention has been made in view of the above-described present situation, and an object thereof is to provide a semiconductor device having excellent reliability, a manufacturing method thereof, and a display device.

The inventors of the present invention have made various studies on a semiconductor device having excellent reliability, a manufacturing method thereof, and a display device. As a result, bumps (element bumps) formed on a semiconductor element such as an IC chip and wiring formed on a wiring board are disclosed. We paid attention to the connection form with the terminal part of the pattern. In the conventional COF type or COB type structure, since the terminal portion is formed on the substrate, the region is pressed by the element bumps of the terminal portion by heating and pressurizing when the IC chip is crimped. Found to sink locally. In addition, at this time, it was found that the terminal part was not sunk evenly in the entire region pressed by the element bumps, but the terminal part was bent and sunk into a substantially V-shaped (U-shaped) cross-sectional view. . Therefore, after the IC chip is crimped, as shown in FIG. 1B, the element bump 132 and the terminal portion 143 come into contact only in the vicinity of the peripheral portion of the element bump 132, and in the central portion of the element bump 132, the element bump It was found that a gap (hereinafter also simply referred to as “gap”) 160 between the bump 132 and the terminal portion 143 is generated.

Therefore, further investigation has revealed that a terminal bump is formed on the terminal portion of the wiring pattern, and this terminal bump and the element bump are electrically connected to suppress the occurrence of a gap between the element bump and the terminal portion. As a result, it has been found that the occurrence of poor connection can be effectively suppressed, and has arrived at the present invention by conceiving that the above-mentioned problems can be solved brilliantly.

That is, the present invention is a semiconductor device having a structure in which a semiconductor element having element bumps is mounted on a wiring board in which a wiring pattern is formed on the board, and the wiring board is connected to a terminal portion of the wiring pattern. The semiconductor device having a bump is a semiconductor device having a structure in which a terminal bump and an element bump are electrically connected. As described above, by the terminal bump being interposed between the element bump and the terminal portion of the wiring pattern, it is possible to suppress the occurrence of a gap between the element bump and the terminal portion. Therefore, the contact area between the element bump and the terminal portion increases, and the occurrence of contact failure between the element bump and the terminal portion can be effectively suppressed. As a result, a semiconductor device having excellent reliability can be realized.

The configuration of the semiconductor device of the present invention is not particularly limited as long as such a component is formed as an essential component, and may or may not include other components. .

As described in Patent Documents 3 and 4, even if the terminal part itself is processed to form grooves or irregularities in the terminal part, the gap is not filled, and the occurrence of poor connection due to the gap is suppressed. I can't do it.

The semiconductor device described in Patent Document 2 is a TAB type semiconductor device that does not have protrusions (bumps) on both the electrode and inner lead of the semiconductor element, and bumps are formed on both the semiconductor element and the terminal portion of the wiring pattern. This is clearly distinguished from the present invention in which is formed. Further, in Patent Document 2, as a problem of the conventional TAB type semiconductor device, an electrical short (edge short) between the IC edge and the inner lead and damage due to the inner lead tip contacting the circuit portion of the semiconductor element are avoided. Therefore, it is only described that it is necessary to provide a bump on either the electrode of the semiconductor element or the tip of the inner lead of the flexible circuit board, and about forming the bump on both the semiconductor element and the terminal portion of the wiring pattern. There is no description.
A preferred embodiment of the semiconductor device of the present invention will be described in detail below.

The terminal bump preferably includes gold (Au) and / or tin (Sn), and the element bump preferably includes Au and / or Sn. As described above, since the terminal bump and / or the element bump includes a relatively soft metal as compared with the material of the terminal portion or the like, the generation of the gap can be more effectively suppressed. Therefore, the reliability of the semiconductor device can be further improved. In addition, it can be said that the terminal bumps and / or element bumps are preferably formed of a metal softer than the terminal component constituent material.

In addition, from the viewpoint of further improving the reliability of the semiconductor device, the terminal bump and the element bump preferably include Au and / or Sn, and are formed of a metal softer than the constituent material of the terminal portion. Is preferred. Each of Au and Sn may be a simple substance or a compound (alloy). In other words, the terminal bump and / or the element bump are preferably made of a single metal of Au and / or Sn or a compound (alloy). Examples of the compound (alloy) include solder that is an Sn alloy.

The semiconductor device preferably has a form in which the terminal bump and the element bump are metal-bonded, or a form having an alloy layer between the terminal bump and the element bump. Thereby, since the connection between the element bump and the terminal bump can be made stronger, the reliability of the semiconductor device can be further improved.

The alloy layer is preferably formed when the terminal bump and the element bump are metal-bonded. That is, the semiconductor device includes a form having an alloy layer formed by metal bonding between a terminal bump and an element bump, and a terminal bump constituent material and an element bump constituent material between the terminal bump and the element bump. A form having the formed alloy layer is preferable. Moreover, it does not specifically limit as a material of the alloy which comprises an alloy layer, Au-Sn eutectic, Au / Sn alloy, Au / Sn ₂ alloy, Au / Sn ₄ alloy etc. are mentioned.

The element bump may have a recess (unevenness) on the surface of the terminal bump. In the case where the element bump has a concave portion, conventionally, the gap is particularly likely to be large, and connection failure often occurs. However, according to the semiconductor device of the present invention, the space in the recess is effectively filled with the terminal bump, and the element bump and the terminal bump can be reliably connected. Therefore, the effect of the present invention can be further exerted in the form in which the element bump has a recess.

The present invention is also a method for manufacturing a semiconductor device having a structure in which a semiconductor element having element bumps is mounted on a wiring board having a wiring pattern formed on the substrate, wherein the manufacturing method includes a terminal portion of the wiring pattern. The method of manufacturing a semiconductor device includes a step of forming terminal bumps on the substrate and a step of crimping a semiconductor element to a wiring board and electrically connecting the terminal bumps and the element bumps. Thereby, it is possible to suppress the occurrence of a gap when the semiconductor element is pressure-bonded to the wiring board. Therefore, similarly to the semiconductor device of the present invention, a semiconductor device having excellent reliability can be easily manufactured.

The method for manufacturing a semiconductor device of the present invention is not particularly limited by other steps as long as it has these steps, but usually includes a step of aligning element bumps and terminal bumps.
A preferred embodiment of the method for manufacturing a semiconductor device of the present invention will be described in detail below.

The element bump may have a recess (unevenness) on the surface of the terminal bump. As described above, when the element bump has a recess before the semiconductor element is pressure-bonded, conventionally, the gap is particularly likely to be large, and connection failure often occurs. However, according to the manufacturing method of the semiconductor device of the present invention, as in the semiconductor device of the present invention, the space in the recess can be effectively filled with the terminal bump, and the element bump and the terminal bump can be reliably connected. it can. Therefore, the effect of the present invention can be further exerted in the form in which the element bump has a recess.

Note that various forms described in the semiconductor device of the present invention can be appropriately applied to the form of the components of the semiconductor device in the method of manufacturing a semiconductor device of the present invention.

The present invention is also a display device including the semiconductor device of the present invention, or a display device including the semiconductor device manufactured by the semiconductor device manufacturing method of the present invention. According to the present invention, since the reliability of the semiconductor device can be improved, the reliability of the display device can be improved.

According to the semiconductor device of the present invention, since the wiring board has the terminal bumps on the terminal portions, and the terminal bumps and the element bumps are electrically connected, the reliability of the semiconductor device can be improved.

Embodiments will be described below, and the present invention will be described in more detail with reference to the drawings. However, the present invention is not limited only to these embodiments. In the following embodiments, the present invention will be described using a liquid crystal display device as an example. However, the display device of the present invention is not only a liquid crystal display device but also various display devices such as an organic electroluminescence (EL) display device, an inorganic EL display device, a plasma display panel (PDP), and a vacuum fluorescent display (VFD) device. It can be applied to various display devices such as electronic paper. Further, the present invention can be applied not only to display devices but also to various electronic devices such as mobile phones, PDAs (Personal Digital Assistants), OA devices, and the like.

(Embodiment 1)
1A and 1B are schematic cross-sectional views illustrating a semiconductor device according to the first embodiment. FIG. 1A illustrates an IC chip mounting region and its vicinity, and FIG. FIG.

As illustrated in FIG. 2, the liquid crystal display device 100 includes a liquid crystal display panel 10 and a semiconductor device 20 connected to the liquid crystal display panel 10.

The liquid crystal display panel 10 includes an element substrate 11 on which switching elements are formed, a counter substrate 12 disposed to face the element substrate 11, and a liquid crystal layer interposed between the two substrates. The counter substrate 12 includes a common electrode provided on almost the entire display area on the substrate, and a color filter layer. The liquid crystal layer is made of a nematic liquid crystal material having electro-optical characteristics.

The element substrate 11 includes a plurality of gate wirings provided on the substrate so as to extend in parallel with each other, a source wiring provided so as to extend in parallel with each other in a direction orthogonal to the gate wirings, and a gate wiring. And a TFT provided at each intersection of the source wiring and a pixel electrode provided corresponding to each TFT.

In addition, the liquid crystal display panel 10 includes a driver IC 13 that is flip-chip mounted on a substrate by a COG (Chip On Glass) method.

The semiconductor device 20 includes a wiring board 40, an IC chip 31 connected to the wiring board 40, and a passive element 21 such as a capacitor and a resistor.

The IC chip 31 is flip-chip mounted on the wiring substrate 40 by a COF (Chip On Film) method or a COB (Chip On Board) method, and functions as a controller IC, a power supply IC, or the like of the liquid crystal display device 100. The external dimensions of the IC chip 31 are, for example, 5 mm long, 5 mm wide, and 400 μm high. Further, as shown in FIG. 1, the IC chip 31 is fixed on the wiring board 40 by the adhesive layer 22. Further, the IC chip 31 has element bumps 32 which are protruding bump electrodes on the wiring board 40 side. Of course, the IC chip 31 and the driver IC 13 may be LSI chips (large scale integrated circuits).

A plurality of element bumps 32 are provided on the outer periphery of the bottom surface of the IC chip 31 (surface on the wiring board 40 side) so as to protrude in the normal direction of the bottom surface of the IC chip 31. The element bump 32 becomes an input / output terminal of the IC chip 31. The shape of the element bump 32 is not particularly limited, and may be a substantially cubic body, a substantially cylindrical body, a substantially spherical body, a substantially elliptical spherical body, or the like in addition to the substantially rectangular parallelepiped as shown in FIG. In the present embodiment, the element bumps 32 are so-called straight plating bumps having a substantially rectangular parallelepiped shape, and the outer dimensions thereof are, for example, 60 μm in length and width and 15 to 19 μm in height, and the pitch of each element bump 32 is Is, for example, 80 μm. Thereby, the fine pitch of the element bumps 32 can be achieved. In addition, the shape of the element bump 32 may be a shape in which each of the above shapes is crushed from the vertical direction (from the IC chip 31 side and the wiring substrate 40 side).

In the wiring substrate 40, a wiring pattern 42 having a thickness of 15 μm is formed on the main surface of an insulating substrate (base material) 41. The wiring pattern 42 connects the IC chip 31 to an input signal connector (not shown), the liquid crystal display panel 10 and the like. A resist 45 having a thickness of 25 μm and having an opening region is provided on the main surface of the substrate 41 so as to cover the wiring pattern 42. A terminal exposed portion of the wiring pattern 42 extended to the opening region of the resist 45 becomes a terminal portion 43 connected to the element bump 32 of the IC chip 31. The opening area of the resist 45 becomes an IC chip mounting area.

On the terminal portion 43 (on the IC chip side of the terminal portion 43), terminal bumps 44, which are protruding bump electrodes, are formed. As a result, not only the element bump 32 but also both the element bump 32 and the terminal bump 44 are deformed when the IC chip 31 is crimped. Therefore, in the semiconductor device 20, since the terminal bump 44 is interposed between the element bump 32 and the terminal portion 43 as shown in FIG. As described above, the element bumps 32 and the terminal bumps 44 are substantially in contact with each other.

The shape of the terminal bump 44 is not particularly limited, and may be a substantially cubic body, a substantially cylindrical body, a substantially spherical body, a substantially elliptical sphere, or the like in addition to a substantially rectangular parallelepiped as shown in FIG. In the present embodiment, the shape of the terminal bump 44 is, for example, a substantially rectangular parallelepiped having a length and width of 60 μm and a height of about 15 to 19 μm. Thus, for example, by making the shapes and / or sizes of the terminal bumps 44 and the element bumps 32 substantially the same, the occurrence of a gap can be sufficiently suppressed. The shape of the terminal bump 44 may be a shape obtained by crushing each of the above shapes from the vertical direction (from the IC chip 31 side and the wiring substrate 40 side).

Below, the manufacturing method of the liquid crystal display device of Embodiment 1 is demonstrated. FIG. 3 is a schematic plan view showing the wiring board of the first embodiment in the IC chip mounting region and the vicinity thereof. FIG. 4 is a schematic perspective view of the wiring board and the attaching device of the first embodiment in the adhesive layer supplying step. Further, FIG. 5 is a schematic cross-sectional view of the semiconductor device of Embodiment 1 in the IC chip alignment process and the crimping process.

First, the wiring board 40 is produced by a conventional method. More specifically, after the wiring pattern 42 is formed on the substrate 41 by a subtractive method, an additive method or the like, the substrate 41 is covered by the printing method or the like so as to cover the wiring pattern 42 except for the IC chip mounting region. A wiring substrate 40 having terminal portions 43 is formed by applying a resist 45 to the substrate. Thus, the wiring board 40 is a printed wiring board.

The surface of the terminal portion 43 may be subjected to Ni plating and Au plating after the resist 45 is formed. Further, the wiring board 40 may be a flexible printed circuit board (FPC (Flexible Printed Circuit) board) or a PWB (Printed Wiring Board).

Next, a process of forming terminal bumps 44 is performed. More specifically, the terminal bumps 44 are formed on the terminal portions 43 as shown in FIG. 3 by, for example, wire bonding, etching using a mask, or plating (plating). At this time, the terminal bump 44 is formed at a position corresponding to the element bump 32 of the IC chip 31. In more detail, the etching using the mask means that a metal layer made of the constituent material of the terminal bump 44 is formed on the surface of the terminal portion 43 by plating or the like, and then a mask having a desired opening is formed on the metal layer. Forming and etching the metal layer. As the material of the terminal bump 44, Au, Sn, or solder is used. Since these materials are relatively soft compared to the material of the wiring pattern 42 (usually copper), they are easily deformed when the IC chip is subsequently pressed, and a gap is generated between the element bump 32 and the terminal bump 44. It can suppress more effectively. In addition, the shape of the terminal bump 44 before the IC chip press-bonding may be a substantially cubic body, a substantially cylindrical body, a substantially spherical body, a substantially elliptical sphere, etc. in addition to the substantially rectangular parallelepiped as shown in FIG.

Next, a mounting process of the passive element 21 is performed. More specifically, after applying cream solder to a connection terminal (not shown) for mounting the passive element 21 provided on the circuit board 20a by a screen printing method, a dispenser method or the like, the passive element 21 is mounted. Then, the passive element 21 is connected to the circuit board 20a by melting the solder in a reflow furnace at about 230 to 260 ° C.

Next, an adhesive layer supplying step and an IC chip (semiconductor element) mounting step are performed. More specifically, first, as shown in FIG. 4, the wiring board 40 on which the passive element 21 is mounted is positioned below the pressurizing part (crimping head) 51 of the film adhesive bonding apparatus 50. Arrange on stage 55. In addition, as the sticking apparatus 50, the ACF thermocompression bonding machine generally marketed can be used.

Next, an adhesive film 54 having a thickness of 100 to 130 μm having a two-layer structure of an NCF (Non-Conductive Film) 20 to 50 μm thick that functions as the adhesive layer 22 and a separator 80 μm thick that functions as a protective layer. Is sent from the supply reel 52 between the wiring board 40 and the pressure unit 51. A cutter 53 that cuts the NCF to a set dimension is disposed below the adhesive film 54 that travels between the supply reel 52 and the pressure unit 51. This cutter is set so as to cut only the NCF and not the separator.

The adhesive film 54 can be produced by applying a solution of a thermosetting resin such as an epoxy resin to the separator and drying the applied solution. As the separator, PET (polyethylene terephthalate) having a film thickness of 80 μm is used. Further, the adhesive layer material is not limited to a non-conductive material such as NCF, and may be an anisotropic conductive material such as ACF (Anisotropic Conductive Film). Furthermore, the adhesive layer material is not limited to a film, and may be a paste.

Next, the pressurizing unit 51 heated to 50 to 70 ° C. is lowered, and the adhesive film 54 is pressed against the wiring board 40 for 1 to 4 seconds at a pressure of 1 to 5 MPa, thereby transferring the NCF to the wiring board 40. At this time, NCF is about 60 ° C., but does not flow completely.

Next, an IC chip on which the element bumps 32 are formed is prepared. As the material of the element bump 32, Au, Sn, or solder is preferable similarly to the terminal bump 44. As a result, it is possible to more effectively suppress the occurrence of a gap between the element bump 32 and the terminal bump 44 during the subsequent IC chip press bonding. As described above, the material of the terminal bump 44 and the element bump 32 is preferably one of Au, Sn, and solder, respectively. In addition, the shape of the element bump 32 before the IC chip press bonding may be a substantially cubic body, a substantially cylindrical body, a substantially spherical body, a substantially elliptical sphere, or the like, in addition to the substantially rectangular parallelepiped as shown in FIG. The element bump 32 may be Au plated on the surface thereof.

Next, the IC chip 31 is crimped. More specifically, first, as shown in FIG. 5, alignment is performed so that the element bumps 32 and the terminal bumps 44 are in contact with each other. Next, the pressurizing part 51 heated to 180 to 250 ° C. is pressed at a pressure of 60 to 200 MPa for 5 to 20 seconds. At this time, the terminal portion 43 is curved as shown in FIG. 1A, but there is almost no gap between the element bump 32 and the terminal bump 44 due to the terminal bump 44. Therefore, the adhesive layer 22 is cured while the element bumps 32 and the terminal bumps 44 are in contact with each other over substantially the entire surface. As a result, the occurrence of contact failure can be effectively suppressed.

The semiconductor device 20 manufactured as described above is connected to the liquid crystal display panel 10 by ACF or the like, for example. Thus, the liquid crystal display device 100 of this embodiment can be manufactured easily.

In the present embodiment, the element bump 32 and the terminal bump 44 may be metal-bonded. In this case, the material of the element bump 32 and the terminal bump 44 is preferably Au and Sn, or a combination of Au and Au. In addition, when performing metal joining, what is necessary is just to press the IC chip 31 to the wiring board 40 with the pressure of 10-100 MPa for 2 to 5 seconds using the pressurization part 51 heated at 350-400 degreeC, for example.

In the present embodiment, an alloy layer may be formed between the element bump 32 and the terminal bump 44. The alloy species constituting the alloy layer is not particularly limited, and examples thereof include Au—Sn eutectic, Au / Sn alloy, Au / Sn ₂ alloy, Au / Sn ₄ alloy and the like. Thus, the alloy type constituting the alloy layer is preferably an alloy formed from the material of the element bump 32 and the terminal bump 44. In this case, the material of the element bump 32 and the terminal bump 44 is preferably a combination of Au and Sn. In the case of forming the alloy layer, for example, the IC chip 31 may be pressed against the wiring substrate 40 at a pressure of 60 to 200 MPa for 5 to 20 seconds using the pressurizing unit 51 heated to 180 ° C. or higher.

In this way, by connecting the element bump 32 and the terminal bump 44 by metal bonding and / or via an alloy layer, the element bump 32 and the terminal bump 44 can be fused and integrated at the atomic level. Therefore, the occurrence of connection failure can be more effectively suppressed.

Note that ultrasonic bonding may be used as a method for performing metal bonding. When forming an alloy layer, the IC chip 31 may be mechanically or ultrasonically vibrated when the IC chip 31 is crimped.

In the present embodiment, the element bump 32 may have a recess (unevenness) 33 on the surface of the terminal bump 44 as shown in FIG. Even in such a case, since the terminal bump 44 effectively fills the space inside the recess 33, occurrence of contact failure can be suppressed.

Furthermore, in this embodiment, the adhesive layer 22 may be formed by a post-coating method. However, in this case, since the element bump 32 and the terminal bump 44 need to be securely fixed when the IC chip is crimped, the material of the element bump and the terminal bump may be a combination of Au and Sn. preferable. In addition, as a crimping | compression-bonding condition at this time, what is necessary is just to use the pressurization part 51 heated to 180 degreeC or more, and to make the pressure 60-200 MPa for the press time 5-20 second.

In the manufacturing method described above, the mounting process of the IC chip 31 (semiconductor element) is performed after the mounting process of the passive element 21. However, the semiconductor element mounting process may be performed before the passive element mounting process. However, from the viewpoint of narrowing the distance between the semiconductor element and the passive element, an embodiment in which the semiconductor element mounting process is performed after the passive element mounting process is performed as described above. As a result, the distance between the semiconductor element and the passive element can be reduced to, for example, about 0.5 mm.

2A and 2B are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment, in which FIG. 1A illustrates an IC chip mounting region and the vicinity thereof, and FIG. 2B is an enlarged view illustrating a connection region vicinity of the IC chip and the wiring board. 2 is a schematic plan view of the liquid crystal display device of Embodiment 1. FIG. It is a plane schematic diagram which shows the wiring board of Embodiment 1 in an IC chip mounting area and its vicinity. It is a perspective schematic diagram of the wiring board and the sticking device of Embodiment 1 in the supplying process of the adhesive layer. It is a cross-sectional schematic diagram of the semiconductor device of Embodiment 1 in an IC chip alignment process and a crimping process. It is a cross-sectional schematic diagram which shows the modification of the semiconductor device of Embodiment 1 in the connection area | region vicinity of an IC chip and a wiring board. It is a cross-sectional schematic diagram showing a conventional semiconductor device, where (a) shows an IC chip mounting region and its vicinity, and (b) is an enlarged view showing the vicinity of the connection region of the IC chip and the wiring board.

Explanation of symbols

10: Liquid crystal display panel 11: Element substrate 12: Counter substrate 13: Driver IC
20, 120: Semiconductor device 21: Passive element 22, 122: Adhesive layer 31, 131: IC chip 32, 132: Element bump 33: Recess 40, 140: Wiring substrate 41, 141: Substrate 42, 142: Wiring pattern 43, 143: terminal portion 44: terminal bump 45, 145: resist 50: sticking device 51: pressurizing portion 52: supply reel 53: cutter 54: adhesive film 55: stage 100: liquid crystal display device 160: element bump and terminal portion Air gap (gap) between

Claims (10)

A semiconductor device having a structure in which a semiconductor element having an element bump is mounted on a wiring board in which a wiring pattern is formed on a substrate,
The wiring board has terminal bumps on the terminal portions of the wiring pattern,
The semiconductor device has a structure in which terminal bumps and element bumps are electrically connected. The semiconductor device according to claim 1, wherein the terminal bump includes gold and / or tin. The semiconductor device according to claim 1, wherein the element bump includes gold and / or tin. 2. The semiconductor device according to claim 1, wherein the terminal bump and the element bump are metal-bonded. 2. The semiconductor device according to claim 1, wherein the semiconductor device has an alloy layer between the terminal bump and the element bump. The semiconductor device according to claim 1, wherein the element bump has a recess on a surface on a terminal bump side. A method of manufacturing a semiconductor device having a structure in which a semiconductor element having an element bump is mounted on a wiring board having a wiring pattern formed on the substrate,
The manufacturing method includes a step of forming a terminal bump on a terminal portion of the wiring pattern;
A method of manufacturing a semiconductor device, comprising: a step of crimping a semiconductor element to a wiring board and electrically connecting a terminal bump and an element bump. The method of manufacturing a semiconductor device according to claim 7, wherein the element bump has a recess on a surface on a terminal bump side. A display device comprising the semiconductor device according to claim 1. 9. A display device comprising a semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 7 or 8.

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