JP2008035391A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus which can output video images of charge coupled devices (CCD) at a high speed, without any design change in the charge coupled devices. <P>SOLUTION: The apparatus includes a charge coupled device 3 (CCD3) and a control section 2 contained in a camera for controlling reading of the charge coupled device 3 (CCD3). By a transfer clock control by a transfer clock generating circuit (CG)22 in the control section 2 in the camera, picture elements of a vertical register 11 of the charge coupled device 3 (CCD3) are transferred before a horizontal register 12 of the charge coupled device 3 becomes empty, whereby partial reading of the horizontal register 12 can be performed. In this manner, output of video image in a screen area where an object does not exist can be avoided and video image output time can be reduced, which attains a high speed for video image output. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image pickup apparatus using a CCD as an image pickup element.

In an image pickup apparatus using a CCD as an image pickup element, pixel data for one screen is usually read for all pixel data for one line of the CCD. In a CCD digital camera applied to a predetermined specific purpose such as industrial use, observation purpose, monitoring purpose, etc., a high-speed video output is required depending on the purpose. As a conventional technique for realizing this, there is a method of cutting out partial data by post-processing after CCD pixel output to reduce the amount of data to be output. Although this video output speed-up method can increase the data transfer speed by reducing the amount of data to be output, it cannot increase the video output speed (pixel data output) of the CCD. Conventionally, as a technique for increasing the image output speed of the CCD, there is a technique in which a CCD horizontal register has a function of sweeping away unnecessary electrification. However, this technique involves a change in the design of the CCD itself and cannot be applied to commercially available CCDs that are currently popular.
Japanese Patent Laid-Open No. 11-112868 Japanese Patent Laid-Open No. 9-331483

  As described above, conventionally, there has been no effective technique for increasing the image output speed of a CCD for a commercially available CCD, which is currently in widespread use, without changing the design of the CCD itself.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an imaging apparatus capable of increasing the image output speed of a CCD without changing the design of the CCD itself.

  The present invention provides a CCD and control means for supplying a horizontal transfer clock to a horizontal register provided in the CCD, supplying a vertical transfer clock to a vertical register provided in the CCD, and reading imaging data from the CCD. In the imaging apparatus, the control means is configured to variably control the number of clocks of the horizontal transfer clock supplied to the horizontal register, with the number of clocks necessary for pixel transfer for one line of the CCD being the maximum number of clocks. Transfer clock supply means for supplying the vertical transfer clock to the vertical register in synchronization with the end of the variably controlled horizontal clock is provided.

  According to the imaging apparatus of the present invention, the image output speed of the CCD can be increased without changing the design of the CCD itself.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  An image pickup apparatus according to an embodiment of the present invention includes a CCD and a control unit for reading and controlling the CCD, and the horizontal register of the CCD is emptied (pixels for one line) by transfer clock control of the control unit. The horizontal register can be partially read by shifting the vertical register of the CCD before all the image is read out), thereby eliminating the video output of the screen area where no subject exists and outputting the video (pixel data output). ) Characterized by shortening the period and increasing the video output speed. Hereinafter, this imaging device is referred to as a CCD digital camera.

  1 and 2 are diagrams for explaining the outline of the CCD digital camera according to the embodiment of the present invention described above.

  FIG. 1 shows a CCD digital camera 1 according to an embodiment of the present invention and a subject (P) photographed by the CCD digital camera 1.

  FIG. 2 shows a video image and an output video image on the vertical register 11 when the subject P shown in FIG. 1 is photographed by the CCD digital camera 1 shown in FIG.

  As shown in FIG. 2, the CCD digital camera 1 includes a vertical register 11, a horizontal register 12, and an output buffer 13. Each of these components is an existing component that the CCD originally has.

  The imaging data on the vertical register 11 includes areas A and B where the subject (P) does not exist.

  In the video image 14 output from the output buffer 13, the pixel data (video signal) of the region B is overwritten (overwritten) on the region A, and the pixel data of the region B remains in the region A. Yes. This area is indicated by “A + B”. The area “A + B” in the video image 14 is generated by shifting the vertical register 11 before the horizontal register 12 becomes empty (all pixels for one line are read out).

  This region “A + B” is not a normal video image because charge addition is performed on the horizontal register 12. However, this area “A + B” is an area in which the subject (P) does not exist, and is an unnecessary area that is not necessary for outputting a video image externally.

  As shown in FIG. 2, the partial output of the horizontal register 12 by the transfer clock control for the vertical register 11 and the horizontal register 12 eliminates the video output (pixel output) of the screen area where the subject (P) does not exist. The video output (pixel data output) period can be shortened to increase the video output speed.

  3 and 4 show the configuration of the main part of the CCD digital camera 1 according to the above-described embodiment of the present invention.

  The CCD digital camera 1 according to the embodiment of the present invention is connected to an external control device 5 such as a personal computer and executes an imaging process under the control of the external control device 5. This external control device 5 is an instruction signal (reference numeral shown in FIG. 3) for designating the CCD digital camera 1 in an area where image output is not required (area B shown in FIG. 2) on the imaging screen of the CCD digital camera 1. CT reference) is output.

  The CCD digital camera 1 includes an in-camera control unit 2 that controls the inside of the camera, and a CCD 3 that constitutes an imaging device that is controlled and operated by the in-camera control unit 2.

  As shown in FIG. 2, the CCD 3 includes a vertical register (V-Reg) 11, a horizontal register (H-Reg) 12, and an output buffer 13.

  The vertical register 11 transfers (shifts) pixel data for one line to the horizontal register 12 by receiving a vertical transfer clock (V-CLK) from the in-camera control unit 2. The horizontal register 12 receives a horizontal transfer clock (H-CLK) from the in-camera control unit 2 and outputs pixel data to the output buffer 13 in units of pixels.

  The in-camera control unit 2 temporarily stores the imaging data output from the CCD 3, and a transfer clock supply for supplying the horizontal transfer clock (H-CLK) and the vertical transfer clock (V-CLK) to the CCD 3. A transfer clock generation circuit (CG) 22 serving as means.

  The transfer clock generation circuit (CG) 22 variably controls the number of clocks of the horizontal transfer clock (H-CLK) supplied to the horizontal register 12 with the maximum number of clocks required for pixel output of one line of the CCD 3 as the maximum clock number. The vertical transfer clock (V-CLK) is supplied to the vertical register 11 of the CCD 3 in synchronization with the end of the variably controlled horizontal transfer clock (H-CLK).

  The horizontal transfer clock (H-CLK) is a signal for transferring an image signal (pixel data) for one pixel from the horizontal register 12 to the output buffer 13, and the vertical transfer clock (V-CLK) is This is a signal for transferring (shifting) a video signal (pixel data) for one line from the vertical register 11 to the horizontal register 12.

  As shown in FIG. 4, the transfer clock generation circuit (CG) 22 includes an interface for inputting an instruction signal (CT) output from the external control device 5, and performs horizontal transfer according to the input instruction signal (CT). The number of clocks (H-CLK) is variably controlled. The horizontal transfer clock (H-CLK) variably controlled and the vertical transfer clock (V-CLK) output in synchronization with the end of the horizontal transfer clock (H-CLK) are sent to the horizontal register 12 of the CCD 3. On the other hand, partial readout with a shortened pixel output period is enabled.

  A transfer clock that can be generated by the transfer clock generation circuit (CG) 22 is illustrated in FIG.

  FIG. 5A shows a horizontal transfer clock (H-CLK) and a vertical transfer clock (H-CLK) and a vertical transfer clock (having the number of clocks necessary for pixel output for one line of the CCD 3 as well as an existing transfer clock ( V-CLK). FIG. 5B shows a horizontal transfer clock (H-CLK) and a vertical transfer clock (V-CLK) at transfer timing [TB], in which the number of horizontal transfer clocks is variably controlled in accordance with the instruction signal (CT). Yes.

  In the transfer clock variable control example shown in FIG. 5B, the horizontal transfer clock number at the transfer timing [TB] is set to about 2/3 of the horizontal transfer clock number at the transfer timing [TA].

  By controlling the vertical register 11 and the horizontal register 12 of the CCD 3 with the transfer clock at the transfer timing [TB], the video (pixels) in the area B shown in FIG. With this transfer control, video output (pixel output) corresponding to the number of overwritten pixels is omitted, and the video output (pixel data output) period is shortened.

  Examples of video output when the vertical register 11 and the horizontal register 12 of the CCD 3 are controlled by the transfer clock at the transfer timing [TB] are shown in time series (state transition) in FIGS.

  The operation timing shown in FIG. 6 indicates a state where the vertical transfer clock (V-CLK) has not yet been input to the CCD 3 (see the observation point). At this operation timing, the horizontal register 12 is still in an “empty” state (a state in which no video is accumulated in the horizontal register 12).

  The operation timing shown in FIG. 7 shows a state immediately after the vertical transfer clock (V-CLK) is input to the CCD 3 (see the observation point). At this operation timing, one line of video (pixels) is transferred from the vertical register 11 to the horizontal register 12.

  The operation timing shown in FIG. 8 shows a state where the vertical transfer clock (V-CLK) is input to the CCD 3 by the number of horizontal transfer clocks of the transfer timing [TB] (see the observation point). At this operation timing, a partial image of the subject (P) is output from the horizontal register 12 to the output buffer 21 via the output buffer 13.

  Also, at this operation timing, unlike the existing operation, the horizontal transfer clock (H-CLK) stops at this point, so that an extra video other than the subject (P) remains in the horizontal register 12.

  The operation timing shown in FIG. 9 shows a state immediately after the vertical transfer clock (V-CLK) is input to the CCD 3 again (see the observation point). At this operation timing, video (pixels) for the next one line is further transferred from the vertical register 11 to the horizontal register 12. Further, at this operation timing, a video overwriting portion (video overlapping region) 15 is formed in the horizontal register 12. In this video overlap area 15, video is overwritten also in the transfer operation associated with the subsequent vertical transfer clock (V-CLK). As a result, the video (pixels) in the area B shown in FIG. 2 is overwritten in the area A in units of one line, and the video output operation for the number of overwritten pixels is omitted. Pixel data output) period is shortened.

  With such a transfer control function according to the embodiment of the present invention, for example, when the necessary area (subject area) is ½ of the entire CCD imaging screen, the video output period is 3/4, and the necessary area (subject When the (region) is 1/3 of the entire CCD imaging screen, the video output period is shortened to 2/3, and the video output speed can be increased by the shortened operation time. Furthermore, the video output speed to the outside can be further increased by deleting the data of the video overlap area 15 on the output buffer 21 or when transferring the imaging data from the output buffer 21 to the external control device 5. .

  Increasing the video output speed by the transfer control function according to the above-described embodiment of the present invention can be realized only by changing the peripheral circuit of the CCD without changing the design of the CCD.

The figure which shows the state which image | photographs the to-be-photographed object for demonstrating the outline | summary of the imaging device which concerns on embodiment of this invention. The figure which shows the video image for demonstrating the outline | summary of the imaging device which concerns on the said embodiment. The block diagram which shows the structure of the principal part of the imaging device which concerns on the said embodiment. The block diagram which shows the structure of the principal part of the imaging device which concerns on the said embodiment. FIG. 6 is a diagram showing an example of transfer timing of horizontal and vertical transfer clocks of the imaging apparatus according to the embodiment. The figure which shows the state transition for demonstrating operation | movement of the imaging device which concerns on the said embodiment. The figure which shows the state transition for demonstrating operation | movement of the imaging device which concerns on the said embodiment. The figure which shows the state transition for demonstrating operation | movement of the imaging device which concerns on the said embodiment. The figure which shows the state transition for demonstrating operation | movement of the imaging device which concerns on the said embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... CCD digital camera, 2 ... In-camera control part, 3 ... CCD, 5 ... External control apparatus (personal computer), 11 ... Vertical register (V-Reg), 12 ... Horizontal register (H-Reg), 13 ... Output Buffer, 14 ... video image, 15 ... overlapped portion of video (video overlap region), 21 ... output buffer, 22 ... transfer clock generation circuit (CG), H-CLK ... horizontal transfer clock, V-CLK ... vertical transfer clock , CT: instruction signal.

Claims (3)

An imaging device comprising: a CCD; and a control means for supplying a horizontal transfer clock to a horizontal register provided in the CCD, supplying a vertical transfer clock to a vertical register provided in the CCD, and reading imaging data from the CCD. In the device
In the control means,
The number of clocks required for pixel output for one line of the CCD is set as the maximum number of clocks, and the number of horizontal transfer clocks supplied to the horizontal register is variably controlled, and synchronized with the end of the variably controlled horizontal clock. An imaging apparatus comprising transfer clock supply means for supplying a vertical transfer clock to the vertical register.   The transfer clock supply means variably controls the number of clocks of the horizontal transfer clock in accordance with an externally input signal that designates an area that does not require pixel output on the CCD imaging screen, and this variably controlled horizontal transfer The image pickup apparatus according to claim 1, wherein partial readout is performed with respect to the horizontal register by shortening a pixel output period by a clock.   The imaging apparatus according to claim 2, wherein the control unit includes a unit that excludes pixel data of an overwritten portion remaining in the horizontal register from a transfer target to the outside.

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