[go: up one dir, main page]

JP2008034694A - Passive element - Google Patents

Passive element Download PDF

Info

Publication number
JP2008034694A
JP2008034694A JP2006207867A JP2006207867A JP2008034694A JP 2008034694 A JP2008034694 A JP 2008034694A JP 2006207867 A JP2006207867 A JP 2006207867A JP 2006207867 A JP2006207867 A JP 2006207867A JP 2008034694 A JP2008034694 A JP 2008034694A
Authority
JP
Japan
Prior art keywords
film
passive element
resin
cover film
inorganic cover
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006207867A
Other languages
Japanese (ja)
Inventor
Koichi Takemura
浩一 竹村
Yasuhiro Ishii
康博 石井
Akinobu Shibuya
明信 渋谷
Toru Mori
透 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2006207867A priority Critical patent/JP2008034694A/en
Publication of JP2008034694A publication Critical patent/JP2008034694A/en
Withdrawn legal-status Critical Current

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a passive element, and a passive element integrated circuit device in which the characteristic fluctuation of an element or a circuit after manufacturing is prevented from occurring with an inexpensive and high performance thin film passive element formed on a main inter-layer insulating film with resin as main components or a thin film passive element integrated circuit. <P>SOLUTION: In a passive element configured by alternately laminating one or more wiring and organic inter-layer insulating films on a base substrate, and including one or more passive elements in the lamination structure and a passive element integrated circuit, an inorganic cover film is formed on an organic resin inter-layer insulating film covering the uppermost layer wiring, or on the uppermost wiring layer including one or more passive elements formed on the resin in-layer insulating film. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、受動素子、及び受動素子を包含したインターポーザ、半導体チップキャリア、配線基板、半導体集積回路装置に関する。   The present invention relates to a passive element, an interposer including the passive element, a semiconductor chip carrier, a wiring board, and a semiconductor integrated circuit device.

近年、デバイス動作の高周波化、高速化と同時に、携帯機器等では回路、部品の小型化、高集積化が強く要求されている。そこで、半導体プロセスや、それに類似した薄膜プロセスを用いた薄膜受動素子やそれらの集積化技術が研究されている。例えば、特許文献1では、Si基板上に形成された薄膜LCフィルターが開示されている。   In recent years, there has been a strong demand for miniaturization and high integration of circuits and components in portable devices and the like simultaneously with higher frequency and higher speed of device operation. Therefore, studies are being made on thin film passive elements using a semiconductor process, a thin film process similar to the semiconductor process, and an integration technique thereof. For example, Patent Document 1 discloses a thin film LC filter formed on a Si substrate.

また、特許文献2及び3では、薄膜受動素子を集積化した半導体接続用の基板が開示されている。いずれも、層間絶縁膜には、BCB(ベンゾシクロブテン)やポリイミドという樹脂を用いた構造となっている。これらの樹脂は低誘電率、低誘電損失な高周波特性に優れた絶縁体であり、簡単に塗布形成でき、感光性を付与することで容易にビア形成も可能な材料である。   Patent Documents 2 and 3 disclose a semiconductor connection substrate in which thin-film passive elements are integrated. In either case, the interlayer insulating film has a structure using a resin such as BCB (benzocyclobutene) or polyimide. These resins are insulators excellent in high-frequency characteristics with low dielectric constant and low dielectric loss, and can be easily applied and formed, and vias can be easily formed by imparting photosensitivity.

特許文献4では、キャパシタ内蔵フィルム状インターポーザが記載されている。キャパシタを作製するベース層及びキャパシタのカバー層ともにポリイミドなどの樹脂が用いられている。   In Patent Document 4, a film-like interposer with a built-in capacitor is described. Resin such as polyimide is used for both the base layer for manufacturing the capacitor and the cover layer of the capacitor.

更に、特許文献5、6では、半導体集積回路上への受動素子集積化技術が開示されている。半導体集積回路上では基板との電気的、磁気的結合による受動素子や受動素子集積回路の特性低下が問題となる。特許文献5では、受動素子のうち特に基板との結合が問題になるインダクタを最上層に配置してそのインダクタの上下の層間絶縁膜にはBCBを用いて問題を解決している。樹脂層間絶縁膜を用いない場合、特許文献6に記載されているように、基板との結合を遮断するためのシールド層を受動素子と基板との間に特別に設けた構造を採用することになる。   Furthermore, Patent Documents 5 and 6 disclose passive element integration techniques on a semiconductor integrated circuit. On the semiconductor integrated circuit, there is a problem that the characteristics of the passive element and the passive element integrated circuit are deteriorated due to electrical and magnetic coupling with the substrate. In Patent Document 5, an inductor that is particularly problematic in coupling with a substrate among passive elements is arranged in the uppermost layer, and the problem is solved by using BCB for interlayer insulating films above and below the inductor. When the resin interlayer insulating film is not used, as described in Patent Document 6, a structure in which a shield layer for blocking the coupling with the substrate is specially provided between the passive element and the substrate is adopted. Become.

特開平10−079469号公報Japanese Patent Application Laid-Open No. 10-079469 特開2000−124358号公報JP 2000-124358 A WO2003/007369号公報WO2003 / 007369 特開2002−083892号公報Japanese Patent Laid-Open No. 2002-083892 特開2002−141473号公報JP 2002-141473 A 特開2001−267320号公報JP 2001-267320 A

しかしながら、図6に示す従来技術の一例を含め、これら従来の薄膜受動素子や受動素子集積回路では、素子や基板形成後の素子特性変動のばらつきが大きく、所望の特性を安定して得られないことが問題であった。この原因は、素子や基板が置かれている雰囲気や、接続などの実装工程に起因する。その理由は必ずしも解明されていないが、受動素子を覆う樹脂層間絶縁膜が、柔らかく外部応力の影響を受けやすいこと、外部からの吸湿や内部からのガス放出が考えられる。   However, these conventional thin-film passive elements and passive element integrated circuits including the example of the prior art shown in FIG. 6 have a large variation in element characteristics after the elements and substrates are formed, and the desired characteristics cannot be stably obtained. That was the problem. This is caused by the atmosphere in which the elements and the substrate are placed and the mounting process such as connection. The reason is not necessarily elucidated, but the resin interlayer insulating film covering the passive element is soft and easily affected by external stress, and moisture absorption from outside and gas release from inside can be considered.

素子や基板形成後の環境において、層間絶縁膜である樹脂は外部から水分を吸収したり、吸収したりキュア時に完全に放出されなかった水分や各種ガスを内部から放出したりするので体積の膨張や収縮が発生する。これらの膨張、収縮により発生する応力や、実装工程などで受ける外部応力により、受動素子には様々な変形が発生する。このような変形により、容量素子であれば電極間隔が変わったり、抵抗素子であれば素子断面積や長さが変わったり、インダクタであれば配線間隔が変わったりするために、素子特性が作製直後の値から変化することになる。   In the environment after the device or substrate is formed, the resin that is the interlayer insulation film absorbs moisture from the outside, or absorbs moisture or releases from the inside moisture and various gases that were not completely released during curing. Shrinkage occurs. Various deformations occur in the passive element due to the stress generated by the expansion and contraction and the external stress received in the mounting process. Due to such deformation, the electrode characteristics change if it is a capacitive element, the cross-sectional area and length of the element change if it is a resistance element, and the wiring interval changes if it is an inductor. Will change from the value of.

変形の原因となる応力は、素子や基板が置かれている環境や、実装などの工程、素子や基板の構造などにより様々であり、そのために変動量をあらかじめ予測して設計することが困難であり、また変動量のばらつきも大きい。   The stress that causes deformation varies depending on the environment in which the element or board is placed, the process of mounting, the structure of the element or board, etc. There is also a large variation in variation.

樹脂ではなく無機絶縁膜を層間絶縁膜に使用すればこれらの課題は解決される可能性はあるが、樹脂より誘電率や誘電損失が大きくかつ厚く形成することが困難なために高周波特性に劣ること、層間膜形成工程が複雑になること、半導体基板上では特許文献6に記載のように結合を遮断する層を導入する必要があり一層作製工程が複雑になること、という問題がある。   If an inorganic insulating film instead of resin is used for the interlayer insulating film, these problems may be solved. However, since the dielectric constant and dielectric loss are larger than resin and it is difficult to form thicker, the high frequency characteristics are inferior. In addition, there are problems that the interlayer film forming process is complicated, and that a layer for blocking bonding needs to be introduced on the semiconductor substrate as described in Patent Document 6, and the manufacturing process is further complicated.

本発明の目的は、作製後に外部変動要因をうけにくく素子特性が安定するために信頼性が高く、しかも生産性に優れた受動素子、及び受動素子集積回路を提供することにある。   An object of the present invention is to provide a passive element and a passive element integrated circuit that are highly reliable and highly productive because the element characteristics are less likely to be affected by external variation after fabrication and the productivity is excellent.

本発明の第1の形態における受動素子、及び受動素子集積回路は、ベース基板上に1層以上の配線と層間絶縁膜が交互に積層され、その積層構造に1つ以上の受動素を内包した構造と、最上層配線を覆う樹脂を主たる成分とする樹脂層間絶縁膜と、該層間絶縁膜上に配置される無機カバー膜とを有する。   In the passive element and the passive element integrated circuit according to the first aspect of the present invention, one or more wirings and interlayer insulating films are alternately stacked on a base substrate, and one or more passive elements are included in the stacked structure. It has a structure, a resin interlayer insulating film whose main component is a resin covering the uppermost layer wiring, and an inorganic cover film disposed on the interlayer insulating film.

本発明の第2の形態における受動素子集積回路は、ベース基板の上に、1層以上の配線と層間絶縁膜が交互に積層され、その積層構造に1つ以上の受動素子を内包した構造と、樹脂を主たる成分とする樹脂層間絶縁膜上に形成され1つ以上の受動素子を含んだ最上配線層と、該最上配線層を覆う無機カバー膜とを有する。   The passive element integrated circuit according to the second aspect of the present invention has a structure in which one or more wirings and interlayer insulating films are alternately stacked on a base substrate, and one or more passive elements are included in the stacked structure. And an uppermost wiring layer including one or more passive elements formed on a resin interlayer insulating film containing resin as a main component, and an inorganic cover film covering the uppermost wiring layer.

本発明の第3の形態における受動素子、及び受動素子内蔵回路は、少なくとも1つの薄膜受動素子を内包した樹脂フィルムにおいて、その受動素子を覆う樹脂層の上下外側に無機カバー膜を有する。   The passive element and the passive element built-in circuit according to the third embodiment of the present invention have an inorganic cover film on the upper and lower sides of the resin layer covering the passive element in a resin film including at least one thin film passive element.

これらの発明における無機カバー膜は、シリコン酸化膜、シリコン窒化膜、酸化アルミニウム、窒化アルミニウム、高融点金属の酸化物、高融点金属の窒化膜、高融点金属の少なくともいずれか1つを主たる成分とすることが望ましい。   The inorganic cover film in these inventions is mainly composed of at least one of silicon oxide film, silicon nitride film, aluminum oxide, aluminum nitride, refractory metal oxide, refractory metal nitride film, and refractory metal. It is desirable to do.

本発明のこれらの実施形態において、前記無機カバー膜上に有機樹脂カバー膜を有することが望ましい。更に本発明の別の実施形態として、前記無機カバー膜が、下層の樹脂層間絶縁膜の側面を覆う構造とすることが望ましい。   In these embodiments of the present invention, it is desirable to have an organic resin cover film on the inorganic cover film. Furthermore, as another embodiment of the present invention, it is desirable that the inorganic cover film has a structure that covers the side surface of the lower resin interlayer insulating film.

受動素子を内蔵した回路全体を、外部応力や外部環境からの吸湿や内部からのガス放出のバリアとして機能する無機カバー層やベース基板で覆うことで、回路形成後の樹脂層間絶縁膜の膨張や収縮による受動素子の変形が抑制され、受動素子、受動素子集積回路の特性変動がない信頼性高い受動素子や受動素子集積回路を提供することができる。   By covering the entire circuit containing passive elements with an inorganic cover layer or base substrate that functions as a barrier against external stress, moisture absorption from the external environment, and gas release from the inside, expansion of the resin interlayer insulation film after circuit formation and It is possible to provide a highly reliable passive element or passive element integrated circuit in which the deformation of the passive element due to the contraction is suppressed, and the characteristics of the passive element and the passive element integrated circuit are not changed.

無機カバー膜が、外部応力から内部の樹脂層間絶縁膜の変形を妨げると同時に、環境からの吸湿や内部からのガス放出のバリアとして働くのでそれによる樹脂層間絶縁膜の膨張や収縮も抑制される。   The inorganic cover film prevents deformation of the internal resin interlayer insulation film from external stress, and at the same time acts as a barrier against moisture absorption from the environment and gas release from the interior, thereby suppressing expansion and contraction of the resin interlayer insulation film. .

次に、本発明の実施の形態について図面を参照して詳細に説明する。図1は本発明の第1の実施形態として、GaAs基板上に形成された受動素子集積回路の断面図を示す。シリコン酸化膜でカバーされたGaAs基板112上に、下部電極107と誘電体108と上部電極109とで構成されたMIMキャパシタ110、抵抗106、インダクタ105が3次元的に形成されている。最上配線層104にはインダクタ105が形成されており、樹脂絶縁膜101で覆われている。さらに、その樹脂絶縁膜101の上に無機カバー膜102が形成されている。この無機カバー膜102が回路全体を覆うことで、表面側から樹脂絶縁膜101の吸湿や表面側へのガス放出を抑制する。   Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a sectional view of a passive element integrated circuit formed on a GaAs substrate as a first embodiment of the present invention. On a GaAs substrate 112 covered with a silicon oxide film, a MIM capacitor 110, a resistor 106, and an inductor 105, each including a lower electrode 107, a dielectric 108, and an upper electrode 109, are formed in a three-dimensional manner. An inductor 105 is formed on the uppermost wiring layer 104 and is covered with a resin insulating film 101. Further, an inorganic cover film 102 is formed on the resin insulating film 101. The inorganic cover film 102 covers the entire circuit, thereby suppressing moisture absorption of the resin insulating film 101 from the surface side and gas release to the surface side.

また、実装工程での外部応力による下層の樹脂絶縁膜101の変形も抑制する。受動素子集積回路裏面側は、GaAs基板112やその上に形成されたシリコン窒化膜111が表面側の無機カバー層102と同じ役割を担うことになる。従って、回路形成後には、樹脂絶縁膜101に変形を生じることなく、内蔵された受動素子の特性変動を抑制できる。   Further, deformation of the lower resin insulating film 101 due to external stress in the mounting process is also suppressed. On the back side of the passive element integrated circuit, the GaAs substrate 112 and the silicon nitride film 111 formed thereon play the same role as the inorganic cover layer 102 on the front side. Therefore, after the circuit is formed, fluctuations in the characteristics of the built-in passive element can be suppressed without causing deformation of the resin insulating film 101.

本実施形態では、従来の回路の製造方法に、無機カバー膜形成工程を追加するだけでよく、容易に作製できることが特徴である。   The present embodiment is characterized in that it can be easily manufactured by adding an inorganic cover film forming step to the conventional circuit manufacturing method.

図1の無機カバー膜102は、シリコン酸化膜、シリコン窒化膜、酸化アルミニウム、窒化アルミニウム、高融点金属の酸化物、高融点金属の窒化膜、高融点金属の少なくともいずれか1つを主たる成分とすることが望ましい。これらの材料は、水分や各種ガスに対するバリア性の優れると同時に、硬く強度に優れるために外部応力に対するバリア層としても機能する。更に、CVD法(化学的気相成長法)やスパッタリング法で容易に低温で形成することが可能であり、実用性に優れる。   The inorganic cover film 102 in FIG. 1 includes a main component of at least one of a silicon oxide film, a silicon nitride film, aluminum oxide, aluminum nitride, a refractory metal oxide, a refractory metal nitride film, and a refractory metal. It is desirable to do. These materials have excellent barrier properties against moisture and various gases, and at the same time function as a barrier layer against external stress because they are hard and excellent in strength. Furthermore, it can be easily formed at a low temperature by a CVD method (chemical vapor deposition method) or a sputtering method, and is excellent in practicality.

図1において導電性の無機カバー膜102を適用する場合には、必要に応じて外部接続パッドとの絶縁を取る必要があるが、ノイズに対するシールド層としての役割を担うことも可能である。このとき、シールド層の電気抵抗を下げるために、無機カバー膜102に金や銅などの低抵抗金属を積層するとより効果的である。   In the case where the conductive inorganic cover film 102 is applied in FIG. 1, it is necessary to insulate the external connection pad as necessary, but it can also serve as a shield layer against noise. At this time, in order to lower the electrical resistance of the shield layer, it is more effective to stack a low resistance metal such as gold or copper on the inorganic cover film 102.

図1では、無機カバー膜102上に更に有機カバー膜103が形成されている。これは、受動素子集積回路と他のデバイスとを接続する際の応力緩和層として機能し、内部の有機樹脂絶縁層101への外部応力のバリア効果を一層向上させると同時に、半田接続部の信頼性も向上できるという利点がある。   In FIG. 1, an organic cover film 103 is further formed on the inorganic cover film 102. This functions as a stress relaxation layer when connecting the passive element integrated circuit and other devices, further improving the barrier effect of external stress on the internal organic resin insulating layer 101, and at the same time, reliability of the solder connection portion. There is an advantage that the performance can be improved.

図2は本発明の第2の実施形態として、ガラス基板208上に形成された受動素子集積回路の断面図を示す。ガラス基板208上にインダクタ205が形成されており、層間絶縁膜として樹脂絶縁膜201が形成された上に抵抗206が形成された最上配線層204が形成されている。層間絶縁膜を利用してキャパシタ207も形成されている。最上配線層204は無機カバー膜202で覆われている。本実施形態においても、無機カバー膜202が回路全体を覆うことで、表面側から樹脂絶縁膜201の吸湿や表面側へのガス放出を抑制する。   FIG. 2 shows a sectional view of a passive element integrated circuit formed on a glass substrate 208 as a second embodiment of the present invention. An inductor 205 is formed on a glass substrate 208, and an uppermost wiring layer 204 in which a resistor 206 is formed on a resin insulating film 201 as an interlayer insulating film is formed. A capacitor 207 is also formed using the interlayer insulating film. The uppermost wiring layer 204 is covered with an inorganic cover film 202. Also in this embodiment, the inorganic cover film 202 covers the entire circuit, thereby suppressing moisture absorption of the resin insulating film 201 from the surface side and gas release to the surface side.

また、実装工程での外部応力による下層の樹脂絶縁膜201の変形も抑制する。受動素子集積回路裏面側は、ガラス基板が無機カバー膜202と同様の機能を果たす。本実施形態では、絶縁基板を用いてインダクタ205を最上層以外へ配置できる回路構成が可能な場合、配線上に直接無機カバー膜202を形成できるので、工程が簡略化でき生産性が向上するという利点を有する。   In addition, deformation of the lower resin insulating film 201 due to external stress in the mounting process is also suppressed. On the back side of the passive element integrated circuit, the glass substrate performs the same function as the inorganic cover film 202. In the present embodiment, when a circuit configuration in which the inductor 205 can be disposed on a layer other than the uppermost layer using an insulating substrate is possible, the inorganic cover film 202 can be formed directly on the wiring, which simplifies the process and improves productivity. Have advantages.

図2において、無機カバー膜202は、配線と接する部分は絶縁性でなくてはならない。シリコン酸化膜、シリコン窒化膜、酸化アルミニウム、窒化アルミニウム、絶縁性の高融点金属の酸化物、絶縁性の高融点金属の窒化膜の少なくともいずれか1つを主たる成分とすることが望ましい。これらの材料は、水分や各種ガスに対するバリア性の優れると同時に、硬く強度に優れるために外部応力に対するバリア層としても機能する。更に、CVD法(化学的気相成長法)やスパッタリング法で容易に低温で形成することが可能であり、実用性に優れる。   In FIG. 2, the portion of the inorganic cover film 202 that contacts the wiring must be insulative. It is desirable that at least one of a silicon oxide film, a silicon nitride film, aluminum oxide, aluminum nitride, an insulating refractory metal oxide, and an insulating refractory metal nitride film be a main component. These materials have excellent barrier properties against moisture and various gases, and at the same time function as a barrier layer against external stress because they are hard and excellent in strength. Furthermore, it can be easily formed at a low temperature by a CVD method (chemical vapor deposition method) or a sputtering method, and is excellent in practicality.

図1、図2ともに、基板はシリコン、GaAs、GaNなどの半導体、金属、ガラス、セラミックスが望ましい。半導体基板は能動素子を形成した上に、本発明による受動素子集積回路を形成することも可能であり、その場合には一層の高集積化が期待できる。金属基板は他の基板材料よりも、一般的に、安価であることや、割れにくく取り扱いが容易であることなどの利点がある。   1 and 2, the substrate is preferably a semiconductor such as silicon, GaAs, or GaN, metal, glass, or ceramic. In addition to forming active elements on the semiconductor substrate, it is also possible to form a passive element integrated circuit according to the present invention. In that case, higher integration can be expected. Metal substrates are generally more advantageous than other substrate materials in that they are inexpensive and are difficult to break and easy to handle.

更に、金属基板は他の基板材料よりも、一般的に、熱伝導性がよいので、半導体集積回路を搭載した際に冷却効率を高くできる点が優れている。ガラス基板は安価で表面平坦性や絶縁性に優れ、高周波回路の形成に適している。セラミックス基板は、それ自身にも受動素子を内蔵することが可能であることや、基板内部を通り基板表面と基板裏面とを結ぶ配線形成が容易であることとから、一層の回路の高集積化やモジュール部品化に適している。   Furthermore, since the metal substrate generally has better thermal conductivity than other substrate materials, it is excellent in that the cooling efficiency can be increased when a semiconductor integrated circuit is mounted. A glass substrate is inexpensive and excellent in surface flatness and insulation, and is suitable for forming a high-frequency circuit. The ceramic substrate itself can contain passive elements, and because it is easy to form wiring that passes through the substrate and connects the substrate surface and the back surface of the substrate, higher circuit integration is achieved. And suitable for modular parts.

図3は本発明の第3の実施形態として、フィルム状キャパシタの断面図を示す。裏面に無機カバー膜303が形成された有機ベース膜302上に、下部電極306と誘電体307と上部電極308とで構成されたMIMキャパシタ309が形成され、その上に層間絶縁膜として樹脂絶縁膜301、更に無機カバー膜303、接続パッド305、有機カバー膜304の順で形成されている。受動素子の上下を無機カバー膜303が覆う構造とすることで、樹脂絶縁膜301の吸湿や表面側へのガス放出、更には実装工程での外部応力による下層の樹脂絶縁膜301の変形も抑制する。フィルム状素子は、基板上に作製した素子と比較して、厚さが薄く、装置全体の薄型化や、プリント基板などへ内蔵する素子として優れている。実質的に無機カバー膜303で表面と裏面を覆う構造にすることで、ベース基板がなくても第1及び第2の実施形態と同様な効果を得ることができる。   FIG. 3 shows a cross-sectional view of a film capacitor as a third embodiment of the present invention. A MIM capacitor 309 composed of a lower electrode 306, a dielectric 307, and an upper electrode 308 is formed on an organic base film 302 having an inorganic cover film 303 formed on the back surface, and a resin insulating film as an interlayer insulating film thereon. 301, an inorganic cover film 303, a connection pad 305, and an organic cover film 304 are formed in this order. By adopting a structure in which the inorganic cover film 303 covers the upper and lower sides of the passive element, moisture absorption of the resin insulating film 301, gas release to the surface side, and further deformation of the lower resin insulating film 301 due to external stress in the mounting process are suppressed. To do. A film-like element is thinner than an element produced on a substrate, and is excellent as an element incorporated in a printed circuit board or the like as a whole device is thinned. By substantially covering the front and back surfaces with the inorganic cover film 303, the same effects as those of the first and second embodiments can be obtained without a base substrate.

外部環境との接触面積が大きい素子表面、及び裏面に、無機カバー膜303やベース基板が配置されることで、素子形成後の特性変動を抑制することが可能となるが、素子側面も無機カバー膜303で覆うことで一層の効果がある。   By arranging the inorganic cover film 303 and the base substrate on the element front and back surfaces having a large contact area with the external environment, it is possible to suppress the characteristic fluctuation after the element formation, but the element side surface is also covered with the inorganic cover. A further effect is obtained by covering with the film 303.

図4は、その実施形態の説明として、ガラス基板407上に形成した受動素子集積回路の個片化前の状態の断面図を示す。ガラス基板407上に複数の受動素子集積回路408〜410をビルドアップで形成するときに、樹脂絶縁膜401をスピンコート法で基板全面に塗布し、ビア形成のリソグラフィーで各回路の境界部分も樹脂絶縁膜401を除去しておく。そして、無機カバー膜402を形成すれば、回路表面だけではなく、側面も無機カバー膜402で覆われた構造とすることができる。   FIG. 4 shows a cross-sectional view of a passive element integrated circuit formed on a glass substrate 407 before separation as an explanation of the embodiment. When a plurality of passive element integrated circuits 408 to 410 are formed on a glass substrate 407 by build-up, a resin insulating film 401 is applied to the entire surface of the substrate by a spin coat method, and a boundary portion of each circuit is also resin by via formation lithography. The insulating film 401 is removed. If the inorganic cover film 402 is formed, not only the circuit surface but also the side surface can be covered with the inorganic cover film 402.

図4では、更に無機カバー膜402、その上層の有機カバー膜403も既に形成された内側の樹脂絶縁膜401より大きな形状で回路ごとに分離している。このような構造にすることで、ダイシングライン411、412でダイシングして個片化する際にダイシングブレードがガラス基板のみを切断することになり、無機カバー膜402へクラックが入ったり剥離したりすることを防止できるという利点がある。素子側面も無機カバー膜402で覆う効果は、第2、第3の実施形態においても同様である。   In FIG. 4, the inorganic cover film 402 and the upper organic cover film 403 are also separated for each circuit in a shape larger than the already formed inner resin insulating film 401. With this structure, the dicing blade cuts only the glass substrate when dicing into individual pieces by dicing lines 411 and 412, and the inorganic cover film 402 is cracked or peeled off. There is an advantage that can be prevented. The effect of covering the element side surface with the inorganic cover film 402 is the same in the second and third embodiments.

図5は本発明の第5の実施形態として、シリコン基板上へ形成した受動素子集積回路の断面図を示す。本実施形態では、最下層の受動素子はシリコン熱酸化膜502、シリコン酸化膜501の層間絶縁膜で覆われている。このように、層間絶縁膜の一部が無機絶縁膜である場合、無機絶縁膜で覆われた受動素子は作製工程途中での特性変動も抑制することができるという利点がある。特に、抵抗体や誘電体が樹脂絶縁膜のキュア時に発生する水分の影響を受けやすい材料の場合に効果が大きい。この場合も、インダクタ105は低誘電率、低損失な樹脂絶縁膜101で覆われているとインダクタ105の特性を損ねることがなく、無機カバー膜102で覆うことで作製後のインダクタ105を含んだ配線の特性変動を抑制することが可能となる。   FIG. 5 shows a sectional view of a passive element integrated circuit formed on a silicon substrate as a fifth embodiment of the present invention. In the present embodiment, the lowermost passive element is covered with an interlayer insulating film of a silicon thermal oxide film 502 and a silicon oxide film 501. As described above, when a part of the interlayer insulating film is an inorganic insulating film, the passive element covered with the inorganic insulating film has an advantage that the characteristic variation during the manufacturing process can be suppressed. In particular, the effect is great when the resistor or the dielectric is a material that is easily affected by moisture generated when the resin insulating film is cured. Also in this case, if the inductor 105 is covered with the resin insulating film 101 having a low dielectric constant and low loss, the characteristics of the inductor 105 are not impaired. It is possible to suppress fluctuations in wiring characteristics.

尚、本発明は受動素子単体として用いられるほかに、デカップリング、フィルターなどの機能回路素子や、それらを内包した半導体チップキャリア、モジュール基板、インターポーザ、半導体集積回路装置に使用される。   In addition to being used as a passive element alone, the present invention is used for functional circuit elements such as decoupling and filters, and semiconductor chip carriers, module substrates, interposers, and semiconductor integrated circuit devices that contain them.

本発明の第1の実施形態を示す断面図。Sectional drawing which shows the 1st Embodiment of this invention. 本発明の第2の実施形態を示す断面図。Sectional drawing which shows the 2nd Embodiment of this invention. 本発明の第3の実施形態を示す断面図。Sectional drawing which shows the 3rd Embodiment of this invention. 本発明の第4の実施形態を示す断面図。Sectional drawing which shows the 4th Embodiment of this invention. 本発明の第5の実施形態を示す断面図。Sectional drawing which shows the 5th Embodiment of this invention. 従来の受動素子内蔵回路の形態を示す断面図。Sectional drawing which shows the form of the conventional passive element built-in circuit.

符号の説明Explanation of symbols

101 有機樹脂絶縁膜
102 無機カバー膜
103 有機カバー膜
104 配線
105 インダクタ
106 抵抗
107 下部電極
108 誘電体
109 上部電極
110 MIMキャパシタ
111 シリコン窒化膜
112 GaAs基板
113 半導体集積回路装置
201 有機樹脂絶縁膜
202 無機カバー膜
203 有機カバー膜
204 配線
205 インダクタ
206 抵抗
207 キャパシタ
208 ガラス基板
209 半導体集積回路装置
301 有機樹脂絶縁膜
302 有機ベース膜
303 無機カバー膜
304 有機カバー膜
305 接続パッド
306 下部電極
307 誘電体
308 上部電極
309 MIMキャパシタ
401 有機樹脂絶縁膜
402 無機カバー膜
403 有機カバー膜
404 配線
405 インダクタ
406 キャパシタ
407 ガラス基板
408〜410 受動素子内蔵回路
411、412 ダイシングライン
501 シリコン酸化膜
502 シリコン熱酸化膜
DESCRIPTION OF SYMBOLS 101 Organic resin insulating film 102 Inorganic cover film 103 Organic cover film 104 Wiring 105 Inductor 106 Resistance 107 Lower electrode 108 Dielectric 109 Upper electrode 110 MIM capacitor 111 Silicon nitride film 112 GaAs substrate 113 Semiconductor integrated circuit device 201 Organic resin insulating film 202 Inorganic Cover film 203 Organic cover film 204 Wiring 205 Inductor 206 Resistance 207 Capacitor 208 Glass substrate 209 Semiconductor integrated circuit device 301 Organic resin insulating film 302 Organic base film 303 Inorganic cover film 304 Organic cover film 305 Connection pad 306 Lower electrode 307 Dielectric 308 Upper part Electrode 309 MIM capacitor 401 Organic resin insulating film 402 Inorganic cover film 403 Organic cover film 404 Wiring 405 Inductor 406 Capacitor 407 Glass substrate 408 to 410 In passive element Warehouse circuits 411, 412 Dicing line 501 Silicon oxide film 502 Silicon thermal oxide film

Claims (10)

ベース基板上に、1層以上の配線と層間絶縁膜が交互に積層され、その積層構造に1つ以上の受動素子を内包した構造と、最上層配線を覆う樹脂を主たる成分とする樹脂層間絶縁膜と、該層間絶縁膜上に配置される無機カバー膜とを有することを特徴とする受動素子。 On the base substrate, one or more layers of wiring and interlayer insulating films are alternately stacked, and the structure in which one or more passive elements are included in the stacked structure and the resin interlayer insulation mainly composed of resin covering the uppermost layer wiring A passive element having a film and an inorganic cover film disposed on the interlayer insulating film. 前記無機カバー膜は、シリコン酸化膜、シリコン窒化膜、酸化アルミニウム、窒化アルミニウム、高融点金属の酸化物、高融点金属の窒化膜、高融点金属の少なくともいずれか1つを主たる成分とすることを特徴とする請求項1記載の受動素子。 The inorganic cover film is mainly composed of at least one of silicon oxide film, silicon nitride film, aluminum oxide, aluminum nitride, refractory metal oxide, refractory metal nitride film, and refractory metal. The passive element according to claim 1, wherein: ベース基板の上に、1層以上の配線と層間絶縁膜が交互に積層され、その積層構造に1つ以上の受動素子を内包した構造と、樹脂を主たる成分とする樹脂層間絶縁膜上に形成され1つ以上の受動素子を含んだ最上配線層と、該最上配線層を覆う無機カバー膜とを有することを特徴とする受動素子。 On the base substrate, one or more layers of wiring and interlayer insulating film are alternately stacked, and the stacked structure includes one or more passive elements and a resin interlayer insulating film containing resin as the main component. A passive element comprising: an uppermost wiring layer including at least one passive element; and an inorganic cover film covering the uppermost wiring layer. 前記無機カバー膜は、シリコン酸化膜、シリコン窒化膜、酸化アルミニウム、窒化アルミニウム、絶縁性の高融点金属の酸化物、絶縁性の高融点金属の窒化物の少なくとも1つを主たる成分とすることを特徴とする請求項3記載の受動素子。 The inorganic cover film includes at least one of a silicon oxide film, a silicon nitride film, aluminum oxide, aluminum nitride, an insulating refractory metal oxide, and an insulating refractory metal nitride as a main component. 4. The passive element according to claim 3, wherein 前記無機カバー膜が、下層の樹脂層間絶縁膜の側面を覆うことを特徴とする請求項1から4に記載の受動素子。 The passive element according to claim 1, wherein the inorganic cover film covers a side surface of a lower resin interlayer insulating film. 前記無機カバー膜上に樹脂カバー膜を有することを特徴とする請求項1から5に記載の受動素子。 6. The passive element according to claim 1, further comprising a resin cover film on the inorganic cover film. 前記ベース基板が、半導体、金属、ガラス、セラミックスのいずれかであることを特徴とする請求項1から6に記載の受動素子。 The passive element according to claim 1, wherein the base substrate is any one of a semiconductor, a metal, glass, and ceramics. 少なくとも1つの薄膜受動素子を内包した樹脂フィルムにおいて、その受動素子を覆う樹脂層の上下外側に、無機カバー膜を有することを特徴とする受動素子。 A passive element comprising a resin film including at least one thin-film passive element, wherein an inorganic cover film is provided on the upper and lower outer sides of the resin layer covering the passive element. 前記無機カバー膜は、シリコン酸化膜、シリコン窒化膜、酸化アルミニウム、窒化アルミニウム、高融点金属の酸化物、高融点金属の窒化膜、高融点金属の少なくともいずれか1つを主たる成分とすることを特徴とする請求項8記載の受動素子。 The inorganic cover film is mainly composed of at least one of silicon oxide film, silicon nitride film, aluminum oxide, aluminum nitride, refractory metal oxide, refractory metal nitride film, and refractory metal. 9. The passive element according to claim 8, wherein 前記無機カバー膜上の少なくとも接続端子を配置した側に、有機樹脂カバー膜を有することを特徴とする請求項8及び9に記載の受動素子。
10. The passive element according to claim 8, further comprising an organic resin cover film on a side of the inorganic cover film on which the connection terminal is disposed.
JP2006207867A 2006-07-31 2006-07-31 Passive element Withdrawn JP2008034694A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006207867A JP2008034694A (en) 2006-07-31 2006-07-31 Passive element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006207867A JP2008034694A (en) 2006-07-31 2006-07-31 Passive element

Publications (1)

Publication Number Publication Date
JP2008034694A true JP2008034694A (en) 2008-02-14

Family

ID=39123798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006207867A Withdrawn JP2008034694A (en) 2006-07-31 2006-07-31 Passive element

Country Status (1)

Country Link
JP (1) JP2008034694A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019197791A (en) * 2018-05-09 2019-11-14 凸版印刷株式会社 Capacitor built-in glass substrate and capacitor built-in circuit substrate
CN112103284A (en) * 2019-06-17 2020-12-18 罗姆股份有限公司 Chip component
US11862588B2 (en) 2021-01-14 2024-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
JP2024010101A (en) * 2018-04-24 2024-01-23 ウルフスピード インコーポレイテッド Packaged electronic circuit with moisture protection encapsulation and method of forming the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024010101A (en) * 2018-04-24 2024-01-23 ウルフスピード インコーポレイテッド Packaged electronic circuit with moisture protection encapsulation and method of forming the same
JP7706519B2 (en) 2018-04-24 2025-07-11 マコム テクノロジー ソリューションズ ホールディングス, インコーポレイテッド Packaged electronic circuit having moisture-protective encapsulation and method of forming same
JP2019197791A (en) * 2018-05-09 2019-11-14 凸版印刷株式会社 Capacitor built-in glass substrate and capacitor built-in circuit substrate
CN112103284A (en) * 2019-06-17 2020-12-18 罗姆股份有限公司 Chip component
JP2020205342A (en) * 2019-06-17 2020-12-24 ローム株式会社 Chip component
JP7323343B2 (en) 2019-06-17 2023-08-08 ローム株式会社 chip parts
CN112103284B (en) * 2019-06-17 2024-01-05 罗姆股份有限公司 Chip components
US11862588B2 (en) 2021-01-14 2024-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US12368120B2 (en) 2021-01-14 2025-07-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method

Similar Documents

Publication Publication Date Title
US7176556B2 (en) Semiconductor system-in-package
JP5093327B2 (en) Thin film capacitor
JP3843708B2 (en) Semiconductor device, manufacturing method thereof, and thin film capacitor
JP5576334B2 (en) Semiconductor device, wiring board and manufacturing method thereof
US7923302B2 (en) Method for manufacturing a semiconductor package
WO2004047167A1 (en) Semiconductor device, wiring substrate, and method for manufacturing wiring substrate
KR102423309B1 (en) Semiconductor device, imaging device, and manufacturing method of semiconductor device
JP2003338541A (en) Semiconductor device
US7319271B2 (en) Semiconductor device
TWI651741B (en) Semiconductor device with capacitor
US11800635B2 (en) Integrated passive component
JP2008034694A (en) Passive element
JP2011253898A (en) Semiconductor device and method for manufacturing semiconductor device
US20060269753A1 (en) Creamic substrate and production method thereof
JP4844392B2 (en) Semiconductor device and wiring board
US20050272252A1 (en) Circuit device
US20100176515A1 (en) Contact pad supporting structure and integrated circuit
JP2007294746A (en) Semiconductor package and semiconductor package manufacturing method
JP4864313B2 (en) Thin film capacitor substrate, manufacturing method thereof, and semiconductor device
JP2011066331A (en) Mounting substrate and method of manufacturing the same, and electronic apparatus
JP2003347157A (en) Thin-film electronic components
KR102819094B1 (en) Glass substrate and multi-layered wiring substrate including the same
JP4578254B2 (en) Multilayer wiring board
JPWO2007029445A1 (en) Capacitor-mounted semiconductor device
JP3565872B2 (en) Thin film multilayer wiring board

Legal Events

Date Code Title Description
RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20080616

A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20091006