JP2008032919A - Semiconductor integrated circuit - Google Patents

Abstract

In a semiconductor integrated circuit for driving a liquid crystal display panel with a built-in TFT, power consumption in a power supply circuit is further reduced in the case of binary display.
The semiconductor integrated circuit is supplied with first to third power supply potentials in a normal display mode, and converts image data into a plurality of gradation voltages by a plurality of digital / analog converters. Are supplied to the sources of the plurality of thin film transistors by amplifying the grayscale voltages of the plurality of operational amplifier circuits. In the binary display mode, the fourth power supply potential is supplied, and the sources of the respective thin film transistors are supplied based on the image data. Driving circuit for selectively supplying one of the fourth power supply potential and the ground potential, a common potential generation circuit for generating a common potential, and driving the first to third power supply potentials in the normal display mode. And a power supply circuit for supplying a fourth power supply potential to the driver circuit in the binary display mode.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit for driving a liquid crystal display panel including a plurality of thin film transistors (TFTs).

  Liquid crystal display panels are often used in portable terminals such as portable telephones and PDAs (Personal Digital Assistance) that have been widely used in recent years. In addition, a portable terminal includes a semiconductor integrated circuit (liquid crystal driver IC) that includes a drive circuit for driving a display panel and a power supply circuit for supplying a plurality of types of power to the drive circuit. Such a semiconductor integrated circuit is required to reduce power consumption and circuit size. For example, the following techniques are known for reducing power consumption.

  As one technique for reducing power consumption, a partial display technique used in a mobile phone or the like is known. In the partial display, only a selected area is driven and displayed on the display panel. In the case of partial display, since an unnecessary area is not driven, power consumption can be reduced.

  As another technique for reducing power consumption, a binary display technique is known. In the binary display, each of R (red), G (green), and B (blue) in an RGB image signal is expressed by binary values (two kinds of gradations) compared to normal full color display, and eight colors are displayed. Display. Such a binary display technique may be realized in combination with a partial display technique.

  Generally, a power supply circuit built in a liquid crystal driver IC includes a power supply circuit that generates a plurality of types of power supply potentials supplied to a drive circuit that drives a display panel based on a single power supply voltage supplied from the outside. It is out. Various technologies have been developed to reduce power consumption in power supply circuits as well as power consumption in drive circuits by partial display technology or binary display technology.

  As a related technique, the following Patent Document 1 discloses a clock from a pulse generation source based on a control pulse provided from a partial mode control circuit in a power saving mode in a power supply circuit using a charge pump type power supply voltage conversion circuit. By prohibiting the passage of the pulse by the AND circuit and stopping the supply of the switching pulse, the pumping operation of the charge pump circuit is stopped during most of the non-display region period, thereby reducing the current supply capability of the power supply circuit. It is disclosed to do so.

According to this power supply circuit, an unnecessary through current can be prevented from flowing in the charge pump circuit during a non-display period in which the current consumption in the driver circuit is small. Patent Document 1 discloses that the current supply capability of the power supply circuit is reduced in the partial display, but no other measures are disclosed in particular.
JP 2002-175049 (6th page, FIG. 4)

  Therefore, in view of the above points, an object of the present invention is to further reduce power consumption in a power supply circuit in the case of binary display in a semiconductor integrated circuit that drives a liquid crystal display panel incorporating a TFT.

  In order to solve the above problems, a semiconductor integrated circuit according to one aspect of the present invention includes a liquid crystal display having a plurality of individual electrodes to which drains of a plurality of thin film transistors are respectively connected, and a common electrode facing the plurality of individual electrodes. A semiconductor integrated circuit for driving a panel, wherein first to third power supply potentials are supplied in a normal display mode, and image data is converted into a plurality of gradation voltages by a plurality of digital / analog converters. The plurality of gradation voltages are power-amplified by a plurality of operational amplifier circuits and supplied to the sources of the plurality of thin film transistors. In the binary display mode, a fourth power supply potential is supplied, and each of the gradation voltages is supplied based on image data. A driving circuit that selectively supplies one of the fourth power supply potential and the ground potential to the source of the thin film transistor, and a common potential applied to the common electrode. And a power supply circuit that supplies the first to third power supply potentials to the drive circuit in the normal display mode and supplies the fourth power supply potential to the drive circuit in the binary display mode. .

  Here, the power supply circuit supplies the fifth power supply potential and the sixth power supply potential to the common potential generation circuit in the normal display mode, and generates the fourth power supply potential and the ground potential in the binary display mode. You may make it supply to a circuit.

  In that case, the power supply circuit boosts the voltage supplied from the outside to generate the first boosted voltage, and boosts the voltage supplied from the outside to generate the second boosted voltage. Second booster circuit to be generated and first to third operational amplifiers for generating first to third power supply potentials based on a plurality of voltages obtained by dividing the first boosted voltage in the normal display mode And a fourth operational amplifier that generates a fourth power supply potential based on a voltage obtained by dividing the first boosted voltage in the binary display mode, and the first boosted voltage in the normal display mode. A fifth operational amplifier that generates a fifth power supply potential based on the voltage obtained by voltage reduction, and a sixth power supply potential based on the voltage obtained by dividing the second boosted voltage in the normal display mode. The sixth operational amplifier and the binary display mode Te may be an output terminal of the sixth operational amplifier to include a switch circuit connected to the ground potential.

  Alternatively, the power supply circuit supplies the fourth power supply potential and the fifth power supply potential to the common potential generation circuit in the normal display mode, and the fourth power supply potential and the ground potential in the binary display mode. You may make it supply to.

  In that case, the power supply circuit boosts the voltage supplied from the outside to generate the first boosted voltage, and boosts the voltage supplied from the outside to generate the second boosted voltage. Second booster circuit to be generated and first to third operational amplifiers for generating first to third power supply potentials based on a plurality of voltages obtained by dividing the first boosted voltage in the normal display mode A fourth operational amplifier that generates a fourth power supply potential based on a voltage obtained by dividing the first boosted voltage in the normal display mode and the binary display mode, and the first operational amplifier in the normal display mode. A fifth operational amplifier for generating a fifth power supply potential based on a voltage obtained by dividing the boosted voltage, and a switch circuit for connecting the output terminal of the fifth operational amplifier to the ground potential in the binary display mode; May be included.

  According to the present invention, by switching the operation of the drive circuit and the power supply system in the normal display mode and the binary display mode, the power consumption in the power supply circuit can be further reduced in the case of binary display.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings. In addition, the same reference number is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a diagram showing a configuration including a semiconductor integrated circuit and a liquid crystal display panel according to the first embodiment of the present invention. In FIG. 1, a semiconductor including a source drive circuit 200, a RAM (Random Access Memory) 300, a power supply circuit 400, a gate potential generation circuit 500, a common potential generation circuit 600, and a control circuit 700. An integrated circuit (liquid crystal driver IC) and a liquid crystal display panel 100 are shown.

  As one method for driving a liquid crystal display panel, an active matrix method is used in which a plurality of active elements are arranged for each dot arranged in a two-dimensional matrix on the liquid crystal display panel, and pixels are driven by these active elements. ing. TFTs are widely used as active elements.

  In the liquid crystal display panel 100 shown in FIG. 1, for example, the same number of TFTs 111, 112,... Are arranged in a two-dimensional matrix corresponding to 720 × 132 dots. The source of the TFT in each column is connected to each of the source lines S1, S2,..., And the gate of the TFT in each row is connected to each of the gate lines G1, G2,.

  When the TFTs 111, 112,... Are turned on, an image signal supplied to the source is output from the drain, whereby a plurality of individual electrodes (segment electrodes) E111, E112,. ..Supply image signals to In the liquid crystal display panel 100, a common electrode (common electrode) (not shown) is provided to face the plurality of segment electrodes E111, E112,... Between the plurality of segment electrodes and the common electrode. The formed capacitors are represented as liquid crystal capacitors C111, C112,.

  The source drive circuit 200 includes a plurality of operational amplifier circuits 210 that perform a power amplification operation, and a plurality of DACs (Digital Analog Converter: Digital / Analog Converter) that convert image data (digital image signals) read from the RAM 300 into analog image signals. Converter 220).

  The RAM 300 temporarily stores red (R), green (G), and blue (B) image data input from an external MPU (microprocessor) or the like. Image data read from the RAM 300 is input to a plurality of DACs 220 and converted into analog image signals subjected to γ correction. Further, the analog image signal is output to the source lines S1, S2,... Via a plurality of operational amplifier circuits 210. Here, for example, the image signal supplied to the source line S1 is applied to the sources of the TFTs 111, 121,..., And the image signal supplied to the source line S2 is applied to the sources of the TFTs 112, 122,. Applied.

  The power supply circuit 400 generates a desired power supply potential by boosting or dividing a power supply voltage supplied from the outside with a plurality of boosting circuits and voltage dividing circuits, and a source driving circuit 200, a gate potential generating circuit 500, and , And supplied to the common potential generation circuit 600. The internal configuration of the power supply circuit 400 will be described later.

In accordance with the control signal supplied from the control circuit 700, the gate potential generation circuit 500 selects one of the gate lines G1, G2,... Corresponding to the line of the liquid crystal display panel 100 to which the image signal is supplied. One is supplied with a high level gate signal.
The common potential generation circuit 600 generates a common potential according to a control signal supplied from the control circuit 700 and supplies the common potential to the common electrode of the liquid crystal display panel 100.
The gate potential generation circuit 500 and the common potential generation circuit 600 may be separately formed as a gate driver IC.

  The control circuit 700 controls the reading operation of the image data from the RAM 300 based on the vertical synchronization signal and the horizontal synchronization signal supplied from the outside, and the source driving circuit 200, the power supply circuit 400, the gate potential generation circuit 500, and The common potential generation circuit 600 is controlled.

The power supply circuit 400 includes a first booster circuit 410, a second booster circuit 420, a third booster circuit 430, a fourth booster circuit 440, a first voltage divider circuit 450, and a second voltage divider circuit 450. A pressure circuit 460 and a switch circuit 470 are included. Although the power supply potential V _DD and _VSS are supplied to the power supply circuit 400, in this embodiment, the power supply potential _{VSS is set} to 0 V (ground potential), so that the power supply voltage (V _DD −V _SS ) = V _DD Become.

The first booster circuit 410 boosts a power supply voltage V _DD (for example, 3V) supplied from the outside by a factor of 2, and supplies a power supply potential V _OUT (for example, 6V) used in the first voltage divider circuit 450. Generate.

The second booster circuit 420 boosts the power supply voltage V _DD supplied from the outside by a factor of 1 with a reverse polarity, and supplies the power supply potential V _OUTM (for example, −3 V) used in the second voltage divider circuit 460. Generate.

The first voltage dividing circuit 450 includes power supply potentials V _DDHS and V _GMH supplied to the source driver circuit 200 based on the power supply potential V _DD and the power supply potential _VOUT supplied from the first boost circuit 410. and V _GML, generates a power supply potential _{V COMHP} and _{V COMH} supplied to the common potential generation circuit 600, and a power supply potential _{V OFREG} and _{V ONREG} supplied to the subsequent stage of the booster circuit.

The second voltage dividing circuit 460 is based on the power supply potential V _DD , the power supply potential _VOUT supplied from the first booster circuit 410, and the power supply potential _VOUTM supplied from the second booster circuit 420. The power supply potential V _COML supplied to the common potential generation circuit 600 is generated.

The third booster circuit 430 boosts the power supply potential V _ONREG supplied from the first voltage divider circuit 450 to 3 to 5 times, and is supplied to the gate potential generation circuit 500 and the fourth booster circuit 440. A power supply potential V _DDHG is generated.

Fourth booster circuit 440, obtained by boosting the potential difference between power supply potential _{V OFREG} supplied from the third power supply potential _{V DDHG} a first voltage divider circuit 450 which is supplied from the booster circuit 430 to 1x in reverse polarity A power supply potential V _EE (= (V _DDHG −V _OFREG ) × (−1)) is generated.

FIG. 2 is a diagram showing a configuration example of a booster circuit used as the first to fourth booster circuits shown in FIG.
The booster circuit shown in FIG. 2 includes P-channel transistors QP1 to QP3 that perform charge pump operations, capacitors C1 to C3 connected to these transistors, and P-channel transistors QP11 and N-channel transistors that constitute a first inverter IV1. and QN11, and P-channel transistors QP12 and N-channel transistors QN12 constituting the second inverter IV2, a level shifter 1-3 and an inverter for supplying respectively the gate voltage _V G 1 to V _G 3 to the transistor QP1 to QP3 IV11～ IV33. In FIG. 2 also, the power supply potential _{VSS is set} to 0 V (ground potential). In the following description of FIG. 2, the input voltage input to the booster circuit is V1, and the boosted output voltage is V2.

  The booster circuit shown in FIG. 2 is supplied with boosted clock signals CK1 and CK2 from the outside and performs a charge pump operation to boost the input voltage V1 and generate an output voltage V2. The charging and discharging of the capacitors C1 and C2 are repeated by the switching operation of the transistors QP1 to QP3 and the inversion operation of the first and second inverters, and the charge moves accordingly, and the charge pump operation is performed. As a result, the capacitor C3 is charged from the drain of the transistor QP1, and the output voltage V2 at one end of the capacitor C3 gradually rises and reaches about three times the input voltage V1 in a steady state.

  In FIG. 2, the case where the boosting ratio of the boosting circuit is three times has been described as an example, but a boosting circuit having a desired boosting ratio can be configured by changing the number of stages of the inverter, the level shifter, and the transistor. . A charge pump circuit that obtains a negative boosted potential based on a positive power supply potential is also generally known.

FIG. 3 is a diagram showing a configuration of the first voltage dividing circuit shown in FIG.
As shown in FIG. 3, the first voltage dividing circuit 450 includes a resistor R101~R108 used to generate a plurality of voltages based on the reference voltage V _REG, 7 kinds of power supply potential based on their voltage 7 differential amplifier circuits OP1 to OP7 that generate (V _COMH , V _COMHP , V _ONREG , V _OFREG , V _DDHS , V _GMH , V _GML ). The reference voltage V _REG is, for example, 3 V, and is generated by another IC not shown. In the present embodiment, an operational amplifier composed of MOS transistors is used as the differential amplifier circuit.

  The operational amplifiers OP1 to OP7 are configured so that the output signal is negatively fed back to the inverting input terminal, and the resistors R1 and R2 are used as negative feedback resistors for the operational amplifier OP1. Similarly, resistors R3 and R4 are used for operational amplifier OP2, resistors R5 and R6 are used for operational amplifier OP3, resistors R7 and R8 are used for operational amplifier OP4, resistors R9 and R10 are used for operational amplifier OP5, and resistors R11 and R11 are used. R12 is used in the operational amplifier OP6, and resistors R13 and R14 are used in the operational amplifier OP7.

  Control signals (enable signals) CTL1, CTL2, CTL3 to CTL5 are supplied from the control circuit 700 to the operational amplifiers OP1, OP2, OP5 to OP7. The operational amplifiers OP1, OP2, OP5 to OP7 perform an amplification operation when the respective control signals are activated, and stop the amplification operation when the respective control signals are deactivated.

A plurality of voltages obtained by dividing the reference voltage V _REG by the resistors R101 to R108 are supplied to the non-inverting input terminals of the operational amplifiers OP1 to OP7.
The output potential of the operational amplifier OP1 is supplied to the common potential generation circuit 600 as the power supply potential V _COMH and the output potential of the operational amplifier OP2 is _supplied as the power supply potential V _COMHP . The output potential of the operational amplifier OP3 is _supplied as the power supply potential V _ONREG to the third booster circuit 430, and the output potential of the operational amplifier OP4 is supplied as the power supply potential V _OFREG to the fourth booster circuit 440.

The output potential of the operational amplifier OP5 is supplied to the source drive circuit 200 as the power supply potential V DDHS, the output potential of the operational amplifier OP6 is _supplied as the power supply potential V _GMH , and the output potential of the operational amplifier OP7 is supplied as the power supply potential V _GML . As shown in FIG. 3, a power supply potential _VOUT or V _DD is used as a power supply for the operational amplifiers OP1 to OP7. In the present embodiment, the power supply potentials _VOUT and V _DD are, for example, 6V and 3V.

The power supply potentials V _DDHS , V _GMH , and V _GML are, for example, 4.5 V, 4 V, and 0.5 V, and are supplied to the source driving circuit 200. The power supply potentials V _COMH and V _COMHP are, for example, 4.5 V and 5 V, and are supplied to the common potential generation circuit 600. Further, the power supply potentials V _ONREG and V _OFREG are, for example, 4.5 V and 4 V, and are supplied to the third booster circuit 430 and the fourth booster circuit 440, respectively.

In general, a constant current source is incorporated in the operational amplifier, and the constant current source is one of the factors that determine the consumption current of the operational amplifier. In the present embodiment, the operational amplifier OP2 that outputs the power supply potential V _COMHP is designed to have a smaller current consumption than the operational amplifiers OP1 and OP3 to OP9 by designing the current value of the constant current source to be small.

FIG. 4 is a diagram showing the configuration of the second voltage dividing circuit and its peripheral circuits shown in FIG.
As shown in FIG. 4, a second voltage divider circuit 460 includes a resistor R109~R111 used to generate a plurality of voltages based on the reference voltage _{V REG,} 2 types of potential based on their voltage ( V _COMW , V _COML ), and two differential amplifier circuits OP8 and OP9. A voltage obtained by dividing the reference voltage V _REG by the resistors R109 to R111 is supplied to the non-inverting input terminal of the operational amplifier OP8.

Further, the operational amplifier OP8 is configured such that the output signal is negatively fed back to the inverting input terminal, and the resistors R15 and R16 are used as negative feedback resistors for the operational amplifier OP8. The power supply of the operational amplifier OP8, the power supply potential _{V OUT} and _{V SS} is used. The output terminal of the operational amplifier OP8 is connected to the output terminal of the operational amplifier OP9 via the resistors R17 and R18, and the connection point between the resistor R17 and the resistor R18 is connected to the inverting input terminal of the operational amplifier OP9. .

A voltage obtained by dividing the reference voltage V _REG by the resistors R109 to R111 is input to the non-inverting input terminal of the operational amplifier OP9. Further, a voltage obtained by _dividing the potential difference between the output potential V _COML of the operational amplifier OP9 and the output potential V _COMW of the operational amplifier OP8 by the resistors R17 and R18 is negatively fed back to the inverting input terminal of the operational amplifier OP9. Further, the output terminal of the operational amplifier OP9 is connected to the drain of the N-channel transistor QN1 constituting the switch circuit 470, and the power supply potential V _COML output from the second voltage dividing circuit 460 is supplied to the common potential generation circuit 600. It is supplied to the source of N channel transistor QN13. In FIG. 4, the power supply potential V _DD and V _OUTM are used as the power supply of the operational amplifier _OP9 .

  Control signals (enable signals) CTL6 and CTL7 are supplied from the control circuit 700 to the operational amplifiers OP8 and OP9, respectively. The operational amplifiers OP8 and OP9 perform an amplification operation when the respective control signals are activated, and stop the amplification operation when the respective control signals are deactivated.

In the switch circuit 470, the source of the transistor QN1 is connected to the power supply potential _{V SS.} The transistor QN2 is Darlington-connected to the transistor QN1. When the control signal CTL8 input from the control circuit 700 to the gate of the transistor QN2 is at a low level, the transistors QN1 and QN2 are turned off. When the control signal CTL8 is at a high level, the transistors QN1 and QN2 are turned on. Alternatively, a combination of a P-channel transistor and an N-channel transistor may be used instead of the transistors QN1 and QN2.

The power supply potential V _COMH generated by the first voltage dividing circuit 450 is supplied to the source of the P-channel transistor QP13 in the common potential generating circuit 600. As already described, the reference potential V _COML generated by the second voltage dividing circuit 460 is supplied to the source of the N-channel transistor QN13 in the common potential generating circuit 600.

In the common potential generation circuit 600, the transistors QN13 and QP13 constitute a CMOS inverter, and when an input voltage _VIN generated inside or outside the common potential generation circuit 600 is applied to the gates of the transistors QP13 and QN13. , the common voltage _{V COM} from the drain of the transistor QP13 and QN13 are output and supplied to the common electrode of the liquid crystal display panel 100.

As shown in FIG. 4, the transistor QN <b> 1 of the switch circuit 470 is connected between the output of the operational amplifier OP <b> 9 and the common potential generation circuit 600. Therefore, when the transistor QN1 is turned off by the control signal CTL8 from the control circuit 700, the power supply potential supplied to the common potential generation circuit 600 becomes the output potential V _COML (for example, −1V) of the operational amplifier OP9. When the transistor QN1 is turned on by the control signal CTL8, the power supply potential V _SS is connected to the source of the transistor QN1 (in this embodiment, the ground potential is 0 V).

  In the present embodiment, the power supply potential supplied to the source drive circuit 200 and the common potential generation circuit 600 is changed between the normal full color display mode (normal display mode) and the binary display mode.

First, the case of the normal display mode will be described.
In the normal display mode, the control circuit 700 shown in FIG. 1 activates the control signals CTL1 and CTL3 to CTL7, so that the operational amplifiers in the first voltage dividing circuit 450 and the second voltage dividing circuit 460 shown in FIGS. OP1 and OP5 to OP9 perform an amplification operation. On the other hand, since the control circuit 700 deactivates the control signals CTL2 and CTL8, the operational amplifier OP2 stops the amplification operation, and the switch circuit 470 is turned off. Note that the operational amplifiers OP3 and OP4 operate in any mode.

As a result, the power supply potentials V _DDHS , V _GMH , and V _GML output from the first voltage dividing circuit 450 are supplied to the source driving circuit 200. Further, the power supply potential V _COMH output from the first voltage dividing circuit 450 and the power supply potential V _COML output from the second voltage dividing circuit 460 are supplied to the common potential generation circuit 600.

Therefore, the power supply potential V _DDHS is supplied as a power supply potential to the operational amplifier circuit 210 that drives the source lines S1, S2,..., And the power supply potentials V _GMH and V _GML respectively generate a plurality of gradation voltages in the DAC 220. Is supplied to both ends of the series resistor group. Further, the power supply potential _{V COMH} and _{V COML} is fed to the common potential generation circuit 600, respectively used as the power source potential and the power supply potential on the low potential side of the high potential side to generate a common potential _{V COM.}

  In the normal display mode, one gray scale voltage is selected by the switch circuit from the plurality of gray scale voltages in the DAC 220 based on the image data input from the RAM 300. In this way, the image data is converted into one gradation voltage by the DAC 220, and this gradation voltage is input to the corresponding operational amplifier circuit 210. The operational amplifier circuit 210 operates as a voltage follower, and outputs the input gradation voltage to a corresponding one of the source lines S1, S2,.

Next, the case of the binary display mode will be described.
In the binary display mode, the control circuit 700 shown in FIG. 1 deactivates the control signals CTL1 and CTL3 to CTL7. Therefore, the first voltage dividing circuit 450 and the second voltage dividing circuit 460 shown in FIGS. The operational amplifiers OP1 and OP5 to OP9 in FIG. On the other hand, since the control circuit 700 activates the control signals CTL2 and CTL8, the operational amplifier OP2 starts an amplification operation, and the switch circuit 470 is turned on.

As a result, the power supply potential V _COMHP output from the first voltage dividing circuit 450 is supplied to the source driving circuit 200 and the common potential generating circuit 600. The power supply potential V _COMHP, in the source driver circuit 200, the used as the power source potential on the high potential side for driving binary source lines, the common potential generation circuit 600, a high potential for generating a common potential V _COM Used as the power supply potential on the side. Further, since the switch circuit 470 is turned on, the power supply potential V _COML supplied to the common potential generation circuit 600 becomes the power supply potential V _SS (the ground potential is 0 V in this embodiment).

As already described, in the binary display mode, since the operational amplifier OP5 stops the amplification operation, the power supply potential V _DDHS is not supplied to the operational amplifier circuit 210. Further, since the operational amplifiers OP6 and OP7 also stop the amplification operation, the power supply potentials V _GMH and V _GML are not supplied to the DAC 220. However, in the binary display mode, since the operational amplifier circuit 210 and the DAC 220 are not used, there is no particular problem.

Instead, the switch circuit in the source driver circuit 200 (not shown), one of the power supply potential _{V COMHP} and the power supply voltage _{V SS} is, the source lines S1, S2, selectively to each of ... Supplied. That is, in the binary display mode, and the power supply potential _{V COMHP} and the power supply voltage _{V SS} is used to represent the two types of gradation.

Generally, an operational amplifier OP1 outputs a power supply potential _{V COMH,} an operational amplifier OP9 that outputs _{V COML,} an operational amplifier OP6 to output a power supply potential _{V GMH,} the operational amplifier OP7 for outputting a _{V GML,} have a high driving capability, Large current consumption. In the present embodiment, in the binary display mode, the amplifying operation of these operational amplifiers is stopped, and the power supply potential V _COMHP generated by the operational amplifier OP2 designed to reduce current consumption in advance is source-driven. By commonly using the power supply potential on the high potential side in the circuit 200 and the common potential generation circuit 600, power consumption in the power supply circuit is reduced.

Next, a second embodiment of the present invention will be described.
FIG. 5 is a diagram showing a configuration including a semiconductor integrated circuit and a liquid crystal display panel according to the second embodiment of the present invention. In the first embodiment shown in FIG. 1, the power supply potential V _COMHP is generated by the first voltage dividing circuit 450 in the binary display mode. However, in the second embodiment shown in FIG. The generation of the power supply potential V _COMHP is omitted in one voltage dividing circuit 480. Instead, the power supply potential V _COMH is used for the source drive circuit 200 and the common potential generation circuit 600 in the binary display mode. Other points are the same as those of the first embodiment shown in FIG.

FIG. 6 is a diagram showing a configuration of the first voltage dividing circuit shown in FIG.
The first voltage divider circuit 480 shown in FIG. 6 includes a resistor R201~R207 used to generate a plurality of reference voltages based on the reference voltage _{V REG,} and a operational amplifier OP1 and OP3～OP7. The resistors constituting the negative feedback in each operational amplifier and the power supply potential supplied to the operational amplifier are the same as those in FIG. As shown in FIG. 6, the first voltage dividing circuit 480 _outputs power supply potentials V _COMH , V _ONREG , V _OFREG , V _DDHS , V _GMH , and V _GML .

Since the operation of the semiconductor integrated circuit according to this embodiment is the same as that of the first embodiment in the normal display mode, the case of the binary display mode will be described.
In the binary display mode, the power supply potential V _COMH output from the first voltage dividing circuit 480 is supplied to the source driving circuit 200 and the common potential generating circuit 600. Further, the power supply potential V _COML output from the second voltage dividing circuit 460 is supplied to the common potential generating circuit 600.

The power supply potential V _COMH is used as a high-potential-side power supply potential for binary driving of the source line in the source drive circuit 200, and is a high potential for generating the common potential V _COM in the common potential generation circuit 600. Used as the power supply potential on the side. Further, since the switch circuit 470 is turned on, the power supply potential V _COML supplied to the common potential generation circuit 600 becomes the power supply potential V _SS (the ground potential is 0 V in this embodiment).

  Since the amplification operation of the operational amplifier OP1 with large current consumption is performed even in the binary display mode, the effect of reducing the power consumption in the power supply circuit is smaller than that in the first embodiment, but the operational amplifier OP2 and the resistor R3 shown in FIG. Since R4 need not be provided, the circuit scale can be made smaller than in the first embodiment.

1 is a diagram showing a semiconductor integrated circuit and a liquid crystal display panel according to a first embodiment of the present invention. The figure which shows the structural example of the booster circuit used as the 1st-4th booster circuit shown in FIG. The figure which shows the structure of the 1st voltage dividing circuit shown in FIG. The figure which shows the structure of the 2nd voltage dividing circuit shown in FIG. 1, and its peripheral circuit. The figure which shows the semiconductor integrated circuit and liquid crystal display panel which concern on the 2nd Embodiment of this invention. The figure which shows the structure of the 1st voltage dividing circuit shown in FIG.

Explanation of symbols

  1 to 3 level shifter, 100 liquid crystal display panel, 111 to 112, 121 to 122 TFT, 200 source drive circuit, 210 operational amplifier circuit, 220 DAC, 300 RAM, 400 power supply circuit, 410 first booster circuit, 420 second Booster circuit, 430 third booster circuit, 440 fourth booster circuit, 450, 480 first voltage divider circuit, 460 second voltage divider circuit, 470 switch circuit, 500 gate potential generator circuit, 600 common potential generator circuit 700 control circuit, C1-C3 capacitor, C111-C122 liquid crystal capacitance, E111-E122 segment electrode, R1-R207 resistance, QP1-QP13 P-channel transistor, QN1-QN13 N-channel transistor, IV1-IV33 inverter Data, OP1~OP9 operational amplifier

Claims (5)

A semiconductor integrated circuit for driving a liquid crystal display panel having a plurality of individual electrodes respectively connected to drains of a plurality of thin film transistors and a common electrode facing the plurality of individual electrodes,
In the normal display mode, the first to third power supply potentials are supplied, the image data is converted into a plurality of gradation voltages by a plurality of digital / analog converters, and the plurality of gradation voltages are converted into a plurality of operational amplifier circuits. In the binary display mode, the fourth power supply potential is supplied to the sources of the plurality of thin film transistors, and the fourth power supply potential and the ground potential are supplied to the sources of the respective thin film transistors based on the image data. A drive circuit that selectively supplies one of
A common potential generation circuit for generating a common potential applied to the common electrode;
A power supply circuit for supplying first to third power supply potentials to the drive circuit in a normal display mode, and a fourth power supply potential to the drive circuit in binary display mode;
A semiconductor integrated circuit comprising:   The power supply circuit supplies a fifth power supply potential and a sixth power supply potential to the common potential generation circuit in the normal display mode, and generates a fourth power supply potential and a ground potential in the binary display mode. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is supplied to a circuit. The power supply circuit is
A first booster circuit for boosting an externally supplied voltage to generate a first boosted voltage;
A second booster circuit for boosting an externally supplied voltage to generate a second boosted voltage;
First to third operational amplifiers for generating first to third power supply potentials based on a plurality of voltages obtained by dividing the first boosted voltage in the normal display mode;
A fourth operational amplifier for generating a fourth power supply potential based on a voltage obtained by dividing the first boosted voltage in the binary display mode;
A fifth operational amplifier for generating a fifth power supply potential based on a voltage obtained by dividing the first boosted voltage in the normal display mode;
A sixth operational amplifier for generating a sixth power supply potential based on a voltage obtained by dividing the second boosted voltage in the normal display mode;
A switch circuit for connecting an output terminal of the sixth operational amplifier to a ground potential in a binary display mode;
The semiconductor integrated circuit according to claim 2, comprising:   The power supply circuit supplies a fourth power supply potential and a fifth power supply potential to the common potential generation circuit in the normal display mode, and generates a fourth power supply potential and a ground potential in the binary display mode. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is supplied to a circuit. The power supply circuit is
A first booster circuit for boosting an externally supplied voltage to generate a first boosted voltage;
A second booster circuit for boosting an externally supplied voltage to generate a second boosted voltage;
First to third operational amplifiers for generating first to third power supply potentials based on a plurality of voltages obtained by dividing the first boosted voltage in the normal display mode;
A fourth operational amplifier that generates a fourth power supply potential based on a voltage obtained by dividing the first boosted voltage in the normal display mode and the binary display mode;
A fifth operational amplifier for generating a fifth power supply potential based on a voltage obtained by dividing the first boosted voltage in the normal display mode;
A switch circuit for connecting an output terminal of the fifth operational amplifier to a ground potential in a binary display mode;
The semiconductor integrated circuit according to claim 4, comprising:

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