JP2008028811A - Analog front-end device and imaging device - Google Patents

Abstract

In a mode in which a high-speed electronic shutter operation is performed with an exposure control period of less than one horizontal period, a control pulse proceeds as a simultaneous operation during an effective data output period, and discontinuous noise components due to the control pulse output operation adversely affect each part , Fixed pattern noise (FPN) appears in the image.
A pre-processing unit 3 including processing for converting an image signal from a solid-state image sensor 20 into digital image data, and a drive pulse for driving the solid-state image sensor continuously and discontinuously are generated periodically. A timing generator 2 that generates and outputs an output stop position signal indicating an output stop position when the image sensor is driven discontinuously, and is input from the preprocessing unit 3 in a discontinuous state when the output stop position signal is valid. A continuous data generation unit 10 that converts the incoming image data to generate continuous image data, and a digital data output unit 7 that receives the image data generated by the continuous data generation unit and forwards it to the external digital signal processing device 30 Is provided.
[Selection] Figure 1

Description

  The present invention relates to an analog front-end device interposed between a solid-state imaging sensor and a digital signal processing device in a digital camera, and more particularly to a technique for suppressing the influence of digital noise during image data transfer.

  In recent years, there has been a remarkable shift from analog technology to digital technology in the camera industry. In particular, digital still cameras that do not require film or development are booming. As for mobile phones, camera-mounted types have become the mainstream, and there are significant improvements in image quality due to image processing along with the increase in the number of pixels.

  FIG. 5 is a block diagram showing a configuration of a conventional analog front-end device. 20 is a solid-state image sensor that is a MOS type image sensor, 30 is a digital signal processing device (DSP) that performs image processing, A ′ is an analog front-end device, and 1 is a synchronization signal generating unit that generates a periodic synchronization signal. 2 is a timing generator that generates a pulse for driving the solid-state imaging sensor 20, 3 is a preprocessing unit, 4 is a CDS (correlated double sampling) unit, 5 is a GCA (gain control amplifier) unit, and 6 is an A / A A D conversion unit, 7 is a digital data output unit, 8 is a CPU interface, and 9 is a clock multiplication unit that multiplies an input clock from the outside and outputs it.

  In the conventional analog front-end device A ′, when imaging light is incident on the solid-state imaging sensor 20 through a lens (not shown), it is converted into an electrical signal by a photodiode or the like, and vertical and horizontal driving from the timing generator 2 is performed. An image signal which is an analog continuous signal is generated and output by the pulse. The output image signal is subjected to gain control by the GCA unit 5 after the 1 / f noise is appropriately reduced by the sample hold circuit of the CDS unit 4, and digital image signal data (RGB data) by the A / D conversion unit 6. ). The converted image signal data is output from the digital data output unit 7 to the external digital signal processing device 20 in the parallel data format or the serial data format converted from parallel to serial, and the luminance signal processing, color separation, color matrix processing, etc. Various processes are performed.

  When the electronic shutter mechanism in the solid-state imaging sensor 20 is not the all-pixel simultaneous readout system but the sequential readout type rolling shutter system, an electronic shutter drive control pulse is output for each line.

When operating the electronic shutter at high speed in a highlight environment, if the exposure control period is less than one horizontal period, a control pulse is output from the timing generator 2 within the effective data period, as shown in FIG. Input to the solid-state imaging sensor 20. The solid-state imaging sensor 20 is driven by a control pulse from the timing generator 2, performs CDS, GCA, A / D conversion simultaneously with the effective data output period, and outputs the resulting sensor output data from the digital data output unit 7. . At this time, the operation noise due to the control pulse output within the effective data period is generated during the effective period in both the solid-state imaging sensor 10 and the analog front end device A ′.
Japanese Patent Laying-Open No. 2005-244709 (page 5-6, FIG. 1)

  In the above conventional analog front-end device, in the mode in which the exposure control period is less than one horizontal period and the high-speed electronic shutter operation is performed, the control pulse output operation output at an arbitrary position within the effective data period is simultaneously performed during the effective data output period. Therefore, the discontinuous noise component due to the control pulse operation is generated in each part (inside the solid-state image sensor, connection part between the solid-state image sensor and the analog front-end device, timing generator of the analog front-end device, CDS unit, GCA unit, A As a result of adversely affecting the / D converter, fixed pattern noise (FPN (Fixed Pattern Noise)) appears in the image (see “5”, “10”, “15”, and “20” of the image data P0 in FIG. 6).

  The present invention was created in view of such circumstances, and an object thereof is to provide an analog front-end device that can output high-quality sensor data without fixed pattern noise.

The analog front-end device according to the present invention is
A pre-processing unit including a process of inputting an analog image signal output from a solid-state imaging sensor that photoelectrically converts a light image of a subject and converting it into digital image data;
An output stop position signal that periodically generates drive pulses for driving the solid-state image sensor continuously and discontinuously and indicates an output stop position when the solid-state image sensor is driven discontinuously in synchronization with the drive pulses A timing generator that generates and outputs
When the image data from the pre-processing unit is input, the image data is passed through when the output stop position signal from the timing generator is invalid, and is discontinuous when the output stop position signal is valid A continuous data generation unit that converts the image data input in step S to generate continuous image data;
A digital data output unit that receives the image data generated by the continuous data generation unit, and transfers and outputs the image data to an external digital signal processing device.

  In this configuration, during normal operation, the image signal obtained from the solid-state imaging sensor is a continuous signal, and the image data from the preprocessing unit is also continuous. The output stop position signal of the timing generator is invalid, and the continuous data generation unit passes through the continuous image data from the preprocessing unit and transfers the data from the digital data output unit to the digital signal processing device.

  On the other hand, during the high-speed electronic shutter operation in which the electronic shutter is operated in less than one horizontal period, the image signal obtained from the solid-state imaging sensor is a discontinuous signal, and the image data from the preprocessing unit is also discontinuous. . Then, the output stop position signal of the timing generator becomes valid, and the continuous data generation unit converts the discontinuous image data from the preprocessing unit into continuous image data using the output stop position signal, and from the digital data output unit Data is transferred to the digital signal processor.

  That is, during the high-speed electronic shutter operation, the output of the solid-state imaging sensor is temporarily stopped to be a discontinuous output at the timing when the discontinuous noise component generated due to the control pulse output operation in the effective period is generated. Then, the continuous data generation unit converts the discontinuous image data into continuous image data and outputs it. As a result, fixed pattern noise on the image due to discontinuous noise components for each part (inside of solid-state image sensor, connection part of solid-state image sensor and analog front-end device, timing generator of analog front-end device, pre-processing unit) Is suppressed, and high-quality sensor data can be obtained.

  In the analog front-end device having the above-described configuration, the timing generator temporarily stops the horizontal pixel signal readout pulse when the exposure control period of the solid-state imaging sensor is set to less than one horizontal period. There is a mode in which a pulse for controlling the accumulated charge amount of the solid-state image sensor is output, and then a pixel signal readout pulse in the horizontal direction is restarted.

  According to this configuration, it is possible to manage the pulse timing for suppressing the discontinuous noise component at the time of the high-speed electronic shutter on the analog front end device side.

  In the analog front-end device having the above-described configuration, the continuous data generation unit can minimize the time required for processing by multiplying the number of times image data output is stopped within one horizontal period by the number of clocks in one stop period. By connecting the clock delay devices for one stop period as many times as the number of stops, selecting the image data before the one stop period delay at the stop position in order from the beginning of one horizontal period. There is a mode of generating simple image data.

  According to this configuration, the pulse timing and the discontinuous period for suppressing the discontinuous noise component are managed on the analog front-end device side, and then the continuous data generation unit is controlled so that there is no fixed pattern noise. Quality sensor data can be obtained.

  In the analog front-end device having the above-described configuration, the continuous data generation unit includes a memory having a recording capacity of one horizontal period or more of valid data, and the image is sequentially stored in the memory from the head of one horizontal period. When writing data, the invalid data portion at the output stop position of the solid-state imaging sensor is discarded and written, and the image data is read continuously from the memory to output the continuous image data There is a mode of doing.

  According to this configuration, the pulse timing for suppressing the discontinuous noise component and the discontinuous period are managed on the analog front end device side, and then the memory writing and reading of the continuous data generation unit are controlled, thereby fixing High-quality sensor data without pattern noise can be obtained.

  In the analog front-end device having the above-described configuration, the continuous data generation unit includes a memory having a recording capacity of one horizontal period or more of valid data, and the image is sequentially stored in the memory from the head of one horizontal period. When writing data, write in a state including invalid data at the output stop position of the solid-state imaging sensor, and reading the image data from the memory skips the invalid data portion and reads the continuous image data. There is a mode of outputting.

  According to this configuration, the pulse timing for suppressing the discontinuous noise component and the discontinuous period are managed on the analog front end device side, and then the memory writing and reading of the continuous data generation unit are controlled, thereby fixing High-quality sensor data without pattern noise can be obtained.

  In the analog front-end device having the above configuration, the digital data output unit may output the continuous image data from the memory at a readout timing of n times a pixel clock (n is a natural number of 2 or more) in a horizontal blanking period. Is read out in parallel data format or serial data format.

  According to this configuration, the horizontal timing is controlled by controlling the memory writing and reading of the continuous data generation unit after managing the pulse timing and the discontinuous period for suppressing the discontinuous noise component on the analog front end device side. By outputting in a period, high-quality sensor data without fixed pattern noise can be obtained.

  In the analog front-end device having the above-described configuration, the timing generator outputs the output stop position signal as a timing flag signal. Alternatively, the timing generator may output the output stop position signal as an address signal using a counter value that operates during one horizontal period.

  Furthermore, in the analog front-end device having the above-described configuration, there is an aspect in which the timing generator and the continuous data generation unit include a register that independently sets an output stop position of the solid-state imaging sensor.

  According to this configuration, by managing the pulse timing and the discontinuous period for suppressing the discontinuous noise component on the analog front end device side, it becomes possible to cope with only the setting change at the time of switching the electronic shutter mode. In the digital signal processing apparatus, the same interface as that for continuous reading is usually sufficient.

  An imaging apparatus according to the present invention includes any one of the analog front-end devices described above, the solid-state imaging sensor, the digital signal processing device, a lens, and a monitor.

  According to the present invention, during the high-speed electronic shutter operation, at the timing when the discontinuous noise component generated due to the control pulse output operation in the effective period occurs, the output of the solid-state imaging sensor is temporarily stopped to be a discontinuous output, Discontinuous image data is converted into continuous image data and output by the continuous data generation unit, so that fixed pattern noise in the image due to discontinuous noise components for each unit is suppressed, and high-quality sensor data is obtained. be able to.

  Embodiments of an analog front end device according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an analog front-end device according to an embodiment of the present invention. In FIG. 1, A is an analog front-end device, 20 is a solid-state image sensor that is a MOS (Metal Oxide Semiconductor) type image sensor, and 30 is a digital signal processing device (DSP) that performs image processing and the like. 1 is a synchronous signal generator (SSG) that generates a periodic synchronization signal, 2 is a timing generator that periodically generates pulses for driving the solid-state image sensor 20, and 3 is output from the solid-state image sensor 20. A preprocessing unit including a process of inputting an analog image signal and converting it to digital image data. The pre-processing unit 3 is a CDS (correlated double sampling) unit 4 that removes noise from the analog charge signal input from the solid-state image sensor 20, and a GCA (gain that controls the DC component by feedback control while controlling the gain of the signal. A control amplifier) unit 5 and an n-bit A / D conversion unit 6. 7 is a digital data output unit that receives image data and transfers it to an external digital signal processing device 30; 8 is an interface with an external CPU; 9 is a clock multiplier that multiplies a clock input from the outside and supplies it internally. Part. 10 as a new constituent element is output from the solid-state image sensor 20, and when the data input through the CDS unit 4, the GCA unit 5 and the A / D conversion unit 6 is discontinuous, the discontinuous data is obtained. It is a continuous data generation unit for converting into continuous image data. The timing generator 2 periodically generates pulses for driving the solid-state image sensor 20 continuously and discontinuously, and outputs an output stop position when driving the solid-state image sensor 20 discontinuously in synchronization with the drive pulse. A stop position signal is generated and output to the continuous data generation unit 10.

  FIG. 2 shows the state of the solid-state image sensor 20 when the solid-state image sensor 20 is driven continuously and discontinuously by periodically stopping the solid-state image sensor 20 when the control pulse corresponding to the high-speed electronic shutter in one horizontal period is output from the timing generator 2. An example of output data arrangement is shown.

  FIG. 3 shows a configuration example of the continuous data generation unit 10. FIG. 4 is an example of an operation timing chart of the continuous data generation unit 10 when it is assumed that the number of horizontal drive stops is four and one stop period is a 1T period. HBLK is a horizontal blanking pulse.

  The number of stops within one horizontal period is 4, the number of clocks in one stop period is 1, the minimum group delay is 4 clocks, and the one clock delay device 11 for one stop period is equal to the number of stops. That is, four are connected to form an internal delay, and the selector 12 selects data before the delay of one stop period at the stop position in order from the beginning of one horizontal period, thereby outputting continuous image data. An example is shown.

  Next, the operation of the analog front end device A of the present embodiment configured as described above will be described.

  First, when imaging light is incident on the solid-state imaging sensor 20 through a lens (not shown), the imaging light is converted into an electrical signal by a photodiode or the like of the solid-state imaging sensor 20. Then, an image signal which is an analog dot sequential signal is generated and output by the vertical drive pulse and the horizontal drive pulse from the timing generator 2. The image signal output from the solid-state imaging sensor 20 is gain-controlled by the GCA unit 5 after the 1 / f noise is appropriately reduced by the sample and hold circuit of the CDS unit 4 in the preprocessing unit 3, and the A / D conversion unit 6 is converted into digital image signal data (RGB data). The image signal data is output from the digital data output unit 7 to the external digital signal processing device 20 via the continuous data generation unit 10 in a parallel data format or a serial data format converted from parallel to serial. The sensor data captured by the digital signal processing device 20 is subjected to various processes such as luminance signal processing, color separation, and color matrix processing.

  Next, the operation when the exposure control period is less than one horizontal period when the electronic shutter is operated at high speed under a highlight environment will be described.

  When the timing generator 2 outputs a pulse for controlling the electronic shutter of less than one horizontal period, the pixel signal readout pulse in the horizontal direction is temporarily stopped at the rising edge and falling edge of the pulse shown in FIG. Then, during the stop period, the logic of the pulse is inverted and output in order to control the accumulated charge amount of the solid-state imaging sensor 20 that is a noise generation source. Then, horizontal pixel signal readout is resumed.

  In FIG. 2, assuming two pulses within the valid period, there are four rising and falling edge positions. At this time, since pixel readout from the solid-state image sensor 20 is stopped, the discontinuous image data P0 output from the solid-state image sensor 20 has four invalid data. That is, the output discontinuous image data P0 from the solid-state imaging sensor 20 includes periodic discontinuity information.

  In the discontinuous image data P0 including the periodic discontinuity information, the 1 / f noise is appropriately reduced by the sample hold circuit of the CDS unit 4 as in the normal operation. Further, the gain is controlled by the GCA unit 5 and converted into image signal data including periodic discontinuity information by the A / D conversion unit 6. Further, the image signal data including the periodic discontinuity information is converted into continuous image data by the continuous data generation unit 10.

  (1) A first embodiment as a configuration of the continuous data generation unit 10 will be described.

  FIG. 3 shows a specific configuration of the continuous data generation unit 10 assuming that the number of horizontal drive stops is four and one stop period is a 1T period. 11 is a one-clock delay device, and 12 is a selector. A set of one clock delay 11 and selector 12 is connected in a series of four. This corresponds to the case where the number of times of stoppage within one horizontal period is 4, the number of clocks in one stop period is 1, and the minimum group delay is 4 clocks. That is, since the number of clocks in one stop period is 1, the 1-clock delay device 11 is employed as the delay device. Further, since the number of times of stopping in one horizontal period is four, the number of sets of one clock delay unit 11 and selector 12 is four.

  FIG. 4 is a timing chart showing the operation of the continuous data generation unit 10 corresponding to the configuration of FIG. With respect to the discontinuous image data P0 inputted, the image data of 1 clock delay is P1, the clock delay signal is P2, the clock delay signal is P3, the clock delay signal is P4. Also, the first output stop position signal corresponding to the discontinuous image data P4 with a 4-clock delay is S4, and the second output stop position signal corresponding to the discontinuous image data P3 with a 3-clock delay is S3, 2 clocks. The third output stop position signal corresponding to the delay discontinuous image data P2 is S2, and the fourth output stop position signal corresponding to the one clock delay discontinuous image data P1 is S1. Each selector 12 operates using the output stop position signals S1 to S4 as selection control signals.

  The first stage selector 12 selects the discontinuous image data P0 and the discontinuous image data P1 with one clock delay obtained by delaying the discontinuous image data P0 by the first clock delay unit 11. Output to the second stage. The second-stage selector 12 selects the selection signal Q2 and the two-clock discontinuous image data P2 obtained by delaying the one-clock-delay discontinuous image data P1 by the second-stage one-clock delay device 11. Output to the third stage. The selector 12 at the third stage selects the selection signal Q3 and the non-continuous image data P3 at the three clock delay obtained by delaying the discontinuous image data P2 at the two clock delay by the first clock delay unit 11 at the third stage. Output to the 4th stage. The selector 12 at the fourth stage selects the selection signal Q4 and the discontinuous image data P4 at the four clock delay obtained by delaying the discontinuous image data P3 at the three clock delay by the first clock delay unit 11 at the fourth stage. And output as continuous image data Pout.

  The discontinuous image data P0 is converted into discontinuous image data P1 with a one-clock delay by the first-stage 1-clock delay device 11, and is input to the first-stage selector 12. The discontinuous image data P1 with 1 clock delay is converted into discontinuous image data P2 with 2 clock delay by the 1st clock delay device 11 at the 2nd stage, and is input to the selector 12 at the 2nd stage. The discontinuous image data P2 having the two clock delay is converted into the discontinuous image data P3 having the three clock delay by the first clock delay device 11 at the third stage, and is input to the selector 12 at the third stage. The discontinuous image data P3 with a delay of 3 clocks becomes discontinuous image data P4 with a delay of 4 clocks by the 1-clock delay device 11 at the 4th stage, and is input to the selector 12 at the 4th stage.

  In the fourth-stage selector 12, 4T of discontinuous image data P4 with a 4-clock delay is selected during the period when the output stop position signal S4 is at "L" level, and "1", "2", "3", " 4 "(timing t1 to t2).

  When the output stop position signal S4 becomes “H” level at the timing t2, the fourth-stage selector 12 selects the selection signal Q4 from the third-stage selector 12. In the third-stage selector 12, the output stop position signal S3 is at the “L” level until timing t3. Therefore, the third-stage selector 12 selects discontinuous image data P3 with a three-clock delay. Accordingly, the fourth stage selector 12 in the “H” level side selected state has the data “5”, “6”, “7”, “8” at the timings t2 to t3 in the discontinuous image data P3 with the delay of 3 clocks. "Is selected and output.

  When the output stop position signal S3 becomes “H” level at the timing t3, the third-stage selector 12 selects the selection signal Q3 from the second-stage selector 12. In the second stage selector 12, the output stop position signal S2 is at "L" level until timing t4, so the second stage selector 12 selects discontinuous image data P2 with a delay of two clocks. Therefore, the third and fourth stage selectors 12 in the “H” level side selected state have the data “9”, “10”, “11” at timings t3 to t4 in the discontinuous image data P2 with a two-clock delay. ”And“ 12 ”are selectively output.

  When the output stop position signal S2 becomes “H” level at the timing t4, the second-stage selector 12 selects the selection signal Q2 from the first-stage selector 12. In the first stage selector 12, the output stop position signal S1 is at "L" level until timing t5, so the first stage selector 12 selects discontinuous image data P1 with one clock delay. Accordingly, the second, third, and fourth stage selectors 12 in the “H” level side selected state have the data “13” and “14” at timings t4 to t5 in the discontinuous image data P1 with one clock delay. ”,“ 15 ”, and“ 16 ”are selectively output.

  When the output stop position signal S1 becomes “H” level at the timing t5, the first-stage selector 12 selects the discontinuous image data P0. Accordingly, the first, second, third, and fourth stage selectors 12 in the “H” level side selected state have the data “17” and “18” after timing t5 in the discontinuous image data P0. , “19” is selectively output. This is continuous image data Pout.

  In summary, the continuous data generation unit 10 outputs valid continuous data “1” to “19” from the selector 12 at the fourth stage.

  (2) A second embodiment as a configuration of the continuous data generation unit 10 will be described.

  In the second embodiment, the continuous data generation unit 10 is equipped with a memory 13 composed of a RAM for storing image data for one line. When the discontinuous image data P0 shown in FIG. 2 is input, the invalid data period portion is held without writing and skipped by writing control to the memory 13. By doing so, the data written in the memory 13 becomes continuous image data. The memory read control started before the write operation can output continuous image data with an arbitrary delay by sequentially reading from the head address.

  Also, when writing data to the memory 13, discontinuous image data P0 including invalid data is written as it is, and when reading sequentially from the top address in memory read control, the address of the invalid data period portion is skipped and read. It may be configured. Also in this case, continuous image data with an arbitrary delay can be output.

  The memory control address of the continuous data generation unit 10 may be supplied from the timing generator 2, or an address generation counter may be provided inside the continuous data generation unit 10.

  When the continuous data generator 10 and the timing generator 2 each have a built-in horizontal address counter and control discontinuous image data, a discontinuous position setting register is independently provided for the timing generator 2 and the continuous data generator 10. The operation is set in advance via the CPU interface 8.

  With this configuration, the discontinuous period can be managed on the analog front end device A side. Then, before and after the timing at which the discontinuous noise component is generated by the control pulse operation when the high-speed electronic shutter is operated, each part (the interior of the solid-state image sensor, the connection between the solid-state image sensor and the analog front-end device, the analog front-end device) The timing generator, CDS unit, GCA unit, and A / D conversion unit) are stopped. After the image data is digitally converted without affecting the horizontal drive pulse and the sensor analog signal, the continuous data generation unit 10 can obtain high-quality sensor data without fixed pattern noise.

  The analog front-end device of the present invention eliminates the influence of discontinuous noise components generated due to the control pulse output operation in the effective period when the electronic shutter is operated at high speed under a highlight environment using a MOS sensor, It can output high-quality sensor data without fixed pattern noise, and is useful as a relay device between a solid-state image sensor and a digital signal processing device in a digital camera.

The block diagram which shows the structure of the analog front-end apparatus of embodiment of this invention Timing chart showing the operation of the analog front-end device according to the embodiment of the present invention The block diagram of the continuous data generation part in the analog front end apparatus of embodiment of this invention The timing chart which shows operation | movement of the continuous data generation part in the analog front-end apparatus of embodiment of this invention Block diagram showing the configuration of a conventional analog front-end device Timing chart showing the operation of a conventional analog front-end device

Explanation of symbols

A Analog front-end device 1 Synchronization signal generator (SSG)
2 timing generator 3 preprocessing unit 4 CDS unit 5 GCA unit 6 A / D conversion unit 7 digital data output unit 8 CPU interface 9 clock multiplication unit 10 continuous data generation unit 11 1 clock delay unit 12 selector 13 memory (RAM)
20 Solid-state image sensor 30 Digital signal processor (DSP)

Claims (10)

A pre-processing unit including a process of inputting an analog image signal output from a solid-state imaging sensor that photoelectrically converts a light image of a subject and converting it into digital image data;
An output stop position signal that periodically generates drive pulses for driving the solid-state image sensor continuously and discontinuously and indicates an output stop position when the solid-state image sensor is driven discontinuously in synchronization with the drive pulses A timing generator that generates and outputs
When the image data from the pre-processing unit is input, the image data is passed through when the output stop position signal from the timing generator is invalid, and is discontinuous when the output stop position signal is valid A continuous data generation unit that converts the image data input in step S to generate continuous image data;
An analog front-end device comprising: a digital data output unit that receives the image data generated by the continuous data generation unit and transfers and outputs the image data to an external digital signal processing device.   The timing generator temporarily stops a horizontal pixel signal readout pulse when setting the exposure control period of the solid-state image sensor to less than one horizontal period, and determines the accumulated charge amount of the solid-state image sensor during the stop period. The analog front end device according to claim 1, wherein after the control pulse is output, the horizontal pixel signal readout pulse is restarted.   The continuous data generation unit sets a time obtained by multiplying the number of times output of image data is stopped within one horizontal period and the number of clocks of one stop period as a minimum group delay for processing, for one stop period. The clock delay devices are connected as many times as the number of stops, and the continuous image data is generated by selecting image data before the delay of one stop period at the stop position in order from the beginning of one horizontal period. The analog front end device according to claim 2.   The continuous data generation unit is equipped with a memory having a recording capacity of one horizontal period or more of valid data, and the solid-state image sensor is used when the image data is written to the memory sequentially from the beginning of one horizontal period. The invalid data portion at the output stop position is discarded and written, and the reading of the image data from the memory is continuously performed to output the continuous image data. An analog front-end device according to any one of the above.   The continuous data generation unit is equipped with a memory having a recording capacity of one horizontal period or more of valid data, and the solid-state image sensor is used when the image data is written to the memory sequentially from the beginning of one horizontal period. 4. The writing is performed in a state including invalid data at the output stop position, and reading of the image data from the memory skips the invalid data portion and outputs the continuous image data. An analog front-end device according to any one of the above.   The digital data output unit reads the continuous image data from the memory in a parallel data format or a serial data format at a readout timing of n times a pixel clock (n is a natural number of 2 or more) in a horizontal blanking period. The analog front end device according to claim 4 or 5.   The analog front end device according to any one of claims 1 to 6, wherein the timing generator outputs the output stop position signal as a timing flag signal.   The analog front end device according to any one of claims 1 to 6, wherein the timing generator outputs the output stop position signal as an address signal using a counter value that operates during one horizontal period.   The analog front end device according to any one of claims 1 to 6, wherein the timing generator and the continuous data generation unit each include a register that independently sets an output stop position of the solid-state imaging sensor.   An imaging apparatus comprising: the analog front-end device according to claim 1; the solid-state imaging sensor; the digital signal processing device; a lens and a monitor.

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