JP2008028604A - Multiplexing processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve the desired number of multiplexings without using a buffer amplifier having high performance. <P>SOLUTION: A multiplexing system 10 comprises a multiplexing unit 1, a multiplexing control unit 5, a signal adjusting unit 6, a clock adjusting unit 4, a DAC unit 2, and a sample holding unit 3. The multiplexing unit 1 multiplexes digital data D1 to D4 on a time-division basis to generate multiplexed data DOUT. The multiplexing control unit 5 generates preSH and preSEL signals based upon a CS signal and an SCLK signal. The signal adjusting unit 6 delays the preSH and preSEL signals respectively and outputs SH and SEL signals. The clock adjusting unit 4 delays a SCLK signal and outputs a DACCLK signal. The DAC unit converts the multiplexed data DOUT into a DACOUNT signal in synchronism with the DACCLK signal. The sample holding unit 3 samples and holds the DACOUNT signal in parallel based upon the SH and SEL signals to demultiplex the signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multiplexing processing system that performs signal processing on a plurality of digital data using a one-channel D / A converter and a plurality of channels of sample and hold circuits.

  FIG. 11 is a diagram showing a configuration of a general digital I / F liquid crystal panel drive system. In FIG. 11, an image sensor 100 converts a captured image into an imaging signal that is an electrical signal. An analog front end (AFE) 101 performs noise removal and preamplifier processing on an input image signal. An output signal from the AFE 101 is converted into digital data by an analog / digital converter (ADC) 102, and image processing such as gamma correction is performed by a microprocessor (μP) 103. At this time, the image data is output as color difference signal (YUV) data. The μP 103 generates a timing control signal for adjusting the output timing of the liquid crystal panel display (RGB) signal in order to cope with the control signal in the subsequent processing and various liquid crystal (LCD) panels 109. Thereafter, the image data is converted into RGB data by the YUV → RGB conversion circuit 104. At the time of output, RGB output timing is controlled by a signal from the timing adjustment circuit 105. The timing adjustment circuit 105 also outputs conversion clocks for the DACs 106a to 106c. Each RGB data is converted into an analog signal by the DACs 106a to 106c and displayed on the LCD panel 109 via the low pass filters (LPF) 107a to 107c and the drivers (DRV) 108a to 108c. However, the digital I / F liquid crystal panel drive system requires a DAC circuit and a DAC conversion clock control circuit as many as the number of signals in order to process a plurality of digital data.

  In the D / A converter of the conventional example described in Patent Document 1, D / A conversion is performed after multiplexing digital data of a plurality of channels into one channel, and an analog signal is separated and output by a sample and hold circuit. The area of the integrated circuit was reduced.

Japanese Patent Laid-Open No. 2002-76892 (FIG. 1).

  However, in the D / A converter of the conventional example, when the operating frequency is increased by increasing the number of channels to be multiplexed in a system for multiplexing a plurality of digital data, the sample hold for demultiplexing as follows: There was a problem that the buffer amplifier in the circuit had to be improved in performance. For example, when four digital data are multiplexed, the sample-and-hold circuit must operate at four times the frequency at the time of demultiplexing, and if such a high-performance buffer amplifier is used, current consumption and circuit area are reduced. There was a problem that increased.

  An object of the present invention is to solve the above problems and to provide a multiplexing processing system capable of realizing a desired multiplexing number without using a high-performance buffer amplifier.

  According to a first aspect of the present invention, there is provided a multiplexing processing system for time-division multiplexing a plurality of input digital data to generate and output multiplexed data, and a control signal and a clock signal input from the outside. A plurality of sample and hold control signals and a plurality of sample and hold selection signals, and a plurality of sample and hold control signals and a plurality of sample and hold selection signals that are input, A signal adjusting means for delaying the delay time and outputting the delayed sample hold control signal and the delayed sample hold selection signal; and delaying the clock signal input from the outside by a second delay time; A clock adjusting means for outputting a clock signal; and the multiplexed data is analyzed in synchronization with the delayed clock signal. Conversion and output to the analog signal, and based on the delayed sample and hold control signal and the delayed sample and hold selection signal, the analog signal is sampled and held in parallel and demultiplexed and output. And a sample hold means.

  In the multiplexing processing system, the multiplexing unit time-divides each digital data by the number of the digital data, and sequentially selects each time-divided digital data based on an input multiplexing selection signal. It is characterized by time division multiplexing by outputting.

  In the multiplexing processing system, the conversion means is a current addition type D / A converter.

  Further, in the multiplexing processing system, the sample and hold means includes the same number of separation circuits as the plurality of digital data, and the separation circuits are connected in parallel to each other and based on the delayed sample and hold control signal. A plurality of demultiplexing sample hold circuits for sequentially sampling and holding the analog signals at different timings in all the demultiplexing demultiplexing sample hold circuits in the sample hold means, and the plurality of demultiplexing demultiplexing circuits An output selection circuit that is connected to a subsequent stage of the sample hold circuit and selects and outputs an analog signal sampled and held by each of the demultiplexing sample hold circuits based on the delayed sample hold selection signal; It is characterized by that.

  Still further, in the multiplexing processing system, the multiplexing control means counts the clock signal with a predetermined multiple bit length and outputs the multiple bit length count value; and the output total A first comparing means for generating and outputting the plurality of sample and hold control signals each having a predetermined value when the numerical value and each different value represented by the plurality of bit lengths are compared and matched; When the value of a predetermined bit position of the output count value is compared with each value that can be taken at the bit position, two sample hold selection signals each having a predetermined value are generated and output. And a first delay circuit that outputs the respective sample and hold selection signals from the second comparison means with a delay time different from each other. The sample hold control signals from the first comparison means and the sample hold selection signals input from the second comparison means and the first delay circuit are delayed by a third delay time. And a second delay circuit for outputting.

  Further, in the multiplexing processing system, the signal adjustment means may be configured such that the output timings of the delayed sample hold control signals and the delayed sample hold selection signals do not overlap each other. It includes a plurality of first non-overlapping circuits for adjusting the timing of each delayed sample hold control signal and each delayed sample hold selection signal. Here, the first non-overlapping circuit and the clock adjusting means include an inverter circuit, first and second NOR logic circuits, a third delay circuit, and a fourth delay circuit, and are substantially mutually connected. The inverter circuit inverts and outputs an input signal, and the first NOR logic circuit includes the input signal and the output signal from the fourth delay circuit. A NOR logic operation is performed on the signal, and a signal of the operation result is output to the second NOR logic circuit via the third delay circuit, and the third NOR logic circuit receives a signal from the inverter circuit. And an output signal from the third delay circuit, a NOR logic operation is performed, and a signal of the operation result is output to the first NOR logic circuit via the fourth delay circuit. And

  Furthermore, in the multiplexing processing system, the first delay time of the signal adjusting means is longer than the second delay time of the clock adjusting means.

  In the multiplexing processing system, the multiplexing control means controls whether or not to simultaneously output at least two sample hold selection signals among the plurality of sample hold selection signals based on the control signal. It is characterized by.

  Further, in the multiplexing processing system, each digital data includes an RGB signal for liquid crystal panel display.

  Still further, in the multiplexing processing system, each of the digital data includes a liquid crystal panel display luminance signal.

  Therefore, according to the multiplexing processing system of the present invention, a plurality of digital data are multiplexed, then D / A converted, and sampled and held in parallel for the converted analog signal, multiplexed and separated for output. Since the holding means is provided, the number of D / A converters can be reduced and the operating frequency at the time of sample holding can be lowered. Thus, a desired multiplexing number can be realized without using a high-performance buffer amplifier in the sample hold means.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  FIG. 1 is a block diagram showing an example of the configuration of a multiplexing processing system 10 according to an embodiment of the present invention. In FIG. 1, a multiplexing processing system 10 includes a multiplexing unit 1, a current addition type digital / analog conversion (DAC) unit 2, a sample hold unit 3, a clock adjustment unit 4, a multiplexing control unit 5, and a signal adjustment unit. 6, in particular, a sample hold unit 3 configured as shown in FIG. 4.

  Multiplexing unit 1 receives digital data D1 to D4 of a plurality of channels, and inputs the digital data D1 to D4 in an order based on a multiplexing selection signal (hereinafter referred to as a PSEL signal) from multiplexing control unit 5. It is time-division multiplexed onto a single channel signal and output as a digitally multiplexed data signal (hereinafter referred to as DOUT signal). The digital data D1 to D3 are RGB signals for liquid crystal panel display, and the digital data D4 is a luminance signal for liquid crystal panel display. The DAC unit 2 receives the DOUT signal from the multiplexing unit 1 and the DAC clock signal (hereinafter referred to as the DACCLK signal) from the clock adjustment unit 4, and converts the DAC signal to an analog signal in synchronization with the DACCLK signal. Then, an analog multiplexed signal (hereinafter referred to as a DACOUT signal) is output. The clock adjustment unit 4 receives a system clock signal having a period of 1T (hereinafter referred to as an SCLK signal), performs non-overlapping processing to be described later on the SCLK signal, adds an analog delay amount, and serves as a DACCLK signal. The data is output to the DAC unit 2.

  The multiplexing control unit 5 is based on the input control signals CS and SCLK signals, and the pre-adjustment sample-and-hold control signals preSH1a to preSH4a and preSH1b to preSH4b (hereinafter referred to as “pre-adjustment”) before being adjusted by the signal adjustment unit 6. , And the pre-adjustment sample hold selection signals preSEL1a to preSEL4a and preSEL1b to preSEL4b (hereinafter referred to as preSEL signals). The signal adjustment unit 6 performs delay processing and non-overlapping processing on the input preSH signal and preSEL signal in accordance with the output timing of the DACOUT signal, and performs adjusted sample hold control signals SH1a to SH4a, SH1b to SH4b ( Hereinafter, it is referred to as an SH signal) and adjusted sample hold selection signals SEL1a to SEL4a, SEL1b to SEL4b (hereinafter referred to as SEL signals). The sample hold unit 3 demultiplexes the DACOUT signal input from the DAC unit 2 based on the SH signal and the SEL signal from the signal adjustment unit 6 and outputs the demultiplexed signals as a plurality of demultiplexed signals VOUT1, VOUT2, VOUT3, and VOUT4. (Details will be described later).

  FIG. 2 is a block diagram showing a detailed configuration of the multiplexing unit 1 of FIG. In FIG. 2, the multiplexing unit 1 includes a 4-input selector 12. The selector 12 inputs four digital data D1 to D4 and a 2-bit PSEL signal for selecting any one of the digital data, and determines the order of multiplexing each digital data according to the PSEL signal. In this order, the digital data D1 to D4 are time-division multiplexed and a 1-channel multiplexed signal is output.

  FIG. 3 is a block diagram showing a detailed configuration of the clock adjustment unit 4 of FIG. In FIG. 3, the clock adjusting unit 4 includes 2-input NOR logic circuits 52 and 53 and inverter circuits 51 and 54 to 59. The SCLK signal is input to one input terminal of the NOR logic circuit 52, and the output signal of the inverter circuit 59 is input to the other input terminal. The output signal of the NOR logic circuit 52 is output to one input terminal of the NOR logic circuit 53 via the inverter circuits 54 to 56. The SCLK signal inverted by the inverter circuit 51 is input to the other input terminal of the NOR logic circuit 53. The output signal of the NOR logic circuit 53 is output as a DACCLK signal via the inverter circuits 57-59. The output signal of the inverter circuit 59 is fed back to the other input terminal of the NOR logic circuit 52. Since the configuration of the clock adjusting unit 4 is a known general non-overlapping circuit, a detailed description thereof is omitted. The non-overlapping circuit changes only the duty ratio without changing the period of the input signal. In the case of the above configuration, the non-overlapping circuit operates so as to shorten the on-duty (the ratio of the on period in one period).

  FIG. 4 is a block diagram showing a detailed configuration of the sample hold unit 3 of FIG. In FIG. 4, the sample hold unit 3 includes separation circuits 40a to 40d. The separation circuit 40a includes a first multiplexing / separation sample / hold circuit composed of a switch 41a, a capacitance 43a, and a buffer amplifier 45a, and a second multiplexing composed of a switch 41b, a capacitance 43b, and a buffer amplifier 45b. The sample-and-hold circuit for separation, and the sample-and-hold circuit for output selection constituted by the switches 42a and 42b, the capacitance 44, and the buffer amplifier 46 are included. The first and second demultiplex / separate sample and hold circuits are connected in parallel to each other, and an output selection sample and hold circuit is connected to the subsequent stage thereof. The output selection sample hold circuit selects and outputs the DACOUT signal sampled and held by the first and second demultiplexing sample hold circuits. In FIG. 4, the output selection sample-and-hold circuit has a sample-and-hold function by the capacitance 44 and the buffer amplifier 46. However, the output selection sample-and-hold circuit is not limited to this and may be an output selection circuit from which the capacitance 44 and the buffer amplifier 46 are removed. Good.

  The switches 41a and 41b are controlled to be turned on and off by the adjusted sample and hold control signals SH1a and SH1b, respectively. The switches 42a and 42b are controlled to be turned on and off by the adjusted sample hold selection signals SEL1a and SEL1b, respectively. Capacitances 43a and 43b are charged when switches 41a and 41b are on, respectively. Capacitance 44 is charged when switch 42a or 42b is on. With this configuration, the DACOUT signal input after the switch 41a or 41b is turned on is sampled and held by the capacitance 43a and the buffer amplifier 45a, and the capacitance 43b and the buffer amplifier 45b, respectively. The sampled DACOUT signal is output as a demultiplexed signal VOUT1 when the switches 41a and 41b are turned off and the switches 42a and 42b are turned on, respectively. Each of the separation circuits 40b to 40d in FIG. 4 has the same configuration as the above-described separation circuit 40a and operates in the same manner. However, the switches 41a and 41b of the separation circuits 40b to 40d are controlled to be turned on and off by adjusted sample and hold control signals SH2a to SH4a and SH2b to SH4b, respectively, instead of the adjusted sample and hold control signals SH1a and SH1b. The switches 42a and 42b of the separation circuits 40b to 40d are controlled to be turned on and off by the adjusted sample and hold selection signals SEL2a to SEL4a and SEL2b to SEL4b, respectively, instead of the adjusted sample and hold selection signals SEL1a and SEL1b.

  FIG. 5 is a block diagram showing a detailed configuration of the multiplexing control unit 5 of FIG. In FIG. 5, the multiplexing control unit 5 includes a 3-bit counter 31, a comparison unit 32, a D flip-flop circuit 33, a selector unit 34, and an output flip-flop circuit 35. Here, the control signal CS input from the outside is a bus signal in which a reset signal used in the 3-bit counter 31 and a simultaneous output selection signal used in the selector unit 34 are combined. The 3-bit counter 31 repeatedly counts “000” to “111” of 3 bits in synchronization with the input SCLK signal and outputs a count value. The 3-bit counter 31 resets the count value to “000” when the reset signal included in the control signal CS becomes high level. In the present embodiment, a description is given taking an example of multiplexing four digital data, so a 3-bit counter is used, but the number of bits of the count value is changed according to the number of input digital data. Also good. Specifically, the number of bits may be any number that can generate a bit pattern more than twice the number of input digital data. The lower 2 bits of the output signal of the 3-bit counter 31 are output as a PSEL signal to the multiplexing unit 1, and the multiplexing unit 1 time-division-multiplexes a plurality of digital data D1 to D4 according to the 2-bit signal. Control the order of conversion. The comparison unit 32 includes comparators 32a to 32j. The comparators 32a to 32h compare the input signal from the 3-bit counter 31 with a 3-bit value held in advance, and output a high level signal only when they match. The comparators 32i and 32j compare the most significant bit (MSB) of the input signal from the 3-bit counter 31 with the 1-bit value held in advance, and output a high level signal only when they match. To do. Output signals of the comparators 32a to 32h are input to the output flip-flop circuit 35 as a signal pSH1a, a signal pSH1b, a signal pSH2a, a signal pSH2b, a signal pSH3a, a signal pSH3b, a signal pSH4a, and a signal pSH4b, respectively. The output signals of the comparators 32i and 32j are input to the output flip-flop circuit 35 as a signal pSEL1a and a signal pSEL1b, respectively.

  The D flip-flop circuit 33 includes one-stage D flip-flops 33a and 33b, two-stage D flip-flops 33c and 33d, and three-stage D flip-flops 33e and 33f. The D flip-flops 33a, 33c, and 33e delay the input signal from the comparator 32i of the comparison unit 32 by the number of stages of each flip-flop and output the delayed signal. The D flip-flops 33b, 33d, and 33f delay the input signal from the comparator 32j of the comparison unit 32 by the number of stages of the respective flip-flops, and output the delayed signals. Output signals of the flip-flops 33e and 33f are input to the output flip-flop circuit 35 as a signal pSEL4a and a signal pSEL4b, respectively. The selector unit 34 includes two-input selectors 34a to 34d, and each of the selectors 34a to 34d selects and outputs one of the input signals according to the simultaneous output selection signal included in the control signal CS. That is, the selectors 34a to 34d determine whether to match the output timing of the digital data D2 and D3 with the output timing of the digital data D1 according to the simultaneous output selection signal. The output signals of the selectors 34a to 34d are input to the output flip-flop circuit 35 as a signal pSEL2a, a signal pSEL2b, a signal pSEL3a, and a signal pSEL3b, respectively. The output flip-flop circuit 35 delays and outputs each input signal by one clock in order to match the output timing of the DACOUT signal from the DAC unit 2. The output signals of the output flip-flop circuit 35 are output to the signal adjustment unit 6 as the pre-adjustment sample hold control signal preSH and the pre-adjustment sample hold selection signal preSEL, respectively.

  FIG. 6 is a block diagram showing a detailed configuration of one non-overlapping circuit 6-1 among a plurality of non-overlapping circuits constituting the signal adjustment unit 6 of FIG. 6, the non-overlapping circuit 6-1 includes 2-input NOR logic circuits 82 and 83 and inverter circuits 81 and 84 to 91. The preSH1a signal is input to one input terminal of the NOR logic circuit 82, and the output signal of the inverter circuit 89 is input to the other input terminal. The output signal of the NOR logic circuit 82 is output to one input terminal of the NOR logic circuit 83 via the inverter circuits 84 to 86. The preSH1a signal inverted by the inverter circuit 81 is input to the other input terminal of the NOR logic circuit 53. The output signal of the NOR logic circuit 83 is output as the SH1a signal via the inverter circuits 87-91. The output signal of the inverter circuit 89 is fed back to the other input terminal of the NOR logic circuit 82. The configuration of the non-overlapping circuit 6-1 includes inverter circuits 90 and 91, and the clock adjustment unit shown in FIG. 3 is the same except that the output signal is delayed by the delay time by the inverter circuits 90 and 91. Since the configuration is the same as that of FIG. The signal adjustment unit 6 includes non-overlapping circuits 6-2 to 6-16 (not shown) in addition to the non-overlapping circuit 6-1 shown in the drawing, but these non-overlapping circuits 6-2 to 6-16 are also shown. Has a configuration similar to that of the non-overlapping circuit 6-1, and detailed description thereof will be omitted. However, the non-overlapping circuits 6-2 to 6-16 replace the pre-adjustment sample hold control signal preSH1a with the pre-adjustment sample hold control signals preSH2a to preSH4a, preSH1b to preSH4b, and the pre-adjustment sample hold selection signals preSEL1a to preSEL4a, PreSEL1b to preSEL4b are input, respectively, and adjusted sample hold control signals SH2a to SH4a, SH1b to SH4b and adjusted sample hold selection signals SEL1a to SEL4a, SEL1b to SEL4b are output instead of the adjusted sample hold control signal SH1a.

  FIG. 7 is a timing chart for explaining operations in the clock adjustment unit 4 and the signal adjustment unit 6 of FIG. As shown in FIG. 7, the clock adjusting unit 4 outputs a DACCLK signal obtained by delaying the input SCLK signal by a predetermined time and changing the on-duty with the configuration shown in FIG. The DOUT signal input to the DAC unit 2 is delayed by a predetermined period in synchronization with the DACCLK signal and output as a DACOUT signal. The signal adjustment unit 6 outputs the SH signal and the SEL signal obtained by delaying the input preSH signal and the preSEL signal by a predetermined time and changing the on-duty with the configuration shown in FIG. The SH signal and the SEL signal are delayed by the same delay time as the delay time of the DACCLK signal from the SCLK signal plus a delay time T1 by the inverters 90 and 91 in FIG. That is, as shown in FIG. 7, the rise of the SH1a signal is further delayed by a predetermined time T1 from the rise of the DACCLK signal. Since the SH1a signal controls the switch 41a for sample-holding the DACOUT signal in the sample-and-hold circuit 3 shown in FIG. 4, the period during which the SH1a signal is high, that is, the sample-and-hold circuit ON time is determined by the predetermined data of the DACOUT signal. By keeping it within, the operation of the sample and hold circuit can be stabilized.

  FIG. 8 is a timing chart showing changes of each signal during normal operation of the multiplexing processing system 10 according to the embodiment of the present invention. In FIG. 8, a plurality of digital data D1 to D4, a signal CNT3b, a DOUT signal, and changes of signals pSH1a to pSH4a, pSH1b to pSH4b, pSEL1a to pSEL4a, and pSEL1b to pSEL4b generated in the multiplexing control unit 5 It is shown. The DOUT signal is a signal obtained by multiplexing a plurality of digital data D1 to D4. Here, the digital data D1 to D4 are all in phase, and maintain their data length (4T in this embodiment) according to the number of digital data. Further, the output timings of the three digital data D1 to D3 have a correlation with each other, and the digital data D4 has no correlation with the digital data D1 to D3. Ta and Tb in the figure indicate the difference between the output timing of the digital data D1 and the output timing of the digital data D2, and the difference between the output timing of the digital data D1 and the output timing of the digital data D3, respectively. To do.

  As shown in FIG. 8, when the value of the signal CNT3b from the 3-bit counter 31 of the multiplexing control unit 5 is “000”, the signal pSH1a becomes high level. When the value of the signal CNT3b is “100”, the signal pSH1b becomes high level. Similarly, each signal corresponding to the value of the signal CNT3b is sequentially set to the high level. Further, when the value of the re-higher order bit of the signal CNT3b is “0”, the signal pSEL1a becomes high level, and when the re-higher order bit of the signal CNT3b is “1”, the signal pSEL1b becomes high level. The signals pSEL2a, pSEL3a, and pSEL4a are signals obtained by delaying the signal pSEL1a by 1T, 2T, and 3T, respectively. Similarly, the signals pSEL2b, pSEL3b, and pSEL4b are signals obtained by delaying the signal pSEL1b by 1T, 2T, and 3T, respectively.

  The signals pSH1a to pSH4a, pSH1b to pSH4b, pSEL1a to pSEL4a, and pSEL1b to pSEL4b are delayed by one clock by the output flip-flop circuit 35 of the multiplexing control unit 5 to match the output timing with the DOUT signal. This is a preSEL signal. Thereafter, the output timing and on-duty are further adjusted by the signal adjustment unit 6 and input to the sample hold unit 3 as the SH signal and the SEL signal, and are used for demultiplexing of the DACOUT signal. As described with reference to FIG. 4, the demultiplexing sample and hold unit 3 includes a demultiplexing and demultiplexing sample and hold circuit having two upper and lower stages, and each of the signals shown in FIG. The sample hold circuit alternately samples and holds. This ensures a long switch-on time in the output selection sample-and-hold circuit in the subsequent stage, greatly relaxes the specifications of the buffer amplifier characteristics in the sample-and-hold circuit, and speeds up the system even without a high-performance buffer amplifier. It becomes possible to cope with.

  FIG. 9 is a timing chart showing changes of each signal when the D1-D3 simultaneous output setting of the multiplexing processing system 10 according to the embodiment of the present invention is set. 9, the output timing of signals pSEL1a to pSEL3a and pSEL1b to pSEL3b is different from the timing chart of FIG. As shown in FIG. 9, after the digital data D1 to D3 having correlation with each other are separated by the signals pSH1a to pSH3a, the signals pSEL1a to pSEL3a are turned on at the same timing, thereby outputting the multiplexed separated signals VOUT1 to VOUT3. Timing will be at the same time. The signals pSEL1a to pSEL3a can be controlled to be turned on at the same timing by the simultaneous output selection signal included in the control signal CS input to the selector unit 34 of the multiplexing control unit 5. At this time, the digital data D4 may be dummy data having no correlation with the digital data D1 to D3, or may be other data such as a liquid crystal panel display luminance signal. The same applies to the signals pSEL1b to pSEL3b. As described above, the output timings of the demultiplexed signals VOUT1 to VOUT3 can be made simultaneous by making the output timings of the signals pSEL1a to pSEL3a and pSEL1b to pSEL3b simultaneous.

  As described above, according to the multiplexing processing system according to this embodiment, the sample-and-hold unit 3 that samples and holds analog signals in parallel and demultiplexes and outputs them is provided. The number of D / A converters can be reduced to one, so that the circuit scale can be reduced and the speed of the system can be increased without imposing a burden on the buffer amplifier in the sample hold unit 3. In addition, by using a multi-bit D / A converter with one channel instead of a plurality of conventional D / A converters, the resolution of the system can be increased at a relatively low cost. Furthermore, the power consumption can be reduced by using the waste current of the current adding type DAC unit 2 for offset generation for adjusting the input range of the buffer amplifier.

  As an application example of the multiplexing processing system 10 according to the present embodiment, for example, as shown in FIG. 10, the multiplexing processing system 10 may be incorporated in a digital I / F liquid crystal panel driving device. FIG. 10 is a block diagram showing an example of the configuration of a digital I / F liquid crystal panel drive device incorporating the multiplexing processing system 10 according to the present embodiment. The digital I / F liquid crystal panel drive system of FIG. 10 is a multiplexing according to this embodiment in place of the timing adjustment circuit 105 and the DACs 106a, 106b, and 106c of the general digital I / F liquid crystal panel drive system shown in FIG. The processing system 10 is different from the general digital I / F liquid crystal panel driving system shown in FIG. Other components are the same as those of the general digital I / F liquid crystal panel driving system shown in FIG.

  In the present embodiment, the multiplexing processing system 10 inputs 4-channel digital data D1 to D4. However, the present invention is not limited to this number, and the multiplexing processing system 10 may input digital data having less than four channels or digital data having more than four channels.

  Further, in the present embodiment, the digital data D1 to D3 are RGB signals for liquid crystal panel display, and the digital data D4 is a luminance signal for liquid crystal panel display. However, the present invention is not limited to this configuration, and the digital data D1 to D4 may be signals other than these, and any one or more of the digital data may be dummy data.

  As described above in detail, according to the multiplexing processing system of the present invention, a plurality of digital data is multiplexed and then D / A converted, and the converted analog signal is sampled and held in parallel and multiplexed and separated. Since the sample and hold means for outputting is provided, the number of D / A converters can be reduced and the operating frequency at the time of sample and hold can be lowered. Thus, a desired multiplexing number can be realized without using a high-performance buffer amplifier in the sample hold means. The multiplexing processing system according to the present invention is useful, for example, in RGB signal processing for liquid crystal panels having a multiplexing processing method of a plurality of digital data such as a digital I / F.

It is a block diagram which shows an example of a structure of the multiplexing processing system 10 which concerns on one Embodiment of this invention. It is a block diagram which shows the detailed structure of the multiplexing part 1 of FIG. It is a block diagram which shows the detailed structure of the clock adjustment part 4 of FIG. It is a block diagram which shows the detailed structure of the sample hold part 3 of FIG. It is a block diagram which shows the detailed structure of the multiplexing control part 5 of FIG. It is a block diagram which shows the detailed structure of one non-overlapping circuit 6-1 among the non-overlapping circuits which comprise the signal adjustment part 6 of FIG. 2 is a timing chart for explaining operations in a clock adjustment unit 4 and a signal adjustment unit 6 in FIG. 1. It is a timing chart which shows change of each signal at the time of normal operation of multiplexing processing system 10 concerning one embodiment of the present invention. It is a timing chart which shows the change of each signal at the time of D1-D3 simultaneous output setting of the multiplexing processing system 10 which concerns on one Embodiment of this invention. 1 is a block diagram showing a configuration of a digital I / F liquid crystal panel drive system incorporating a multiplexing processing system 10 according to an embodiment of the present invention. It is a figure which shows the structure of a general digital I / F liquid crystal panel drive system.

Explanation of symbols

1 ... Multiplexer,
2 ... DAC section,
3 ... Sample hold section,
4 ... Clock adjustment unit,
5: Multiplexing control unit,
6 ... Signal adjustment unit,
10: Multiplexing processing system,
12 ... 4 input selector,
31 ... 3-bit counter,
32 ... Comparison part,
33 ... flip-flop circuit,
34 ... selector section,
35. Output flip-flop circuit,
40a to 40d: separation circuit.

Claims (11)

Multiplexing means for time-division multiplexing a plurality of input digital data to generate and output multiplexed data;
Multiplexing control means for generating and outputting a plurality of sample hold control signals and a plurality of sample hold selection signals based on an externally input control signal and a clock signal;
A signal adjustment unit that delays the input plurality of sample hold control signals and the plurality of sample hold selection signals by a first delay time, and outputs the delayed sample hold control signal and the delayed sample hold selection signal, respectively. When,
A clock adjusting means for delaying the clock signal input from the outside by a second delay time and outputting the delayed clock signal;
Conversion means for converting the multiplexed data into an analog signal and outputting the same in synchronization with the delayed clock signal;
Sample hold means for sampling and holding the analog signal in parallel, demultiplexing and outputting based on the delayed sample and hold control signal and the delayed sample and hold selection signal; Multiplexing processing system.   The multiplexing means time-division multiplexes by time-dividing each digital data by the number of the digital data, and sequentially selecting and outputting each time-division digital data based on an input multiplex selection signal. The multiplex processing system according to claim 1, wherein   3. The multiplexing processing system according to claim 1, wherein the conversion means is a current addition type D / A converter. The sample hold means includes
The same number of separation circuits as the plurality of digital data are provided,
Each of the separation circuits is
Based on the delayed sample and hold control signal, a plurality of demultiplex and demultiplex sample and hold circuits in the sample and hold means sequentially sample and hold the analog signals at different timings based on the delayed sample and hold control signal. A sample and hold circuit for demultiplexing, and
The analog signal sampled and held by each of the demultiplexing sample-and-hold circuits is selected and output based on the delayed sample-and-hold selection signal. 4. The multiplexing processing system according to claim 1, further comprising an output selection circuit. The multiplexing control means includes:
A multi-bit counter that counts the clock signal with a predetermined multiple-bit length and outputs a count value with the multiple-bit length;
A first sample-and-hold control signal having a predetermined value is generated and output when the output count value and the different values represented by the plurality of bit lengths are compared and matched. A comparison means;
When the value of a predetermined bit position of the output count value is compared with each value that can be taken at the bit position, two sample hold selection signals each having a predetermined value are generated and output. A second comparison means;
A first delay circuit that outputs the sample-hold selection signals from the second comparison means with a delay time different from each other;
The sample hold control signals from the first comparison means and the sample hold selection signals input from the second comparison means and the first delay circuit are delayed by a third delay time. 5. The multiplexing processing system according to claim 1, further comprising a second delay circuit that outputs the second delay circuit.   The signal adjusting means includes the analog signal and the delayed sample-and-hold control signals and the delayed sample-and-hold control signals and the delayed sample-and-hold selection signals so that the output timings of the delayed and delayed sample-and-hold selection signals do not overlap each other. 6. The multiplexing processing system according to claim 1, further comprising a plurality of first non-overlapping circuits that adjust timing with each of the delayed sample-and-hold selection signals. . The first non-overlapping circuit and the clock adjusting means include an inverter circuit, first and second NOR logic circuits, a third delay circuit, and a fourth delay circuit, and are substantially similar to each other. Having a circuit configuration of
The inverter circuit inverts and outputs an input signal,
The first NOR logic circuit performs a NOR logic operation on the input signal and an output signal from the fourth delay circuit, and outputs a signal of the operation result through the third delay circuit. Output to the second NOR logic circuit;
The third NOR logic circuit performs a NOR logic operation on a signal from the inverter circuit and an output signal from the third delay circuit, and a signal of the operation result is passed through the fourth delay circuit. 7. The multiplexing processing system according to claim 6, wherein the data is output to the first NOR logic circuit.   The multiplexing processing system according to claim 1, wherein the first delay time of the signal adjustment unit is longer than the second delay time of the clock adjustment unit. .   9. The multiplexing control unit controls whether or not to simultaneously output at least two sample-hold selection signals among the plurality of sample-hold selection signals based on the control signal. The multiplexing processing system according to any one of the above.   10. The multiplexing processing system according to claim 1, wherein each of the digital data includes an RGB signal for displaying a liquid crystal panel. The multiplexing processing system according to claim 1, wherein each digital data includes a liquid crystal panel display luminance signal.

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