JP2008026169A - Measuring method of duty ratio variation and circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To measure a duty ratio variation of a delay cell. <P>SOLUTION: This method makes connection between an input and an output of the delay cell in a loop shape so as to cause a monopulse signal which has a shorter pulse width than a delay time of the delay cell to be input and circulated in the loop, and counts the number of the monopulse signals which circulate in the loop, and then a duty ratio variation of the delay cell is measured based on the counted value. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method and a circuit for measuring duty breakdown of a pulse signal passing through a delay cell.

  For example, in a memory controller that inputs / outputs data to / from a DDR (double data rate) type memory device, the writing / reading is controlled in synchronization with both rising and falling edges of the clock signal, thereby increasing the speed. I am trying.

  FIG. 4 is a diagram showing the configuration of the data output side (read side) of this memory controller. The n-bit data DQ read from the memory device is synchronized with the strobe signal DQS1. This data DQ is taken into one n-bit flip-flop 3 by the rising edge of the strobe signal DQS2 generated by delaying the phase of the strobe signal DQS1 by the delay cell 1 by π / 2, and the other n by the falling edge. It is taken into the flip-flop 4 having a bit configuration. The delay cell 1 is composed of a DLL circuit or the like.

FIG. 5 shows a timing chart of the operation on the data output side. If the strobe signal DQS2 is exactly delayed by π / 2 with respect to the data DQ, the setup time Ts1 and hold time Th1 of the data D1 in the flip-flop 3 and the setup time Ts2 and hold time Th2 of the data D2 in the flip-flop 4 Can be secured sufficiently (see, for example, FIG. 2B of Patent Document 1).
JP 2001-337862 A

  However, when the characteristics of the delay cell 1 are insufficient and the fall time becomes shorter than the rise time, the setup time Ts1 and hold time Th1 of the data D1 in the flip-flop 3 as shown in the timing chart of FIG. Can be ensured, but the setup time Ts2 of the data D2 in the flip-flop 4 is shortened, and the data D2 may not be captured.

  On the other hand, when the fall time becomes longer than the rise time, as shown in the timing chart of FIG. 7, even if the setup time Ts1 and hold time Th1 of the data D1 in the flip-flop 3 can be secured, the flip-flop 4, the hold time Th2 of the data D2 becomes shorter, and the data D2 cannot be captured.

  As described above, when a difference occurs between the rise time and the fall time of the delay cell 1, the duty ratio of the probe signal delayed there collapses from 50%, and either the setup time or the hold time in the flip-flop is cut. As a result, the timing margin is reduced and a malfunction may occur.

  In the above description, the data output side of the memory controller has been described. However, on the data input side (write side), if there is a difference between the rise time and fall time of the delay cell that delays the strobe signal, the data is taken into the flip-flop. A similar problem arises.

  As described above, if there is a difference between the rise time and the fall time of the pulse signal passing through the delay cell, the timing margin is reduced, and a malfunction may occur particularly in a system with a high data transfer rate. It is important to measure the duty ratio collapse at the inspection stage.

  An object of the present invention is to provide a duty ratio measuring method and circuit that can easily measure the duty ratio collapse of a delay cell.

In order to achieve the above object, the duty ratio collapse measuring method according to the first aspect of the present invention includes a loop connection between the input and output of a delay cell, and a pulse width shorter than the delay time of the delay cell in the loop. The single pulse signal is inputted to circulate the loop, the number of the single pulse signals circulated through the loop is counted, and the duty ratio collapse of the delay cell is measured by the count value.
The invention according to claim 2 is the duty ratio collapse measurement method according to claim 1, wherein the count value when the H pulse signal is input as the single pulse, and the count value when the L pulse signal is input. And a small count value of both count values is employed as a value indicating the duty ratio collapse of the delay cell.
According to a third aspect of the present invention, there is provided a circuit for measuring a duty ratio collapse comprising a loop circuit for connecting the input and output of a delay cell in a loop, and a single pulse signal having a pulse width shorter than the delay time of the delay cell in the loop circuit. A single pulse signal input means for inputting, a selection means for switching the single pulse signal input means between active and inactive, and a counting means for counting the single pulse signal circulating in the loop circuit To do.
According to a fourth aspect of the present invention, there is provided a first NAND circuit in which one input is connected to a single pulse signal input terminal and the other input is connected to a select signal input terminal via an inverter. A second NAND circuit having one input connected to the select signal input terminal and the other input connected to the output of the delay cell; and one input connected to the output of the first NAND circuit; A third NAND circuit having an input connected to an output of the second NAND circuit and an output connected to an input of the delay cell; an output pulse signal of the third NAND circuit; and an output pulse signal of the delay cell Or a counter that counts an output pulse signal of the second NAND circuit.

  According to the duty ratio breakdown measuring method and circuit of the present invention, the delay cell input / output is connected in a loop so that a single pulse signal is circulated in the loop and the number of cycles of the single pulse signal is counted. The pulse width of the single pulse signal decreases earlier as the cell duty ratio collapses, and the pulse signal cannot be counted earlier, so that the degree of duty collapse can be measured by the count value.

  FIG. 1 is a circuit diagram showing a configuration of a duty ratio measuring circuit according to one embodiment of the present invention. 1 is a delay cell composed of a DLL circuit or the like with a delay time T1, 2 is an m-bit counter, INV1 is an inverter, NAND1 to NAND3 are NAND circuits, IN1 is a single pulse signal input terminal, and IN2 is a select signal input terminal. . The pulse signal at the output node A of the NAND circuit NAND3 is input to the counter 2 and the delay cell 1. In relation to the claims, the loop circuit includes a delay cell 1, a NAND circuit NAND2, and a NAND3. The single pulse signal input means includes a single pulse signal input terminal IN1, a NAND circuit NAND1, and a NAND circuit NAND3. The selection means is composed of a select signal input terminal IN2, an inverter INV1, and NAND circuits NAND1 to NAMND3.

  In this duty ratio measuring circuit, since the output of the delay cell 1 is initially “L”, when both the input terminals IN1 and IN2 are “L”, the outputs of the NAND circuits NAND1 and NAND2 are “H” and the NAND circuit The output of the NAND3 is “L”. In this state, as shown in FIG. 2, when the H pulse signal S1 that becomes “H” for a time T2 shorter than the delay time T1 of the delay cell 1 is input to the single pulse signal input terminal IN1, the H pulse signal S1 is The signal is inverted by the NAND circuit NAND1, further inverted by the NAND circuit NAND3, output to the node A as the H pulse signal S3, and input to the delay cell 1. As a result, the H pulse signal delayed from the delay cell 1 by the time T1 is input to the NAND circuit NAND2.

  Therefore, as shown in FIG. 2, the select signal S2 is applied before the output of the delay cell 1 rises to “H” after the H pulse signal S1 is applied to the input terminal IN1, that is, after the time T2 has elapsed and before the time T1 has elapsed. In addition, when switching from “L” to “H” (at this time, the counter 2 also switches its reset signal from “L” to “H”), the NAND circuit NAND1 closes the gate at the time of switching, Since the NAND circuit NAND2 opens the gate, the H pulse signal output from the delay cell 1 will be inverted by the NAND gate NAND2 and further inverted by the NAND gate NAND3 and output to the node A as the H pulse signal S3. That is, the NAND gates NAND2 and NAND3 function as an inverter, and the H pulse signal S3 input to the delay cell 1 circulates through the loop of the NAND gates NAND2 and NAND3 and the delay cell 1.

  At this time, if there is a difference between the rising edge and the falling edge of the delay cell 1, the pulse width of the H pulse signal S3 of the node A is shortened every time it goes around the loop, and the duty ratio further collapses. Since the NAND gates NAND2 and NAND3 function as inverters, they are canceled even if there is a difference between their rise and fall. The H pulse signal S3 of the node A is counted by the counter 2 every cycle, but when the pulse width is not recognized by the input FF (flip-flop) of the counter 2, the operation of the counter 2 is stopped, and the count value is changed there. Stop.

Therefore, the duty ratio collapse X is defined as follows. The pulse width of the H pulse S1 is T2, the minimum recognition pulse width of the input FF of the counter 2 is Tmin, and the count value when the counter 2 is stopped is C.
X = (T2-Tmin) / C (1)
Can be obtained.

  Here, for example, assuming that the pulse width T2 of the H pulse signal S1 is 5 ns, the delay time T1 of the delay cell 1 is 10 ns, and the bit width of the counter 2 is 10 bits, the counter 2 counts up to 1024 under this condition. Since it is possible, the circulation can be repeated until “10 ns × 1024 = 10 μs” has elapsed.

When the rise time of the delay cell 1 is longer than the fall time, as shown in FIG. 2, the pulse width of the H pulse signal S3 at the node A is sequentially shortened. For example, the counter 2 cannot recognize the pulse p1. Assume that the count operation is stopped at a count value of 256 (= 80 h). Assuming that the duty ratio collapse X at this time is the minimum pulse width Tmin = 0.5 ns recognized by the input FF of the counter 2,
X = (5 ns-0.5 ns) /256=17.5 ps (2)
It becomes. This indicates that every time the H pulse signal passes through the delay cell 1, the pulse width is cut by 17.5 ps.

  On the other hand, when the rise time of the delay cell 1 is smaller than the fall time, as shown in FIG. 3, instead of the H pulse signal S1 of FIG. 2, an L pulse signal S1 ′ having a pulse width T2 is used as a single pulse input terminal. Input to IN1. Also in this case, after the L pulse signal S1 ′ is input, the select signal S2 is switched from “L” to “H” (the reset signal of the counter 2 is also switched from “L” to “H”), and the single pulse is input. When the terminal IN1 is disconnected, the L pulse signal S1 ′ circulates through the loop of the NAND gates NAND2 and NAND3 and the delay cell 1.

  At this time, the pulse width of the L pulse signal S3 'at the node A is shortened every time it goes around the loop, and the duty ratio is lost. The L pulse signal S3 'is counted by the counter 2 every round. For example, if the counter 2 cannot recognize the pulse p2 under the same conditions as above, and the count operation is stopped at a count value of 256 (= 80h), the duty ratio collapse X is expressed by the equation (2). Each time the L pulse signal S1 ′ passes through the delay cell 1, its pulse width is reduced by 17.5 ps.

As described above, in order to measure the collapse of the duty ratio of the delay cell 1, it is desirable to input both the H pulse signal and the L pulse signal to the input terminal IN1. When the count value when the H pulse signal S1 is input is C1, the count value when the L pulse signal S1 ′ is input is C2, and the maximum count value of the counter 2 is Cmax,
(a): C1 <C2
(b): C1> C2
(c): C1 = C2 = Cmax
There may be cases. It can be said that the smaller the count value is, the larger the duty ratio collapses. Therefore, in (a), C1 represents the duty ratio collapse of the delay cell, and in (b), C2 represents the duty ratio collapse. In the case of (c), it can be said that the duty ratio collapse is very small.

  Therefore, the count values C1 and C2 are compared with a preset threshold value Cth by a comparison circuit (not shown), and when the count values C1 and C2 are lower than the threshold value Cth, a determination circuit for generating a flag NG. By providing an LSI tester, it is possible to perform a pre-shipment test of delay cells to select delay cells with a large duty ratio breakdown, and to reduce malfunctions after product shipment.

  In the duty ratio collapse measurement circuit of FIG. 1 described above, the single pulse taken into the counter 2 is not limited to the output from the NAND circuit NAND3, but may be taken from the output side of the delay cell 1, the output side of the NAND circuit NAND2, or the like. good.

It is a circuit diagram of a duty ratio collapse measuring circuit of one example of the present invention. FIG. 2 is a waveform diagram in the case where the duty ratio collapse is measured by inputting an H pulse to a single pulse input terminal of the duty ratio collapse measuring circuit of FIG. 1. FIG. 2 is a waveform diagram when measuring the duty ratio breakdown by inputting an L pulse to the single pulse input terminal of the duty ratio breakdown measurement circuit of FIG. 1. It is a block diagram which shows the structure on the data output side of a memory controller. FIG. 5 is a waveform diagram when the duty ratio of a strobe signal is normal on the data output side of FIG. 4. FIG. 5 is a waveform diagram when the rising time of the strobe signal is larger than the falling time on the data output side of FIG. 4. FIG. 5 is a waveform diagram when the rising time of the strobe signal is smaller than the falling time on the data output side of FIG. 4.

Explanation of symbols

1: Delay cell 2: Counter 3, 4: Flip-flop

Claims (4)

  The single pulse that circulates the loop by connecting the input and output of the delay cell in a loop, and inputting a single pulse signal having a pulse width shorter than the delay time of the delay cell in the loop to circulate the loop. A duty ratio collapse measuring method, wherein the number of signals is counted and the duty ratio collapse of the delay cell is measured by the count value. In the duty ratio collapse measuring method according to claim 1,
The count value when the H pulse signal is input as the single pulse and the count value when the L pulse signal is input are obtained, and the smaller count value of both count values is lost in the duty ratio of the delay cell. A duty ratio collapse measuring method, characterized in that it is adopted as a value indicating.   A loop circuit for connecting the input and output of the delay cell in a loop; a single pulse signal input means for inputting a single pulse signal having a pulse width shorter than the delay time of the delay cell in the loop circuit; and the single pulse signal input A duty ratio collapse measuring circuit comprising: selecting means for switching the means to active / inactive; and counting means for counting the single pulse signal that circulates in the loop circuit. A first NAND circuit having one input connected to the single pulse signal input terminal and the other input connected to the select signal input terminal via an inverter;
A second NAND circuit having one input connected to the select signal input terminal and the other input connected to the output of the delay cell;
A third NAND circuit having one input connected to the output of the first NAND circuit, the other input connected to the output of the second NAND circuit, and an output connected to the input of the delay cell;
A counter that counts the output pulse signal of the third NAND circuit, the output pulse signal of the delay cell, or the output pulse signal of the second NAND circuit;
A duty ratio collapse measuring circuit comprising:

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