JP2008022611A - Voltage conversion circuit, boost circuit, and nonvolatile memory device - Google Patents

Abstract

The present invention provides a booster circuit that can improve boosting efficiency while suppressing an increase in circuit scale.
A voltage conversion circuit includes a voltage conversion capacitor provided between a charge storage node NC and a voltage change node ND whose voltage level changes based on a clock CK, a second power supply VDD, and a charge storage. A precharge circuit 42 provided between the node NC and the precharge circuit 42 for precharging the charge storage node NC, and provided between the charge storage node NC and the output node NF, and stored in the charge storage node NC during the charge transfer period. A charge transfer circuit 44 that transfers the generated charge to the output node NF, and a discharge circuit 46 that is provided between the output node and the first power supply VSS and discharges the output node NF during the discharge period.
[Selection] Figure 1

Description

  The present invention relates to a voltage conversion circuit, a booster circuit, and a nonvolatile memory device.

  In recent years, with the miniaturization of the manufacturing process, the withstand voltage of the transistor is lowered, and the power supply voltage supplied to the integrated circuit device tends to be lowered. When the power supply voltage is lowered in this way, there arises a problem that a circuit such as a DRAM that has been operated at a high power supply voltage cannot be operated at a low power supply voltage.

  Conventionally, a booster circuit that boosts a voltage by a charge pump method is known. This booster circuit is used to generate a high voltage necessary for a write operation of a nonvolatile memory device such as an EEPROM or a flash memory, or to generate a high voltage necessary for an operation of an LCD driver.

  In this charge pump type booster circuit, the voltage is boosted using a charge pump capacitor. According to this booster circuit, when the power supply voltage is VDD and the generated boosted voltage is VPP, the boosted voltage VPP corresponding to the magnitude of the power supply voltage VDD and the number of stages of the charge pump unit can be generated.

However, in practice, there is a problem that the boosting efficiency of the booster circuit is reduced due to charge leakage in each charge pump unit or the substrate bias effect of the transistor.
Japanese Patent Application Laid-Open No. 2004-247689

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a voltage conversion circuit having a high boosting efficiency, a boosting circuit, and a nonvolatile memory device including the same. It is in.

  The present invention provides a voltage conversion capacitor provided between a charge storage node and a voltage change node whose voltage level changes based on a clock, and changes the voltage level of the charge storage node according to the voltage level of the clock. , Provided between the second power supply and the charge storage node, and provided between the charge storage node and the output node, and a precharge circuit for precharging the charge storage node, A charge transfer circuit for transferring the charge stored in the charge storage node to the output node; a discharge circuit provided between the output node and the first power supply for discharging the output node in a discharge period; This relates to a voltage conversion circuit including

  According to the present invention, in the discharge period, the discharge node discharges the output node. The precharge circuit precharges the charge storage node. The voltage level of the charge storage node changes according to the voltage level of the clock by a voltage conversion capacitor provided between the voltage change node and the charge storage node. In the charge transfer period, the charge stored in the charge storage node is transferred to the output node by the charge transfer circuit. As a result, a conversion clock obtained by boosting the voltage level of the clock can be output to the output node, and a voltage conversion circuit with high boosting efficiency can be realized.

  According to the present invention, the precharge circuit includes a P-type precharge transistor provided between a second power supply and the charge storage node, the gate, drain and substrate of which are connected to the charge storage node. It may be included.

  In this way, it is possible to prevent a situation in which the voltage at the charge storage node and the voltage at the output node are lowered due to an increase in threshold voltage due to the substrate bias effect, and boost efficiency can be improved.

  In the present invention, the charge transfer circuit includes a P-type charge transfer transistor provided between the charge storage node and the output node and turned on during the charge transfer period. An N-type discharge transistor that is provided between the output node and the first power supply and is turned on during the discharge period; wherein the voltage conversion capacitor is formed of a low withstand voltage capacitor, the precharge transistor, The charge transfer transistor may be formed of a low breakdown voltage transistor, and the discharge transistor may be formed of a high breakdown voltage transistor having a higher breakdown voltage than the low breakdown voltage capacitor and the low breakdown voltage transistor.

  In this way, if the voltage conversion capacitor is formed of a low breakdown voltage capacitor and the precharge transistor and the charge transfer transistor are formed of a low breakdown voltage transistor, the boosting efficiency can be improved while reducing the circuit scale.

  In the present invention, the precharge circuit may include a P-type precharge transistor that is provided between a second power supply and the charge storage node and whose gate is connected to the output node.

  In this way, when the output node is discharged by the discharge circuit, the P-type precharging transistor whose output node is connected to the gate can be completely turned on. Therefore, it is possible to prevent a situation in which the voltage at the charge storage node decreases by the threshold voltage of the transistor and the voltage at the output node decreases by the threshold voltage, and the boosting efficiency can be improved.

  In the present invention, the charge transfer circuit includes a P-type charge transfer transistor provided between the charge storage node and the output node and turned on during the charge transfer period. An N-type voltage difference adjusting transistor provided between the output node and the first power supply and having the second power supply input to the gate, and the voltage difference adjustment between the output node and the first power supply. An N-type discharge transistor that is provided in series with the register for use and is turned on during the discharge period may be included.

  If the voltage difference adjusting transistor is provided in this way, the voltage difference applied to the discharge transistor can be reduced, and the discharge transistor can be formed of a low breakdown voltage transistor.

  The present invention also includes the voltage conversion circuit described above and a charge pump capacitor connected to the output node of the voltage conversion circuit, based on a clock whose voltage level is converted by the voltage conversion circuit. A booster circuit that performs a boosting operation, wherein the voltage conversion capacitor is formed of a low breakdown voltage capacitor, the precharge transistor is formed of a low breakdown voltage transistor, and the charge pump capacitor is the low breakdown voltage capacitor, The present invention relates to a booster circuit formed by a high breakdown voltage capacitor having a higher breakdown voltage than a low breakdown voltage transistor.

  According to the present invention, the boosting operation is performed based on the clock whose voltage level is converted by the voltage conversion circuit, so that the boosting efficiency of the boosting circuit can be improved. Further, according to the present invention, the voltage conversion capacitor is formed of a low breakdown voltage capacitor and the precharge transistor is formed of a low breakdown voltage transistor, so that boosting efficiency can be improved while minimizing the scale of the circuit.

  The present invention also includes the voltage conversion circuit described above and a charge pump capacitor connected to the output node of the voltage conversion circuit, based on a clock whose voltage level is converted by the voltage conversion circuit. A boosting circuit that performs a boosting operation, wherein the voltage conversion capacitor is formed of a low breakdown voltage capacitor, and the precharge transistor, the charge transfer transistor, the voltage difference adjustment transistor, and the discharge transistor are low breakdown voltage transistors. The charge pump capacitor is related to a boost circuit formed by the low breakdown voltage capacitor and the high breakdown voltage capacitor having a breakdown voltage higher than that of the low breakdown voltage transistor.

  According to the present invention, the boosting operation is performed based on the clock whose voltage level is converted by the voltage conversion circuit, so that the boosting efficiency of the boosting circuit can be improved. According to the present invention, the voltage conversion capacitor is formed of a low breakdown voltage capacitor, and the precharge transistor, the charge transfer transistor, the voltage difference adjustment transistor, and the discharge transistor are formed of a low breakdown voltage transistor. Boosting efficiency can be improved while minimizing the scale.

  In addition, the present invention includes first and second voltage conversion circuits as the voltage conversion circuit described in any of the above, and boosts based on a clock whose voltage level is converted by the first and second voltage conversion circuits. A booster circuit that performs an operation, wherein the first voltage conversion circuit includes a first voltage conversion capacitor, a first voltage conversion capacitor, a precharge circuit, a charge transfer circuit, and a discharge circuit. A precharge circuit, a first charge transfer circuit, and a first discharge circuit, wherein the second voltage conversion circuit includes the voltage conversion capacitor, the precharge circuit, the charge transfer circuit, and the discharge circuit. The first voltage conversion circuit includes two voltage conversion capacitors, a second precharge circuit, a second charge transfer circuit, and a second discharge circuit. During the period in which the first charge transfer circuit performs charge transfer from the first charge accumulation node to the first output node of the first voltage conversion circuit, the second voltage conversion circuit includes the second charge conversion circuit. The second discharge circuit discharges the second output node of the second voltage conversion circuit, and the second charge transfer circuit of the second voltage conversion circuit includes a second output node of the second voltage conversion circuit. In the period during which charge transfer from the two charge storage nodes to the second output node is performed, the first discharge circuit of the first voltage conversion circuit has the first discharge circuit of the first voltage conversion circuit. The present invention relates to a booster circuit that discharges an output node.

  According to the present invention, the boosting operation is performed based on the clock whose voltage level is converted by the first and second voltage conversion circuits, so that the boosting efficiency of the boosting circuit can be improved. In addition, it is possible to prevent such a situation that the charge of the first charge storage node is discharged to the first power supply side or the charge of the second charge storage node is discharged to the first power supply side, thereby improving the boosting efficiency. it can.

  In the present invention, the first and second voltage conversion circuits are supplied with a first clock and a second clock that is non-overlapping with respect to the first clock. When the second clock is at the second voltage level and the second clock is at the first voltage level, the first charge transfer circuit is connected to the first output node from the first charge storage node. The second discharge circuit discharges the second output node, the first clock is at the first voltage level, and the second clock is at the second voltage level. The second charge transfer circuit transfers the charge from the second charge storage node to the second output node, and the first discharge circuit transfers the first output node. The discharger It may be carried out.

  In this case, the first and second clocks are effectively utilized in the non-overlapping relationship, so that the charge on the first charge storage node is discharged to the first power source side, It is possible to prevent such a situation that the charge of the charge storage node is discharged to the first power supply side.

  In the present invention, the first charge transfer circuit is provided between the first charge accumulation node and the first output node, and the first clock is at a second voltage level. A P-type first charge transfer transistor which is turned on; the first discharge circuit is provided between the first output node and a first power supply; and the second clock is a second clock An N-type first discharge transistor that is turned on when the voltage level is equal to the first voltage level, and the second charge transfer circuit is provided between the second charge storage node and the second output node. And a P-type second charge transfer transistor that is turned on when the second clock is at the second voltage level, the second discharge circuit including the second output node and the first output node. Provided between Serial first clock may include a N-type second discharge transistor of which is turned on when a second voltage level.

  In this way, the first and second voltage conversion circuits can convert the voltage level of the clock using the first and second clocks.

  The present invention further includes charge pump first and second capacitors connected to the first and second output nodes of the first and second voltage conversion circuits, the first capacitor and the A circuit other than the first voltage conversion capacitor of the first voltage conversion circuit is disposed between the first voltage conversion capacitor, the second capacitor, and the second voltage conversion capacitor. Between these, a circuit other than the second voltage conversion capacitor of the second voltage conversion circuit may be arranged.

  In this way, efficient layout along the signal flow becomes possible, and adverse effects of parasitic capacitance and the like on the boosting operation can be reduced.

  In the present invention, the first and second capacitors are formed by high withstand voltage capacitors, and the first and second voltage conversion capacitors are formed by low withstand voltage capacitors having a withstand voltage lower than that of the high withstand voltage capacitor. You may do it.

  In this way, it is possible to arrange high voltage elements such as high voltage capacitors together in the high voltage region, and arrange low voltage elements such as low voltage capacitors in the low voltage region.

  The present invention further includes a clock supply circuit that generates and supplies a charge pump clock, and the first and second voltage conversion circuits are provided between the first and second capacitors and the clock supply circuit. May be arranged.

  In this way, efficient layout along the signal flow becomes possible, and adverse effects such as noise from the clock supply circuit can be minimized.

  In the present invention, a wiring region is provided between the clock supply circuit and the first and second voltage conversion circuits, in which a signal line including a clock signal line supplied by the clock supply circuit is provided. You may do it.

  This makes it possible to increase the distance between the clock supply circuit and the first and second voltage conversion circuits and the first and second capacitors by using this wiring region. It is possible to minimize adverse effects such as noise from the supply circuit.

  Further, the present invention provides a memory cell array in which a plurality of nonvolatile memory cells are arranged, and writing, reading, and erasing of data in the nonvolatile memory cells based on a boosted voltage generated by any of the boosting circuits described above. And an access control circuit for performing at least one of the following.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Voltage Conversion Circuit FIG. 1A shows a configuration example of the voltage conversion circuit 40 of the present embodiment. The voltage conversion circuit 40 includes a voltage conversion capacitor CC, a precharge circuit 42, a charge transfer circuit 44, and a discharge circuit 46.

  The voltage conversion capacitor CC is provided between the charge storage node NC and the voltage change node ND. The voltage change node ND is a node whose voltage level changes based on the clock CK. The voltage conversion capacitor CC changes the voltage level of the charge storage node NC (the voltage level after precharging) according to the voltage level of the clock CK.

  The precharge circuit 42 is provided between VDD (second power supply in a broad sense) and the charge storage node NC, and precharges the charge storage node NC based on VDD. Specifically, the precharge circuit 42 is provided between the VDD and the charge storage node NC, and has a P type (second conductivity type in a broad sense) whose gate, drain, and substrate are connected to the charge storage node NC. A precharge transistor TC is included. The charge storage node NC is precharged to VDD-VTH by the precharge transistor TC.

  The charge transfer circuit 44 is provided between the charge storage node NC and the output node NF. Then, in the charge transfer period (for example, the period in which CK is at the H level), the charge stored in the charge storage node NC is transferred to the output node NF. Specifically, the charge transfer circuit 44 includes a P-type charge transfer transistor TD that is provided between the charge storage node NC and the output node NF and is turned on during the charge transfer period. That is, the node NE is connected to the gate of the charge transfer transistor TD, and an inverted signal of the clock CK is supplied. Therefore, when the clock CK is at H level, the node NE is at L level, the charge transfer transistor TD is turned on, and charge transfer is performed. The substrate of the charge transfer transistor TD is connected to the charge storage node NC.

  The discharge circuit 46 is provided between the output node NF of the voltage conversion circuit 40 and VSS (first power supply in a broad sense), and discharges the output node NF in a discharge period (for example, a period in which CK is at L level). I do. Specifically, the discharge circuit 46 includes an N-type (first conductivity type in a broad sense) discharge transistor TE that is provided between the output node NF and VSS and is turned on during the discharge period. That is, the node NE is connected to the gate of the discharge transistor NE, and an inverted signal of the clock CK is supplied. Therefore, when the clock CK is at L level, the node NE becomes H level, the discharge transistor TE is turned on, and charge is discharged.

  As shown in FIG. 1B, when the voltage level of the clock CK is 0 V (first voltage level, VSS), the charge storage node NC is precharged to VDD-VTH by the precharging transistor TC. The At this time, since the charge transfer transistor TD is off, it is possible to prevent a situation where the charge of the charge storage node NC is discharged. Further, since the discharge transistor TE is on, the charge of the output node NF is discharged, and thereby the output node NF becomes 0V.

  On the other hand, when the voltage level of the clock CK becomes VDD (second voltage level), the voltage level of the charge storage node NC is boosted by VDD due to capacitive coupling by the capacitor CC, and becomes 2VDD−VTH. At this time, since the charge transfer transistor TD is on and the discharge transistor TE is off, the charge precharged to the charge storage node NC is transferred to the output node NF. As a result, the output node NF can be boosted from 0V to 2VDD−VTH.

  When the voltage level of the clock CK becomes VDD and the charge accumulation node NC becomes 2VDD−VTH, the precharging transistor TC is a diode whose reverse bias direction is the direction from the charge accumulation node NC to the power supply VDD. Functions as a diode-connected transistor. Therefore, it is possible to prevent a situation in which the charge accumulated in the charge accumulation node NC flows backward to the power supply VDD side, and the boosting efficiency of the voltage conversion circuit 40 can be improved.

  According to the voltage conversion circuit 40 of FIG. 1A, the amplitude of the clock CK can be converted to about 2VDD only by using the voltage conversion capacitor CC and the transistors TC, TD, TE, and the like. Therefore, voltage conversion with high boosting efficiency can be realized with a simple and small circuit configuration.

  In FIG. 1A, only a voltage difference of about VDD is applied to the voltage conversion capacitor CC and the transistors TC and TD. Therefore, the voltage conversion capacitor CC can be formed of a low breakdown voltage (LV) capacitor, and the transistors TC and TD can be formed of a low breakdown voltage (LV) transistor. Accordingly, the layout area of these capacitors and transistors can be reduced, and the circuit scale can be reduced.

  The discharge transistor TE is formed of a high breakdown voltage (HV) transistor having a higher breakdown voltage than the low breakdown voltage capacitor and the low breakdown voltage transistor because a voltage difference of about 2VDD is applied.

  In FIG. 1A, the precharge transistor TC of the precharge circuit 42 is formed of a P-type transistor. Therefore, it is possible to prevent a substrate bias effect which becomes a problem when the precharge transistor TC is formed of an N-type transistor. Therefore, it is possible to prevent the threshold voltage VTH from becoming high due to the substrate bias effect and the output voltage at the output node NF from becoming small, and boost efficiency can be improved.

2. First Modification of Voltage Conversion Circuit FIG. 2A shows a first modification of the voltage conversion circuit 40. In FIG. 2A, the precharge circuit 42 is provided between the VDD (second power supply) and the charge storage node NC, and a P-type precharge transistor TC2 whose gate is connected to the output node NF. including. Other than that, the circuit configuration is the same as in FIG. The substrate of the transistor TC2 is connected to the charge storage node NC. The transistor TC2 is formed of a low breakdown voltage transistor.

  In FIG. 1A, the voltage of the charge storage node NC becomes VDD−VTH in the precharge period in which the clock CK becomes 0V. That is, in FIG. 1A, since the transistor TC needs to be turned on in the precharge period, the voltage of the charge storage node NC is lower than VDD by the threshold voltage VTH.

  On the other hand, in FIG. 2A, since the discharge transistor TE is turned on in the precharge period in which the clock CK is 0V, the output node NF becomes 0V. Therefore, since the P-type precharge transistor TC2 to which the voltage of 0 V is input to the gate is completely turned on, the charge storage node NC is precharged to VDD instead of VDD-VTH. . Therefore, in the charge transfer period in which the clock CK is set to VDD and the charge transfer transistor TD is turned on, the voltage of the output node NF is boosted to 2VDD instead of 2VDD−VTH. At this time, since the P-type precharge transistor TC2 to which the voltage of 2VDD is inputted to the gate is completely turned off, the backflow of charges from the charge storage node NC to the VDD power supply can be prevented.

  As described above, in FIG. 1A, only the clock CK ′ having the amplitude of 2VDD−VTH is obtained, whereas according to the first modification of FIG. 2A, the clock CK having the amplitude of 2VDD is obtained. 'Can be obtained, so the boosting efficiency can be improved.

3. Second Modification of Voltage Conversion Circuit FIG. 2B shows a second modification of the voltage conversion circuit 40. In FIG. 2B, the discharge circuit 46 is provided between the output node NF and VSS (first power supply), and is for N-type voltage difference adjustment in which VDD (second power supply) is input to the gate. Includes a transistor TF. The discharge circuit 46 includes an N-type discharge transistor TG that is provided in series with the voltage difference adjusting transistor TF between the output node NF and VSS and is turned on during the discharge period.

  In FIG. 2B, the output node NF is connected to the gate of the precharging transistor TC2 as in FIG. 2A, but the gate of the transistor TC2 is charged as shown in FIG. Variations connected to the storage node NC are also possible.

  According to the second modification of FIG. 2B, the N-type transistors TF and TG constituting the discharge circuit 46 can be formed by low breakdown voltage transistors. Therefore, the layout area of the voltage conversion circuit 40 can be reduced as compared with the case where the transistor TE constituting the discharge circuit 46 is formed of a high breakdown voltage transistor as shown in FIG. That is, in FIG. 2B, the capacitor CC and the transistors TC2, TD, TF, and TG constituting the voltage conversion circuit 40 can all be formed by low withstand voltage transistors. Accordingly, the gate length of the transistors TF and TG can be reduced to reduce the layout area, and the capacitor CC and the transistors TC2, TD, TF, and TG can be laid out collectively in a low withstand voltage region, so that FIG. Compared to the layout area, the layout area can be reduced.

4). Third Modification Example of Voltage Conversion Circuit FIG. 3A shows a third modification example of the voltage conversion circuit and the booster circuit including the voltage conversion circuit.

  In the voltage conversion circuit of FIG. 1A, the same node NE is connected to the transistors TD and TE. Therefore, in the transition period of the voltage level of the node NE, a situation occurs in which both the transistors TD and TE are turned on, and a through current is generated. When such a through current is generated, the charge stored in the storage node NC is discharged to the VSS side, and the boosting efficiency is deteriorated. According to the third modification of FIG. 3A, such a problem can be solved.

  In FIG. 3A, a first voltage conversion circuit 40-11 includes a capacitor CC11 as a first voltage conversion capacitor, a first precharge circuit, a first charge transfer circuit, and a first discharge circuit, respectively. , Transistor TC11, transistor TD11, transistors TF11 and TG11. The second voltage conversion circuit 40-12 includes a capacitor CC12, a transistor TC12, and a transistor as a second voltage conversion capacitor, a second precharge circuit, a second charge transfer circuit, and a second discharge circuit, respectively. Includes TD12, transistors TF12 and TG12.

  FIG. 3A shows the case where the configuration of FIG. 2B is adopted as each of the voltage conversion circuits 40-11 and 40-12, but FIG. 3A and FIG. A configuration or the like may be adopted.

  In FIG. 3A, as indicated by B1 in FIG. 3B, the transistor TD11 (first charge transfer circuit) of the voltage conversion circuit 40-11 is connected to the charge storage node NC11 (first charge storage node). In a period (first charge transfer period) in which charge is transferred to the output node NF11 (first output node), as shown by B2, the transistor TG12 (second discharge circuit) of the voltage conversion circuit 40-12 Discharges the output node NF12 (second output node). That is, during the period in which the charge transfer transistor TD11 of the voltage conversion circuit 40-11 is turned on, the discharge transistor TG12 of the voltage conversion circuit 40-12 is turned on and discharge is performed.

  Further, as indicated by B3 in FIG. 3B, the transistor TD12 (second charge transfer circuit) of the voltage conversion circuit 40-12 is changed from the charge storage node NC12 (second charge storage node) to the output node NF12 (second charge transfer node). In the period (second charge transfer period) during which charge is transferred to the output node of the output node), the transistor TG11 (first discharge circuit) of the voltage conversion circuit 40-11 is connected to the output node NF11 (first discharge circuit) as indicated by B4. The first output node) is discharged. That is, during the period in which the charge transfer transistor TD12 of the voltage conversion circuit 40-12 is turned on, the discharge transistor TG11 of the voltage conversion circuit 40-11 is turned on and discharge is performed.

  As shown at B5 and B6 in FIG. 3B, the voltage conversion circuits 40-11 and 40-12 include a clock CK11 (first clock) and a clock that is non-overlapping with respect to the clock CK11. CK12 (second clock) is supplied.

  The charge transfer circuit 40-11 is provided between the charge storage node NC11 and the output node NF11, and turns on when the clock CK11 is at the H level (second voltage level). A transistor TD11 is included. Also included is an N-type discharge transistor TG11 which is provided between the output node NF11 and VSS (first power supply) and is turned on when the clock CK12 is at the H level. That is, the inverted signal of the clock CK11 is input to the gate of the transistor TD11, and the non-inverted signal of the clock CK12 is input to the gate of the transistor TG11.

  The charge transfer circuit 40-12 includes a P-type charge transfer transistor TD12 which is provided between the charge storage node NC12 and the output node NF12 and is turned on when the clock CK12 is at the H level. Also included is an N-type discharge transistor TG12 which is provided between the output node NF12 and VSS and is turned on when the clock CK11 is at the H level. That is, an inverted signal of the clock CK12 is input to the gate of the transistor TD12, and a non-inverted signal of the clock CK11 is input to the gate of the transistor TG12.

  When the clock CK11 is at H level (second voltage level) and the clock CK12 is at L level (first voltage level) as shown at B5, the inverted signal of CK11 is shown at B1. The transistor TD11 (first charge transfer circuit) input to the gate is turned on, and charge transfer from the charge storage node NC11 to the output node NF11 is performed. As indicated by B2, the transistor TG12 (second discharge circuit) to which the non-inverted signal of the clock CK11 is input is turned on, and the output node NF12 is discharged.

  On the other hand, when the clock CK12 is at the H level (second voltage level) as shown at B6 and the clock CK11 is at the L level (first voltage level), the inverted signal of CK12 is shown at B3. The transistor TD12 (second charge transfer circuit) that is input to the gate is turned on, and charge transfer from the charge storage node NC12 to the output node NF12 is performed. As indicated by B4, the transistor TG11 (first discharge circuit) to which the non-inverted signal of the clock CK12 is input is turned on, and the output node NF11 is discharged.

  As described above, according to the third modification, as shown by B1 and B4 in FIG. 3B, the period in which the charge transfer transistor TD11 of the voltage conversion circuit 40-11 is turned on and the discharge transistor TG11 are The on period is non-overlapping, and an off period as shown in B7 always exists between these periods. Therefore, it is possible to prevent a situation in which the accumulated charge of the charge accumulation node NC11 is discharged to the VSS side due to the through current through the transistors TD11 and TG11. Similarly, as indicated by B2 and B3 in FIG. 3B, the period in which the charge transfer transistor TD12 of the charge transfer circuit 40-12 is turned on and the period in which the discharge transistor TG12 is turned on are non-overlapping. Between these periods, an off period as indicated by B8 always exists. Therefore, it is possible to prevent a situation in which the accumulated charge of the charge accumulation node NC12 is discharged to the VSS side due to the through current through the transistors TD12 and TG12, and the boosting efficiency can be improved.

  In particular, the third modification focuses on the existence of non-overlapping clocks CK11 and CK12 necessary for the charge pump operation, and effectively utilizes these non-overlapping clocks CK11 and CK12 to prevent a through current. There is a feature. That is, the clocks CK11 and CK12 are mutually used between the voltage conversion circuits 40-11 and 40-12, and the transistor TD11 of the voltage conversion circuit 40-11 and the transistor TG12 of the voltage conversion circuit 40-12 are driven by the clock CK11. ON / OFF control. The transistor TG11 of the voltage conversion circuit 40-11 and the transistor TD12 of the voltage conversion circuit 40-12 are controlled to be turned on / off by the clock CK12 having a non-overlapping relationship with the clock CK11. In this way, the non-overlap relationship between the clocks CK11 and CK12 as shown in B5 and B6 can be effectively used to prevent the through current through the transistors TD11 and TG11 and the through current through the transistors TD12 and TG12. Boosting efficiency can be improved.

5. Booster Circuit FIG. 4 shows a configuration example of a booster circuit including the voltage conversion circuit of this embodiment. This booster circuit includes a charge pump circuit 10. The charge pump circuit 10 includes a plurality of charge pump units 20-1 to 20-N (first to Nth charge pump units in a broad sense, where N is an integer of 2 or more) connected in series. The power supply voltage VDD is input to the first-stage charge pump unit 20-1, and the last-stage charge pump unit 20-N outputs the boosted voltage VPP by the charge pump. A smoothing circuit may be provided at the output of the charge pump unit 20-N. Further, the booster circuit including the voltage conversion circuit of the present embodiment is not limited to the configuration shown in FIG. 4, and various modifications can be made.

  The booster circuit can also include a clock supply circuit 50. The clock supply circuit 50 generates charge pump clocks CK11, CK12, CK21, CK22,... CKN1, CKN2 and supplies them to the charge pump circuit 10.

  Here, the clocks CK11 and CK12, CK21 and CK22,... CKN1 and CKN2 have a non-overlapping relationship. That is, in the period when the clock CK11 is active (second voltage level, for example, H level), the clock CK12 is inactive (first voltage level, for example, L level), and in the period where the clock CK12 is active, CK11 becomes inactive. The relationship between other clocks such as CK21 and CK22 or CKN1 and CKN2 is similar.

  The clock supply circuit 50 can include a ring oscillator 54 (clock generation circuit in a broad sense). The ring oscillator 54 includes, for example, inverters (buffers) connected in series, and generates and outputs multiphase clocks RCK1, RCK2, RCK3,... RCKJ (J is an integer of 2 or more). These clocks RCK1, RCK2, RCK3,... RCKJ are clocks output from the output nodes of the inverters included in the ring oscillator 54.

  The clock supply circuit 50 can include a decoder 52. The decoder 52 decodes the multiphase clocks RCK1 to RCKJ from the ring oscillator 54 to generate clocks CK11, CK12, CK21, CK22,... CKN1, CKN2, and outputs them to the charge pump circuit 10. .

  The charge pump unit 20-1 includes a charge transfer circuit 30-1, charge pump capacitors CA11 and CA12 (first and second capacitors), and voltage conversion circuits 40-11 and 40-12 (first and second capacitors). Voltage conversion circuit). The same applies to the charge pump units 20-2... 20-N.

  The charge transfer circuit 20-1 (20-2 to 20-N) is a circuit for performing charge transfer between charge pump capacitors (and preventing backflow of charges between capacitors). Specifically, for example, charge transfer from the previous stage charge pump unit or charge transfer to the next stage charge pump unit is performed. In addition, the charge is prevented from flowing back from the capacitors CA12 to CA11.

  One ends (upper electrodes) of the charge pump capacitors CA11 and CA12 are connected to the charge transfer circuit 30-1. That is, the capacitors CA11 and CA12 are provided between the charge transfer circuit 30-1 and the voltage conversion circuits 40-11 and 40-12.

  The first voltage conversion circuit 40-11 (40-21 to 40-N1) is provided between the first clock supply node to which the first clock CK11 is supplied and the other end (lower electrode) of the capacitor CA11. Provided. The voltage conversion circuit 40-11 (sub boost circuit, level shifter) outputs a clock CK11 ′ (first conversion clock) obtained by boosting (level shifting) the voltage of the clock CK11 to the other end of the capacitor CA11. . Specifically, as shown in FIG. 5, when the clock CK11 is at the L (Low) level (first voltage level in a broad sense), the voltage conversion circuit 40-11 has the L level voltage clock CK11 ′. Is output to the other end of the capacitor CA11. When the clock CK11 is at the H (High) level (second voltage level in a broad sense), the voltage difference (VDD) between the L level and the H level (first and second voltage levels) is doubled, for example. A clock CK11 ′ of a voltage boosted to (2VDD) or about twice (2VDD−VTH) (a voltage boosted to M times (M> 1 in a broad sense)) is output to the other end of the capacitor CA11.

  The second voltage conversion circuit 40-12 (40-22 to 40-N2) is provided between the second clock supply node to which the second clock CK12 is supplied and the other end (lower electrode) of the capacitor CA12. Provided. Then, the clock CK12 '(second conversion clock) obtained by boosting the voltage of the clock CK12 is output to the other end of the capacitor CA12. Specifically, when the clock CK12 is at the L level (eg, 0 V), the voltage conversion circuit 40-12 outputs the clock CK12 'having the L level voltage to the other end of the capacitor CA12. When the clock CK12 is at the H level, the clock CK12 ′ having a voltage obtained by boosting the voltage difference (VDD) between the L level and the H level to, for example, twice (2VDD) or about twice (2VDD−VTH) Output to the other end of CA12.

  In recent years, power supply voltage tends to decrease with process miniaturization. Therefore, in order to obtain the boosted voltage VPP necessary for writing into the nonvolatile memory device using the conventional method when the power supply voltage is lowered in this way, it is necessary to increase the number of stages of the charge pump unit. This leads to an increase in circuit scale and power consumption.

  In this regard, in the present embodiment, the voltage conversion circuits 40-11 and 40-12 boost the voltages of the clocks CK11 and CK12, and the clocks CK11 ′ and CK12 ′ (first and second conversion clocks) whose voltages are boosted. ) Is output to capacitors CA11 and CA12. Therefore, the charge pump unit 20-1 can perform a charge pump operation using the capacitors CA11 and CA12 based on the clocks CK11 'and CK12' having an amplitude of 2VDD. Therefore, the boosting efficiency can be improved as compared with the conventional method in which the charge pump is performed with the clock having the amplitude of VDD, and a high boosted voltage VPP can be obtained with the charge pump unit having a small number of stages. In addition, since the increase in circuit scale is not so large as compared with the method of supplying the original power supply voltage twice in advance, the desired boosted voltage VPP can be achieved while minimizing the increase in circuit scale and power consumption. Can be obtained.

  In the booster circuit in which the charge pump units are connected in series, the boosted voltage VPP corresponding to the magnitude of VDD-VTH and the number of stages of the charge pump unit is generated. However, in the N-type transistor of the charge pump unit close to the final stage, the threshold voltage VTH increases due to the substrate bias effect. Therefore, in the conventional booster circuit, the closer to the final stage the charge pump unit, the smaller the VDD-VTH voltage difference becomes, and the boosting efficiency deteriorates.

  In contrast, in the present embodiment, the charge pump operation is performed based on a clock whose amplitude is converted from VDD to about 2VDD. Therefore, even in a charge pump unit that can raise the saturation level of boosting, the voltage difference of 2VDD-VTH is not so small, and deterioration of boosting efficiency can be minimized.

6). Detailed Configuration Example of Charge Pump Unit FIG. 6 shows a detailed configuration example of the charge pump unit. In FIG. 6, the charge transfer circuit 30-1 (30-2 to 30-N) of the charge pump unit 20-1 includes N-type first and second transistors TA1 and TB1.

  Here, the first transistor TA1 is provided between the input node NA11 of the charge pump unit 20-1 and the output node NA12 to which one end (upper electrode) of the capacitor CA12 is connected. The gate of the capacitor CA11 is connected to the node NB11 which is one end (upper electrode) of the capacitor CA11. The second transistor TB1 is provided between the input node NA11 and the node NB11 which is one end of the capacitor CA11. The gate is connected to the output node NA12 of the charge pump unit 20-1.

  The output node NF11 of the voltage conversion circuit 40-11 is connected to the other end (lower electrode) of the capacitor CA11. The output node NF12 of the voltage conversion circuit 40-12 is connected to the other end (lower electrode) of the capacitor CA12.

  According to the configuration of FIG. 6, a clock CK11 ′ obtained by boosting the voltage of the clock CK11 by about twice is applied to the other end of the capacitor CA11, and a clock CK12 ′ obtained by boosting the voltage of the clock CK12 by about twice is applied to the capacitor CA12. Applied to the other end, a charge pump operation is performed. Therefore, the boosting efficiency in each charge pump unit can be improved, and a high boosted voltage VPP can be obtained with a charge pump unit having a small number of stages.

  Here, in FIG. 6, the capacitor CA11 functions as a sub capacitor for controlling the gate of the transistor TA1 with respect to the main capacitor CA12. For this reason, the capacitance value of the capacitor CA11 is smaller than that of the capacitor CA12.

  In FIG. 6, the capacitors CC11 and CC12 of the voltage conversion circuits 40-11 and 40-12 are formed of low withstand voltage (LV) capacitors. The transistors TC11, TD11, TC12, and TD12 are also formed of low breakdown voltage transistors. On the other hand, the charge pump capacitors CA11 and CA12 are formed of high withstand voltage (HV) capacitors having a higher withstand voltage than the low withstand voltage capacitors. The transistors TA1 and TB1 are also formed of high voltage transistors having a higher breakdown voltage than the low voltage transistors.

  The charge transfer circuit 30-1 (30-2 to 30-N) of the present embodiment is not limited to the configuration shown in FIG. 6, and various modifications are possible. For example, the configuration shown in FIG. Good. In FIG. 7, the charge transfer circuit 30-1 includes diode-connected N-type transistors TA1 and TB1. The transistor TA1 functions as a diode that prevents a reverse flow of charge from the node NA12 to NB11 while performing charge transfer from the node NB11 to NA12. That is, it functions as a diode whose forward direction is from the node NB11 to the NA12. Similarly, the transistor TB1 functions as a diode whose forward direction is from the node NA11 to the NB11.

7). Drive Waveform FIG. 8 shows an example of the drive waveform of the charge pump circuit. FIG. 8 shows a case where the clocks generated by the ring oscillator 54 in FIG. 4 are five-phase clocks RCK1 to RCK5 and the number of stages of the charge pump units 20-1 to 20-N is five (N = 5). It is an example. That is, the decoder 52 decodes the five-phase clocks RCK <b> 1 to RCK <b> 5 from the ring oscillator 54, generates clocks CK <b> 11, CK <b> 12, CK <b> 21, CK <b> 22,.

  In the drive waveform of FIG. 8, the clock supply circuit 50 has the second voltage conversion circuit of the Kth (1 ≦ K <N) charge pump unit among the charge pump units 20-1 to 20 -N. In the period in which the second clock pulse is supplied as the second clock, the second clock pulse is applied to the first voltage conversion circuit of the (K + 1) th charge pump unit next to the Kth charge pump unit. The first clock pulse having a shorter pulse width is supplied as the first clock.

  That is, during the period indicated by A1 in FIG. 8, the clock is supplied to the voltage conversion circuit 40-12 (second voltage conversion circuit) of the charge pump unit 20-1 (Kth charge pump unit) as indicated by A2. A second clock pulse having a long pulse width is supplied as CK12 (second clock). During the period indicated by A1, the voltage conversion circuit 40-21 (first voltage conversion circuit) of the charge pump unit 20-2 (K + 1th charge pump unit) subsequent to the charge pump unit 20-1 is supplied to the voltage conversion circuit 40-21. On the other hand, the first clock pulse A3 having a shorter pulse width than the second clock pulse A2 is supplied as the clock CK21 (first clock).

  Similarly, in the period indicated by A4, the clock CK22 having a long pulse width is supplied to the voltage conversion circuit 40-22 of the charge pump unit 20-2 as indicated by A5. During the period indicated by A4, the pulse width of the voltage conversion circuit 40-23 (not shown) of the charge pump unit 20-3 subsequent to the charge pump unit 20-2 is larger than that of the clock CK22 of A5. Is supplying a short clock CK31 as indicated by A6.

  As shown in the drive waveform of FIG. 8, in this embodiment, the clocks CK11 and CK12 have a non-overlapping relationship (a relationship in which the active periods do not overlap), and the clocks CK21 and CK22 also have a non-overlapping relationship. It has become. The clocks CK11 and CK21 are also non-overlapping, and the clocks CK12 and CK22 are also non-overlapping.

  According to the drive waveform of FIG. 8, the clock CK21 (CK21 ') becomes H level as indicated by A3 within the period indicated by A1 when the clock CK12 (CK12') becomes H level. Accordingly, the voltage of the node NB21 on the upper electrode side of the capacitor CA21 in FIG. 6 is increased, and the transistor TA2 is turned on. Thereby, the electric charge accumulated in the capacitor CA12 is efficiently transferred to the capacitor CA22 via the transistor TA2. At this time, since the transistor TB2 can be set off, it is possible to prevent the charge from the capacitor CA12 from leaking to the capacitor CA21 side through the transistor TB2, thereby improving the boosting efficiency.

  That is, in the drive waveform of FIG. 8, the voltage of the node NB21 is pushed up by the clock CK21 for a short period in the period in which the voltage of the node NA12 of FIG. 6 is pushed up by the clock CK12. Thus, in this short period, the transistor TA2 is turned on, and efficient charge transfer from the capacitor CA12 of the previous stage charge pump unit 20-1 to the capacitor CA22 of the next stage charge pump unit 20-2 is performed. It becomes possible. That is, since the charge transfer efficiency can be improved as compared with the technique in which the clocks CK11, CK12, CK21, and CK22 in FIG. 6 are all non-overlapping, the boosting efficiency can be improved. In particular, in the method of boosting the clock voltage by the voltage conversion circuit as in this embodiment, the boosting efficiency can be further improved by adopting the drive waveform as shown in FIG.

  The drive waveform of this embodiment is not limited to that shown in FIG. 8, and various modifications can be made. For example, in the drive waveform of FIG. 9, the clocks generated by the ring oscillator 54 of FIG. 4 are 11-phase clocks RCK1 to RCK11, and the number of stages of the charge pump units 20-1 to 20-N is 5 (N = 5). It is an example in the case of. That is, the decoder 52 decodes the 11-phase clocks RCK1 to RCK11 from the ring oscillator 54, generates clocks CK11, CK12, CK21, CK22,... CK51, CK52, and supplies them to the charge pump circuit 10. Become.

8). Example of Boost Circuit Layout FIG. 10 shows a layout example (circuit pattern arrangement example) of the booster circuit of this embodiment. In FIG. 10, the charge pump units 20-1 to 20-N (first to Nth charge pump units) are arranged (laid out) along the direction D1 (first direction). For example, in the charge pump unit 20-1 (each charge pump unit), charge pump capacitors CA11 and CA12 (first and second capacitors) are arranged along the direction D1. That is, the capacitor CA12 is disposed adjacent to the capacitor CA11 on the D1 direction side. When the direction orthogonal to the D1 direction is the D2 direction (second direction), the capacitor CA11 and the voltage conversion circuit 40-11 are arranged along the D2 direction, and the capacitor CA12 and the voltage conversion circuit 40-12 are Arranged along the direction D2. The same applies to the other charge pump units 20-2 to 20-N.

  In FIG. 10, a circuit other than the capacitor CC11 of the voltage conversion circuit 40-11 (for example, the transistor of FIG. 3A) is provided between the capacitor CA11 (first capacitor) and the capacitor CC11 (first voltage conversion capacitor). TC11, TD11, TF11, TG11) are arranged. Further, a circuit other than the capacitor CC12 of the voltage conversion circuit 40-12 (for example, the transistors TC12 and TD12 in FIG. 3A) is provided between the capacitor CA12 (second capacitor) and the capacitor CC12 (second voltage conversion capacitor). , TF12, TG12) are arranged. The same applies to the other charge pump units 20-2 to 20-N.

  Here, the capacitors CA11 and CA12 are formed of high voltage capacitors. Similarly, the charge transfer circuit 30-1 is formed by a high voltage transistor. On the other hand, the voltage conversion capacitors CC11 and CC12 are formed of a low breakdown voltage capacitor having a breakdown voltage lower than that of the high breakdown voltage capacitor. Similarly, circuits other than CC11 and CC12 of the voltage conversion circuits 40-11 and 40-12 are formed by low breakdown voltage transistors having a breakdown voltage lower than that of the high breakdown voltage transistors. The same applies to the other charge pump units 20-2 to 20-N.

  In FIG. 10, a clock supply circuit 50 that generates and supplies a charge pump clock is arranged. For example, in the charge pump unit 20-1, voltage conversion circuits 40-11 and 40-12 are arranged between the capacitors CA11 and CA12 and the clock supply circuit 50. A wiring region is provided between the clock supply circuit 50 and the voltage conversion circuits 40-11 and 40-12. In this wiring area, signal lines including signal lines of clocks (CK11 to CKN2) supplied by the clock supply circuit 50 are wired. The same applies to the other charge pump units 20-2 to 20-N.

  According to the layout of FIG. 10, the capacitors CA11 and CA12 are arranged along the direction D1. When the direction opposite to the D2 direction is the D4 direction (fourth direction), the voltage conversion circuit 40-11 is disposed on the D4 direction side of the capacitor CA11, and the voltage conversion circuit 40-12 is disposed on the D4 direction side of the capacitor CA12. Is placed. In this way, the voltage conversion circuits 40-11 and 40-12 can be arranged by effectively utilizing the space on the D4 direction side of the capacitors CA11 and CA12. The layout efficiency can be improved.

  Further, according to the layout of FIG. 10, high breakdown voltage elements (high breakdown voltage capacitors, high breakdown voltage transistors) such as capacitors CA11 and CA12 are arranged in a high breakdown voltage region, and low breakdown voltage elements such as capacitors CC11 and CC12 (low voltage). With regard to the breakdown voltage capacitor and the low breakdown voltage transistor, they can be arranged together in the low breakdown voltage region. Then, only the distance relationship between the high withstand voltage region and the low withstand voltage region in FIG. Therefore, the layout efficiency can be improved and the layout area of the booster circuit can be reduced as compared with the method in which the high breakdown voltage element and the low breakdown voltage element are mixedly arranged.

  In FIG. 10, circuits other than CC11 and CC12 of the voltage conversion circuits 40-11 and 40-12 are arranged between the capacitors CA11 and CA12 and the capacitors CC11 and CC12. Therefore, an efficient layout along the signal flow becomes possible. That is, in FIG. 3A, signals corresponding to the clocks CK11 and CK12 are input to the lower electrodes of the capacitors CC11 and CC12. Transistors TC11, TD11, TC12, TD12, etc. are connected to the upper electrodes of the capacitors CC11, CC12. Therefore, according to the layout of FIG. 10, signal lines can be wired along the signal flow of the circuit of FIG. Therefore, it is possible to shorten the wiring length of the nodes NC11, NF11, NC12, and NF12 and connect them by a short path, and the parasitic capacitance of these nodes can be reduced. Thereby, the adverse effect of these parasitic capacitances on the boosting operation can be minimized.

  In FIG. 10, a wiring region is provided between the clock supply circuit 50 and the voltage conversion circuits 40-11 and 40-12. Therefore, the distance between the clock supply circuit 50 and the voltage conversion circuits 40-11 and 40-12 and the capacitors CA11 and CA12 can be further increased by at least the width of the wiring region in the direction D2. As a result, it is possible to prevent the clock noise generated in the clock supply circuit 50 from adversely affecting the charge storage nodes in the voltage conversion circuits 40-11 and 40-12 and the capacitors CA11 and CA12, thereby reducing the boosting efficiency. Can be prevented.

  In FIG. 10, when the direction opposite to the D1 direction is the D3 direction (third direction), the charge transfer circuit 30-1 is on the D2 direction side of the capacitor CA11 and on the D3 direction side of the capacitor CA12. Thus, layout efficiency can be further improved.

  That is, in FIG. 3A, since CA11 is a capacitor for controlling the gate of the transistor TA1, its capacitance value is smaller than that of the main capacitor CA12. Therefore, as shown in FIG. 10, the layout area of the capacitor CA11 is smaller than that of the main capacitor CA12. Therefore, in FIG. 10, the charge transfer circuit 30-1 is arranged by effectively utilizing the space on the D2 direction side of the capacitor CA11. In this way, the capacitors CA11 and CA12 and the charge transfer circuit 30-1 can be efficiently laid out so that no empty space is generated, and the layout efficiency can be improved.

  3A, the capacitor CC11 is provided corresponding to the capacitor CA11 having a small capacitance value, and the capacitor CC12 is provided corresponding to the main capacitor CA12 having a large capacitance value. For this reason, the capacitance value of the capacitor CC11 can be smaller than that of the capacitor CC12, and the layout area of the capacitor CC11 is smaller than that of the capacitor CC12.

  Therefore, in FIG. 10, the capacitors CC11 and CC12 are arranged so as to match the width of the capacitors CA11 and CA12 in the D2 direction. Then, the arrangement pitch of capacitors CA11, CA12, CA21, CA22... CAN1, CAN2 in the D1 direction is made to coincide with the arrangement pitch of capacitors CC11, CC12, CC21, CC22... CCN1, CCN2 in the D1 direction. Yes. By doing so, a layout without waste is possible, and the booster circuit can be reduced in size.

  11A and 11B show examples of a low breakdown voltage transistor and a high breakdown voltage transistor, and FIGS. 11C and 11D show examples of a low breakdown voltage capacitor and a high breakdown voltage capacitor.

  In FIG. 11A, a P-type well PWEL is formed on a P-type substrate PSUB. Then, an N-type low breakdown voltage transistor composed of the source and drain of an N + impurity layer (diffusion region), a gate oxide film, and a gate is formed in this PWEL. Note that the P-type low breakdown voltage transistor can be configured by, for example, forming an N-type well and forming a P + impurity layer, a gate oxide film, and a gate formed in the N-type well.

  On the other hand, in FIG. 11B, the P-type well PWEL is not formed in the P-type substrate PSUB. Then, an N-type high breakdown voltage transistor including a source and drain of an N + impurity layer, a gate oxide film, and a gate is formed directly on the PSUB. That is, in FIG. 11A, since PWEL has a high impurity concentration, the breakdown voltage of the PN junction is lowered, and a low breakdown voltage transistor is formed. On the other hand, in FIG. 11B, since the impurity concentration of PSUB is low, the breakdown voltage of the PN junction can be increased and a high breakdown voltage transistor can be formed.

  The transistors TC11, TD11, TF11, TG11, TC12, TD12, TF12, and TG12 shown in FIG. 3A can be formed using a P-type low-voltage transistor (not shown) or an N-type low-voltage transistor shown in FIG. On the other hand, the transistors TA1 and TB1 can be formed using the high voltage transistor shown in FIG.

  In FIG. 11C, a P-type well PWEL is formed on a P-type substrate PSUB. In addition, a low breakdown voltage capacitor including an N + impurity layer serving as a lower electrode (clock CK input side) and a gate of a transistor serving as an upper electrode (clock CK ′ output side) is formed on the PWEL. . That is, a capacitor is formed using the gate capacitance of the transistor. An N + cross under impurity layer is provided below the gate and the gate oxide film in order to increase the capacitance value with a small layout area.

  On the other hand, in FIG. 11D, a high breakdown voltage capacitor including an N + impurity layer serving as a lower electrode and a gate of a transistor serving as an upper electrode is formed directly on the P-type substrate PSUB. That is, in FIG. 11C, since PWEL has a high impurity concentration, the breakdown voltage of the PN junction is lowered, and a low breakdown voltage capacitor is formed. On the other hand, in FIG. 11D, since PSUB has a low impurity concentration, the breakdown voltage of the PN junction can be increased and a high breakdown voltage capacitor can be formed. An N + cross under impurity layer is provided below the gate and the gate oxide film.

  The voltage conversion capacitors CC11 and CC12 in FIG. 3A can be formed by the low withstand voltage capacitors in FIG. On the other hand, the charge pump capacitors CA11 and CA12 can be formed by the high voltage capacitors shown in FIG.

9. Nonvolatile Memory Device FIG. 12 shows a configuration example of a nonvolatile memory device including the booster circuit 540 of this embodiment. Note that the configuration of the nonvolatile memory device is not limited to that shown in FIG. 12, and various modifications such as omitting some of the components or adding other components are possible.

  In the memory cell array 500 (EEPROM), a plurality of nonvolatile memory cells are arranged in a matrix, for example. The address decoder 510 performs an address decoding process for selecting a word line of the memory cell array 500 and the like. The input / output unit 520 is a circuit for reading and outputting data stored in the nonvolatile memory cell of the memory cell array 500 and inputting data to be stored in the nonvolatile memory cell.

  The access control circuit 530 is a circuit for performing access control of the memory cell array 500. That is, at least one of writing, reading, and erasing of data in the nonvolatile memory cell of the memory cell array 500 is performed. The booster circuit 540 generates the boosted voltage VPP necessary for this access control. That is, the access control circuit 530 uses the boosted voltage VPP generated by the booster circuit 540 to control data writing to the nonvolatile memory cell.

  Note that the nonvolatile memory device in FIG. 12 can be incorporated in various electronic devices. For example, it can be incorporated in an electronic device such as a personal computer, a portable information terminal, a mobile phone, a printer, a scanner, a digital camera, a video camera, or a car navigation system. Alternatively, the nonvolatile memory device of this embodiment may be built in an electronic device such as an ink cartridge that can monitor the remaining amount of ink. In this case, when the printer is turned off, the non-volatile memory device performs the operation of writing the remaining ink amount data into the non-volatile memory cell based on the electric charge stored in the capacity of the power supply device. For this reason, the nonvolatile memory device is desired to have low power consumption, and the nonvolatile memory device including the booster circuit according to the present embodiment having low power consumption is the optimum memory device for such an electronic device as an ink cartridge. become.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, terms (L level) described at least once together with different terms (first voltage level, second voltage level, first power source, second power source, etc.) having a broader meaning or the same meaning. , H level, VSS, VDD, etc.) can be replaced by the different terms anywhere in the specification or drawings.

  Further, the configuration of the booster circuit, the voltage conversion circuit, the nonvolatile memory device, and the drive waveform of the charge pump are not limited to those described in this embodiment, and various modifications can be made. For example, FIG. 13 shows a fourth modification of the voltage conversion circuit. In FIG. 3A, the voltage of the clock CK is boosted twice, but in FIG. 13, the voltage of the clock CK can be boosted three times.

  In FIG. 13, the circuits of FIG. 3A are cascade-connected. That is, the circuit of FIG. 3A is connected in series while inverting the clock CK. Then, a voltage of 2VDD-VTH (double boost) is generated at the intermediate output node NF, and a voltage of 3VDD-VTH (triple boost) is generated at the final output node NFB. More specifically, in FIG. 13, the configuration of the precharge circuit 42-2, the charge transfer circuit 44-2, the discharge circuit 46-2, and the voltage conversion capacitor CCB is added to the configuration of FIG. ing. The precharge circuit 42-2, charge transfer circuit 44-2, discharge circuit 46-2, and voltage conversion capacitor CCB are the same as the precharge circuit 42, charge transfer circuit 44, discharge circuit 46, and voltage conversion capacitor CC. It is a circuit and its connection configuration is also the same. The intermediate output node NF is connected to the source of the precharge transistor TCB of the precharge circuit 42-2. A non-inverted signal of the clock CK is input to the gate of the charge transfer transistor TD of the charge transfer circuit 44 and the gate of the discharge transistor TE of the discharge circuit 46, while the charge transfer of the charge transfer circuit 44-2. The inverted signal of the clock CK is input to the gate of the transistor TDB and the gate of the discharge transistor TEB of the discharge circuit 46-2. An inverted signal of the clock CK is input to the other end (lower electrode) of the voltage conversion capacitor CC, while a non-inverted signal of the clock CK is input to the other end of the voltage conversion capacitor CCB. . According to the circuit of FIG. 13, the voltage of the clock CK can be boosted to 3VDD-VTH, which is a higher voltage. Note that a circuit that generates a voltage that is four times or more boosted can also be configured in the same way as in FIG.

1A and 1B are a configuration example of a voltage conversion circuit according to this embodiment and an operation explanatory diagram thereof. 2A and 2B show first and second modifications of the voltage conversion circuit. 3A and 3B are a third modified example of the voltage conversion circuit and an operation explanatory diagram thereof. 2 is a configuration example of a booster circuit. The signal waveform diagram for demonstrating operation | movement of a voltage converter circuit. The detailed structural example of a charge pump unit. The other example of a detailed structure of a charge pump unit. The example of the drive waveform of a charge pump circuit. The other example of the drive waveform of a charge pump circuit. An example of the layout of the booster circuit. 11A to 11D illustrate examples of a low breakdown voltage transistor, a high breakdown voltage transistor, a low breakdown voltage capacitor, and a high breakdown voltage capacitor. 1 is a configuration example of a nonvolatile memory device according to an embodiment. The 4th modification of a voltage converter circuit.

Explanation of symbols

10 charge pump circuit, 20-1 to 20-N charge pump unit,
30-1 to 30-N charge transfer circuit, 40, 40-11 to 40-N2 voltage conversion circuit,
CA11 to CAN2 charge pump capacitors,
CC, CC11 to CC22 capacitor for voltage conversion,
CK11 to CKN2, RCK1 to RCKJ clock, 42 precharge circuit,
44 charge transfer circuit, 46 discharge circuit, 50 clock supply circuit,
52 decoder, 54 ring oscillator, 500 memory cell array,
510 address decoder, 520 input / output unit, 530 access control circuit,
540 Booster circuit

Claims (15)

A voltage conversion capacitor provided between the charge storage node and a voltage change node whose voltage level changes based on a clock, and changes the voltage level of the charge storage node according to the voltage level of the clock;
A precharge circuit that is provided between a second power source and the charge storage node and precharges the charge storage node;
A charge transfer circuit which is provided between the charge storage node and the output node and transfers the charge stored in the charge storage node to the output node in a charge transfer period;
A voltage conversion circuit, comprising: a discharge circuit provided between the output node and a first power supply and discharging the output node during a discharge period. In claim 1,
The precharge circuit is
A voltage conversion circuit comprising a P-type precharging transistor provided between a second power supply and the charge storage node, the gate, drain and substrate of which are connected to the charge storage node. In claim 2,
The charge transfer circuit includes:
A P-type charge transfer transistor provided between the charge storage node and the output node and turned on during the charge transfer period;
The discharge circuit is
An N-type discharge transistor provided between the output node and the first power supply and turned on during the discharge period;
The voltage conversion capacitor is formed of a low breakdown voltage capacitor, the precharge transistor and the charge transfer transistor are formed of a low breakdown voltage transistor,
The voltage conversion circuit according to claim 1, wherein the discharge transistor is formed of the low breakdown voltage capacitor and a high breakdown voltage transistor having a higher breakdown voltage than the low breakdown voltage transistor. In claim 1,
The precharge circuit is
A voltage conversion circuit comprising a P-type precharging transistor provided between a second power supply and the charge storage node and having a gate connected to the output node. In claim 4,
The charge transfer circuit includes:
A P-type charge transfer transistor provided between the charge storage node and the output node and turned on during the charge transfer period;
The discharge circuit is
An N-type voltage difference adjusting transistor provided between the output node and the first power supply, the second power supply being input to the gate;
A voltage conversion circuit comprising an N-type discharge transistor which is provided in series with the voltage difference adjustment register between the output node and a first power supply and is turned on during the discharge period. 5. The voltage conversion circuit according to claim 4, and a charge pump capacitor connected to the output node of the voltage conversion circuit, wherein the voltage conversion circuit performs a boosting operation based on a clock whose voltage level is converted by the voltage conversion circuit. A boosting circuit to perform,
The voltage conversion capacitor is formed of a low breakdown voltage capacitor, and the precharge transistor is formed of a low breakdown voltage transistor,
2. The booster circuit according to claim 1, wherein the charge pump capacitor is formed of a high breakdown voltage capacitor having a breakdown voltage higher than that of the low breakdown voltage capacitor and the low breakdown voltage transistor. 6. A voltage conversion circuit according to claim 5, and a charge pump capacitor connected to the output node of the voltage conversion circuit, and performing a boosting operation based on a clock whose voltage level is converted by the voltage conversion circuit. A boosting circuit to perform,
The voltage conversion capacitor is formed of a low breakdown voltage capacitor, and the precharge transistor, the charge transfer transistor, the voltage difference adjustment transistor, and the discharge transistor are formed of a low breakdown voltage transistor,
2. The booster circuit according to claim 1, wherein the charge pump capacitor is formed of a high breakdown voltage capacitor having a breakdown voltage higher than that of the low breakdown voltage capacitor and the low breakdown voltage transistor. 6. The voltage conversion circuit according to claim 1, comprising a first voltage conversion circuit and a second voltage conversion circuit, and a voltage boosting operation based on a clock whose voltage level is converted by the first voltage conversion circuit and the second voltage conversion circuit. A booster circuit that performs
The first voltage conversion circuit includes:
The voltage conversion capacitor, the precharge circuit, the charge transfer circuit, and the discharge circuit include a first voltage conversion capacitor, a first precharge circuit, a first charge transfer circuit, and a first discharge circuit. ,
The second voltage conversion circuit includes:
The voltage conversion capacitor, the precharge circuit, the charge transfer circuit, and the discharge circuit include a second voltage conversion capacitor, a second precharge circuit, a second charge transfer circuit, and a second discharge circuit. ,
The first charge transfer circuit of the first voltage conversion circuit performs the charge transfer from the first charge accumulation node to the first output node of the first voltage conversion circuit. The second discharge circuit of the second voltage conversion circuit discharges the second output node of the second voltage conversion circuit;
The second charge transfer circuit of the second voltage conversion circuit performs the charge transfer from the second charge accumulation node to the second output node of the second voltage conversion circuit. 2. The booster circuit according to claim 1, wherein the first discharge circuit of one voltage conversion circuit discharges the first output node of the first voltage conversion circuit. In claim 8,
The first and second voltage conversion circuits are supplied with a first clock and a second clock having a non-overlapping relationship with the first clock,
When the first clock is at a second voltage level and the second clock is at a first voltage level, the first charge transfer circuit is connected to the first charge storage node from the first charge storage node. The second discharge circuit discharges the second output node, and charges are transferred to the output node.
When the first clock is at a first voltage level and the second clock is at a second voltage level, the second charge transfer circuit is connected to the second charge storage node from the second charge storage node. The booster circuit is characterized in that charge transfer to the output node is performed, and the first discharge circuit discharges the first output node. In claim 9,
The first charge transfer circuit includes:
A P-type first charge transfer transistor provided between the first charge accumulation node and the first output node and turned on when the first clock is at a second voltage level. Including
The first discharge circuit includes:
An N-type first discharge transistor provided between the first output node and a first power supply and turned on when the second clock is at a second voltage level;
The second charge transfer circuit includes:
A P-type second charge transfer transistor provided between the second charge accumulation node and the second output node and turned on when the second clock is at a second voltage level. Including
The second discharge circuit includes:
An N-type second discharge transistor is provided between the second output node and a first power supply, and is turned on when the first clock is at a second voltage level. A booster circuit. In any one of Claims 8 thru | or 10.
Including first and second capacitors for charge pumps connected to the first and second output nodes of the first and second voltage conversion circuits,
A circuit other than the first voltage conversion capacitor of the first voltage conversion circuit is arranged between the first capacitor and the first voltage conversion capacitor,
A booster circuit, wherein a circuit other than the second voltage conversion capacitor of the second voltage conversion circuit is disposed between the second capacitor and the second voltage conversion capacitor. In claim 11,
The first and second capacitors are formed by high voltage capacitors,
The booster circuit according to claim 1, wherein the first and second voltage converting capacitors are formed of a low breakdown voltage capacitor having a breakdown voltage lower than that of the high breakdown voltage capacitor. In claim 11 or 12,
Including a clock supply circuit for generating and supplying a clock for a charge pump;
A booster circuit, wherein the first and second voltage conversion circuits are arranged between the first and second capacitors and the clock supply circuit. In claim 13,
A wiring region is provided between the clock supply circuit and the first and second voltage conversion circuits, in which a signal line including a clock signal line supplied by the clock supply circuit is provided. Boost circuit. A memory cell array in which a plurality of nonvolatile memory cells are arranged;
15. An access control circuit for performing at least one of writing, reading, and erasing of data in the nonvolatile memory cell based on the boosted voltage generated by the booster circuit according to claim 6. A non-volatile memory device.

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