JP2008021370A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To vary a write verification range according to relief of a bit line, a use of a memory array, etc. in a nonvolatile memory where a result of write verification can be aggregated to be a small number of bits to be output. <P>SOLUTION: The nonvolatile memory has a memory array (11) provided with two or more nonvolatile memory cells (MC) connected to two or more bit lines BL, two or more one-bit judgment circuits (31) which compares and judges read data of a verification read unit read from the memory array in write verification operation with write data bits of a corresponding write data latch (29) in parallel by bit correspondence, and a judgement aggregation circuit (32) which aggregates judged results of the two or more one-bit judgment circuits. The judgement aggregation circuit can select bits to be aggregated among the judged results of the two or more one-bit judgment circuits. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for aggregating and outputting a write verify processing result of an electrically erasable and writable nonvolatile memory into a small number of bits, for example, a microcomputer in which the nonvolatile memory and a central processing unit are on-chip. It is related to effective technology.

  Japanese Patent Application Laid-Open No. 2004-228561 describes a technique for collecting and outputting the write verify processing results of the nonvolatile memory in a small number of bits. According to this, whether or not the verify-read information of a plurality of bits matches the expected value is compared, and a logical product is taken for each comparison result, and the 1-bit logical product value is output as a write verify result. .

JP-A-9-198883

  However, the technique described in Patent Document 1 does not consider changing the write verify range. That is, in the write verify operation, the verify read data read to the bit line and the latch data of the corresponding write data latch are compared for each corresponding bit, and a logical product is taken for each result to obtain the verify result. It is necessary to exclude a specific memory area from the logical product input if it is not used selectively, and to add it to the logical product input if it is selectively used additionally. Become. For example, when the parity check circuit cannot be used in the power-on reset operation, the logical product input corresponding to the parity data storage area must be excluded from the verify determination in the power-on reset operation. When redundant relief is performed, the comparison determination result between the verify read data and the write latch data for the redundant bit is added to the logical product input, and the comparison determination result is logically calculated for the relief bit rescued by the redundant circuit. Product inputs must be excluded.

  SUMMARY OF THE INVENTION An object of the present invention is to make it possible to vary a write verify range according to bit line relief, memory array use, etc. in a nonvolatile memory capable of collecting and outputting a write verify result in a small number of bits.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A semiconductor device according to the present invention includes an electrically erasable and writable nonvolatile memory (4), and the nonvolatile memory includes a plurality of nonvolatile memory cells connected to a plurality of bit lines (BL). The memory array (11) having (MC) and the read data of the verify read unit read from the memory array in the write verify operation are bit-corresponding to the write data bits of the corresponding write data latch (29, 28). A plurality of 1-bit determination circuits (31) for comparison determination in parallel, a determination aggregation circuit (32, 43, 55) for aggregating determination results of the plurality of 1-bit determination circuits, and a determination aggregation of the determination aggregation circuit An output terminal (TRM) for outputting the result to the outside of the nonvolatile memory. The determination aggregation circuit can select target bits to be aggregated among the determination results of the plurality of 1-bit determination circuits. As a result, the write verify range can be made variable according to the bit line relief, the use of the memory array, etc. in the nonvolatile memory that can output the write verify result in a small number of bits.

  As a specific form of the present invention, the 1-bit determination circuit is connected to a bit line selection transistor (M1) for selecting a bit line designated by a verify read address from a plurality of bit lines, and the bit A data latch selection transistor (M3 to M5) for selecting latch data of the write data latch corresponding to the bit line selected by the line selection transistor, data of the bit line selected by the bit line selection transistor, and the data latch And a comparison circuit (36) for comparing the latch data selected by the selection transistor. Since the comparison circuit can be commonly used for a plurality of bit lines, an increase in circuit scale can be suppressed.

  As a more specific form of the present invention, the decision aggregation circuit includes a mask gate (40) capable of selectively forcing the decision result of the 1-bit decision circuit to coincide with a decision, and the outputs of the respective mask gates. And a selection control circuit (21, 21 and 44, 21 and 56) for selecting and controlling forcing of the determination match by the mask gate. The target bits to be aggregated can be selected from the determination results of the plurality of 1-bit determination circuits with a relatively simple configuration called a mask gate.

  As a more specific form of the present invention, the determination gate circuit has a first logic gate (41) having two inputs arranged for each mask gate, and the first input of the first logic gate is a corresponding mask. Receiving the output of the gate, the second input of the first logic gate receives the output of the first logic gate on the upper side of the signal path and is cascade-connected in order to the lower side, and the cascaded uppermost first logic gate With the state in which the logic value supplied to the second input of the first bit is transmitted to the output of the lowest first logic gate, the determination results of the respective 1-bit determination circuits are all matched. According to this, it is possible to relatively easily realize a configuration in which the bits are aggregated into one bit.

  As another specific form of the present invention, the mask gate is a two-input second logic gate (40), and the first group of mask gates includes a first mask signal (φ1) and a corresponding one bit. The determination result of the determination circuit is supplied, and the second mask signal (φ2) and the corresponding determination result of the 1-bit determination circuit are supplied to the second group of mask gates. The nonvolatile memory cells connected to the bit lines corresponding to the first group of mask gates in the memory array serve as data storage areas, and the nonvolatile memory is connected to the bit lines corresponding to the second group of mask gates. The cell is an area for storing parity data of the data stored in the data storage area. At this time, the selection control circuit sets the first mask signal to a level for deselecting the forcing of the determination coincidence by the mask gate in the write verify operation when writing data without parity in the data storage area. In the write verify operation when writing the data and its parity data in the data storage area, the second mask signal is set to a level where selection of forced determination coincidence by the mask gate is selected, and the first mask signal and the second mask signal Is set to a level at which the forced determination match by the mask gate is not selected. As a result, the write verify range can be made variable according to the presence or absence of parity data.

  As yet another specific form of the present invention, the mask gate is a two-input second logic gate (40), and the first group of mask gates has a first mask signal (φ4) and 1 corresponding thereto. The determination result of the bit determination circuit is supplied, and the second mask signal (φ5) and the corresponding determination result of the 1-bit determination circuit are supplied to the second group of mask gates. The memory array includes a first memory area (BLK1) and a second memory area (BLK2) that can be selected by memory area selection signals (SEL1, SEL2). The first memory region has a nonvolatile memory cell connected to a bit line corresponding to the first group of mask gates as a data storage region (DTAR), and a bit line corresponding to the second group of mask gates The non-volatile memory cell connected to is used as a non-use area (NUAR). The second memory area has a nonvolatile memory cell connected to a bit line corresponding to the first group of mask gates as a data storage area (DTAR), and the second memory area has a bit line corresponding to the second group of mask gates. The connected nonvolatile memory cells are provided as a parity data storage area (PTAR) for storing parity data of data stored in the data storage area. The selection control circuit (21, 44) sets the first mask signal to a level for deselecting the forced determination coincidence by the mask gate in the write verify operation to the first memory area, and the second mask signal. Is set to a level where selection of forced matching of judgment by the mask gate is selected, and in the write verify operation for the second memory area, the forced matching of judgment by the mask gate is not selected for the first mask signal and the second mask signal. To the level you want. According to this, the write verify range can be made variable according to the memory area to be selected.

  As yet another specific form of the present invention, the memory array has a normal memory area (50) and a redundant memory area (51) used for defect repair of the normal memory area. The mask gate is a two-input second logic gate (40), and the mask gate corresponding to the normal memory area includes a first mask signal (TH_D0 to TH_D63) that differs for each mask gate and one bit corresponding thereto. The determination result of the determination circuit is supplied, and the second mask signal (Re) and the corresponding determination result of the 1-bit determination circuit are supplied to the mask gate corresponding to the redundant memory area. The selection control circuit (21, 56) sets the first mask signal to a level for deselecting the forced determination coincidence by the mask gate when relief by the redundant memory area is not performed in the write verify operation. At the same time, the second mask signal is set to a level at which forced determination coincidence by the mask gate is selected. When the relief by the redundant memory area is being performed, the selection of forced determination coincidence by the mask gate is selected for the first mask signal of the mask gate corresponding to the bit line replaced by the redundant memory area. The level of the other first mask signal is set to a level at which the forced judgment match by the mask gate is not selected, and the second mask signal is set to the level at which the forced judgment match by the mask gate is not selected. To. According to this, the write verify range can be made variable according to the presence or absence of redundancy relief.

  As yet another specific form of the present invention, there is provided a central processing unit (2) capable of controlling access to the non-volatile memory, and the central processing unit inputs a determination aggregation result of the determination aggregation circuit.

  [2] A semiconductor device according to another aspect of the present invention includes an electrically erasable and writable nonvolatile memory and a central processing unit, and is formed in one semiconductor chip. A memory array having a plurality of nonvolatile memory cells connected to a plurality of bit lines, and a write data bit of a write data latch corresponding to read data in a verify read unit read from the memory array in a write verify operation; A plurality of 1-bit determination circuits that compare and determine in parallel in correspondence with bits, and a determination aggregation circuit that aggregates the determination results of the plurality of 1-bit determination circuits into one bit. The determination aggregation circuit can select target bits to be aggregated into one bit among the determination results of the plurality of 1-bit determination circuits. The central processing unit instructs a write verify operation of the nonvolatile memory, and receives a result of the write verify operation as a determination aggregation result by the determination aggregation circuit. As a result, the write verify range can be made variable according to the bit line relief, the use of the memory array, etc. in the nonvolatile memory that can output the write verify result in a small number of bits. Naturally, the central processing unit does not have to bear the burden of determining by sequentially comparing the verify read data and the write data in the write verify operation.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, the write verify range can be varied according to bit line relief, the use of the memory array, etc. in a nonvolatile memory that can output the write verify results in a small number of bits.

  FIG. 2 shows a microcomputer (MCU) 1 which is an example of a semiconductor device according to the present invention. The microcomputer 1 is not particularly limited, but is formed on a single semiconductor substrate (semiconductor chip) such as single crystal silicon by a CMOS integrated circuit manufacturing technique or the like. The microcomputer 1 includes a central processing unit (CPU) 2, a RAM 3 as a volatile memory, a flash memory (FLASH) 4 as a nonvolatile memory, a direct memory access controller (DMAC) 5, an input / output port (PRT) ) 6, 7, timer (TMR) 8, clock generator (CPG) 9, etc., and these circuit modules are connected to the internal bus 10. The internal bus 10 includes bus signal lines for address, data, and control signals. The CPU 2 includes an instruction control unit and an execution unit, decodes the fetched instruction, and performs arithmetic processing according to the decoding result. The flash memory 4 stores an operation program and data for the CPU 2. The RAM 3 is a work area or a data temporary storage area of the CPU 2. A clock pulse generator 9 inputs a clock or system clock generated by an oscillation operation in accordance with the resonance frequency of an external crystal resonator, generates an internal clock that is phase-synchronized with the system clock by a PLL circuit, and the microcomputer 1 It is operated in synchronization with the clock and its divided clock. Access to the flash memory 4 is controlled by the CPU 2, and operation modes such as erasing and writing are controlled based on control data set by the CPU 2 in a control register (not shown).

  FIG. 3 shows an example of the flash memory 4. The flash memory 4 has a memory array (MARY) 11 in which a plurality of nonvolatile memory cells MC are arranged in a matrix. Although not particularly limited, here, the nonvolatile memory cell MC includes a gate oxide film, a silicon nitride, an interlayer insulating film, and a memory gate on a channel formation region between the source and the drain. An oxide, nitride, oxide, semiconductor) type stacked gate structure is assumed. The memory gate of the memory cell is connected to the corresponding memory gate line MGL, the drain is connected to the corresponding bit line BL, and the source is connected to the corresponding source line SL. The bit line BL means a main bit line in the main / sub bit line structure. An X address decoder (XDEC) and a driver (XDRV) 12 decode the X address signal input to the address buffer (ADB) 13. The memory gate line MGL and the source line SL are driven according to the decoding result. The driving mode is determined according to the operation (reading, erasing, writing, etc.) of the flash memory. The X address signal is supplied from the address bus ABUS of the internal bus 10 to the address buffer 13.

  The write latch circuit (WRL) 16 has a write latch (LAT) 29 connected to each bit line BL. A Y switch circuit and a Y decoder (YSW / YDEC) 17 are connected to the bit line BL, and the Y decoder (YDEC) decodes the Y address signal input from the address bus ABUS of the internal bus 10 to the address buffer (ADB) 13. To do. The Y switch circuit (YSW) selects the bit line BL according to the decoding result of the Y decoder (YDEC), and the read data on the selected bit line BL is read by the sense amplifier (SA) corresponding to the sense amplifier circuit (SAA) 18. Amplified and output from the input / output circuit (IO) 19 to the data bus DBUS of the internal bus 10. In the write operation, write data supplied from the data bus DBUS of the internal bus 1 to the input / output circuit 19 is selected by the Y switch circuit (YSW) and latched in the write data latch (LAT) 29 of the write latch circuit 16. In the write operation, the bit line BL is set to a level corresponding to the logical value of the write data latched in the write data latch (LAT) 29.

  A high voltage required for erasing and writing of the nonvolatile memory cell MC is generated by the memory power supply circuit (MPS) 20 and supplied to each unit. The memory power supply circuit 20 boosts the external voltage to generate a high voltage used for erase and write operations. The control circuit (CONT) 21 performs read, erase, erase verify, write, and write verify control sequences and operation power supply voltage switching control in accordance with control information set in the control register (CREG) 22. The operation power supply voltage switching control means that the operation power supply and operation timing of the driver (XDRV), the sense amplifier (SA), etc. are appropriately set according to the operation mode in accordance with read, erase, erase verify, write, and write verify. It is the control to switch. The oscillation circuit (OSC) 23 generates a synchronous operation clock signal for the memory power supply circuit 20 and the control circuit 21. The CPU 2 sets control data in the control register 22 for each of read, erase, erase verify, write, and write verify operations, whereby the control circuit 21 controls the operation according to the set control data.

  Although not particularly limited, the nonvolatile memory cell MC here has an n-channel MONOS structure. The source in the nonvolatile memory cell MC is defined as a downstream terminal of a current path formed by being turned on in a read operation, for example. The nonvolatile memory cell MC is written by, for example, hot carrier writing, the write target bit line BL is set to 6 V, the source line SL is set to 0 V, a channel current is passed, and the write target memory gate line MGL is set to 10 V. Hot electrons generated at the drain end of the cell MC are injected into the silicon nitride film. Erasing is performed by setting the memory gate line MGL to 18 V, the source line SL and the well region to 0 V, and extracting electrons from the silicon nitride film to the memory gate line MGL.

  The write operation is not particularly limited, but is performed in units of word lines. For example, the memory gate line is controlled by controlling whether or not the write current is supplied to the memory cell MC according to the logical value of the latch data latched in the write data latch (LAT) 29 corresponding to the bit line for one word line. In synchronism with the application of the high voltage pulse to the MGL, electrons are selectively injected into the memory cell of the word line. In order to determine whether the threshold voltage of the memory cell has successively reached the target threshold voltage, the CPU 2 instructs the writing operation so that the application of the high voltage pulse to the memory gate line MGL is performed in several steps. Instructs the write verify operation.

  In FIG. 3, reference numeral 30 denotes a write verify determination circuit (VDEC). In FIG. 3, the write verify determination circuit 30 is representatively shown only for one bit line, but for example, as a write verify result for a memory cell to be subjected to a write operation such as one word line. This circuit generates a 1-bit verification result signal φvfy and returns it to the CPU 2. The write verify determination circuit 30 reads the read data in the verify read unit read from the memory array 11 to the bit line BL in the write verify operation in parallel with the write data bit of the corresponding write data latch (LAT) 29 in correspondence with the bit. A plurality of 1-bit determination circuits (SBD) 31 for comparison determination, a determination aggregation circuit (DAGR) 32 for aggregating the determination results of the plurality of 1-bit determination circuits 31, and a determination aggregation result of the determination aggregation circuit 32 It has an output terminal TML that outputs to the outside of the flash memory 4 as a verify result signal φvfy. The determination aggregation circuit 32 is configured to be able to select target bits to be aggregated among the determination results of the plurality of 1-bit determination circuits 31.

<< Determination mask control that differs between trimming data area and data area >>
FIG. 1 shows a specific example of the write verify determination circuit 30. Here, the memory array 11 is divided into a plurality of memory mats (MAT) 33. For example, the memory array 11 has 128 bytes, that is, 1024 bit lines, and is divided into 64 as a whole, and has 64 memory mats (MAT) 33 each having 16 bit lines BL. The memory gate line MGL is common to the memory mats 33. In the Y switch circuit (YSW), bit lines in one memory mat (MAT) 33 are commonly connected to a common data line CD via a high breakdown voltage column selection N-channel MOS (NMOS) transistor M1. The column selection NMOS transistor M1 is alternatively turned on by column selection signals yw0 to ywn. Although not shown in particular, the column selection signals yw0 to ywn are shared by 64 memory mats. The 64 common data lines CD are connected to 16 data lines sequentially every 16 lines via a selection gate (not shown), and the 16 data lines can be interfaced to the data bus DBUS. Data can be input / output in parallel with DBUS in units of 16 bits. The selection level of the column selection signals yw0 to ywn is a voltage boosted with respect to the external power supply voltage, and the on-resistance of the column selection NMOS transistor M1 is reduced to obtain a large read signal amount.

  The write data latch 29 has a static latch in which two inverters IV1 and IV2 are connected in antiparallel, and the input / output node of the static latch is connected to the corresponding bit line BL via the selection NMOS transistor M2, and 1 Connected to the bit determination circuit 31. The selection NMOS transistor M2 is turned on in parallel in the write operation.

  The 1-bit determination circuit 31 compares and determines the read data read from each memory mat (MAT) 33 in the write verify operation in correspondence with the write data bit of the corresponding write data latch. In the example of FIG. 1, the 1-bit determination circuit 31 has a verify sense amplifier 37, and the common data line CD of the corresponding memory mat 33 is connected to one input terminal, and column selection is performed based on the verify read address. Read data on the bit line selected by the NMOS transistor M1 is received. The verify sense amplifier 37 is set to the high level when the comparison voltage is input to the other input terminal and the threshold voltage of the memory cell to be verified has reached the target high threshold voltage (the read voltage is lower than the comparison voltage). If it has not been reached (the read voltage is higher than the comparison voltage), a low level is output. The output of the verify sense amplifier 37 indicates whether or not the state of the memory cell is the target write state based on the read data from the corresponding memory cell.

  Further, the 1-bit determination circuit 31 receives the inverted data of the write data latched in the write data latch (LAT) 29 of the corresponding memory mat 33 in the bit correspondence at the gate of the input NMOS transistor M3. The source of the input NMOS transistor M3 is commonly connected to the ground voltage GND, the selection NMOS transistor M4 is connected in series to the drain of the input NMOS transistor M3, the drain of the selection MOS transistor M4 is wired or coupled, and the coupling node ND is P It is pulled up to the power supply voltage Vdd by a channel type MOS (PMOS) transistor M5. The selection NMOS transistor M4 is switch-controlled by column selection signals yw0 'to ywn' generated based on the verify read address (column address in the write verify operation). In the write verify operation, the column selection signals yw0 'to ywn' are equal to the column selection signals yw0 to ywn. The write data latch 29 selects the write operation for the memory cell by latching the high level in the static latch, and deselects the write operation for the memory cell by latching the low level. When the latch data of the write data latch 29 selected by one selection MOS transistor M4 is at a high level (write selection), the coupling node ND maintains a high level and the latch data is at a low level (write non-selection). At this time, the connection node ND is inverted to a low level. The level of the node ND indicates whether or not the memory cell to be verified is a write target.

  A 2-input exclusive negative OR gate 36 is provided as a comparison circuit, and an inverted output of the verify sense amplifier 37 is supplied to one input thereof. The other input of the exclusive negative OR gate 36 is coupled to the output of the two-input type NAND gate 38. The NAND gate 38 is supplied with a node ND and an inverted signal of the write verify enable signal EV. The signal EV is set to a logic level when a write verify operation is designated. When the write data latched in the static latches (IV1 and IV2) is at a high level, the exclusive negative OR gate 36 is at a low level, which means that the verify read signal to the bit line BL indicates the completion of writing. If there is, a high level is output as the 1-bit determination signal φ1, and a low level is output as the 1-bit determination signal φ1 if the verify read signal to the bit line BL indicates a high level indicating that writing is incomplete. Further, when the write data latched in the static latches (IV1, IV2) is at a low level, the exclusive negative OR gate 36 means that the verify read signal to the bit line BL is incompletely written. Since it becomes high level, a high level is output as the 1-bit determination signal φ1. As described above, the 1-bit determination circuit 31 outputs a low level as the 1-bit determination signal φ1 only when the write target memory cell is not yet completed in the write verify operation. A high level is output as the signal φ1.

  The aggregation determination circuit 32 has a two-input type OR gate 40 and a two-input type AND gate 41 corresponding to each 1-bit determination signal φ1. The 64 AND gates 41 have a cascade connection form in which the output terminal of the preceding AND gate 41 is coupled to one input of the following AND gate 41 from the right side to the left side of the drawing. The other input terminal of the AND gate 41 is connected to the output terminal of the corresponding OR gate 40. The OR gate 40 receives the corresponding 1-bit determination signal and the mask signal φ2 or φ3, and functions as a mask gate that can force the determination result indicated by the 1-bit determination signal to coincide with the determination by the high level of the mask signals φ2 and φ3. For example, an activation control signal φvsa (high level is an activation instruction level) of the verify sense amplifier 37 is supplied to one input of the first AND gate 41 of the 64 AND gates connected in cascade as a high level signal. The 64 cascaded AND gates 41 function as a determination gate circuit that determines whether or not all bits match the output of each OR gate 40, and the output signal of the AND gate 41 in the final stage is the above-described output signal. It becomes a verification result signal φvfy which is a result of determination aggregation. When all the outputs of the AND gate 41 are at a high level, the verify result signal φvfy is at a high level.

  In the example of FIG. 1, of the 64 memory mats 33, 63 memory mats 33 from the left are used as data storage areas, and the remaining one memory mat 33 is a parity data storage area for the data areas. . The mask signal φ2 is input to the OR gate 40 corresponding to the memory mat 33 in the data storage area, and the mask signal φ3 is input to the OR gate 40 corresponding to the memory mat 33 in the parity data storage area. Although not shown in FIG. 2, a parity generation circuit and a parity determination circuit for the flash memory 4 are provided. For example, the parity generation circuit and the parity determination circuit are not operated during the power-on reset processing period of the microcomputer 1. . At this time, it is assumed that initialization data used for the power-on reset process is stored in a part of the data storage area of the flash memory 4. For example, the initialization data is trimming data for adjusting circuit characteristics. The control circuit 21 that generates the mask signals φ2 and φ3 controls the mask signal φ2 to a low level and the mask signal φ3 to a high level when writing trimming data, and parity data in a write verify operation for a write operation in units of word lines. By ignoring the state of the storage area, whether or not writing to the data storage area is completed can be obtained by a 1-bit verification result signal φvfy. The control circuit 21 for generating the mask signals φ2 and φ3 controls the mask signals φ2 and φ3 to a low level when writing data other than the trimming data, and determines whether or not the writing to the data storage area and the parity data storage area is completed. The bit verification result signal φvfy can be obtained. As a result, the write verify range can be made variable according to the presence or absence of parity data. The OR gate 40 and the mask signal φ2 corresponding to the data area can be omitted.

  FIG. 4 illustrates a flowchart of the write operation and the write verify operation. The CPU 2 transfers 128 bytes of write data to the write data latch circuit 16 of the flash memory 4 (S1), the CPU 2 sets the write operation mode to the flash memory 4, applies a high voltage of the write target memory gate line, and writes A write current is selectively applied to the bit line based on the data to perform writing to the memory cell (S2). After one write operation, the CPU 2 sets a write verify operation mode in the flash memory 4 (S3), and corresponds to the memory cell MC of 64 bits in total from each memory mat 33 according to the verify address from the CPU 2, and corresponding to it. The write data latch 29 to be selected is selected (S4), and verify read is performed (S5). The read data read-verified from the memory cell and the data read from the write data latch are compared by each 1-bit determination circuit (S6), and the result is aggregated into 1 bit by the aggregation determination circuit and 1-bit verification is performed by the CPU 2. Returns result signal φvfy. The CPU 2 determines whether or not the verify result signal φvfy is at a high level (logic value 1) (S7), and if φvfy = 1, returns to step S2 and repeats the process. If φvfy = 1, it is determined whether writing of 128 bytes has been completed (S8), and if it is not completed, the process returns to step S4 to repeat the process. When the writing for 128 bytes is completed, a series of writing and writing operations are completed. Since the CPU 2 can obtain the result of the write verify in 64-bit units by the 1-bit verify result signal φvfy, the CPU 2 does not have to perform the operation of fetching the verify read data from the memory cell in 16-bit units and comparing it with the write data one by one. Good.

  FIG. 5 illustrates a timing chart of the write operation and the write verify operation. FIG. 4 shows a case where, in the flowchart of FIG. 4, after the write operation in units of 128 bytes, the determination result of the write verify operation in units of 64 bits is the completion of sequential writing (repetition of steps S4 to S8 in FIG. 4).

  FIG. 6 shows an example of the verify sense amplifier 37. The verify sense amplifier 37 functions by a current sense method using, for example, a differential amplifier. A comparison voltage is applied to the non-inverting input terminal of the operational amplifier, a voltage determined by the verify current and the memory cell current is applied to the inverting input terminal, and the output is low when the inverting input terminal voltage is higher than the comparison voltage. When the inverting input terminal voltage is lower than the comparison voltage, the output is set to the high level. The verify current is a current obtained by bit line precharging, and the memory current is a current flowing from the bit line to the source line. Therefore, to realize current sensing, for example, the comparison voltage is applied to the current flowing from the precharge level bit line through the memory cell in the write state to the source line and the memory cell in the erase state from the bit line at the precharge level. This is a voltage formed by a current change in the dummy bit line configured to cause a current change between the current flowing through the source line via the current.

<< Determination mask control that differs between memory blocks >>
FIG. 7 shows another example of selection control for the write verify determination circuit 30 and its mask function. Here, the memory array 11 includes a memory block BLK1 without parity and a memory block BLK2 with parity. In FIG. 7, each of D0 to D63 and P0 to P6 corresponds to the determination output φ1 of the 1-bit determination circuit 31 in FIG. Since the circuit configuration for forming the determination outputs D0 to D63 and P0 to P6 is the same as the configuration 31 corresponding to one memory mat 33 in FIG. 1, detailed description thereof is omitted here. In the memory block BLK1, an area corresponding to the determination outputs D0 to D63 is a data area DTAR, and an area corresponding to the determination outputs P0 to P6 is a non-use area NUAR. In the memory block BLK2, an area corresponding to the determination outputs D0 to D63 is a data area DTAR, and an area corresponding to the determination outputs P0 to P6 is a parity data area PTAR.

  Similar to FIG. 1, the decision aggregation circuit 43 includes a plurality of two-input AND gates 41 connected in cascade and a two-input OR gate 40 connected to one of the AND gates 41. As in FIG. 1, corresponding determination outputs D0 to D63 and P0 to P6 are input to one input of the OR gate 40. The mask signal φ4 is input to the other input of the OR gate 40 that receives the determination outputs D0 to D63 at one input, and the mask signal φ5 is input to the other input of the OR gate 40 that receives the determination outputs P0 to P6 at one input. Is done. The mask signals φ4 and φ5 are formed by the control logic circuit 44 that inputs the selection signal SEL1 of the memory block BLK1 and the selection signal SEL2 of the memory block BLK2 output from the control circuit 21. The control logic 44 inputs a block selection signal SEL1, SEL2 and outputs a mask signal φ4, a NOR gate 45 that outputs a mask signal φ4, an inverter 46 that inverts the block selection signal BLK1, and an output of the inverter 46 and a block selection signal BLK2 that inputs a mask signal. It consists of a NAND gate 47 for generating φ5. The control circuit 21 and the control logic circuit 44 function as a selection control circuit for the mask function of the aggregation determination circuit 43.

  The control circuit 21 controls the block selection signal SEL1 to the high level and the block selection signal SEL2 to the low level in the write verify operation for the memory block BLK1. In response to this, the control logic circuit 44 sets the mask signal φ4 to the low level and the mask signal φ5 to the high level. In the write operation to the memory block BLK1, the non-use area NUAR is not a write target, but in the write verify operation, the determination outputs P0 to P6 corresponding to the non-use area NUAR are masked by the NOR gate 40 receiving the mask signal φ5. A write verify result for the region DTAR can be obtained by a 1-bit verify result signal φvfy.

  On the other hand, the control circuit 21 controls the block selection signal SEL2 to the high level and the block selection signal SEL1 to the low level in the write verify operation for the memory block BLK2. In response to this, the control logic circuit 44 sets both the mask signal φ4 and the mask signal φ5 to the low level. In the write operation to the memory block BLK2, both the data area DTAR and the parity data area PTAR are to be written. In the write verify operation, all judgment outputs D0 to D63 and P0 to P6 for the areas are low level mask signals φ4. , Φ is not masked by the NOR gate 40 receiving φ5, and a write verify result for both the data area DTAR and the parity data area PTAR can be obtained by a 1-bit verify result signal φvfy.

《Determination mask control that differs depending on whether redundancy relief exists or not》
FIG. 8 shows another example of selection control for the write verify determination circuit 30 and its mask function. Here, the memory array 11 includes a normal memory area (hereinafter also referred to as a user memory block (UBLK)) 50 and a redundant memory area (hereinafter also referred to as a repair memory block (RDBLK)) 51 used for defect repair of the user memory block 50. And have. In FIG. 1, each of D0 to D63, R0 corresponds to the determination output φ1 of the 1-bit determination circuit 31 in FIG. Since the circuit configuration for forming the determination outputs D0 to D63 and R0 is the same as the configuration 31 corresponding to one memory mat 33 in FIG. 1, detailed description thereof is omitted here. Din0 to din63 are connected to the user memory block 50, and dinR0 is connected to the relief memory block 51, and each corresponds to the common data line CD in FIG. The selection control logic 52 is a logic circuit for inputting data from the data bus DBUS to din0 to din63 in units of 16 bits. The selection control logic 53 is a logic circuit that enables transfer of write data bits to be relieved in accordance with access to an address (relief address) to be relieved.

  The decision aggregation circuit 55 includes a plurality of two-input AND gates 41 connected in cascade as in FIG. 1 and a two-input OR gate 40 connected to one of the AND gates 41. The corresponding determination outputs D0 to D63 and R0 are input to one input of the OR gate 40 corresponding to the determination outputs D0 to D63 and R0, respectively, and the corresponding mask signals TH_D0 to TH_D63 and Re are input to the other input. . The selection control logic 56 controls the mask signal corresponding to the relief address to a high level when the relief address is rescued in the relief memory area 51 in the write verify operation, and all the mask signals TH_D0 to TH_D63 when the relief is not performed. Is controlled to a low level.

  FIG. 9 shows an example of the selection control logic 52. FDB0 to FDB15 are write data input from the data bus DBUS. FAB1 and FAB2 indicate 2 bits in the transfer destination address of the write data supplied from the address bus ABUS. DIS is a data transfer start signal for write data. The input gate circuit G1 selectively transmits data FDB0 to FDB15 to din0 to din15, the input gate circuit G2 selectively transmits data FDB0 to FDB15 to din16 to din31, and the input gate circuit G3 transmits data FDB0 to FDB15. The input gate circuit G4 selectively transmits data FDB0 to FDB15 to din48 to din63. When the data transfer start signal DIS is activated, the input gates G1 to G4 are sequentially selected by sequentially incrementing the values of the 2-bit address bits FAB1 and FAB2, and are sequentially supplied in units of 16 bits. The incoming write data is sequentially supplied to din0 to din63 in units of 16 bits.

  FIG. 10 shows an example of the selection control logic 53. Re is a relief enable signal, and R0 to R5 are relief address signals. When the write data FDB15 to FDB0 are supplied, the selection control logic 53 is used as an input gate selected by the address bits FAB1 and FAB2 on condition that the 2-bit address bits FAB1 and FAB2 match the relief address bits R0 and R1. Among the corresponding 16-bit write data, the 1-bit write data indicated by the remaining 4 bits of relief address bits R2 to R5 is selected by the selector 57 and supplied to the relief memory block 51 as DinR0. The data DinR0 is latched by the write data latch 29 in the relief mat using a part of the write verify address at that time. The specific contents of the selection logic by the selector 57 are shown in the truth table attached to FIG.

  FIG. 11 shows an example of the selection control logic 56. When the relief is performed by the relief addresses R0 to R5, the relief enable signal Re is at the low level. At this time, one of the mask signals TH_D0 to TH_D63 designated by the relief addresses R0 to R5 is set to the high level. As a result, the judgment output (one of D0 to D63) from the memory mat to be relieved by the relief address is masked by the OR gate 4, and the mask by the OR gate 4 on the judgment output R0 from the redundant memory block 51 is released. The When the redundant relief is not performed, all of the determination outputs D0 to D63 are set to the low level, the mask is released, and the determination output R0 is masked. The write verify range by the aggregation determination circuit 55 can be made variable according to whether the redundancy memory block 51 is relieved, and the write verify result can be obtained by a 1-bit verify result signal φvfy.

  FIG. 12 shows another example of the write data latch, the Y switch, and the 1-bit determination circuit. In the figure, a write data latch 28 has a static latch composed of two NAND gates NAND1 and NAND2 connected in antiparallel, and one of the storage nodes is a CMOS transfer gate comprising an NMOS transistor M10 and a PMOS transistor M11. It is connected to the corresponding common data line CD via the Y switch and the write gate 27 that have been configured. A write selection NMOS transistor M12 is connected to the bit line BL, and a discharge NMOS transistor M13 having a gate coupled to the other storage node of the static latch 28 is connected in series to the NMOS transistor. The 1-bit determination circuit 31 in FIG. 12 operates in the same manner as in FIG.

  According to the flash memory 4 of the microcomputer 1 described above, the write verify result can be aggregated and output as a 1-bit verify result signal φvfy, and can be used for bit line relief, use of parity data or unused. The write verify range can be made variable according to the above. The central processing unit 2 does not have to bear the burden of determining by sequentially comparing the verify read data and the write data in the write verify operation.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the semiconductor device is not limited to a microcomputer including a CPU, and may be a semiconductor device having a volatile memory such as a flash memory.

  The nonvolatile memory is not limited to the flash memory, and may be an EEPROM or the like. The memory cell structure of the flash memory is not limited to the stack type MONOS structure, and may be a structure having a floating gate, or a split gate having a memory transistor portion and a select transistor portion in series. The logic circuit structures of the 1-bit determination circuit and the aggregation determination circuit can be changed as appropriate.

FIG. 5 is a circuit diagram showing an example of a memory mat and a write verify determination circuit corresponding to the memory mat. 1 is a block diagram of a microcomputer as an example of a semiconductor device according to the present invention. It is a block diagram of a flash memory. 5 is a flowchart of a write operation and a write verify operation. 6 is a timing chart of a write operation and a write verify operation. It is an example circuit diagram of a verify sense amplifier. It is a circuit diagram which shows another example of selection control with respect to a write verify determination circuit and its mask function. It is a circuit diagram which shows another example of selection control with respect to a write verify determination circuit and its mask function. FIG. 9 is an example circuit diagram of the selection control logic 52 of FIG. 8. An example of the selection control logic 53 of FIG. 8 is shown. FIG. 9 is an example circuit diagram of the selection control logic 56 of FIG. 8. FIG. 6 is a circuit diagram illustrating another example of a write data latch, a Y switch, and a 1-bit determination circuit.

Explanation of symbols

1 Microcomputer 2 Central processing unit (CPU)
3 RAM
4 Flash memory (FLASH)
5 Direct memory access controller (DMAC)
6, 7 I / O port (PRT)
8 Timer (TMR)
9 Clock generator (CPG)
10 Internal Bus ABUS Address Bus DBUS Data Bus TMR Output Terminal 12 X Address Decoder (XDEC) and Driver (XDRV)
13 Address buffer (ADB)
16 Write latch circuit (WRL)
28, 29 Write data latch (LAT)
BL bit line 17 Y decoder (YSW • YDEC)
18 Sense amplifier circuit (SAA)
19 Input / output circuit (IO)
φvfy 1-bit verify result signal M1 bit line select transistor M3 to M4 data latch select transistor CD common data line 30 write verify determination circuit 30
31 1-bit decision circuit (SBD)
32 Judgment Aggregation Circuit (DAGR)
33 Memory Mat (MAT)
36 exclusive negative OR gate 37 verify sense amplifier φ1 1-bit decision signal φ2, φ3 mask signal 40 OR gate 41 AND gate 43 decision aggregation circuit 44 control logic circuit BLK1, BLK2 memory block SEL1, SEL2 memory block selection signal φ4, φ5 mask Signal DTAR data area PTAR parity data area M1 column selection NMOS transistor yw0 to ywn column selection signal 50 user memory block 51 relief memory block 52, 53, 56 selection control logic 55 decision aggregation circuit

Claims (10)

A semiconductor device comprising a nonvolatile memory that is electrically erasable and writable,
The nonvolatile memory includes a memory array including a plurality of nonvolatile memory cells connected to a plurality of bit lines, and write data corresponding to read data in a verify read unit read from the memory array in a write verify operation. A plurality of 1-bit determination circuits that compare and determine parallel to the write data bits of the latch, a determination aggregation circuit that aggregates the determination results of the plurality of 1-bit determination circuits, and a determination aggregation result of the determination aggregation circuit And an output terminal for outputting to the outside of the non-volatile memory,
The determination aggregation circuit is a semiconductor device capable of selecting target bits to be aggregated among the determination results of the plurality of 1-bit determination circuits.   The 1-bit determination circuit is connected to a bit line selection transistor that selects a bit line specified by a verify read address from a plurality of bit lines, and the write corresponding to the bit line selected by the bit line selection transistor A data latch selection transistor that selects latch data of a data latch, and a comparison circuit that compares data of a bit line selected by the bit line selection transistor with latch data selected by the data latch selection transistor. Item 14. A semiconductor device according to Item 1.   The semiconductor device according to claim 2, wherein the bit line selection transistor has a higher gate breakdown voltage than the data latch selection transistor.   The determination aggregation circuit includes a mask gate capable of selectively forcing the determination result of the 1-bit determination circuit to be a determination match, and a determination gate for determining whether or not all bits match the output of the respective mask gates The semiconductor device according to claim 1, further comprising: a circuit; and a selection control circuit that selectively controls forced determination coincidence by the mask gate.   The determination gate circuit has two input first logic gates arranged for each mask gate, the first input of the first logic gate receives the output of the corresponding mask gate, and the first logic gate of the first logic gate The two inputs receive the output of the first logic gate on the upper side of the signal path and are cascade-connected sequentially to the lower side, and the logic value supplied to the second input of the cascaded uppermost first logic gate is the lowest 5. The semiconductor device according to claim 4, wherein a state in which the determination results of the respective 1-bit determination circuits are all coincident is obtained with the state transmitted to the output of the first logic gate. The mask gate is a two-input second logic gate. The first group of mask gates is supplied with the first mask signal and the determination result of the corresponding 1-bit determination circuit, and the second group of mask gates is supplied with the first mask signal. The second mask signal and the corresponding determination result of the 1-bit determination circuit are supplied,
The nonvolatile memory cells connected to the bit lines corresponding to the first group of mask gates in the memory array serve as data storage areas, and the nonvolatile memory is connected to the bit lines corresponding to the second group of mask gates. The cell is an area for storing parity data of the data stored in the data storage area,
The selection control circuit sets the first mask signal to a level for deselecting forcing the determination coincidence by the mask gate in a write verify operation when writing data without parity in the data storage area. The mask signal is set to a level where selection of forced matching by the mask gate is selected, and the first mask signal and the second mask signal are used as the mask in a write verify operation when writing data and its parity data in the data storage area. 6. The semiconductor device according to claim 5, wherein forcing of determination coincidence by the gate is set to a level for deselecting. The mask gate is a two-input second logic gate. The first group of mask gates is supplied with the first mask signal and the determination result of the corresponding 1-bit determination circuit, and the second group of mask gates is supplied with the first mask signal. The second mask signal and the corresponding determination result of the 1-bit determination circuit are supplied,
The memory array includes a first memory area and a second memory area that can be selected by a memory area selection signal.
The first memory region has a nonvolatile memory cell connected to a bit line corresponding to the first group of mask gates as a data storage region, and is connected to a bit line corresponding to the second group of mask gates. Non-volatile memory cells as non-use areas,
The second memory region has a nonvolatile memory cell connected to a bit line corresponding to the first group of mask gates as a data storage region, and is connected to a bit line corresponding to the second group of mask gates. A non-volatile memory cell as a parity data storage area for storing parity data of data stored in the data storage area;
In the write verify operation for the first memory area, the selection control circuit sets the first mask signal to a level that deselects the forced determination coincidence by the mask gate, and sets the second mask signal to the mask gate. Is set to a level at which selection matching is forced by selection, and the first mask signal and the second mask signal are set to a level at which determination matching by the mask gate is not selected in the write verify operation for the second memory area. The semiconductor device according to claim 5. The memory array has a normal memory area and a redundant memory area used for defect repair of the normal memory area;
The mask gate is a two-input second logic gate, and a mask signal corresponding to the normal memory area is supplied with a first mask signal different for each mask gate and a determination result of a 1-bit determination circuit corresponding thereto. The mask gate corresponding to the redundant memory region is supplied with the second mask signal and the determination result of the 1-bit determination circuit corresponding thereto,
In the write verify operation, the selection control circuit sets the first mask signal to a level for deselecting the forced determination coincidence by the mask gate when relief by the redundant memory region is not performed. When the second mask signal is set to a level at which selection of forced matching by the mask gate is selected and relief is performed by the redundant memory area, the mask corresponding to the bit line being replaced by the redundant memory area The first mask signal of the gate is set to a level for selecting the forced determination match by the mask gate as selected, and the other first mask signal is set to a level for deselecting the forced determination match by the mask gate, and The second mask signal is set to a level that deselects the forced judgment match by the mask gate. The semiconductor device of claim 5, wherein.   The semiconductor device according to claim 1, further comprising: a central processing unit capable of controlling access to the nonvolatile memory, wherein the central processing unit inputs a determination aggregation result of the determination aggregation circuit. A semiconductor device having an electrically erasable and writable nonvolatile memory and a central processing unit, formed on one semiconductor chip,
The nonvolatile memory includes a memory array including a plurality of nonvolatile memory cells connected to a plurality of bit lines, and write data corresponding to read data in a verify read unit read from the memory array in a write verify operation. A plurality of 1-bit determination circuits that compare and determine in parallel with the write data bits of the latch, and a determination aggregation circuit that aggregates the determination results of the plurality of 1-bit determination circuits into one bit;
The determination aggregation circuit can select a target bit to be aggregated into one bit among the determination results of the plurality of 1-bit determination circuits,
The semiconductor device, wherein the central processing unit instructs a write verify operation of the nonvolatile memory, and receives a result of the write verify operation as a determination aggregation result by the determination aggregation circuit.

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