JP2008021134A - Wiring layout-routing method, and data processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To minimize increase in the load for verification of timing using a verification tool, even if PVT condition points, to be confirmed with respect to the result of wiring layout-routing, is increased. <P>SOLUTION: With respect to the result of the wiring layout-routing of the cells decided considering the first PVT condition, a wiring layout-routing method of supporting wiring layout routing of cells simply evaluates (S11) the delay of a signal path decided by wiring layout-routing processing, based on delay data concerning cell operation delay and routing delay on a data table on a first PVT condition, and evaluates (S12) the delay in the signal path on a second PVT condition, based on the product of evaluation coefficients (α, β) and the delay in the signal path used in the first evaluation processing. The evaluation coefficients are coefficients for regulating two or more delay times, calculated with respect to the optional combination of the cell operation delay and the routing delay on the first PVT condition, with respect to two or more delay times calculated to the optional combination of the cell operation delay and the routing delay on the second PVT condition as a linear function. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a placement and routing method of a semiconductor integrated circuit and a data processing system for realizing the placement and routing method, and relates to a technique effective when applied to, for example, an automatic placement and routing (also simply referred to as P & R) tool.

  In the placement and routing of a semiconductor integrated circuit, a placement and routing tool that supports the placement and routing of cells for realizing a required logic function in the semiconductor integrated circuit is used. For the result of placement and routing using the placement and routing tool, it is necessary to satisfy that the operation is stable within the design operation guarantee range by using a verification tool such as a logic simulator. At present, with respect to the result of automatic placement and routing, conditions of a predetermined process (P: semiconductor manufacturing process), voltage (V: operating power supply voltage), and temperature (T: ambient temperature) (these conditions are referred to as PVT in this specification). Since it is necessary to guarantee the operation within the range of (referred to as a condition), the operation timing is confirmed at several PVT condition points. If the required operation timing cannot be guaranteed by this timing verification, it is necessary to correct the layout again using the placement and routing tool.

  In recent years, as the speed of LSI (semiconductor integrated circuit) increases and the operating power supply voltage decreases, the influence of wiring increases (see FIG. 9) and the characteristics of MOS (field effect transistor) devices change, resulting in PVT dependency. It is becoming more complex and the number of PVT condition points to be checked is increasing. In FIG. 9, as the process generation progresses, the wiring width becomes narrower, the dielectric constant of the interlayer film becomes higher, and the wiring material changes from aluminum-based to copper-based, compared to the change in wiring capacitance (characteristic line B). It shows that the resistance change (characteristic line A) is large. FIG. 10 shows the temperature characteristics of a MOS device manufactured by a process with a minimum wiring width of 0.25 micron meter (μm), and FIG. 11 shows a MOS device manufactured by a process with a minimum wiring width of 90 nanometers (nm). The temperature characteristics of are shown. According to this, the wiring becomes low speed (high resistance) at a high temperature and has no voltage dependence, but the MOS device often becomes low speed at a low voltage. Further, when the MOS device has a slow transition time (hereinafter also referred to as slew) when the input signal transitions from a low level (Low) to a high level (High) or vice versa (in the case of low-speed operation). Decreasing speed at low temperatures becomes prominent, and in the opposite case (in the case of high speed operation), there is an increasing tendency to see lower speed on the high temperature side (see FIGS. 10 and 11).

  As described above, when the PVT dependency becomes complicated and the number of PVT condition points to be confirmed increases, the verification tool for performing the timing verification uses the device model to verify the timing information of all paths. The circuit scale is too large to be executed. Therefore, it is common to perform timing verification using static timing analysis (hereinafter also referred to as STA). The STA is a method for accumulating delays of logic circuits in a path and checking timing constraint violation, and is a process for confirming data propagation from a path start point to an end point within a clock cycle time. There is Patent Document 1 as a document describing static timing analysis.

Japanese Patent Application Laid-Open No. 2005-275783

  In static timing analysis, a table (hereinafter also simply referred to as a library) that models output capacity and input Slew is prepared in advance for various devices of a single logic circuit, and when delay times in a path are integrated, Get logic circuit delay and timing information from the library. However, in the confirmation of the timing operation using the verification tool, if the number of PVT condition points to be confirmed increases, it takes an enormous time to create a library for each of a plurality of condition points. In addition, timing verification using a verification tool is performed for each of a plurality of PVT condition points, and when the inconvenience is returned to the use of the placement and routing tool again, the processing becomes complicated and the processing man-hours increase. The present inventor has found that the convergence with respect to the correction of the placement and wiring may be deteriorated.

  An object of the present invention is to provide a placement and routing method capable of suppressing an increase in the burden on timing verification using a verification tool as much as possible even if the number of PVT condition points to be confirmed with respect to the placement and routing results increases, and the An object of the present invention is to provide a data processing system for realizing such a placement and routing method.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A placement and routing method according to the present invention is a placement and routing method (S1) for supporting placement and routing of cells for realizing a required logic function in a semiconductor integrated circuit using a computer device, and a placement and routing process. (S10), a first evaluation process (S11), a second evaluation process (S12), and a correction process (S13) are included. The placement and routing process is a process for determining the placement and routing of cells in consideration of the first PVT condition. The first evaluation process is a process for evaluating the delay of the signal path determined by the placement and routing process based on the delay data related to the cell operation delay and the wiring delay on the data table (LDcpn) in the first PVT condition. The second evaluation process is a process for evaluating the delay of the signal path under the second PVT condition based on a product of an evaluation coefficient (α, β) and the delay of the signal path used in the first evaluation process. The correction process is a process for performing a necessary correction on the signal path determined by the placement and routing process according to the first evaluation process result and the second evaluation process result. The evaluation coefficient is for an arbitrary combination of the cell operation delay and the wiring delay of the second PVT condition with respect to a plurality of delay times calculated for the arbitrary combination of the cell operation delay and the wiring delay of the first PVT condition. This is a coefficient for defining the calculated delay times as a linear function. The evaluation coefficient has, for example, an operation delay coefficient related to the cell operation delay and a wiring delay coefficient related to the wiring delay separately.

  In the above method, the evaluation based on a plurality of PVT conditions can be performed through the first evaluation process and the second evaluation process at the layout stage by the placement and routing process, and the placement and routing process is performed at the layout stage according to the evaluation. It can be corrected. The delay of the signal path under the second PVT condition can be evaluated based on the product of the evaluation coefficient and the delay of the signal path used in the first evaluation process. Even if the number of PVT condition points to be confirmed with respect to the placement and routing results increases, it is not necessary to prepare a data table for each PVT condition, and the layout that is expected to be unable to guarantee the operation timing is placed and routed. Therefore, the increase in the burden on the timing verification using the verification tool is suppressed as much as possible.

  As one specific form, whether or not the evaluation by the first evaluation process and the second evaluation process has a predetermined margin with respect to the setup time and hold time between the cells on the signal path constituting the latch. The signal propagation delay obtained by subtracting the data path delay from the sum of the clock period and the clock path delay is used for setup evaluation, and the hold time is evaluated using the data path delay to the clock path delay. And the signal propagation delay is used.

  As a more specific form, when it is evaluated that there is no predetermined margin or more in the first evaluation process, the second evaluation process includes a margin that is greater than or equal to a setup time and hold time between cells constituting the latch. Evaluate whether there is. It is possible to suppress the useless second evaluation process.

  [2] A placement and routing method (S1) according to another aspect of the present invention is a method of supporting placement and routing of cells for realizing a required logic function in a semiconductor integrated circuit using a computer device. This includes placement and routing processing (S10) for determining cell placement and routing in consideration of the 1PVT condition, evaluation processing (S14), and correction processing (S13). The evaluation process includes a first delay of the signal path determined by the placement and routing process acquired based on the delay data related to the cell operation delay and the wiring delay on the data table in the first PVT condition, the evaluation coefficient, and the first delay. And the second delay of the signal path under the second PVT condition and the second delay of the signal path under the previous first PVT condition. The correction process is a process for performing a necessary correction on the signal path determined by the placement and routing process in accordance with the result of the evaluation process. At this time, the evaluation coefficient is an arbitrary combination of the cell operation delay and the wiring delay of the second PVT condition with respect to a plurality of delay times calculated for the arbitrary combination of the cell operation delay and the wiring delay of the first PVT condition. Is a coefficient for defining a plurality of delay times calculated with respect to as a linear function. The evaluation coefficient has, for example, an operation delay coefficient related to the cell operation delay and a wiring delay coefficient related to the wiring delay separately.

  In the above method, the evaluation based on a plurality of PVT conditions can be performed collectively without performing each PVT condition at the stage of layout by the placement and routing process, and the efficiency of the evaluation process can be improved. Obtaining a second delay in the second PVT condition based on a product of the first delay and the evaluation coefficient determined using the data table in the first PVT condition, and evaluating the signal path using the first and second delays; Can do. Even if the number of PVT condition points to be confirmed with respect to the placement and routing results increases, it is not necessary to prepare a data table for each PVT condition, and a layout that is expected to be unable to guarantee operation timing is placed and routed. Therefore, the increase in the burden on the timing verification using the verification tool is suppressed as much as possible.

  As one specific form of the present invention, the evaluation by the evaluation process is performed by using the second data obtained using the data delay under the first PVT condition and the evaluation coefficient between cells on the signal path constituting the latch. It is evaluated whether or not the ratio to the data delay under the PVT condition is smaller than a predetermined value. Instead, the magnitude of the difference may be evaluated. In addition to the evaluation of the data delay, the magnitude of the ratio or the difference may be evaluated for the clock delay in the same manner as described above.

  As a more specific form of the present invention, the correction process may be performed only when an evaluation that the value is larger than the predetermined value is performed. This is to prevent unnecessary correction processing.

  [3] A data processing system according to the present invention is a system that supports cell placement and routing for realizing a required logic function by a semiconductor integrated circuit, and includes a computer device and a storage device. The storage device holds an evaluation coefficient and a data table. The computer apparatus includes a placement and routing processing unit that determines cell placement and routing in consideration of the first PVT condition, a first evaluation processing unit, a second evaluation processing unit, and a correction processing unit. The first evaluation processing unit evaluates the delay of the signal path determined by the processing of the placement and routing processing unit based on the cell operation delay and the delay data related to the wiring delay on the data table in the first PVT condition read from the storage device. To do. The second evaluation processing unit evaluates the delay of the signal path under the second PVT condition based on the product of the evaluation coefficient read from the storage device and the delay of the signal path used in the first evaluation process. The correction processing unit performs correction necessary for the signal path determined by the placement and routing processing unit in accordance with the processing result of the first evaluation processing unit and the processing result of the second evaluation processing unit. At this time, the evaluation coefficient is an arbitrary combination of the cell operation delay and the wiring delay of the second PVT condition with respect to a plurality of delay times calculated for the arbitrary combination of the cell operation delay and the wiring delay of the first PVT condition. Is a coefficient for defining a plurality of delay times calculated with respect to as a linear function.

  In the data processing system, the evaluation by a plurality of PVT conditions can be performed through the first evaluation processing unit and the second evaluation processing unit at the layout stage by the placement and routing processing unit, and the layout stage is performed according to the evaluation. The placement and routing can be corrected. The delay of the signal path under the second PVT condition can be evaluated based on the product of the evaluation coefficient and the delay of the signal path used in the first evaluation processing unit. Even if the number of PVT condition points to be confirmed with respect to the placement and routing results increases, it is not necessary to prepare a data table for each PVT condition, and the layout that is expected to be unable to guarantee the operation timing is placed and routed. Therefore, the increase in the burden on the timing verification using the verification tool is suppressed as much as possible.

  As one specific form of the present invention, the first evaluation processing unit and the second evaluation processing unit have a predetermined margin for a setup time and a hold time between cells on the signal path constituting the latch. The signal propagation delay time obtained by subtracting the data path delay from the sum of the clock period and the clock path delay is used as the setup time, and the data path delay to the clock path delay is used as the hold time. And the signal propagation delay time is used.

  As a more specific form, the second evaluation processing unit evaluates the setup time and hold time between the cells constituting the latch when the first evaluation processing unit evaluates that there is not a predetermined margin or more by confirmation. Evaluate whether there is a margin greater than or equal to a predetermined value. The useless operation of the second evaluation processing unit can be suppressed.

  [4] A data processing system according to another aspect of the present invention is a system for supporting the placement and routing of cells for realizing a required logic function with a semiconductor integrated circuit, and includes a computer device and a storage device. The storage device holds an evaluation coefficient and a data table. The computer apparatus includes a placement and routing processing unit that determines cell placement and routing in consideration of the first PVT condition, an evaluation processing unit, and a correction processing unit. The evaluation processing unit has a first delay of the signal path determined by the placement and routing processing unit acquired based on the delay data related to the cell operation delay and the wiring delay on the data table in the first PVT condition read from the storage device. , Based on the second delay obtained as a product of the evaluation coefficient read from the storage device and the first delay, the first delay of the signal path in the previous first PVT condition and the signal path in the second PVT condition The second delay is evaluated. The correction processing unit performs necessary corrections on the signal path determined by the processing of the placement and routing processing unit according to the processing result of the evaluation processing unit. At this time, the evaluation coefficient is an arbitrary combination of the cell operation delay and the wiring delay of the second PVT condition with respect to a plurality of delay times calculated for the arbitrary combination of the cell operation delay and the wiring delay of the first PVT condition. Is a coefficient for defining a plurality of delay times calculated with respect to as a linear function.

  In the data processing system, the evaluation based on a plurality of PVT conditions can be performed collectively without performing each PVT condition at the stage of layout by the placement and routing processing unit, and the efficiency of the evaluation process can be improved. Obtaining a second delay in the second PVT condition based on a product of the first delay and the evaluation coefficient determined using the data table in the first PVT condition, and evaluating the signal path using the first and second delays; Can do. Even if the number of PVT condition points to be confirmed with respect to the placement and routing results increases, it is not necessary to prepare a data table for each PVT condition, and the layout that is expected to be unable to guarantee the operation timing is placed and routed. Therefore, the increase in the burden on the timing verification using the verification tool is suppressed as much as possible.

  As one specific form of the present invention, the evaluation processing unit includes the second PVT acquired using the data delay under the first PVT condition and the evaluation coefficient between cells on the signal path constituting the latch. It is evaluated whether the ratio to the data delay under the condition is smaller than a predetermined value. Instead, the magnitude of the difference may be evaluated. In addition to the evaluation of the data delay, the magnitude of the ratio or the difference may be evaluated for the clock delay in the same manner as described above.

  As a more specific form of the present invention, the correction process may be performed only when an evaluation that the value is larger than the predetermined value is performed. This is to prevent unnecessary correction processing.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, even if the number of PVT condition points to be confirmed with respect to the placement and routing result increases, an increase in the burden on timing verification using the verification tool can be suppressed as much as possible.

  FIG. 3 schematically shows a method for developing a semiconductor integrated circuit to which the placement and routing method according to the present invention is applied. Desired semiconductor integrated circuit design data is generated by logic design and circuit design. The design data is composed of logic description data, circuit description data, etc. according to a predetermined format. Based on the design data, placement and routing support processing (S1) for circuit components such as a cell of a component library (LDcpn) and an IP (intellectual property) module is performed. For the result of the placement and routing support process (S1), a delay component (resistance value, capacitance value) is extracted between cells and IP modules (S2), and the placement and routing process is performed using the extracted delay component. Timing verification processing (S3) for the result is performed. For circuit arrangements for which operation performance cannot be guaranteed by timing verification, place and route support processing (S1) is performed again to correct the circuit arrangement. Mask data (Dm) is obtained through necessary corrections and timing verification again. A placement and routing tool is used for the placement and routing support process (S1), and a timing verification tool is used for the timing verification process. In timing verification, timing verification using static timing analysis (hereinafter also referred to as STA) is generally performed. As shown in FIG. 4, the timing verification by the static timing analysis is performed by integrating the delay of the logic circuit in the path, and within the clock cycle time based on the data path delay integrated value and the clock path delay integrated value. This is a process for checking a timing constraint violation by checking whether or not data propagation can be performed from the start point to the end point of the path. In static timing analysis, as illustrated in FIG. 5, an evaluation library (LDeva), which is a table modeling output capacity and input Slew, is prepared in advance for various devices of a single logic circuit. When integrating the delay time, the delay and timing information of the logic circuit is acquired from the library.

  FIG. 1 illustrates a flowchart of the placement and routing support process (S1). The placement and routing support process (S1) shown in the figure is simply the placement and routing process (S10) for determining the placement and routing of the cells in consideration of the first PVT condition, and the delay of the signal path determined by the placement and routing process. The first evaluation process (S11) and the second evaluation process (S12) to be verified, and the correction for performing the necessary correction on the signal path determined by the placement and routing process according to the first evaluation process result and the second evaluation process result Processing (S13).

  The first evaluation process (S11) is a process for evaluating the delay of the signal path determined by the placement and routing process based on the delay data related to the cell operation delay and the wiring delay on the data table in the first PVT condition. . In the data table which is a reference for the evaluation, operation delay data corresponding to the operation delay of various cells under the first PVT condition and wiring delay data corresponding to the wiring delay are stored. It is sufficient that this data table is prepared as a part of the component library LDcpn. In the second evaluation process (S12), the delay in the second PVT condition of the signal path determined by the placement and routing process is evaluated based on the product of the delay of the signal path used in the first evaluation process and the evaluation coefficient. It is processing.

  The evaluation coefficient is for an arbitrary combination of the cell operation delay and the wiring delay of the second PVT condition with respect to a plurality of delay times calculated for the arbitrary combination of the cell operation delay and the wiring delay of the first PVT condition. This is a coefficient for defining the calculated delay times as a linear function.

Here, the principle significance of the evaluation coefficient will be described. Delay information from one logical element to the next logical element under a certain PVT condition A (first PVT condition) is defined as delay_A. This is divided into wiring delay and logic element delay, and the delay under condition A is
delay_A = dg_A + dw_A (Formula 3-1). In Equation 3-1, dw_A means wiring delay under condition A, and dg_A means logic element delay under condition A. If the wiring delay and logic element delay under another PVT condition B (second PVT condition) are expressed as a function of process (P), voltage (V), temperature (T) and dw_A, dg_A,
dg_B = f (P, V, T, dg_A): logic element delay under condition B (Equation 3-3),
dw_B = g (P, V, T, dw_A): Wiring delay under condition B (Equation 3-2). If delay information in this condition B is delay_B,
delay_B = dg_B + dw_B (Expression 3-4)
In this equation 3-4, delay information delay_B under condition B is calculated using coefficient α and coefficient β.
delay_B = α × dg_A + β × dw_A (Equation 3-5) is approximated, and the coefficients α and β are derived in advance to obtain dw_A and dg_A. Can also be predicted. Furthermore, the delay path path_delay_A in which the x-stage logic elements in the condition A are connected is
path_delay_A = delay_A1 + delay_A2 + delay_A3 + ... + delayAx (Equation 3-6)
And using Equation 3-1,
path_delay_A = (dg_A1 + dg_A2 + dg_A3 + ... + dg_Ax)
+ (dw_A1 + dw_A2 + dw_A3 + ... + dw_Ax)
= Σdg_A + Σdw_A… (Equation 3-7),
It becomes. The delay for condition B uses (Equation 3-5) and (Equation 3-7)
path_delay_B = Σdg_B + Σdw_B
= α × Σdg_A + β × Σdw_A (Expression 3-8) α and β are evaluation coefficients, and (Equation 3-7) is used in the first evaluation process, and (Equation 3-8) is used in the second evaluation process.

  The evaluation coefficients α and β are obtained in advance before the first and second evaluation processes. For example, cell operation delays and wiring delays are made for each of a number of paths arbitrarily combining the types of cells (logic elements) such as inverters, NAND gates and NOR gates, the number of cell connection stages, and the lengths of inter-cell wirings. The propagation delay time is actually calculated under the first PVT condition, and the propagation delay time under the second PVT condition is calculated for the same path. For each of the same routes, the first propagation delay time calculated under the first PVT condition is txi, the second propagation delay time calculated under the second PVT condition is yti, and its (txi, tyi) is a two-dimensional coordinate point. The coefficients α and β in (Equation 3-8) are determined using the least square method for the coordinate point data relating to the first and second propagation delay times.

  6 and 7, the evaluation coefficients α and β obtained by the calculation are actually the types of cells (logic elements), the number of cell stages, the length of the inter-cell wiring, etc. as shown in the schematic diagram of FIG. A combination logic circuit is created and verified. FIG. 6 shows the case where verification is performed with a high threshold voltage MOS transistor (HVT_MOS) at 90 nm process and 125 ° C., and FIG. 7 shows the verification with a low threshold voltage MOS transistor (LVT_MOS) at 90 nm process and 125 ° C. Show the case. Triangular samples are exclusively measured values for signal paths with the number of cell stages changed, and square samples are exclusively measured values for signal paths with the inter-cell wiring length changed. Both are within an error range of ± 10% with respect to the linear function by α and β obtained by calculation (solid line passing through the diagonals in FIGS. 6 and 7). In this verification, the slew of the cell input waveform is assumed to be constant for convenience.

  A specific method for the first evaluation process and the second evaluation process will be described. In order to actually guarantee the operation of the semiconductor integrated circuit, as described with reference to FIG. 4, data transfer confirmation from the start point to the end point of the signal propagation path (path) is performed within one cycle time of the clock. A path from the start point to the end point clock pin is called a clock path, and a path from the start point to the end point data pin is called a data path. The path delay required for data propagation confirmation is represented by the sum of delay information between logic elements in the data path or clock path.

For example, the data path delay (data_A) in which the x-stage logic elements are connected under the condition A and the clock path delay (clk_A) in which the y-stage logic elements are connected are expressed by the above (Expression 3-6) and (Expression 3-7),
data_A = Σdata_dg_A + Σdata_dw_A ... (Equation 3-8)
clk_A = Σclk_dg_A + Σclk_dw_A… (Equation 3-9)
Can be expressed as Using these (Equation 3-8) and (Equation 3-9) and evaluation coefficients α and β, the data path delay (data_B) and clock path delay (clk_B) in the case of condition B are
data_B = α × Σdata_dg_A + β × Σdata_dw_A (Equation 3-10)
clk_B = α × Σclk_dg_A + β × Σclk_dw_A (Equation 3-11)
Can be expressed as

As an evaluation using the data path delay and the clock path delay, for example, a case where a setup time (hereinafter referred to as setup) and a hold time (hereinafter referred to as hold) are considered will be described. setup is the time constraint that the data path data must reach before the clock path data is transmitted to the end point, and hold is the time constraint that the data path data must not change until the clock path data reaches the end point It is. When the constraint time (slack) is expressed by an equation,
During setup: slack = period + clock path delay-data path delay
= Period + clk_A − data_A
When hold: slack = data path delay-clock path delay
= data_A−clk_A
Thus, the operation is guaranteed when slack ≧ 0.

When this is taken into consideration, the following equation [1] “slack value determination” may be employed as the operation confirmation determination formula in the first evaluation process and the second evaluation process. In the first evaluation process (S11), (Expression 3-12) and (Expression 3-14) are used. In the second evaluation process (S12), (Expression 3-13) and (Expression 3-15) are used.
[1] Slack value judgment (slack> fixed value)
During setup:
slack = clock period + clk_A−data_A
= Clock cycle + (Σclk_dg_A + Σclk_dw_A)-(Σdata_dg_A + Σdata_dw_A)> constant value (Equation 3-12)
slack = clock period + clk_B−data_B
= Clock cycle + (α × Σclk_dg_A + β × Σclk_dw_A)-(α × Σdata_dg_A + β × Σdata_dw_A)> constant value (Equation 3-13)
During Hold:
slack = data_A−clk_A
= (Σdata_dg_A + Σdata_dw_A) − (Σclk_dg_A + Σclk_dw_A)> constant value (Equation 3-14)
slack = data_B−clk_B
= (α × Σdata_dg_A + β × Σdata_dw_A) − (α × Σclk_dg_A + β × Σclk_dw_A)> constant value (Equation 3-15).

In addition, as the operation confirmation judgment formula, the formula of “data path delay ratio judgment” in [2], the formula of “data path delay difference judgment” in [3], the formula of “clock path delay ratio judgment” in [4], [ 5] “Clock path delay difference determination” may be adopted.
[2] Data path delay ratio judgment
| data_B / data_A |
= (α × Σdata_dg_A + β × Σdata_dw_A) / (Σdata_dg_A + Σdata_dw_A) <Constant value [3] Data path delay difference judgment
| data_B − data_A | = (α−1) × Σdata_dg_A + (β−1) × Σdata_dw_A) <constant value [4] Clock path delay ratio judgment
| clk_B / clk_A |
= (α × Σclk_dg_A + β × Σclk_dw_A) / (Σclk_dg_A + Σclk_dw_A) <Constant value [5] Clock path delay difference judgment
| clk_B − clk_A | = (α−1) × Σclk_dg_A + (β−1) × Σclk_dw_A) <constant value.

  When the determination formulas [2] to [5] are adopted, as is apparent from the formula, the evaluation is not separated into the first evaluation process (S11) and the second evaluation process (S12). The flowchart in this case is as shown in FIG. 2, and evaluation using any of the determination formulas [2] to [5] is performed as the evaluation process (S14). In the evaluation using the determination formulas [2] to [5], an object of evaluation is to prevent a large change in the difference in signal propagation delay time depending on the PVT condition. In addition, the number of evaluations can be reduced. The judgment formulas [1] to [5] may be given to the place and route support tool as judgment conditions in FIG.

According to the placement and routing method described above, the following operational effects can be obtained.
(1) A delay under another PVT condition (Condition B) can be simply calculated by reading a library of one PVT condition (Condition A) at the time of delay calculation performed during the placement and routing process. Therefore, the number of data libraries can be reduced for delay calculation as included in the component library (LDcpn).
(2) After the placement and wiring under a certain PVT condition, the operation timing by the placement and wiring can be simply evaluated so that the operation can be guaranteed even under other PVT conditions. In this way, the placement and routing correction can be repeated in accordance with the contents of the simple evaluation for the placement and routing result in the placement and routing support processing. Therefore, the convergence of the processing in the timing verification processing S3 downstream of the placement and routing support processing is improved. Can be increased. In short, the number of times of return from the timing verification process S3 to the placement and routing support process S1 can be reduced, and the placement and routing design time can be shortened.
(3) After placement and routing under a certain PVT condition, the placement and routing result can be easily evaluated (S12) so that the operation can be guaranteed under other PVT conditions (S12). By repeating the correction (S13), it is possible to reduce downstream timing verification conditions. In this respect, the number of libraries such as the evaluation library LDeva prepared for timing verification can be reduced.

  The placement and routing support processing S1 described with reference to FIGS. 3 and 1 is performed by executing a placement and routing tool. The timing verification process is performed by executing a timing verification tool. For execution of these tools, for example, an engineering workstation or the like may be used as a data processing system. The engineering workstation that executes the placement and routing tool that defines the placement and routing support processing S1 includes a computer device and a storage device, and the storage device is used to store the libraries LDcpn, LDeva, data Dm, and the like. The computer device, as a function realization means for realizing the placement and routing support processing, supports the processing of FIG. 1, a placement and routing processing unit that performs the placement and routing processing S10, a first evaluation processing portion that performs the first evaluation processing S11, A second evaluation processing unit that performs the second evaluation processing S12 and a correction processing unit that performs the correction processing S13 are included. In order to support the processing in FIG. 2, an evaluation processing unit for performing the evaluation processing S14 is further provided.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

For example, the evaluation process performed in the placement and routing support process S1 is not limited to the above process contents. For example, if delay_B is not calculated directly, and the delay ratio of dg_A and dw_A is close to the data path and clock path, the fluctuations in the PVT condition of condition B are similar, so slack is close to A You may use together performing only the operation | movement confirmation by assumption. The judgment condition at that time is
| Σdata_dg_A / Σdata_dw_A−Σclk_dg_A / Σclk_dw_A | <constant value or
| (Σdata_dg_A−Σdata_dw_A) − (Σclk_dg_A−Σclk_dw_A) | <constant value.

Further, in the operation confirmation under the condition A (first evaluation process), the operation confirmation under the condition B (second evaluation process) may be performed only for a path with a small margin (= slack is small). For example, during Hold,
Constant value X <data_A − clk_A <Constant value Y
Confirm that a constant value <data_B − clk_B is satisfied for the path. According to this method, it is possible to increase the speed of the placement and routing process S10 and improve the correction convergence by the correction process S13.

In the above description, the transition time (slew) of the input waveform to the cell is not a parameter in the functions of (Equation 3-2) and (Equation 3-3). Even if the transition time (slew) is assumed to be constant, a relatively simple logic circuit does not deviate significantly from the actual situation, and the processing can be simplified and the data amount of the delay table under the first PVT condition can be reduced accordingly. is there. For complex logic circuits, etc., the transition time (slew) may be taken into account for the input of a required cell in the signal propagation path as necessary. In that case, the following formula
dw_B = f (P, V, T, input slew, dw_A)
dg_B = g (P, V, T, input slew, dg_A)
As shown, the function parameter may include the input slew to the logic element. Verification accuracy can be improved. Naturally, in that case, the delay of the logic element is separated into the internal delay (dg_Ai) and the output part delay (dg_Ao).
dg_A = dg_Ai + dg_Ao
dg_B = α1 × dg_Ai + α2 × dg_Ao
As described above, the coefficient of the evaluation function suitable for each may be set. This improves the verification accuracy.

  In the first evaluation process and the like, the data table used for evaluating the delay of the signal path determined by the placement and routing process is not necessarily limited to the one provided as part of the component library (LDcpn). Instead, it may be a dedicated data table for storing delay data related to cell operation delay and wiring delay in the first PVT condition.

It is a flowchart of the arrangement | positioning wiring assistance process which performs a 1st evaluation process and a 2nd evaluation process. It is a flowchart of the arrangement | positioning wiring assistance process which performs an evaluation process. 3 is a flowchart schematically showing a method for developing a semiconductor integrated circuit to which the placement and routing method according to the present invention is applied. It is explanatory drawing which illustrates the outline of the timing constraint evaluated by static timing verification. It is explanatory drawing of an example of the library for evaluation used for static timing verification. It is explanatory drawing which shows the result of having verified evaluation coefficient (alpha) and (beta) with a high threshold voltage MOS transistor (HVT_MOS) in 90 nm process and 125 degreeC. It is explanatory drawing which shows the result of having verified evaluation coefficient (alpha) and (beta) with the low threshold voltage MOS transistor (LVT_MOS) in 90 nm process and 125 degreeC. It is explanatory drawing of the logic circuit used for evaluation of FIG.6 and FIG.7. It is a characteristic view which shows the change of wiring capacity with respect to progress of a process generation, and the change of wiring resistance. FIG. 6 is a characteristic diagram showing temperature characteristics of a MOS device manufactured by a process having a minimum wiring width of 0.25 micrometer · meter (μm). FIG. 11 is a characteristic diagram showing temperature characteristics of a MOS device manufactured by a process having a minimum wiring width of 90 nanometers (nm).

Explanation of symbols

LDcpn component library S1 Placement and routing support processing S3 Timing verification processing Dm Mask data LDeva evaluation library S10 Placement and routing processing S11 First evaluation processing S12 Second evaluation 2 processing S13 Correction processing S14 Evaluation processing

Claims (20)

A placement and routing method for supporting placement and routing of cells for realizing a required logical function in a semiconductor integrated circuit using a computer device,
A placement and routing process that determines the placement and routing of cells in consideration of the first PVT condition;
A first evaluation process for evaluating a delay of the signal path determined by the placement and routing process based on delay data related to a cell operation delay and a wiring delay on a data table in a first PVT condition;
A second evaluation process for evaluating a delay of the signal path in a second PVT condition based on a product of the delay of the signal path used in the first evaluation process and an evaluation coefficient;
A correction process for performing a correction necessary for the signal path determined by the placement and routing process according to the first evaluation process result and the second evaluation process result,
The evaluation coefficient is for an arbitrary combination of the cell operation delay and the wiring delay of the second PVT condition with respect to a plurality of delay times calculated for the arbitrary combination of the cell operation delay and the wiring delay of the first PVT condition. A placement and routing method, which is a coefficient for defining a plurality of calculated delay times as a linear function.   The evaluation by the first evaluation process and the second evaluation process is confirmation whether there is a predetermined margin with respect to the setup time and the hold time between the cells on the signal path constituting the latch. Is the signal propagation delay obtained by subtracting the data path delay from the sum of the clock period and the clock path delay, and the hold time is evaluated by subtracting the signal path delay from the data path delay to the clock path delay. The placement and routing method according to claim 1, which is used.   When it is evaluated in the first evaluation process that there is no more than a predetermined margin, the second evaluation process evaluates whether there is a predetermined margin or more with respect to the setup time and hold time between the cells constituting the latch. The placement and routing method according to claim 2. A placement and routing method for supporting placement and routing of cells for realizing a required logical function in a semiconductor integrated circuit using a computer device,
A placement and routing process that determines the placement and routing of cells in consideration of the first PVT condition;
Obtained as the product of the first delay of the signal path determined by the placement and routing processing obtained based on the delay data relating to the cell operation delay and the wiring delay on the data table in the first PVT condition, and the first delay and the evaluation coefficient An evaluation process for evaluating a first delay of the signal path in the previous first PVT condition and a second delay of the signal path in the second PVT condition based on the second delay
Correction processing for performing correction necessary for the signal path determined by the placement and routing processing according to the result of the evaluation processing,
The evaluation coefficient is for an arbitrary combination of the cell operation delay and the wiring delay of the second PVT condition with respect to a plurality of delay times calculated for the arbitrary combination of the cell operation delay and the wiring delay of the first PVT condition. A placement and routing method, which is a coefficient for defining a plurality of calculated delay times as a linear function.   In the evaluation by the evaluation process, the ratio between the data delay under the first PVT condition and the data delay under the second PVT condition acquired using the evaluation coefficient between cells on the signal path constituting the latch is predetermined. 5. The place-and-route method according to claim 4, wherein the place-and-route method is an evaluation of whether or not the value is smaller than the value.   In the evaluation by the evaluation process, the difference between the data delay under the first PVT condition and the data delay under the second PVT condition obtained using the evaluation coefficient between cells on the signal path constituting the latch is predetermined. 5. The place-and-route method according to claim 4, wherein the place-and-route method is an evaluation of whether or not the value is smaller than the value.   In the evaluation by the evaluation process, the ratio between the clock delay under the first PVT condition and the clock delay under the second PVT condition acquired using the evaluation coefficient between cells on the signal path constituting the latch is predetermined. 5. The place-and-route method according to claim 4, wherein the place-and-route method is an evaluation of whether or not the value is smaller than the value.   In the evaluation by the evaluation process, the difference between the clock delay under the first PVT condition and the clock delay under the second PVT condition acquired using the evaluation coefficient between cells on the signal path constituting the latch is predetermined. 5. The place-and-route method according to claim 4, wherein the place-and-route method is an evaluation of whether or not the value is smaller than the value.   The placement and routing method according to claim 5, wherein the correction process is performed when an evaluation that the value is larger than the predetermined value is performed.   10. The placement and routing method according to claim 1, wherein the evaluation coefficient has an operation delay coefficient related to the cell operation delay and a wiring delay coefficient related to the wiring delay separately. A data processing system for supporting cell placement and routing for realizing a required logic function in a semiconductor integrated circuit, comprising a computer device and a storage device,
The storage device has an evaluation coefficient and a data table,
The computer apparatus includes a placement and routing processing unit that determines the placement and routing of cells in consideration of the first PVT condition;
A first evaluation processing unit that evaluates the delay of the signal path determined by the processing of the placement and routing processing unit based on the cell operation delay and the delay data related to the wiring delay on the data table in the first PVT condition read from the storage device; ,
A second evaluation processing unit that evaluates a delay of the signal path in a second PVT condition based on a product of the evaluation coefficient read from the storage device and the delay of the signal path used in the first evaluation process;
A correction processing unit that performs correction necessary for the signal path determined by the placement and routing processing unit according to the processing result of the first evaluation processing unit and the processing result of the second evaluation processing unit,
The evaluation coefficient is for an arbitrary combination of the cell operation delay and the wiring delay of the second PVT condition with respect to a plurality of delay times calculated for the arbitrary combination of the cell operation delay and the wiring delay of the first PVT condition. A data processing system that is a coefficient for defining a plurality of calculated delay times as a linear function.   The first evaluation processing unit and the second evaluation processing unit evaluate whether or not there is a predetermined margin with respect to a setup time and a hold time between cells on the signal path constituting the latch, The signal propagation delay time obtained by subtracting the data path delay from the sum of the clock period and the clock path delay is used, and the signal propagation delay time obtained by subtracting the clock path delay from the data path delay is used as the hold time. The data processing system according to claim 11.   When the second evaluation processing unit evaluates that the first evaluation processing unit does not have a predetermined margin or more, whether there is a predetermined margin or more with respect to a setup time and a hold time between cells constituting the latch. The data processing system according to claim 12, wherein whether or not is evaluated. A data processing system for supporting cell placement and routing for realizing a required logic function in a semiconductor integrated circuit, comprising a computer device and a storage device,
The storage device has an evaluation coefficient and a data table,
The computer apparatus includes a placement and routing processing unit that determines the placement and routing of cells in consideration of the first PVT condition;
The first delay of the signal path determined by the placement and routing processing unit acquired based on the delay data related to the cell operation delay and the wiring delay on the data table in the first PVT condition read from the storage device, and the storage device Evaluation of the first delay of the signal path in the previous first PVT condition and the second delay of the signal path in the second PVT condition based on the evaluation delay and the second delay acquired as the product of the first delay An evaluation processing unit for performing
A correction processing unit that performs correction necessary for the signal path determined by the processing of the placement and routing processing unit according to the result of the processing of the evaluation processing unit,
The evaluation coefficient is for an arbitrary combination of the cell operation delay and the wiring delay of the second PVT condition with respect to a plurality of delay times calculated for the arbitrary combination of the cell operation delay and the wiring delay of the first PVT condition. A data processing system that is a coefficient for defining a plurality of calculated delay times as a linear function.   In the evaluation processing unit, a ratio between a data delay in the first PVT condition and a data delay in the second PVT condition acquired using the evaluation coefficient between cells on the signal path constituting the latch is a predetermined value. 15. The data processing system according to claim 14, wherein the evaluation is made to determine whether or not the value is smaller than the value.   The evaluation processing unit is configured such that a difference between a data delay under the first PVT condition and a data delay under the second PVT condition acquired using the evaluation coefficient between cells on the signal path constituting the latch is a predetermined value. 15. The data processing system according to claim 14, wherein the evaluation is performed to determine whether or not the value is smaller.   In the evaluation processing unit, a ratio between the clock delay under the first PVT condition and the clock delay under the second PVT condition acquired using the evaluation coefficient between cells on the signal path constituting the latch is a predetermined value. 15. The data processing system according to claim 14, wherein the evaluation is made to determine whether or not the value is smaller than the value.   In the evaluation processing unit, a difference between the clock delay under the first PVT condition and the clock delay under the second PVT condition acquired using the evaluation coefficient between the cells on the signal path constituting the latch is a predetermined value. 15. The data processing system according to claim 14, wherein the evaluation is made to determine whether or not the value is smaller than the value.   The data processing system according to any one of claims 15 to 18, wherein the correction processing unit performs the correction processing when an evaluation that the correction processing unit is larger than the predetermined value is performed.   20. The data processing system according to claim 11, wherein the evaluation coefficient separately includes an operation delay coefficient related to the cell operation delay and a wiring delay coefficient related to the wiring delay.

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