JP2008016927A - Amplifier circuit - Google Patents

Abstract

An amplifier circuit capable of reducing the size (number) of transistors required to obtain a desired gain difference while suppressing fluctuation due to gain of output impedance is provided.
An amplifier circuit according to the present invention includes first and second main transistors, which have a desired voltage applied to a signal input terminal so that first and second main currents flow, The first and second signal input transistors 5 and 6 to which the second input signal is input, the first and second high gain auxiliary transistors 7 and 8 to which the first control signal S1 is input, and the second control signal And first and second low gain auxiliary transistors 9 and 10 to which S2 is input. The signal current converted from the first and second input signals Vinp and Vinn at the time of low gain is added in the opposite phase to the opposite side of the differential at the first and second output terminals 11 and 12, and only the signal current difference is obtained. The gain is reduced without being taken out from the first and second output terminals 11 and 12.
[Selection] Figure 1

Description

  The present invention relates to an amplifier circuit capable of amplifying a signal input to an input terminal, outputting a signal from an output terminal, and adjusting a gain.

  Conventionally, an amplifier circuit is required to have a function of amplifying a plurality of gain values and to switch between them.

  Some conventional amplification circuits with a gain switching function use a plurality of cascode-connected transistors to create a gain difference based on the current ratio of the base-grounded (or gate-grounded) transistor (= area ratio) ( For example, see Patent Document 1.)

  The conventional amplifier circuit takes out the entire current signal from the output terminal when the gain is high. On the other hand, at the time of low gain, the amplifier circuit takes out only necessary current signals out of all current signals to the output terminal. Then, the remaining current signal flows to the other terminals.

In the conventional amplifier circuit, assuming that the current signal flowing through the output terminal at the time of high gain is Iout1, and the current signal flowing through the output terminal at the time of low gain is Iout2, the current ratio of N: 1 is as shown in Equation 1.

Here, the number of transistors N1total required to obtain a desired current ratio (= transistor area ratio = gain difference) is expressed by Equation 2.

  As shown in Equation 2, 2N-1 transistors are required to obtain the desired gain difference. Therefore, in order to obtain a large gain difference, there is a problem that the size of the grounded base (or grounded gate) transistor has to be increased.

In addition, N transistors are operating at high gain when viewed from the output terminal, but only 1 transistor is operating at low gain, and N−1 transistors are not operating. In this way, the state seen from the output differs depending on the gain setting, and there is a problem that the state of the parasitic element of the transistor itself is changed and the impedance of the output varies depending on the gain.
JP 2001-168660 A

  An object of the present invention is to provide an amplifier circuit capable of reducing the size (number) of transistors necessary for obtaining a desired gain difference while suppressing fluctuation due to gain of output impedance.

  An amplifier circuit according to the present invention is an amplifier circuit that can amplify a signal input to an input terminal and output a signal from an output terminal and adjust a gain, and has one end connected to a power supply potential and a first main current. The first main transistor, in which a desired voltage is applied to the signal input terminal so that the current flows, and one end is connected to the power supply potential, and the desired voltage is applied to the signal input terminal so that the second main current flows. A second main transistor having the same conductivity type as the first main transistor, a first input terminal to which the first input signal is input, and a second input signal obtained by inverting the first input signal. A second input terminal to which an input signal is input, one end is connected to the other end of the first main transistor, the other end is connected to the ground potential, and is connected to the signal input terminal via the first input terminal. The first input signal is input, and the first main transistor is input. A first signal input transistor having the same conductivity type as that of the star, one end connected to the other end of the second main transistor, the other end connected to the ground potential, and a signal input via the second input terminal The second input signal is input to the terminal, the second signal input transistor having the same conductivity type as the first main transistor, one end connected to one end of the first main transistor, and the other end connected to the first main transistor. A first control signal is input to a signal input terminal, the first high gain auxiliary transistor of the same conductivity type as the first main transistor, and one end of the second main transistor is connected to the second main transistor. Connected to one end of the main transistor, the other end is connected to the other end of the second main transistor, a first control signal is input to the signal input terminal, and a second of the same conductivity type as the first main transistor. High gain auxiliary tiger A second register having one end connected to one end of the second main transistor, the other end connected to the other end of the first main transistor, and an inverted signal of the first control signal at a signal input terminal; A control signal is input, the first low-gain auxiliary transistor having the same conductivity type as the first main transistor, one end connected to one end of the first main transistor, and the other end of the second main transistor. Connected to the other end, the second control signal is input to the signal input terminal, and connected to a second low gain auxiliary transistor of the same conductivity type as the first main transistor and one end of the first main transistor And a second output terminal connected to one end of the second main transistor.

  According to the amplifier circuit of one embodiment of the present invention, the size (number) of transistors necessary for obtaining a desired gain difference can be reduced while suppressing fluctuation due to the gain of the output impedance.

  Embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating a circuit configuration of an amplifier circuit during high gain operation according to a first embodiment which is an aspect of the present invention. FIG. 2 is a diagram illustrating a circuit configuration of the amplifier circuit during the low gain operation according to the first embodiment which is an aspect of the present invention.

  As shown in FIG. 1 and FIG. 2, the amplifier circuit 100 has a signal input terminal (base) desired at one end (collector) connected to the power supply potential VCC via the load 1 so that the first main current ia1 flows. Is applied to the first main transistor 2 which is an NPN bipolar transistor, and one end (collector) is connected to the power supply potential VCC via the load 3 so that the second main current ia2 flows. And a second main transistor 4 which is an NPN bipolar transistor having a desired voltage applied to a terminal (base).

  Here, the values of the first main current ia1 and the second main current 1a2 are equal. The first main transistor 2 and the second main transistor 4 have the same area.

  The first main transistor 2 and the second main transistor 4 may be configured by connecting a plurality of transistors as long as they are equivalent in circuit.

  The amplifier circuit 100 also includes a first input terminal 15 to which the first input signal Vinp is input, and a second input terminal 16 to which a second input signal obtained by inverting the first input signal Vinp is input. With.

  The amplifier circuit 100 has one end (collector) connected to the other end (emitter) of the first main transistor 2 and the other end (emitter) connected to the ground potential VEE via the first input terminal 15. The first input signal Vinp is inputted to the signal input terminal (base), the first signal input transistor 5 which is the same NPN type bipolar transistor as the first main transistor 2, and one end (collector) is the second main transistor. 4 is connected to the other end (emitter), the other end (emitter) is connected to the ground potential VEE, and the second input signal Vinn is input to the signal input terminal (base) via the second input terminal 16; And a second signal input transistor 6 that is the same NPN bipolar transistor as the first main transistor 2.

  The amplifier circuit 100 has one end (collector) connected to one end (collector) of the first main transistor 2 and the other end (emitter) connected to the other end (emitter) of the first main transistor 2. The first control signal S1 is inputted to the input terminal (base), the first high gain auxiliary transistor 7 which is the same NPN type bipolar transistor as the first main transistor 2, and one end (collector) is the second main transistor. 4 is connected to one end (collector), the other end (emitter) is connected to the other end (emitter) of the second main transistor 4, and the first control signal S1 is input to the signal input terminal (base). And a second high gain auxiliary transistor 8 which is the same NPN type bipolar transistor as one main transistor.

  The amplifier circuit 100 has one end (collector) connected to one end (collector) of the second main transistor 4 and the other end (emitter) connected to the other end (emitter) of the first main transistor 2. A second control signal S2 obtained by inverting the first control signal S1 is input to an input terminal (base), and a first low gain auxiliary transistor 9 which is the same NPN bipolar transistor as the first main transistor 2; One end (collector) is connected to one end (collector) of the first main transistor 2, the other end (emitter) is connected to the other end (emitter) of the second main transistor 4, and the signal input terminal (base) 2, and a second low gain auxiliary transistor 10 that is the same NPN bipolar transistor as the first main transistor 2.

  The first high gain auxiliary transistor 7, the first low gain auxiliary transistor 9, the second high gain auxiliary transistor 8, and the second low gain auxiliary transistor 10 have the same area.

  Further, here, the value of the first auxiliary current ib1 flowing through the first high gain auxiliary transistor 7 and the first low gain auxiliary transistor 9, the second high gain auxiliary transistor 8, and the second low gain auxiliary transistor. 10 is set to be equal to the value of the second auxiliary current ib <b> 2 flowing to 10.

  If the first high gain auxiliary transistor 7, the first low gain auxiliary transistor 9, the second high gain auxiliary transistor 8, and the second low gain auxiliary transistor 10 are equivalent to each other in circuit, You may make it comprise and connect a transistor.

  The amplifier circuit 100 is connected to one end (collector) of the first main transistor 2, connected to the first output terminal 11 that outputs a voltage signal, and one end (collector) of the second main transistor 4. A second output terminal 12 for outputting a voltage signal is provided.

  The amplifier circuit 100 receives the input of the first control signal S1, outputs an inverted second control signal S2, and has the same time constant as the time constant of the inverter 13, And a delay circuit 14 that receives the control signal S1 and outputs a delayed first control signal S1.

  Here, when the first control signal S1 is inverted by the inverter 13 to generate the second control signal S2, the first control signal S1 is switched by the delay circuit 14 (for example, “High” and “Low” are switched). The timing at which the second control signal S2 is switched (for example, “High” and “Low” are switched) is the same.

  That is, for example, the operation of switching on / off of the first high gain auxiliary transistor 7 and the operation of switching on / off of the first low gain auxiliary transistor 9 are performed simultaneously.

  Therefore, it is possible to suppress a change in the first main current ia1 in the first main transistor 2 when the first and second control signals S1 and S2 are switched.

  The same applies to the operations of the second main transistor 2, the second high gain auxiliary transistor 8, and the second low gain auxiliary transistor 10.

  In this embodiment, the case where a bipolar transistor is used has been described. However, the present invention can be similarly applied to a MOS transistor. In this case, the signal input terminal corresponds to a gate.

  When each of the transistors 2, 4 to 10 is a MOS transistor, the first main transistor 2 and the second main transistor 4 have the same channel length / channel width ratio.

  Further, the first high gain auxiliary transistor 7, the first low gain auxiliary transistor 9, the second high gain auxiliary transistor 8, and the second low gain auxiliary transistor 10 have the same ratio of channel length to channel width. is there.

  In this embodiment, the bipolar transistor is described using an NPN type bipolar transistor. However, the PNP type bipolar transistor can be similarly applied by reversing the polarity.

  FIG. 3 is a diagram illustrating another circuit configuration of the amplifier circuit during the high gain operation according to the first embodiment which is an aspect of the present invention. FIG. 4 is a diagram illustrating another circuit configuration of the amplifier circuit during the low gain operation according to the first embodiment which is an aspect of the present invention.

  As shown in FIGS. 3 and 4, the inverter and the delay circuit are switched, and the amplifier circuit 100 receives the input of the second control signal S2 and outputs the inverted first control signal S1. And a delay circuit 17 having the same time constant as the time constant of the inverter 18 and receiving the second control signal S2 and outputting the delayed second control signal S2. Good.

  Next, the gain and the transistor size (number) N of the amplifier circuit 100 having the above configuration will be described.

  At the time of high gain, as shown in FIG. 1, in the amplifier circuit 100, the first and second high gain auxiliary transistors 7 and 8 are turned on in response to the input of the first and second control signals S1 and S2. The first and second low gain auxiliary transistors 9 and 10 are turned off. As a result, the output current iout1n (first main current ia1 + first auxiliary current ib1) flows to the load 1, and the output current iout1p (second main current ia2 + second auxiliary current ib2) flows to the load 2.

  On the other hand, at the time of low gain, as shown in FIG. 2, in the amplifier circuit 100, the first and second high gain auxiliary transistors 7 and 8 are turned on in response to the input of the first and second control signals S1 and S2. While turning off, the first and second low gain auxiliary transistors 9 and 10 are turned on. As a result, the output current iout2n (first main current ia1-second auxiliary current ib2) flows to the load 1, and the output current iout2p (second main current ia2-first auxiliary current ib1) flows to the load 2. .

  That is, the signal current converted from the first and second input signals Vinp and Vinn at the time of low gain is added in the opposite phase to the opposite side of the differential at the first and second output terminals 11 and 12, and the signal current Only the difference is taken out from the first and second output terminals 11 and 12, and the gain becomes small.

Here, the current signal that flows through the first and second output terminals 11 and 12 when the gain is high is Iout1, and the current signal that flows through the output terminal when the gain is low is Iout2. The size of the first and second main transistors 2 and 4 is 0.5 * (N + 1). The sizes of the first and second high gain auxiliary transistors and the first and second low gain auxiliary transistors are 0.5 * (N−1). In this case, the following Expression 3 is established with respect to the gain of the amplifier circuit 100.

In this case, the _total transistor size N2 _total required to obtain the N: 1 ratio is shown in Equation 4.

  As shown in Equation 4, by increasing N (increasing the current ratio), the transistor size required to obtain the desired current gain can be reduced by about 1/4 compared to the conventional case. .

  Further, when the amplifier circuit 100 is configured as described above, N transistors operate at both high gain and low gain when viewed from the output terminal side, and 0.5 * (N−1) transistors. The transistor of this will not operate. In this way, even when the gain setting is switched, the size (number) of the transistors that operate and the transistors that do not operate are the same as viewed from the output. That is, fluctuations in output impedance are suppressed by the gain setting.

  As described above, according to the amplifier circuit according to the present embodiment, the size (number) of transistors necessary for obtaining a desired gain difference can be reduced while suppressing fluctuation due to the gain of the output impedance.

It is a figure which shows the circuit structure of the amplifier circuit at the time of the high gain operation | movement which concerns on Example 1 which is 1 aspect of this invention. It is a figure which shows the circuit structure of the amplifier circuit at the time of the low gain operation | movement which concerns on Example 1 which is 1 aspect of this invention. It is a figure which shows the other circuit structure of the amplifier circuit at the time of the high gain operation | movement which concerns on Example 1 which is 1 aspect of this invention. It is a figure which shows the other circuit structure of the amplifier circuit at the time of the low gain operation | movement which concerns on Example 1 which is 1 aspect of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Load 2 1st main transistor 3 Load 4 2nd main transistor 5 1st signal input transistor 6 2nd signal input transistor 7 1st high gain auxiliary transistor 8 2nd high gain auxiliary transistor 9 1st Low gain auxiliary transistor 10 Second low gain auxiliary transistor 11 First output terminal 12 Second output terminal 13 Inverter 14 Delay circuit 15 First input terminal 16 Second input terminal 17 Delay circuit 18 Inverter 100 Amplifier circuit

Claims (5)

An amplifier circuit that amplifies the signal input to the input terminal, outputs the signal from the output terminal, and can adjust the gain,
A first main transistor having one end connected to a power supply potential and a desired voltage applied to the signal input terminal so that the first main current flows;
A second main transistor having the same conductivity type as the first main transistor, one end of which is connected to the power supply potential and a desired voltage is applied to a signal input terminal so that a second main current flows;
A first input terminal to which a first input signal is input;
A second input terminal to which a second input signal obtained by inverting the first input signal is input;
One end is connected to the other end of the first main transistor, the other end is connected to the ground potential, the first input signal is input to the signal input terminal via the first input terminal, and the first A first signal input transistor of the same conductivity type as the main transistor of
One end is connected to the other end of the second main transistor, the other end is connected to the ground potential, the second input signal is input to the signal input terminal through the second input terminal, and the second A second signal input transistor of the same conductivity type as the first main transistor;
One end is connected to one end of the first main transistor, the other end is connected to the other end of the first main transistor, a first control signal is input to a signal input terminal, and the first main transistor A first high gain auxiliary transistor of the same conductivity type;
One end is connected to one end of the second main transistor, the other end is connected to the other end of the second main transistor, a first control signal is input to a signal input terminal, and the first main transistor A second high gain auxiliary transistor of the same conductivity type;
One end is connected to one end of the second main transistor, the other end is connected to the other end of the first main transistor, and a second control signal obtained by inverting the first control signal is input to a signal input terminal. A first low gain auxiliary transistor that is input and has the same conductivity type as the first main transistor;
One end is connected to one end of the first main transistor, the other end is connected to the other end of the second main transistor, the second control signal is input to a signal input terminal, and the first main transistor A second low gain auxiliary transistor of the same conductivity type as
A first output terminal connected to one end of the first main transistor;
An amplifier circuit comprising: a second output terminal connected to one end of the second main transistor. Each of the transistors is a bipolar transistor;
The first main transistor and the second main transistor have the same area;
The first high gain auxiliary transistor, the first low gain auxiliary transistor, the second high gain auxiliary transistor, and the second low gain auxiliary transistor have the same area. . Each of the transistors is a MOS transistor,
The first main transistor and the second main transistor have the same ratio of channel length to channel width,
The first high gain auxiliary transistor, the first low gain auxiliary transistor, the second high gain auxiliary transistor, and the second low gain auxiliary transistor have the same ratio of channel length to channel width. The amplifier circuit according to claim 1. An inverter that receives the input of the first control signal and outputs the inverted second control signal;
And a delay circuit having the same time constant as the time constant of the inverter and receiving the input of the first control signal and outputting the delayed first control signal. Item 4. The amplifier circuit according to any one of Items 1 to 3. An inverter that receives the input of the second control signal and outputs the inverted first control signal;
And a delay circuit having the same time constant as the time constant of the inverter and receiving the input of the second control signal and outputting the delayed second control signal. Item 4. The amplifier circuit according to any one of Items 1 to 3.

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