JP2008016638A - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device capable of improving the reliability of a wiring by suppressing the oxidation and corrosion of the wiring even in a region where an actual pattern is formed.
A first wiring is formed on a substrate, a first contact layer is formed on an upper layer of the first wiring and connected to the first wiring, and a first contact layer is formed on an outer periphery of the first contact layer. A second contact layer 32 is formed in a ring shape apart from the first contact layer 31, and a second wiring 33 is formed on the first contact layer 31 and the second contact layer 32 in connection with the first contact layer 31. An insulating layer containing an insulating material having a dielectric constant lower than that of silicon oxide is formed in the gap between the wiring 30, the first contact layer 31, the second contact layer 32, and the second wiring 33.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which contacts are formed between wirings.

In semiconductor devices, miniaturization of semiconductor elements and the like is progressing for higher speed and higher integration, and accordingly, higher integration is also progressed by miniaturization of wirings connecting between semiconductor elements and multilayers.
With the progress of miniaturization and high integration of wiring, the problems of voltage drop and RC delay in wiring have become non-negligible. As countermeasures, the resistance of wiring materials and the capacity of wiring are reduced. Reduction is desired.

Conventionally, aluminum has been mainly used as a wiring material, and silicon oxide has been mainly used as an insulating film between wirings. A combination of low dielectric constant films (so-called low-k films), which is lower than silicon oxide, has come to be used.
For example, a multilayer wiring using copper and a low-k film is formed by forming a wiring groove in the low-k film, forming a copper diffusion prevention layer on the inner wall of the groove, and embedding the groove on the copper diffusion prevention layer. The excess copper deposited outside the groove is removed by chemical mechanical polishing (CMP), so-called damascene method.
Furthermore, a contact hole can be formed on the bottom surface of the groove, and the wiring can be formed by a dual damascene method in which the contact is formed integrally.
A multilayer wiring can be formed by repeating the above steps as appropriate.

  Here, the low-k film has increased moisture permeability and hygroscopicity as the dielectric constant is lowered, so that moisture reaches the wiring part in the subsequent heating process and the like, and the wiring is oxidized and corroded. There has been a problem of reducing the reliability of wiring.

  In Non-Patent Document 1, a dummy wiring that is not actually used is actually used in order to sufficiently degas the Low-k film as a countermeasure against the problems of the oxidation and corrosion of the wiring in the Low-k film. A method of disposing the wiring around the wiring to be used (actual wiring) is disclosed, and Patent Document 1 discloses a method of forming a dummy wiring or a dummy contact.

Since the contact is greatly affected by the oxidation and corrosion described above, it has been studied to form more dummy contacts, but it is practically difficult to place dummy contacts in the area where the actual pattern is formed. A new problem has been caused.
JP 2005-167120 A International Interconnect Technology Conference (IITC) 2005, P.6-8

  An object of the present invention is to provide a semiconductor device capable of improving the reliability of wiring by suppressing the oxidation and corrosion of the wiring even in the region where the actual pattern is formed.

  In order to solve the above problems, a semiconductor device of the present invention includes a first wiring formed on a substrate, a first contact layer connected to the first wiring and formed on an upper layer of the first wiring, A second contact layer formed in a ring shape at a periphery of the first contact layer and spaced from the first contact layer, and connected to the first contact layer and above the first contact layer and the second contact layer An insulating layer including an insulating material having a dielectric constant lower than that of silicon oxide formed in a gap between the formed second wiring and the first wiring, the first contact layer, the second contact layer, and the second wiring. And have.

  In the semiconductor device of the present invention, the first wiring is formed on the substrate, the first contact layer is formed on the first wiring and connected to the first wiring, and the first contact layer is formed on the outer periphery of the first contact layer. A second contact layer is formed in a ring shape apart from the first contact layer, and a second wiring is formed on the first contact layer and the second contact layer in connection with the first contact layer. The first wiring and the first contact layer An insulating layer containing an insulating material having a dielectric constant lower than that of silicon oxide is formed in the gap between the second contact layer and the second wiring.

  In the semiconductor device of the present invention, the ring-shaped second contact layer is formed on the outer periphery of the first contact layer, whereby the amount of moisture reaching the first contact layer from the insulating film is reduced, and the actual pattern becomes Even in the formed region, the wiring reliability can be improved by suppressing the oxidation and corrosion of the wiring.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

First Embodiment FIG. 1 is a plan view of a semiconductor device according to the present embodiment.
For example, the first wiring 30 is formed on the substrate, and the second wiring 33 is formed above the first wiring 30.
The first wiring 30 and the second wiring 33 have an overlapping region, and a first contact layer 31 that connects the first wiring 30 and the second wiring 33 is formed in the overlapping region. The second contact layer 32 is formed in a ring shape at a distance from the first contact layer 31 on the outer periphery of the first contact layer 31.
For example, the first contact layer 31 has a size of about 100 nm × 100 nm, and the second contact layer 32 has a ring shape with a width of 100 nm spaced from the first contact layer 31 by 100 nm.

  For example, the first wiring 30 and the second wiring 33 are wirings formed in the wiring trenches T1 and T2 formed in the insulating film, respectively, and the first contact layer 31 and the second wiring 33 are formed. The two contact layer 32 is a plug-shaped contact layer formed by being buried in the contact holes C1 and C2 formed in the insulating film, respectively.

2A is a cross-sectional view taken along the line AA ′ in FIG. 1, and FIG. 2B is a cross-sectional view taken along the line BB ′ in FIG.
For example, a first insulating film 20 such as silicon oxide is formed on a silicon substrate 10, and a second insulating film 21 made of silicon nitride is formed on the first insulating film 20, and an SiOC film, MSQ (for example) is formed on the upper layer. A third insulating film 22 made of a laminated body of a low dielectric constant insulating film 22a made of a Methyl Silses Quioxane) film, an HSQ (Hydrogen Silses Quioxane) film, an MSQ or HSQ porous film, or a porous silica film, and a silicon oxide film 22b. The first wiring trench T1 reaching the upper surface of the second insulating film 21 along the pattern of the first wiring is formed.

  For example, a barrier metal layer 30a made of tantalum or the like is formed on the inner wall of the first wiring trench T1, and a copper seed layer 30b is formed so as to cover the upper layer, and the first wiring trench T1 is embedded in the upper layer. Thus, the copper layer 30c is formed, and the first wiring 30 is formed.

Further, a fourth insulating film 23 made of silicon nitride is formed on the first wiring 30 and the third insulating film 22, and a low dielectric constant insulating film 24a similar to the above and a silicon oxide are formed on the fourth insulating film 23, for example. A fifth insulating film 24 made of a laminate of the film 24b is formed, and a first contact hole reaching the upper surfaces of the first wiring 30 and the third insulating film 22 along the pattern of the first contact layer and the second contact layer. C1 and a second contact hole C2 are formed.
Here, as shown in FIG. 1, the second contact hole C <b> 2 is formed on the outer periphery of the first contact hole C <b> 1 so as to be spaced apart from the first contact hole C <b> 1 and open in a ring shape.

  Further, for example, the first contact hole C1 is filled with a barrier metal layer 31a made of tantalum or the like, a copper seed layer 31b, and a copper layer 31c to form the first contact layer 31.

  Similarly, in the second contact hole C2, the second contact layer 32 is formed by being buried with the barrier metal layer 32a, the copper seed layer 32b, and the copper layer 32c.

  Further, a sixth insulating film 25 made of silicon nitride is formed on the first contact layer 31, the second contact layer 32, and the fifth insulating film 24, and a low dielectric constant similar to the above is formed on the upper layer, for example. A seventh insulating film 26 composed of a laminate of the insulating film 26a and the silicon oxide film 26b is formed, and the first contact layer 31, the second contact layer 32, and the fifth insulating film 24 are formed along the pattern of the second wiring. A second wiring trench T2 reaching the upper surface of the second wiring is formed.

For example, the second wiring 33 is formed by filling the second wiring trench T2 with a barrier metal layer 33a made of tantalum or the like, a copper seed layer 33b, and a copper layer 33c.
Further, for example, an eighth insulating film 27 made of silicon nitride is formed on the second wiring 33 and the seventh insulating film 26.

  In the semiconductor device of the present embodiment, the first wiring is formed on the substrate, the first contact layer is formed on the first wiring and connected to the first wiring, and the first contact is formed on the outer periphery of the first contact layer. A second contact layer is formed in a ring shape apart from the layer, and a second wiring is formed on the first contact layer and the second contact layer in connection with the first contact layer. The first wiring and the first contact An insulating layer containing an insulating material having a dielectric constant lower than that of silicon oxide is formed in the gap between the layer, the second contact layer, and the second wiring.

In the semiconductor device of this embodiment, the ring-shaped second contact layer is formed on the outer periphery of the first contact layer, whereby the amount of moisture reaching the first contact layer from the insulating film is reduced, and the actual pattern Even in the region where is formed, the wiring reliability can be improved by suppressing the oxidation and corrosion of the wiring.
Moreover, stress migration resistance is also improved. As a result, it is possible to prevent an increase in the inter-wiring capacitance and the inter-wiring leakage current amount of the circuit portion or the like due to the arrangement of the second contact layer.

In the semiconductor device of this embodiment, the second contact layer 32 is formed in connection with the first wiring 30 and / or the second wiring 33. The second contact layer 32 can function as an actual contact that connects the first wiring 30 and the second wiring 33.
Further, the second contact layer 32 is not necessarily connected to the first wiring 30 and / or the second wiring 33, and may be a complete dummy contact.

In the semiconductor device of the present embodiment, as shown in FIGS. 1, 2A and 2B, the second contact layer 32 is sealed so that the inner region of the ring shape is sealed. It is preferable that the first wiring 30 and the second wiring 33 are connected to the contact layer 32.
This prevents moisture from entering from the outside of the second contact layer 32 to the inside of the second contact layer 32 where the first contact layer 31 is formed, and effectively oxidizes and corrodes the first contact layer 31. Can be suppressed.

Alternatively, in the semiconductor device of the present embodiment, it is preferable that a moisture shielding insulating layer is formed on the second contact layer 32.
In the present embodiment, it is possible to prevent moisture from entering from the upper insulating film of the second contact layer 32 and to effectively suppress oxidation and corrosion of the first contact layer 31. Even in a configuration in which the region inside the ring shape of the second contact layer 32 is not sealed by the first wiring 30 and the second wiring 33, the intrusion of moisture from the outside of the second contact layer 32 can be suppressed.

Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. Here, reference is made to FIG. 3A to FIG. 6B which are cross-sectional views showing respective steps in a cross section corresponding to FIG.
First, as shown in FIG. 3A, for example, a first insulating film 20 made of silicon oxide or the like is formed on a silicon substrate 10 by a CVD (Chemical Vapor Deposition) method or the like with a film thickness of 500 nm.
Next, for example, a second insulating film 21 made of silicon nitride or the like with a thickness of 50 nm is formed on the upper layer of the first insulating film 20 by a CVD method or the like, and further, for example, an SiOC film, MSQ (Methyl) A low dielectric constant insulating film 22a made of a Silses Quioxane) film, an HSQ (Hydrogen Silses Quioxane) film, an MSQ or HSQ porous film, or a porous silica film is formed to a thickness of 150 nm, and a silicon oxide film 22b is formed thereon. The third insulating film 22 is formed to have a thickness of 150 nm and is formed of these stacked bodies.
Next, a resist film 40 having an opening in the pattern of the first wiring is formed by a photolithography process.

  Next, as shown in FIG. 3B, for example, an etching process such as plasma etching is performed on the third insulating film 22 formed of a laminate of the low dielectric constant insulating film 22a and the silicon oxide film 22b using the resist film 40 as a mask. Then, a first wiring trench T1 reaching the upper surface of the second insulating film 21 along the pattern of the first wiring is formed. Thereafter, the resist film 40 is removed.

  Next, as shown in FIG. 4A, for example, tantalum or the like is deposited to a thickness of 30 nm so as to cover the inner wall surface of the first wiring trench T1 by a physical vapor deposition method such as sputtering. 30a is formed.

  Next, a copper seed layer 30b having a thickness of 50 nm is formed on the entire surface of the barrier metal layer 30a by physical vapor deposition such as sputtering using a copper target.

  Next, for example, copper is deposited with a thickness of 1 μm by electrolytic plating using the seed layer 30b as one electrode, and the first wiring trench T1 is buried in the upper layer of the seed layer 30b to form the copper layer 30c. .

Next, as shown in FIG. 4B, the copper layer 30c (including the seed layer 30b) outside the first wiring trench T1 is removed by, for example, CMP (Chemical Mechanical Polishing), and then CMP is performed. Processing is performed until the barrier metal layer 30a is removed.
As a result, the first wiring 30 made of the barrier metal layer and the copper layer and embedded in the first wiring trench T1 is formed.

Next, as shown in FIG. 5A, a fourth insulating film 23 made of silicon nitride or the like is formed on the first wiring 30 and the third insulating film 22 in the same manner as described above, and a low dielectric constant insulating film is formed. A fifth insulating film 24 composed of a stacked body of 24a and a silicon oxide film 24b is formed, and a resist film having an opening in the pattern of the first contact layer and the second contact layer is formed.
Next, etching is performed with a pattern of the first contact layer and the second contact layer to form the first contact hole C1 and the second contact hole C2 reaching the upper surfaces of the first wiring 30 and the third insulating film 22. Thereafter, the resist film is removed.
Here, as shown in FIG. 1, the second contact hole C2 is formed in the outer periphery of the first contact hole C1 so as to be spaced apart from the first contact hole C1 and opened in a ring shape.

Next, as shown in FIG. 5B, barrier metal layers 31a and 32a are formed so as to cover the inner wall surfaces of the first contact hole C1 and the second contact hole C2 in the same manner as described above. Seed layers 31b and 32b are formed, and first contact holes C1 and second contact holes C2 are buried in the upper layers of the seed layers 31b and 32b to form copper layers 31c and 32c. Further, the first contact holes are formed by CMP or the like. The copper layer (including the seed layer) and the barrier metal layer outside C1 and the second contact hole C2 are removed.
As a result, the first contact layer 31 made of the barrier metal layer and the copper layer and embedded in the first contact hole C1 is formed. Similarly, the second contact layer 32 embedded in the second contact hole C2 is formed.

Next, as shown in FIG. 6A, a sixth insulating film 25 made of silicon nitride or the like is formed on the first contact layer 31, the second contact layer 32, and the fifth insulating film 24 in the same manner as described above. Then, a seventh insulating film 26 made of a laminate of the low dielectric constant insulating film 26a and the silicon oxide film 26b is formed, and a resist film having an opening in the pattern of the second wiring is formed.
Next, etching is performed with the pattern of the second wiring, thereby forming a first wiring trench T2 that reaches the upper surfaces of the first contact layer 31, the second contact layer 32, and the fifth insulating film 24. Thereafter, the resist film is removed.

Next, as shown in FIG. 6B, in the same manner as described above, a barrier metal layer 33a is formed covering the inner wall surface of the second wiring trench T2, and a copper seed layer 33b is formed on the entire surface. Then, the second wiring trench T2 is embedded in the upper layer of the seed layer 33b to form a copper layer 33c, and a copper layer (including the seed layer) and a barrier metal layer outside the second wiring trench T2 are further formed by CMP or the like. Remove.
As a result, the second wiring 33 made of the barrier metal layer and the copper layer and embedded in the second wiring trench T2 is formed.

Further, an eighth insulating film 27 made of silicon nitride or the like is formed on the second wiring 33 and the seventh insulating film 26.
As described above, a semiconductor device having wiring having the structure shown in FIGS. 1 and 2A and 2B can be manufactured.

  In the manufacturing method of the semiconductor device according to the above-described embodiment, the amount of moisture reaching the first contact layer from the insulating film is reduced by forming the ring-shaped second contact layer on the outer periphery of the first contact layer. In addition, even in the region where the actual pattern is formed, it is possible to manufacture a semiconductor device in which the wiring reliability is improved by suppressing the oxidation and corrosion of the wiring.

Second Embodiment FIG. 7 is a plan view of a semiconductor device according to this embodiment.
For example, the first wiring 30 is formed on the substrate, and the second wiring 33 is formed above the first wiring 30.
The first wiring 30 and the second wiring 33 have an overlapping region, and a first contact layer 31 that connects the first wiring 30 and the second wiring 33 is formed in the overlapping region. The second contact layer 32 is formed in a ring shape at a distance from the first contact layer 31 on the outer periphery of the first contact layer 31. Here, in the present embodiment, the second contact layer 32 having a hexagonal shape is formed.

  For example, the first wiring 30 and the second wiring 33 are wirings formed in the wiring trenches T1 and T2 formed in the insulating film, respectively, and the first contact layer 31 and the second wiring 33 are formed. The two contact layer 32 is a plug-shaped contact layer formed by being buried in the contact holes C1 and C2 formed in the insulating film, respectively.

  The shape of the second contact layer 32 is not particularly limited, and may be various shapes such as the above-described hexagonal shape as long as the shape is a ring shape. For example, a circular shape may be used.

  In the semiconductor device of this embodiment, the ring-shaped second contact layer is formed on the outer periphery of the first contact layer, whereby the amount of moisture reaching the first contact layer from the insulating film is reduced, and the actual pattern Even in the region where is formed, the wiring reliability can be improved by suppressing the oxidation and corrosion of the wiring.

Third Embodiment FIG. 8 is a plan view of a semiconductor device according to this embodiment.
For example, lower-layer first wirings T1a, T1b, and T1c are formed, and upper-layer second wirings T2a, T2b, and T2c are formed.
Here, the first wiring T1a and the second wiring T2a have an overlapping region, and the first contact layer CL1 that connects the first wiring T1a and the second wiring T2a is formed in the overlapping region, A second contact layer CL2 is formed in a ring shape (a hexagonal shape in the drawing) apart from the first contact layer CL1 on the outer periphery of the contact layer CL1.
Further, the first wiring T1b and the second wiring T2b have an overlapping region, and a contact layer CL3 that connects both wirings is formed.

In the semiconductor device of this embodiment, the second contact layer is formed with respect to the first contact layer provided in the region where the distance between the first wiring and the wiring adjacent to the first wiring is a predetermined value or more. The configuration is as follows.
That is, when the first wiring T1a and the second wiring T2a and the first wiring T1c that is a wiring adjacent to the first wiring T1a and the second wiring T2a are separated by a predetermined distance, for example, 5 μm, preferably 10 μm or more. The layout is such that the second contact layer CL2 is provided on the outer periphery of the first contact layer CL1 connecting the first wiring T1a and the second wiring T2a.
On the other hand, since the first wiring T1b and the second wiring T2b to which the first contact layer CL3 is connected have wirings in a close region of 5 μm or less in any direction, the first wiring T1b and the second wiring T2b are connected. The second contact layer is not provided on the outer periphery of the first contact layer CL3.

As described above, when other wiring is present near the first wiring and the second wiring, moisture reaches the other wiring, so that the amount of moisture reaching the first contact layer is reduced, and Thus, it is not always necessary to protect the second contact layer.
When no other wiring exists near the first wiring and the second wiring, for example, within 5 μm, the influence of moisture increases, so that the protection effect by the second contact layer increases.

Fourth Embodiment FIG. 9 is a plan view of a semiconductor device according to this embodiment.
For example, lower-layer first wirings T1a, T1b, T1c, T1d, and T1e are formed, and upper-layer second wirings T2a and T2b are formed.
Here, the first wiring T1a and the second wiring T2a have an overlapping region, and the first contact layer CL1 that connects the first wiring T1a and the second wiring T2a is formed in the overlapping region, A second contact layer CL2 is formed in a ring shape (a hexagonal shape in the drawing) apart from the first contact layer CL1 on the outer periphery of the contact layer CL1.
Further, the first wirings T1c, T1d, T1e and the second wiring T2b have an overlapping region, and contact layers CL3, CL4, CL5 are formed to connect the two wirings.

In the semiconductor device according to the present embodiment, a plurality of first contact layers are provided, and the second contact layer is different from the first contact layer whose distance from the nearest first contact layer is a predetermined value or more. The formed structure is assumed.
That is, when the first contact layer CL1 and the closest first contact layer CL3 are separated by a predetermined distance, for example, 5 μm, preferably 10 μm or more, the second contact layer CL2 is disposed on the outer periphery of the first contact layer CL1. The layout is provided.
On the other hand, since the first contact layer CL3 has a short distance from the closest first contact layer CL4, the second contact layer is not provided on the outer periphery of the first contact layer CL3. The same applies to the other first contact layers CL4 and CL5.

As described above, when another first contact layer is present near the first contact layer, the moisture reaches each first contact layer, so that the amount of moisture reaching each first contact layer is And need not be protected by the second contact layer as described above.
When no other first contact layer exists near the first contact layer, for example, within 5 μm, the influence of moisture increases, so that the protective effect of the second contact layer increases.

FIG. 10 shows the relationship between the distance between adjacent wirings or the first contact interlayer distance S, which is a reference for providing the second contact layer in the third and fourth embodiments, and the dielectric constant k of the insulating material applied to the interlayer insulating film. It is a graph which shows.
For example, when the dielectric constant is about 2.4, the first contact layer formed on the wiring having a distance between adjacent wirings of 10 μm or more, or the first contact layer having a first contact interlayer distance of 10 μm or more It is a standard for providing two contact layers.

The present invention is not limited to the above embodiment.
For example, this embodiment is an example, and changes according to the process and the design rule.
In addition, in the embodiment, the shape of the second contact layer is a square or a hexagon, but is not limited thereto.
The present invention can also be applied to a case where there is a dummy pattern (wiring layer alone or wiring layer + contact layer) in addition to the actual circuit pattern. In that case, the dummy pattern is regarded as an actual pattern and applied to the above embodiment.
In addition, various modifications can be made without departing from the scope of the present invention.

  The semiconductor device of the present invention can be applied to a semiconductor device in which contacts are formed between wirings.

FIG. 1 is a plan view of a semiconductor device according to the first embodiment of the present invention. 2A is a cross-sectional view taken along the line A-A ′ of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line B-B ′ of FIG. 1. FIGS. 3A and 3B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 4 (a) and 4 (b) are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 5A and 5B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 6A and 6B are cross-sectional views illustrating the manufacturing process of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a plan view of a semiconductor device according to the second embodiment of the present invention. FIG. 8 is a plan view of a semiconductor device according to the third embodiment of the present invention. FIG. 9 is a plan view of a semiconductor device according to the fourth embodiment of the present invention. FIG. 10 is a graph showing the relationship between the distance between adjacent wirings or the first contact interlayer distance S and the dielectric constant k of the insulating material applied to the interlayer insulating film.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate, 20 ... 1st insulating film, 21 ... 2nd insulating film, 22 ... 3rd insulating film, 22a ... Low dielectric constant insulating film, 22b ... Silicon oxide film, 23 ... 4th insulating film, 24 ... 1st 5 insulating film, 24a ... low dielectric constant insulating film, 24b ... silicon oxide film, 25 ... sixth insulating film, 26 ... seventh insulating film, 26a ... low dielectric constant insulating film, 26b ... silicon oxide film, 27 ... eighth Insulating film, 30 ... first wiring, 30a ... barrier metal layer, 30b ... seed layer, 30c ... copper layer, 31 ... first contact layer, 31a ... barrier metal layer, 31b ... seed layer, 31c ... copper layer, 32 ... Second contact layer, 32a ... barrier metal layer, 32b ... seed layer, 32c ... copper layer, 33 ... second wiring, 33a ... barrier metal layer, 33b ... seed layer, 33c ... copper layer, 40 ... resist film, C1 ... 1st contact hole, C2 ... 1st Contact hole, T1 ... first wiring groove, T2 ... second wiring method groove, T1a, T1b, T1c, T1d, T1e ... first wiring, T2a, T2b, T2c ... second wiring, CL1, CL3, CL4, CL5 ... first contact layer, CL2 ... second contact layer

Claims (6)

A first wiring formed on the substrate;
A first contact layer connected to the first wiring and formed in an upper layer of the first wiring;
A second contact layer formed in a ring shape at a periphery of the first contact layer and spaced from the first contact layer;
A second wiring connected to the first contact layer and formed in an upper layer of the first contact layer and the second contact layer;
A semiconductor device comprising: the first wiring, the first contact layer, the second contact layer, and an insulating layer including an insulating material having a dielectric constant lower than that of silicon oxide formed in a gap between the second wiring. The semiconductor device according to claim 1, wherein the second contact layer is formed to be connected to the first wiring and / or the second wiring. The semiconductor device according to claim 1, wherein the first wiring and the second wiring are connected to the second contact layer so as to seal a ring-shaped inner region of the second contact layer. The semiconductor device according to claim 1, wherein a moisture shielding insulating layer is formed on an upper layer of the second contact layer. The second contact layer with respect to the first contact layer provided in a region where a distance between the first wiring and the second wiring and a wiring adjacent to the first wiring and the second wiring is a predetermined value or more. The semiconductor device according to claim 1. A plurality of the first contact layers are provided;
The semiconductor device according to claim 1, wherein the second contact layer is formed with respect to the first contact layer whose distance from the closest first contact layer is a predetermined value or more.

Images