JP2008016499A - Semiconductor device, and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which level difference is reduced between the regions where transistors having gate oxide films of different thicknesses are formed, and to provide its fabrication process. <P>SOLUTION: After a thermal oxidation film is formed in the peripheral circuit region RA and the memory cell region by first time thermal oxidation processing , the thermal oxidation film located in the memory cell region is removed. Nitrogen is introduced to the surface of the thermal oxidation film located in the peripheral circuit region, and the region of a semiconductor substrate 1 exposed to the memory cell region by performing plasma nitriding treatment. Subsequently, the thermal oxidation film located in the peripheral circuit region is removed, and second time thermal oxidation processing is performed thus forming an oxide film 9a becoming a thicker gate oxide film in the peripheral circuit region and an oxide film 9b becoming a thinner gate oxide film in the memory cell region. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a trench isolation region and a manufacturing method thereof.

  In a semiconductor device, a plurality of elements having a predetermined function are formed on the surface of a semiconductor substrate (silicon substrate). The plurality of elements are each formed in a predetermined element formation region. In order to electrically isolate the plurality of elements from each other, an element isolation region is formed between the element formation region and another element formation region adjacent thereto.

  One of such element isolation regions is an isolation structure called STI (Shallow Trench Isolation). STI is an isolation structure formed by embedding an insulating film such as a silicon oxide film in a trench formed on the surface of a silicon substrate. There are various methods for forming the STI. For example, in an isolation structure called self-aligned STI (Self Aligned STI), a trench is formed after a gate oxide film of a transistor is formed on the surface of a semiconductor substrate, and an insulating film such as a silicon oxide film is embedded in the trench. It is the separation structure formed by this.

  In this self-aligned STI, the trench is formed after the gate oxide film is formed, so that the sidewall of the trench is formed after the trench is formed as compared with the general STI in which the gate oxide film is formed after the trench is formed. Oxidation by the heat treatment is suppressed, and the compressive stress generated on the side wall of the trench due to oxidation can be greatly reduced. Because of such merits, the self-aligned STI is applied as a countermeasure against crystal defects accompanying compressive stress.

  Next, a flash memory using two types of transistors having different gate oxide film thicknesses will be described as an example of a semiconductor device to which such a self-aligned STI is applied. In this type of flash memory, the thinner gate oxide film is applied as the gate oxide film (tunnel oxide film) of the memory cell transistor formed in the memory cell region, and the thicker gate oxide film is It is applied as a gate oxide film of a MOS (Metal Oxide Semiconductor) transistor formed in a peripheral circuit region for controlling a memory cell transistor.

  Such gate oxide films having different thicknesses are formed as follows. First, a first thermal oxidation process (first time) is performed on the surface of the semiconductor substrate to form an oxide film having a predetermined film thickness. Next, the surface of the semiconductor substrate is removed by removing the portion of the oxide film located in the memory cell region where the memory cell is formed, leaving the portion of the oxide film located in the peripheral circuit region where the peripheral circuit is formed. Expose.

  Next, by performing a second thermal oxidation process (second time), the exposed surface of the semiconductor substrate is oxidized in the memory cell region, and a gate oxide film of the memory cell transistor is formed. On the other hand, in the peripheral circuit region, the already formed oxide film is further grown to form the gate oxide film of the MOS transistor constituting the peripheral circuit.

  The gate oxide film thickness of the MOS transistor in the peripheral circuit region is determined by the first thermal oxidation process and the second thermal oxidation process, and the gate oxide film thickness of the memory cell transistor formed in the memory cell area is the second time. It depends on the thermal oxidation treatment. Therefore, the conditions for the first thermal oxidation process and the second thermal oxidation process are set so that the gate oxide films having different film thicknesses have the desired film thicknesses. After the gate oxide films having different thicknesses are formed in this way, a step (absolute step) is caused in the memory cell region and the peripheral circuit region due to the difference in thickness of the respective gate oxide films.

  In the self-aligned STI, after the gate oxide film is formed in this way, a trench (opening) for element isolation is formed in the gate oxide film and the silicon substrate. By burying a silicon oxide film in the trench and performing chemical mechanical polishing (CMP), the silicon oxide film portion located inside the trench is left, and the other portion is located. A portion of the silicon oxide film is removed. Thus, a self-aligned STI is formed.

Thereafter, in the memory cell region, a memory cell transistor including a gate electrode portion including a floating gate electrode portion and a control gate electrode portion is formed on a semiconductor substrate with a thinner gate oxide film interposed. On the other hand, in the peripheral circuit region, a MOS transistor having a gate electrode portion is formed with a thicker gate oxide film interposed. Thus, the main part of the flash memory is formed. For example, Patent Literature 1 and Patent Literature 2 disclose a method for forming a transistor that is not a self-aligned STI and that uses a gate oxide film having a different thickness in a conventional element isolation structure.
JP 2002-76134 A JP 2001-7217 A

  However, the conventional semiconductor device has the following problems. The silicon oxide film filled in the trench for forming the self-aligned STI is formed on the gate oxide film with a conductive film having a predetermined thickness and an insulating film serving as a mask material interposed. As described above, the thickness of the gate oxide film formed in the peripheral circuit region is larger than the thickness of the gate oxide film formed in the memory cell region. Therefore, the upper surface of the mask material formed in the peripheral circuit region is positioned at a relatively high position with respect to the upper surface of the mask material formed in the memory cell region.

  In this state, when the silicon oxide film embedded in the trench is polished, even if the portion of the silicon oxide film located in the peripheral circuit region having a relatively high step is completely removed, the step is relatively low. Polishing residues may occur in the silicon oxide film portion located in the memory cell region. When a residue of the silicon oxide film is generated, the silicon oxide film itself or the mask material positioned immediately below may become a foreign substance and cause a defect.

  In addition, an electrical short circuit may occur due to a conductive film (polysilicon film) that is located immediately below the silicon oxide film and covers the gate oxide film. In addition, in the memory cell region having a relatively low level difference and the peripheral circuit region having a relatively high level difference, a focus resist is shifted at the time of photolithography of each gate electrode part, and a desired resist pattern is not formed. This also causes a decrease in the dimensional accuracy of the patterning of the part.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device in which steps in regions where transistors having different gate oxide films are formed are reduced. Therefore, another object is to provide a method of manufacturing such a semiconductor device.

  The semiconductor device according to the present invention includes a plurality of first trench isolation regions, a first element formation region, a plurality of second trench isolation regions, a second element formation region, a first oxide film, a first electrode portion, and a second oxide film. And a second electrode part. The plurality of first trench isolation regions are formed in the first region on the main surface of the semiconductor substrate. The first element formation region is formed in a region of the semiconductor substrate sandwiched between one first trench isolation region and another first trench isolation region among the plurality of first trench isolation regions. The plurality of second trench isolation regions are formed in a second region on the main surface of the semiconductor substrate different from the first region. The second element formation region is formed in a region of the semiconductor substrate sandwiched between one second trench isolation region and another second trench isolation region among the plurality of second trench isolation regions. The first oxide film is formed on the surface of the region of the semiconductor substrate located in the first element formation region. The first electrode portion is formed on the first oxide film. The second oxide film is formed on the surface of the region of the semiconductor substrate located in the second element formation region. The second electrode portion is formed on the second oxide film. The first oxide film is thicker than the second oxide film. The first interface between the first oxide film and the surface of the region of the semiconductor substrate located immediately below the first oxide film is the surface of the second oxide film and the surface of the region of the semiconductor substrate located directly below the second oxide film. It is in a position deeper than the second interface. The first trench isolation region is formed deeper than the second trench isolation region.

  The method for manufacturing a semiconductor device according to the present invention includes the following steps, and performs a predetermined thermal oxidation process to form a first oxide film in a predetermined first region on the main surface of the semiconductor substrate, A second oxide film thinner than the first oxide film is formed in a second region different from the first region. A first element isolation region is formed by forming a first trench isolation region in a portion of the first oxide film located in a predetermined region of the first region and a region of the semiconductor substrate located immediately below the portion of the first oxide film. And forming a second element by forming a second trench isolation region in a portion of the second oxide film located in a predetermined region of the second region and a region of the semiconductor substrate located immediately below the portion of the second oxide film. Form a region. A first electrode portion is formed on the surface of the region of the semiconductor substrate located in the first element formation region with a first oxide film interposed. A second electrode portion is formed on the surface of the region of the semiconductor substrate located in the second element formation region with a second oxide film interposed. In the oxide film forming step of forming the first oxide film and the second oxide film, at least a second region is subjected to a plasma nitridation process, and a second thermal oxidation process is performed in a region of the semiconductor substrate located in the second region. By suppressing the region thermal oxidation and proceeding the first region thermal oxidation by the predetermined thermal oxidation process in the region of the semiconductor substrate located in the first region to a region deeper than the second region thermal oxidation, the first oxide film And a region of the semiconductor substrate located immediately below the second oxide film and a second oxide film thinner than the first oxide film at a first interface between the first oxide film and the surface of the region of the semiconductor substrate located immediately below the first oxide film It is formed at a position deeper than the second interface with the surface. In the trench isolation region forming step of forming the first trench isolation region and the second trench isolation region, the first trench isolation region is positioned deeper than the second trench isolation region corresponding to the positional relationship between the first interface and the second interface. Form up to.

  Another semiconductor device manufacturing method according to the present invention includes the following steps. By performing a predetermined thermal oxidation treatment, a first oxide film is formed in a predetermined first region on the main surface of the semiconductor substrate, and a second region thinner than the first oxide film is formed in a second region different from the first region. An oxide film is formed. A first element isolation region is formed by forming a first trench isolation region in a portion of the first oxide film located in a predetermined region of the first region and a region of the semiconductor substrate located immediately below the portion of the first oxide film. And forming a second element by forming a second trench isolation region in a portion of the second oxide film located in a predetermined region of the second region and a region of the semiconductor substrate located immediately below the portion of the second oxide film. Form a region. A first electrode portion is formed on the surface of the region of the semiconductor substrate located in the first element formation region with a first oxide film interposed. A second electrode portion is formed on the surface of the region of the semiconductor substrate located in the second element formation region with a second oxide film interposed. In the oxide film forming step of forming the first oxide film and the second oxide film, the first region thermal oxidation by the predetermined thermal oxidation process in the region of the semiconductor substrate located in the first region is changed to the semiconductor located in the second region. By proceeding to a region deeper than the second region thermal oxidation by a predetermined thermal oxidation process in the region of the substrate, the first oxide film and the first surface of the region of the semiconductor substrate located immediately below the first oxide film The interface is formed at a position deeper than the second interface between the second oxide film thinner than the first oxide film and the surface of the region of the semiconductor substrate located immediately below the second oxide film. In the trench isolation region forming step of forming the first trench isolation region and the second trench isolation region, the first trench isolation region is deeper than the second trench isolation region corresponding to the positional relationship between the first interface and the second interface. Form up to the position.

  In the semiconductor device according to the present invention, the position of the first interface between the first oxide film and the surface of the region of the semiconductor substrate located immediately below the first oxide film is directly below the second oxide film and the second oxide film. The position of the upper surface of the first oxide film and the position of the upper surface of the second oxide film thinner than the first oxide film are located deeper than the position of the second interface with the surface of the region of the semiconductor substrate located at Approaching the same position, the step between the first region and the second region can be greatly reduced.

  In the method for manufacturing a semiconductor device according to the present invention, the second region thermal oxidation by the predetermined thermal oxidation process in the region of the semiconductor substrate located in the second region is suppressed by performing the plasma nitriding process, and the first region The first region thermal oxidation by a predetermined thermal oxidation process in the region of the semiconductor substrate located in the region is advanced to a region deeper than the second region thermal oxidation, thereby being positioned immediately below the first oxide film and the first oxide film. The first interface with the surface of the semiconductor substrate region is deeper than the second interface between the second oxide film thinner than the first oxide film and the surface of the semiconductor substrate region located immediately below the second oxide film. Formed. As a result, the position of the upper surface of the first oxide film and the position of the upper surface of the second oxide film thinner than the first oxide film approach the same position, and the step between the first region and the second region is greatly reduced. can do.

  Furthermore, in another method of manufacturing a semiconductor device according to the present invention, the first region thermal oxidation by the predetermined thermal oxidation process in the region of the semiconductor substrate located in the first region is performed in the region of the semiconductor substrate located in the second region. By proceeding to a region deeper than the second region thermal oxidation by the predetermined thermal oxidation treatment, the first interface between the first oxide film and the surface of the region of the semiconductor substrate located immediately below the first oxide film is the first interface. It is formed at a position deeper than the second interface between the second oxide film thinner than the first oxide film and the surface of the region of the semiconductor substrate located immediately below the second oxide film. As a result, the position of the upper surface of the first oxide film and the position of the upper surface of the second oxide film thinner than the first oxide film approach the same position, and the first region and the second region are not subjected to the plasma nitriding process. Can be greatly reduced.

Embodiment 1
Here, a first example of a semiconductor device including two types of transistors having different gate oxide film thicknesses will be described. The thicker film of the gate oxide film is 30 nm, and the thinner film is 5 nm. First, the manufacturing method will be described.

  As shown in FIG. 1, a thermal oxide film 2a is formed in a peripheral circuit region RA (first region) where a peripheral circuit is formed on the main surface of the semiconductor substrate 1 by performing a predetermined thermal oxidation process (first time). In addition, the thermal oxide film 2b is formed in the memory cell region RB (second region) where the memory cell is formed. The film thickness of the thermal oxide films 2a and 2b is preferably about 10 nm or more in order to prevent the semiconductor substrate (silicon substrate) 1 and nitrogen from reacting by plasma nitriding performed in a later step. The dotted line shown in FIG. 1 represents the position of the surface of the semiconductor substrate 1 before the thermal oxidation treatment.

  Next, by applying a photoresist (not shown) on the thermal oxide films 2a and 2b and performing a predetermined photoengraving process, as shown in FIG. 2, the thermal oxide film 2a located in the peripheral circuit region RA is formed. A resist pattern 70 is formed to cover the film. By performing predetermined etching using the resist pattern 70 as a mask, the thermal oxide film 2b exposed in the memory cell region RB is removed as shown in FIG. Thereafter, the resist pattern 70 is removed.

Next, as nitriding conditions, for example, stage temperature: about 400 ° C., pressure: about 6.67 Pa, RF power: about 1.5 kW, Ar gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ gas flow rate: about Nitrogen plasma is generated under the condition of 40 cm ³ / min (40 sccm). Then, by exposing the semiconductor substrate 1 to the generated plasma for about 30 seconds, nitrogen (nitrogen atoms) 50 are introduced into the thermal oxide film 2a in the peripheral circuit region RA as shown in FIG. In the region RB, nitrogen (nitrogen atoms) 50 is introduced into the surface of the exposed region of the semiconductor substrate 1.

  At this time, in the peripheral circuit region RA, the nitrogen 50 stays in the thermal oxide film 2a and does not reach the interface between the thermal oxide film 2a and the surface of the semiconductor substrate 1 region. Not nitrided. On the other hand, nitrogen 50 is introduced into the surface of the region of the semiconductor substrate 1 exposed in the memory cell region RB, whereby silicon is nitrided to form a nitride layer.

  Next, by performing predetermined etching, as shown in FIG. 5, the thermal oxide film 2a exposed in the peripheral circuit region RA is removed. At this time, the nitrogen 50 introduced into the thermal oxide film 2a is also removed together with the thermal oxide film 2a. On the other hand, in the memory cell region RB, since the nitrogen 50 is strongly bonded to silicon in the semiconductor substrate 1, the nitrogen 50 is not removed. In this etching, it is not necessary to form a resist pattern that covers the memory cell region RB.

Next, as thermal oxidation conditions, for example, temperature: about 850 ° C., pressure: normal pressure, O ₂ gas flow rate: about 5500 cm ³ / min (5500 sccm), H ₂ gas flow rate: about 9900 cm ³ / min (9900 sccm) In the peripheral circuit region RA in which the surface of the region of the semiconductor substrate 1 is not nitrided as shown in FIGS. 6 and 7, by performing the thermal oxidation process (second time) for about 17 minutes 30 seconds, the film thickness is about A 30 nm thermal oxide film 3a is formed. On the other hand, in the memory cell region RB where the surface of the semiconductor substrate 1 is nitrided, thermal oxidation is suppressed by the nitride layer, and a thermal oxide film 3b having a thickness of about 5 nm thinner than the thermal oxide film 3a is formed. By this thermal oxidation, the step S between the peripheral circuit region RA and the memory cell region RB becomes about 13 nm. The value of the step S can be reduced by about 50% compared to the corresponding step of about 27 nm in the case of the comparative example described later. The dotted line shown in FIG. 6 represents the position of the surface of the semiconductor substrate 1 before the thermal oxidation treatment. That is, in this embodiment, it can be said that the step S is smaller than the film thickness difference between the film thickness of the thermal oxide film 3a and the film thickness of the thermal oxide film 3b.

  Further, in the peripheral circuit region RA, thermal oxidation proceeds from the surface of the region of the semiconductor substrate 1 to a deeper region as compared with the memory cell region RB in which thermal oxidation is suppressed. Therefore, the interface 10a between the thermal oxide film 3a in the peripheral circuit region RA and the surface of the semiconductor substrate 1 region is a distance D greater than the interface 10b between the thermal oxide film 3b in the memory cell region RB and the surface of the semiconductor substrate 1 region. It will be located only deep. Assuming that the increase in film thickness due to thermal oxidation proceeds from the surface of the region of the semiconductor substrate 1 toward the outside and the inside at this distance D, the distance D is approximately 30 nm thick and about 5 nm thick. With the oxide film 9b, the distance is almost the same as the step S (about 13 nm). The cross-sectional structure shown in FIG. 7 shows the cross-sectional structure shown in FIG. 6 with a different scale.

  Thus, in the peripheral circuit region RA, the thermal oxide film 3a is formed as the oxide film 9a that becomes the thicker gate oxide film. On the other hand, in the memory cell region RB, the thermal oxide film 3b is formed as an oxide film 9b that becomes the thinner gate oxide film. Next, as shown in FIG. 8, polysilicon films 11a and 11b are formed on the semiconductor substrate 1 by, for example, a CVD (Chemical Vapor Deposition) method, and the silicon nitride film 12a is further formed on the polysilicon films 11a and 11b. , 12b are formed. The step S between the peripheral circuit region RA and the memory cell region RB in the state where the silicon nitride films 12a and 12b are formed is substantially the same as the step S (about 13 nm) in the state where the thermal oxide films 3a and 3b are formed. It is.

  Next, a resist pattern (not shown) for forming a trench is formed on the silicon nitride films 12a and 12b. By performing anisotropic etching on the silicon nitride films 12a and 12b, the polysilicon films 11a and 11b, and the oxide films 9a and 9b using the resist pattern as a mask, as shown in FIG. 9, in the peripheral circuit region RA, the semiconductor substrate An opening 13a that exposes the surface of the region 1 is formed, and an opening 13b that exposes the surface of the region of the semiconductor substrate 1 is formed in the memory cell region RB. At this time, corresponding to the positional (height) relationship between the interface 10a and the interface 10b, the bottom of the opening 13a in the peripheral circuit region RA is located deeper than the bottom of the opening 13b in the memory cell region RA.

  Next, as shown in FIG. 10, by using the silicon nitride film mask as a mask, the region of the semiconductor substrate 1 exposed at the bottom of the openings 13a and 13b is further subjected to anisotropic etching, so that a trench is formed in the peripheral circuit region RA. 14a is formed, and a trench 14b is formed in the memory cell region RB. At this time, the bottom of the trench 14a is higher than the bottom of the trench 14b, corresponding to the position (height) relationship of the surface (interfaces 10a, 10b) of the region of the semiconductor substrate 1 exposed at the bottom of the openings 13a, 13b. It is located deeper by a distance D (about 13 nm). Thus, in the peripheral circuit region RA, the element formation region EA is formed in the region of the semiconductor substrate 1 sandwiched between one trench 14a and another trench 14a. In the memory cell region RB, an element formation region EB is formed in a region of the semiconductor substrate 1 sandwiched between one trench 14b and another trench 14b.

  Next, as shown in FIG. 11, thermal oxide films 15a and 15b are formed on the sidewalls of the trenches 14a and 14b, respectively, by performing a predetermined thermal oxidation process. Next, silicon oxide film 16 is formed on silicon nitride films 12a and 12b so as to fill trenches 14a and 14b, for example, by CVD. Next, as shown in FIG. 12, the silicon oxide film 16 is subjected to chemical mechanical polishing to remove the silicon oxide film 16 located on the upper surfaces of the silicon nitride films 12a and 12b. The upper surfaces of the films 12a and 12b are exposed. At this time, the step S (about 13 nm) between the peripheral circuit region RA and the memory cell region RB is reduced by about 50% compared to the comparative example described later, so that the memory cell region PB remains unpolished. The portion (polishing residue) of the silicon oxide film 16 can be greatly reduced.

  Thereafter, by immersing the semiconductor substrate 1 in hydrofluoric acid or the like, the silicon oxide films 16a and 16b are formed on the silicon oxide films 16a and 16b until the upper surfaces of the silicon oxide films 16a and 16b filled in the trenches 14a and 14b are at desired positions (heights). Etching is performed. Next, by immersing the semiconductor substrate 1 in hot phosphoric acid, as shown in FIG. 13, the silicon nitride films 12a and 12b used as masks are selectively removed, and the surfaces of the polysilicon films 11a and 11b are removed. Exposed. Thus, in the peripheral circuit region RA, the trench isolation region TA including the silicon oxide film 16a filled in the trench 14a is formed, and in the memory cell region RB, the trench isolation region TB including the silicon oxide film 16b filled in the trench 14b. Is formed. The trench isolation regions TA and TB are self-aligned STI.

  Next, as shown in FIG. 14, a doped polysilicon film 17 is formed on the semiconductor substrate 1 so as to cover the polysilicon films 11a and 11b by, eg, CVD. Next, on the doped polysilicon film 17, a resist pattern 72 for covering the doped polysilicon film 17 in the peripheral circuit region RA and patterning a part of the floating gate electrode portion in the memory cell region RB. Is formed.

  By performing anisotropic etching on the doped polysilicon film 17 using the resist pattern 72 as a mask, a doped polysilicon film 17b that becomes a part of the floating gate electrode portion is formed in the memory cell region RB. In the circuit region RA, the doped polysilicon film 17a is left as it is without being etched. Thereafter, as shown in FIG. 15, the resist pattern 72 is removed.

  Next, as shown in FIG. 16, an ONO is formed by sequentially stacking a silicon oxide film, a silicon nitride film, and a silicon oxide film on the semiconductor substrate 1 so as to cover the doped polysilicon films 17a and 17b, for example, by the CVD method. An (Oxide Nitride Oxide) film 18 is formed. Next, as shown in FIG. 17, on the ONO film 18, the ONO film 18 is covered in the memory cell region RB, and the ONO film 18 located in a predetermined region where the gate electrode portion is formed in the peripheral circuit region RA. A resist pattern 73 exposing the portion is formed.

  Next, by etching the ONO film 18 using the resist pattern 73 as a mask, a portion of the ONO film 18 located in a predetermined region where the gate electrode portion is formed is removed in the peripheral circuit region RA. In the memory cell region RB, the ONO film 18 is left without being etched. Thereafter, as shown in FIG. 18, the resist pattern 73 is removed.

  Next, as shown in FIG. 19, a polycide film 19 including a polysilicon film and a metal silicide film is formed on the semiconductor substrate 1 so as to cover the ONO film 18 by, eg, CVD. Next, as shown in FIG. 20, a silicon nitride film 20 is formed on the polycide film 19 by, eg, CVD. The silicon nitride film 20 serves as a mask when patterning the gate electrode portion.

  Next, as shown in FIGS. 21 and 22, the gate electrode portion is patterned on the silicon nitride film 20 in the peripheral circuit region RA, and the gate including the control gate electrode portion and the floating gate electrode portion in the memory cell region RB. A resist pattern 74 for patterning the electrode portion is formed. 22 is a cross-sectional view in a direction perpendicular to the paper surface of FIG. By performing anisotropic etching on the silicon nitride film 20 using the resist pattern 74 as a mask, silicon nitride films 20a and 20b (see FIG. 24) as etching masks are formed. Thereafter, the resist pattern 74 is removed.

  Using the silicon nitride films 20a and 20b as a mask, anisotropic etching is performed on the polycide film 19, ONO film 18 doped polysilicon films 17a and 17b, polysilicon films 11a and 11b, and the like, as shown in FIGS. As described above, the gate electrode portion 21 of the MOS transistor T1 is formed in the peripheral circuit region RA. 24 is a cross-sectional view in a direction perpendicular to the paper surface of FIG. The gate electrode portion 21 is constituted by a polysilicon film 11a, a doped polysilicon film 17a, and a polycide film 19a. Further, the doped polysilicon film 17a and the polycide film 19a are electrically connected through a portion where the ONO film 18a is removed.

  On the other hand, in the memory cell region RB, the gate electrode portion 24 of the memory cell transistor T2 including the floating gate electrode portion 22 and the control gate electrode portion 23 is formed. The floating gate electrode portion 22 is composed of a polysilicon film 11b and a doped polysilicon film 17b, and the control gate electrode portion 23 is composed of a polycide film 19b. Here, since the gate electrode portion 21 in the peripheral circuit region RA and the gate electrode portion 24 in the memory cell region RB are formed with substantially the same film configuration, the height of only the electrode portion is substantially the same. Thus, the main part of the semiconductor device is formed.

  In the semiconductor device thus formed, first, in the peripheral circuit region RA, the element formation region EA is formed in the region of the semiconductor substrate 1 sandwiched between the trench isolation regions TA. On the other hand, in the memory cell region RB, the element formation region EB is formed in the region of the semiconductor substrate 1 sandwiched between the trench isolation regions TB.

  In the element formation region EA, the MOS transistor T1 including the gate electrode portion 21 is formed on the surface of the semiconductor substrate 1 with the gate oxide film 9a interposed. The gate electrode portion 21 is constituted by a polysilicon film 11a, a doped polysilicon film 17a, and a polycide film 19a. Further, the doped polysilicon film 17a and the polycide film 19a are electrically connected to each other through a portion where the ONO film 18a is removed.

  On the other hand, in the memory cell region RB, a memory cell transistor including a gate electrode portion 24 including a floating gate electrode portion 22, an ONO film 18b, and a control gate electrode portion 23 with a gate oxide film 9b interposed on the surface of the semiconductor substrate 1. T2 is formed. The floating gate electrode portion 22 has a two-layer structure of a polysilicon film 11b and a doped polysilicon film 17b. Further, the interface between the polysilicon film 11b and the doped polysilicon film 17b is at a position lower than the upper surface of the silicon oxide film 16b in the trench region TB.

  The gate oxide film 9a is formed thicker than the gate oxide film 9b. The interface 10a between the gate oxide film 9a and the surface of the region of the semiconductor substrate 1 located immediately below the gate oxide film 9a is the surface of the region of the semiconductor substrate 1 located directly below the gate oxide film 9b and the gate oxide film 9b. It is in a position deeper than the interface 10b. Further, the bottom of the trench isolation region TA is at a position deeper than the bottom of the trench isolation region TB, and the trench isolation region TA is formed at a position deeper than the trench isolation region TB.

(Comparative example)
Next, the effect of the semiconductor device described above will be described in relation to a comparative example. First, a method for manufacturing a semiconductor device according to the comparative example will be described.

  As shown in FIG. 25, thermal oxidation treatment forms a thermal oxide film 102a in the peripheral circuit region RA on the main surface of the semiconductor substrate 101, and a thermal oxide film 102b in the memory cell region RB. Note that the dotted line shown in FIG. 25 represents the position of the surface of the semiconductor substrate 101 before the thermal oxidation treatment. Next, by performing a predetermined photoengraving process on the surfaces of the thermal oxide films 102a and 102b, a resist pattern 170 covering the thermal oxide film 102a located in the peripheral circuit region RA is formed as shown in FIG. By performing predetermined etching using resist pattern 170 as a mask, as shown in FIG. 27, thermal oxide film 102b exposed in memory cell region RB is removed. Thereafter, the resist pattern 170 is removed.

  Next, as shown in FIG. 28, by performing a predetermined thermal oxidation process, in the peripheral circuit region RA, the thermal oxide film 102a grows to form a thermal oxide film 103a having a thickness of about 30 nm. On the other hand, in the memory cell region RB, the exposed surface of the semiconductor substrate 101 is oxidized to form a thermal oxide film 103b having a thickness of about 5 nm thinner than the thermal oxide film 103a. This thermal oxide film 103a is formed as an oxide film 109a that becomes a thicker gate oxide film, and the thermal oxide film 103b is formed as an oxide film 109b that becomes a thinner gate oxide film. . In FIG. 28, the dotted line shown in the memory cell region RB represents the position of the surface of the semiconductor substrate 101 before the thermal oxidation process.

  In particular, the oxide film 109a is formed as a thermal oxide film 103a having a desired thickness in the second thermal oxidation process without removing the thermal oxide film 102a formed by the first thermal oxidation process. Therefore, the region thermally oxidized downward from the surface of the region of the semiconductor substrate 101 in the peripheral circuit region RA is the thermal oxide film 103a having a desired film thickness in the second thermal oxidation process after removing the thermal oxide film 102a. Compared to the case of forming the film, it is shallow.

  Therefore, even if the oxide films 109a and 109b have substantially the same thickness as the oxide films 9a and 9b of the semiconductor device according to the present embodiment, as shown in FIG. A step (absolute step) SS between the formed peripheral circuit region RA and the memory cell region RB in which the oxide film 109b is formed is about 27 nm.

  Further, the height of the interface 110a between the thermal oxide film 103a and the surface of the semiconductor substrate 101 in the peripheral circuit region RA and the height of the interface 110b between the thermal oxide film 103b and the surface of the semiconductor substrate 101 in the memory cell region RB. The difference DD (see FIG. 28) is also about 2 nm, and the interface 110b of the memory cell region RB becomes deeper. However, when the gate oxide film in the memory cell region RB is thin as in this comparative example, as shown in FIG. 29, the interface 110a and the interface 110b are positioned substantially at the same position (height) as shown in FIG. become. Note that the cross-sectional structure shown in FIG. 29 shows the cross-sectional structure shown in FIG. 28 at a different scale.

  Next, as shown in FIG. 30, polysilicon films 111a and 111b are formed on the semiconductor substrate 101 by, eg, CVD, and silicon nitride films 112a and 112b are formed on the polysilicon films 111a and 111b. The The step SS between the peripheral circuit region RA and the memory cell region RB in the state where the silicon nitride films 112a and 112b are formed is substantially the same step (about 27 nm) as the step S in the state where the oxide films 109a and 109b are formed. is there.

  Next, a resist pattern (not shown) for forming a trench is formed on the silicon nitride films 112a and 112b. By performing anisotropic etching on the silicon nitride films 112a and 112b, the polysilicon films 111a and 111b, and the oxide films 109a and 109b using the resist pattern as a mask, as shown in FIG. 31, in the peripheral circuit region RA, the semiconductor substrate An opening 113a that exposes the surface of the region 101 is formed, and an opening 113b that exposes the surface of the region of the semiconductor substrate 101 is formed in the memory cell region RB. At this time, the bottom of the opening 113a in the peripheral circuit region RA is slightly shallower than the bottom of the opening 113b in the memory cell region RA in accordance with the positional (height) relationship between the interface 110a and the interface 110b. It is located at almost the same position (height).

  Further, by performing anisotropic etching on the region of the semiconductor substrate 101 exposed at the bottoms of the openings 113a and 113b using the silicon nitride mask as a mask, the trench 114a is formed in the peripheral circuit region RA as shown in FIG. The trench 114b is formed in the memory cell region RB. At this time, the bottom of the trench 114a is slightly shallower than the bottom of the trench 114b, corresponding to the position (height) relationship between the interfaces 110a and 110b, but is located at substantially the same position (height) when viewed macroscopically. (See inside circle).

  Thus, in the peripheral circuit region RA, the element formation region EA is formed in the region of the semiconductor substrate 101 sandwiched between one trench 114a and another trench 114a. On the other hand, in the memory cell region RB, an element formation region EB is formed in a region of the semiconductor substrate 101 sandwiched between one trench 114b and another trench 14b. Next, as shown in FIG. 33, thermal oxide films 115a and 115b are formed on the sidewalls of the trenches 114a and 114b, respectively, by performing a predetermined thermal oxidation process. Next, silicon oxide film 116 is formed on silicon nitride films 112a and 112b so as to fill trenches 114a and 114b by, for example, the CVD method. Next, as shown in FIG. 34, the silicon oxide film 116 is subjected to chemical mechanical polishing.

  At this time, in the peripheral circuit region RA having a relatively high level difference, the portion of the silicon oxide film 116 located on the upper surface of the silicon nitride film 112a is removed, and the upper surface of the silicon nitride film 112a is exposed. On the other hand, in the memory cell region RB having a relatively low level difference, a portion of the silicon oxide film 116 located on the upper surface of the silicon nitride film 112b is not completely removed, and a polishing residue of the silicon oxide film 116 is generated. Yes (see inside circle).

  Thereafter, by immersing the semiconductor substrate 101 in hydrofluoric acid or the like, the silicon oxide films 116a and 116b are formed on the silicon oxide films 116a and 116b until the upper surfaces of the silicon oxide films 116a and 116b filled in the trenches 114a and 114b become desired positions (heights). Etching is performed. Next, by immersing the semiconductor substrate 101 in hot phosphoric acid, as shown in FIG. 35, the silicon nitride films 112a and 112b used as masks are selectively removed, and the surfaces of the polysilicon films 111a and 111b are removed. Exposed. Thus, the trench isolation region TA including the silicon oxide film 116a filled in the trench 114a is formed in the peripheral circuit region RA, and the trench isolation region TB including the silicon oxide film 116b filled in the trench 114b is formed in the memory cell region RB. Is formed. Here, in the memory cell region RB, since the silicon oxide film 116 by the chemical mechanical polishing process is not completely removed, the height of the trench isolation region TB from the upper surface of the polysilicon film 111b is set in the peripheral circuit region RA. The height of the trench isolation region TA is higher than the height from the upper surface of the polysilicon film 111a.

  Next, as shown in FIG. 36, a doped polysilicon film 117 is formed on the semiconductor substrate 101 so as to cover the polysilicon films 111a and 111b by, eg, CVD. Next, a resist pattern 172 for covering the doped polysilicon film 117 in the peripheral circuit region RA and patterning a part of the floating gate electrode in the memory cell region RB is formed on the doped polysilicon film 117. .

  Next, as shown in FIG. 37, by using the resist pattern 172 as a mask, the doped polysilicon film 117 is subjected to anisotropic etching, so that the memory cell region RB becomes a part of the floating gate electrode portion. The top polysilicon film 117b is formed, and is left as it is as the doped polysilicon film 117a without being etched in the peripheral circuit region RA. Thereafter, the resist pattern 172 is removed.

  Next, as shown in FIG. 38, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked on the semiconductor substrate 101 so as to cover the doped polysilicon films 117a and 117b by, for example, the CVD method. A film 118 is formed. Next, a resist pattern 173 is formed on the ONO film 118 so as to cover the ONO film 118 in the memory cell region RB and to expose a portion of the ONO film 118 located in a predetermined region where the gate electrode portion is formed in the peripheral circuit region RA. It is formed.

  Next, by etching the ONO film 118 using the resist pattern 173 as a mask, a portion of the ONO film 118 located in a predetermined region where the gate electrode portion is formed is removed in the peripheral circuit region RA. In the memory cell region RB, the ONO film 118 is left without being etched. Thereafter, the resist pattern 173 is removed.

  Next, as shown in FIG. 39, a polycide film 119 including a polysilicon film and a metal silicide film is formed on the semiconductor substrate 101 so as to cover the ONO film 118 by, eg, CVD. Next, a silicon nitride film 120 is formed on the polycide film 119 by, eg, CVD. The silicon nitride film 120 serves as a mask when patterning the gate electrode portion.

  Next, as shown in FIGS. 40 and 41, the gate electrode portion is patterned in the peripheral circuit region RA on the silicon nitride film 120, and the gate including the control gate electrode portion and the floating gate electrode portion in the memory cell region RB. A resist pattern 174 for patterning the electrode portion is formed. 41 is a cross-sectional view in a direction perpendicular to the paper surface of FIG. By performing anisotropic etching on the silicon nitride film 120 using the resist pattern 174 as a mask, silicon nitride films 120a and 120b (see FIG. 43) as etching masks are formed. Thereafter, the resist pattern 174 is removed.

  By performing anisotropic etching on the polycide film 119, the ONO film 118, the doped polysilicon films 117a and 117b, the polysilicon films 112a and 112b, etc. using the silicon nitride films 120a and 120b as masks, FIG. 42 and FIG. As shown, the gate electrode portion 121 of the MOS transistor T1 is formed in the peripheral circuit region RA. 43 is a cross-sectional view in a direction perpendicular to the paper surface of FIG. The gate electrode portion 121 includes a polysilicon film 111a, a doped polysilicon film 117a, and a polycide film 119a. Also, the doped polysilicon film 117a and the polycide film 119a are electrically connected via the portion from which the ONO film 118 is removed.

  On the other hand, in the memory cell region RB, the gate electrode portion 124 of the memory cell transistor T2 including the floating gate electrode portion 122 and the control gate electrode portion 123 is formed. The floating gate electrode portion 122 is composed of a polysilicon film 111b and a doped polysilicon film 117b, and the control gate electrode portion 123 is composed of a polycide film 119b. Thus, the main part of the semiconductor device according to the comparative example is formed.

  In the semiconductor device according to the comparative example described above, the step SS between the peripheral circuit region RA and the memory cell region RB is about 27 nm in the state where the thermal oxide films 103a and 103b are formed as the gate oxide films 109a and 109b (FIG. 29). Therefore, when the chemical mechanical polishing process is performed on the silicon oxide film 116 filling the trenches 114a and 114b, in the memory cell region RB having a relatively low level difference, the silicon oxide film 116 positioned on the upper surface of the silicon nitride film 112b. This portion may not be completely removed, and a polishing residue of the silicon oxide film 116 may be generated.

  When a polishing residue of the silicon oxide film 116 is generated, for example, as shown in FIG. 44, the portion of the silicon nitride film located immediately below the residue of the silicon oxide film 116 may not be removed and may remain as a residue 112d. . On the other hand, doped polysilicon film 111b located under silicon nitride film 112b needs to be removed in a predetermined region other than the region where memory cell transistors are formed in memory cell region RB.

  Therefore, when the silicon nitride film 112b is to be removed originally, if the silicon nitride film residue 112d is generated in such a region, the doped polysilicon film 111b located immediately below the silicon nitride film residue 112d There is a possibility that an electrical short circuit may occur due to the remaining portion of the doped polysilicon film 111b that remains without being removed. In addition, residues such as the silicon oxide film 116 and the silicon nitride film 112d that are left without being removed become foreign substances, which may be one cause of defects in the semiconductor device. Note that the silicon nitride film residue 112d shown in FIG. 44 is not only intended to be a residue generated in the element formation region EB but also a residue generated in a region other than the element formation region EB in the memory cell region RB. Is.

  The height of the trench isolation region TB in the memory cell region RB from the upper surface of the polysilicon film 111b is higher than the height of the trench isolation region TA in the peripheral circuit region RA from the upper surface of the polysilicon film 111a. Therefore, when the polysilicon film 117b is patterned, a residue of the polysilicon film is formed on the side surface of the portion protruding above the trench isolation region TB, which may cause a short circuit.

  In the semiconductor device according to the comparative example, defocusing may occur in photoengraving when the gate electrode portion is patterned due to the step SS (about 27 nm) between the peripheral circuit region RA and the memory cell region RB. . Therefore, for example, as shown in FIG. 41, a resist pattern 274 having a dimension different from that of a desired resist pattern 174 is formed, and as shown in FIG. 43, a gate electrode portion 224 having a dimension different from the predetermined dimension is formed. The gate electrode portion 124 having a predetermined dimension may not be formed.

  On the other hand, in the semiconductor device according to the present embodiment, the surface of the region of the semiconductor substrate 1 exposed in the memory cell region RB is subjected to plasma nitridation, thereby performing thermal oxidation when performing the second thermal oxidation. Will be suppressed. Thus, in the state where the oxide films 9a and 9b to be the gate oxide films are formed, the step between the peripheral circuit region RA and the memory cell region RB is about 13 nm, and the step of the semiconductor device according to the comparative example (about 27 nm). Compared with FIG. 5, the step between the peripheral circuit region RA and the memory cell region RB is reduced by about 50%.

  That is, by performing the plasma nitridation process, the thermal oxidation (second area thermal oxidation) by the thermal oxidation process in the area of the semiconductor substrate 1 located in the memory cell area RB (second area) is suppressed, and the peripheral circuit area RA ( The oxide film 9a (first oxide film) is obtained by advancing thermal oxidation (first area thermal oxidation) by thermal oxidation in the region of the semiconductor substrate 1 located in the first region) to a region deeper than the second region thermal oxidation. ) And the surface of the region of the semiconductor substrate 1 located immediately below the oxide film 9a, the interface 10a (first interface) is an oxide film 9b (second oxide film) thinner than the oxide film 9a and the oxide film 9b. It is formed at a position deeper than the interface 10b (second interface) with the surface of the region of the semiconductor substrate 1 located immediately below. Therefore, the position of the upper surface of the oxide film 9a and the position of the upper surface of the oxide film 9b thinner than the oxide film 9a approach the same position (height), and the step between the peripheral circuit region RA and the memory cell region RB is greatly increased. To be reduced.

  Thereby, when the silicon oxide film 16 filling the trenches 14a and 14b is subjected to the chemical mechanical polishing process, the residue of the silicon oxide film 16 is suppressed, and the residue of the silicon oxide film 16 is generated. An electrical short circuit like the semiconductor device according to the comparative example can be prevented. Further, residues that become foreign matters are reduced, so that defects in the semiconductor device can be reduced.

  Furthermore, in the semiconductor device according to the present embodiment, the step between the peripheral circuit region RA and the memory cell region RB is significantly reduced, and defocusing occurs in photolithography when the gate electrode portion is patterned. Thus, a resist pattern 74 having a predetermined dimension can be formed. Thereby, desired gate electrode portions 21 and 24 can be formed with high dimensional accuracy.

  In the semiconductor device according to the comparative example, the bottom of the trench isolation region TA formed in the peripheral circuit region RA and the bottom of the trench isolation region TB formed in the memory cell region RB are located at the positions of the interfaces 110a and 110b (high Corresponding to the relationship, the bottom of the trench isolation region TA formed in the peripheral circuit region RA becomes shallower. (From a macro perspective, the two bottoms are located at substantially the same position as shown by the dotted line in FIG. 35). Therefore, a peripheral circuit region RA in which a MOS transistor with a thick gate oxide film driven at a higher voltage is formed, and a memory cell region RB in which a memory cell transistor with a thin gate oxide film driven at a lower voltage is formed, There is a possibility that the margin of the isolation breakdown voltage is low.

  In contrast, in the semiconductor device according to the present embodiment, the interface 10a between the thermal oxide film 3a in the peripheral circuit region RA and the surface of the region of the semiconductor substrate 1 corresponds to the thermal oxide film 3b in the memory cell region RB and the semiconductor substrate. The bottom of the trench isolation region TA formed in the peripheral circuit region RA is located in the trench isolation region TB formed in the memory cell region RB by being positioned deeper than the interface 10b with the surface of the region 1 by the distance D. It is located at a position deeper than the bottom of the substrate by a distance D (about 13 nm) (see FIG. 10). Accordingly, the peripheral circuit region RA to which a higher voltage is applied and the memory cell region RB to which a lower voltage is applied compared to the semiconductor device according to the comparative example in which the bottom positions of the trench isolation regions TA and TB are the same. The isolation breakdown voltage can be improved.

  Further, in the semiconductor device according to the comparative example, the oxide film 109a in the peripheral circuit region RA is formed by two thermal oxidations, and the oxide film 109b in the memory cell region RB is formed by one thermal oxidation. In particular, in the formation of the oxide film 109a, a resist pattern 170 is formed on the surface of the thermal oxide film 103a formed by the first thermal oxidation, and the thermal oxide film 102b formed in the memory cell region RB is formed by wet etching. Since it is removed, there is a risk of contamination with resist or etchant. Therefore, the reliability of the gate oxide film 109a may be impaired.

  On the other hand, in the semiconductor device according to the present embodiment, both the oxide film 9a in the peripheral circuit region RA and the oxide film 9b in the memory cell region RB are formed by the second thermal oxidation process, and are thermally oxidized. The number of treatments is formed by one thermal oxidation treatment. Then, in the oxide film 9a in the peripheral circuit region RA, the thermal oxide film 3a formed by the first thermal oxidation process and covered with the resist pattern is removed. As a result, there is no risk of contamination by the resist or the etching solution, and the reliability of the oxide film 9a that becomes the gate oxide film including the oxide film 9b can be improved as compared with the semiconductor device according to the comparative example.

  Further, in the semiconductor device according to the present embodiment, compared with the semiconductor device according to the comparative example, the thermal oxide film 3a formed in the peripheral circuit region RA is removed in the plasma nitriding process step and the first thermal oxidation process. Therefore, the step of the semiconductor device can be greatly reduced by minimizing an increase in the number of steps.

(Plasma nitriding)
As described above, in the semiconductor device according to the present embodiment, the gate oxide film having a thin film thickness is formed by suppressing the oxidation of the semiconductor substrate by the thermal oxidation process by performing the plasma nitriding process when forming the gate oxide film. A film is formed. Therefore, the oxidation resistance by plasma nitriding and the controllability of the oxide film thickness will be described.

  As a sample, a semiconductor substrate (silicon substrate) having a thermal oxide film having a thickness of about 1.8 nm as a base oxide film was used. After subjecting the semiconductor substrate to plasma nitriding under various conditions, the film thickness (optical film thickness) of the thermal oxide film formed by applying predetermined re-oxidation treatment was measured. The reoxidation treatment was performed under the condition that a thermal oxide film having a film thickness of 12 nm was formed on the surface of the semiconductor substrate.

The result is shown in FIG. The horizontal axis represents the optical film thickness of the oxide film after reoxidation, which is a value measured by an ellipsometer with a refractive index n of 1.42. Among the plasma nitriding conditions shown on the vertical axis, the condition A is as follows: pressure: about 66.7 Pa, RF power: about 1.2 kW, Ar / N ₂ = about 1000 cm ³ / min (1000 sccm) / about 40 cm ³ / min ( 40 sccm). Condition B is pressure: about 6.67 Pa, RF power: about 1.5 kW, Ar / N ₂ = about 1000 cm ³ / min (1000 sccm) / about 40 cm ³ / min (40 sccm). Condition C is: pressure: about 4.0 Pa, RF power: about 2.0 kW, Ar / N ₂ = about 500 cm ³ / min (500 sccm) / about 200 cm ³ / min (200 sccm). The non-nitrided sample is obtained by re-oxidizing a semiconductor substrate on which a base oxide film is formed without performing plasma nitriding. The stage temperature is about 400 ° C.

  As shown in FIG. 45, for example, as shown in condition B, by increasing the nitriding time even under the same plasma nitriding conditions, the oxidation resistance by nitriding advances, and the film thickness after reoxidation can be made thinner. it can. Even when the nitriding time is the same (60 seconds), as shown in the conditions A, B, and C, the film thickness after reoxidation can be made thinner as nitriding progresses. Thus, it can be seen that by distributing the plasma nitriding conditions, the film thickness of the oxide film (oxynitride film) formed on the semiconductor substrate can be controlled even under the same thermal oxidation conditions.

  Next, the relationship between the oxidation resistance by plasma nitriding and the thickness of the base oxide film formed on the semiconductor substrate will be described. First, a thermal oxide film having a film thickness of 1.8 nm, 2.4 nm, and 5.5 nm was formed as a base oxide film on the surface of a semiconductor substrate (silicon substrate). The semiconductor substrate was subjected to a predetermined plasma nitriding treatment and then subjected to a predetermined re-oxidation treatment to measure the thickness (optical film thickness) of the thermal oxide film formed. As the plasma nitriding treatment, the above-described condition C plasma nitriding treatment was performed for 60 seconds.

  The result is shown in FIG. The horizontal axis represents the oxide film thickness (monitor film thickness) formed on the surface of the semiconductor substrate by reoxidation. The vertical axis represents the optical film thickness after reoxidation. As shown in FIG. 46, even if the reoxidation conditions are the same (for example, the reoxidation film thickness is about 12 nm), the film thickness (optical film thickness) of the oxide film after reoxidation is different if the film thickness of the base oxide film is different. It can be seen that by changing the thickness of the base oxide film, the finished film thickness of the oxide film after reoxidation can be controlled.

Embodiment 2
Here, a second example of a semiconductor device including two types of transistors having different gate oxide film thicknesses will be described. First, the manufacturing method will be described. As shown in FIG. 47, by performing a predetermined thermal oxidation process (first time), a thermal oxide film 2a is formed in the peripheral circuit region RA of the semiconductor substrate 1, and a thermal oxide film 2b is formed in the memory cell region RB. Is done. The thermal oxide films 2a and 2b have a film thickness in the case of the semiconductor device described above because the degree of nitridation by the plasma nitridation process performed in a later process is stronger than the plasma nitridation process (Embodiment 1). It is preferable to make it thicker than the thickness (10 nm or more). 47 represents the position of the surface of the semiconductor substrate 1 before the thermal oxidation treatment.

  Next, by applying a photoresist (not shown) on the thermal oxide films 2a and 2b and performing a predetermined photoengraving process, as shown in FIG. 48, the thermal oxide film 2a located in the peripheral circuit region RA is formed. A resist pattern 70 is formed to cover the film. By performing predetermined etching using resist pattern 70 as a mask, thermal oxide film 2b exposed in memory cell region RB is removed as shown in FIG. Thereafter, the resist pattern 70 is removed.

Next, a plasma nitridation process is performed on the semiconductor substrate 1. At this time, in order to obtain a desired thermal oxide film thickness by the plasma nitriding treatment and the second and third thermal oxidation treatments performed in the subsequent steps, the above-described plasma nitriding treatment is also performed under conditions in which the degree of nitridation is strong. Is done. As the nitriding conditions, for example, stage temperature: about 400 ° C., pressure: about 6.67 Pa, RF power: about 1.5 kW, Ar gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ gas flow rate: about 40 cm ³ Nitrogen plasma is generated under the condition of / min (40 sccm). Then, by exposing the semiconductor substrate 1 to the generated plasma for about 45 seconds, as shown in FIG. 50, in the peripheral circuit region RA, nitrogen (nitrogen atoms) 50 is introduced into the thermal oxide film 2a, and the memory cell. In the region RB, nitrogen (nitrogen atoms) 50 is introduced into the surface of the exposed region of the semiconductor substrate 1. Thus, nitrogen 50 is introduced into the surface of the region of the semiconductor substrate 1 exposed in the memory cell region RB, so that silicon is nitrided to form a nitride layer.

  Next, by performing predetermined etching, as shown in FIG. 51, the thermal oxide film 2a exposed in the peripheral circuit region RA is removed. At this time, the nitrogen 50 introduced into the thermal oxide film 2a is also removed together with the thermal oxide film 2a. In this etching, it is not necessary to form a resist pattern that covers the memory cell region RB.

Next, as thermal oxidation conditions, for example, temperature: about 850 ° C., pressure: normal pressure, O ₂ gas flow rate: about 5500 cm ³ / min (5500 sccm), H ₂ gas flow rate: about 9900 cm ³ / min (9900 sccm) Then, by performing the thermal oxidation process (second time) for about 21 minutes and 30 seconds, as shown in FIG. 52, in the peripheral circuit region RA where the surface of the region of the semiconductor substrate 1 is not nitrided, a thick thermal oxidation is performed. A film 3a is formed. On the other hand, in the memory cell region RB where the surface of the semiconductor substrate 1 is nitrided, thermal oxidation is suppressed by the nitride layer, and a thermal oxide film 3b thinner than the thermal oxide film 3a is formed.

  Note that in the second thermal oxidation process, the upper surface of the thermal oxide film formed in the peripheral circuit region RA and the upper surface of the thermal oxide film formed in the memory cell region RB are substantially the same due to the third thermal oxidation process described later. Thermal oxidation conditions are set so as to be at the same position (height). In FIG. 52, the dotted line shown in the peripheral circuit region RA represents the position of the surface of the semiconductor substrate 1 before the thermal oxidation process.

  Next, by applying a photoresist (not shown) on the thermal oxide films 3a and 3b and performing a predetermined photoengraving process, as shown in FIG. 53, the thermal oxide film 3b located in the memory cell region RB. A resist pattern 71 is formed to cover the pattern. By performing predetermined etching using the resist pattern 71 as a mask, the thermal oxide film 3a exposed in the peripheral circuit region RA is removed as shown in FIG. Thereafter, the resist pattern 71 is removed.

Next, as thermal oxidation conditions, for example, temperature: about 850 ° C., pressure: normal pressure, O ₂ gas flow rate: about 5500 cm ³ / min (5500 sccm), H ₂ gas flow rate: about 9900 cm ³ / min (9900 sccm) Thus, by performing the thermal oxidation process (third time) for about 17 minutes 30 seconds, as shown in FIG. 55, the thermal oxide film 4a is formed in the peripheral circuit region RA where the surface of the region of the semiconductor substrate 1 is not nitrided. The On the other hand, in the memory cell region RB where the surface of the region of the semiconductor substrate 1 is nitrided, thermal oxidation is suppressed by the nitride layer, and a thermal oxide film 4b thinner than the thermal oxide film 4a is formed.

  As shown in FIG. 55, the upper surface of the thermal oxide film 4a formed in the peripheral circuit region RA and the thermal oxide film 4b formed in the memory cell region RB by the second thermal oxidation process and the third thermal oxidation process. The upper surface is almost at the same position (height), and the step between the peripheral circuit region RA and the memory cell region RB is almost eliminated. In FIG. 55, the dotted line shown in the peripheral circuit region RA represents the position of the surface of the semiconductor substrate 1 before the thermal oxidation treatment. On the other hand, the dotted line shown in the memory cell region RA represents the position of the interface between the thermal oxide film 3 b and the surface of the region of the semiconductor substrate 1.

  Thereafter, through steps similar to those shown in FIGS. 9 and 10, the silicon oxide film 16 is formed on the silicon nitride films 12a and 12b so as to fill the trenches 14a and 14b as shown in FIG. Is done. Next, as shown in FIG. 57, the silicon oxide film 16 is subjected to chemical mechanical polishing to remove the silicon oxide film 16 located on the upper surfaces of the silicon nitride films 12a and 12b. The upper surfaces of the films 12a and 12b are exposed. At this time, compared with the semiconductor device according to the comparative example, the step (absolute step) between the peripheral circuit region RA and the memory cell region RB is almost eliminated, so that the memory cell region PB is left unpolished. The portion (polishing residue) of the silicon oxide film 16 is almost eliminated.

  Next, through a process similar to that shown in FIG. 13, as shown in FIG. 58, trench isolation region TA including silicon oxide film 16a filled in trench 14a is formed in peripheral circuit region RA, and the memory cell In the region RB, a trench isolation region TB including the silicon oxide film 16b filled in the trench 14b is formed.

  14 to FIG. 21, the gate electrode portion is patterned in the peripheral circuit region RA on the silicon nitride film 20 as shown in FIGS. 59 and 60, and the memory cell region RB. Then, a resist pattern 74 for patterning the gate electrode portion including the control gate electrode portion and the floating gate electrode portion is formed. Next, anisotropic etching is performed on the silicon nitride film 20 using the resist pattern 74 as a mask, thereby forming silicon nitride films 20a and 20b (see FIG. 62) as etching masks. Thereafter, the resist pattern 74 is removed.

  Next, anisotropic etching is performed on the polycide film 19, the ONO film 18, the doped polysilicon films 17a and 17b, the polysilicon films 11a and 11b, and the like using the silicon nitride films 20a and 20b as masks, so that FIGS. As shown in FIG. 5, in the peripheral circuit region RA, the gate electrode portion 21 of the MOS transistor T1 is formed. The gate electrode portion 21 is constituted by a polysilicon film 11a, a doped polysilicon film 17a, and a polycide film 19a. Further, the doped polysilicon film 17a and the polycide film 19a are electrically connected through a portion where the ONO film 18 is removed.

  On the other hand, in the memory cell region RB, the gate electrode portion 24 of the memory cell transistor T2 including the floating gate electrode portion 22 and the control gate electrode portion 23 is formed. The floating gate electrode portion 22 is composed of the polysilicon film 11b and the doped polysilicon film 17b, and the control gate electrode 23 is composed of the polycide film 19b. Thus, the main part of the semiconductor device is formed.

  In the semiconductor device described above, by performing plasma nitriding when forming the gate oxide film, the following effects can be obtained in addition to the effects of the semiconductor device (Embodiment 1) described above. That is, in the semiconductor device according to the present embodiment, the position of the upper surface of the thermal oxide film 4a that becomes the gate oxide film formed in the peripheral circuit region RA and the thermal oxidation that becomes the gate oxide film formed in the memory cell region RB. The position of the upper surface of the film 4b is the same position (height).

  Thereby, when the silicon oxide film 16 filling the trenches 14a and 14b is subjected to a chemical mechanical polishing process, the residue of the silicon oxide film 16 can be almost eliminated. As a result, it is possible to reliably prevent an electrical short circuit such as that of the semiconductor device according to the comparative example caused by the residue of the silicon oxide film 16 and to reliably reduce defects in the semiconductor device. . In addition, it is possible to reliably prevent the occurrence of defocus in photolithography when patterning the gate electrode portion, and it is possible to accurately form a desired gate electrode portion.

  Thus, in the semiconductor device according to the present embodiment, the number of steps of the thermal oxidation treatment is increased by one step as compared with the case of the semiconductor device (the first embodiment) described above, but the nitridation of the plasma nitriding treatment is performed together with the thermal oxidation conditions. By adjusting the conditions, the step between the peripheral circuit region RA and the memory cell region RB can be almost eliminated. Note that the position of the upper surface of the thermal oxide film 4a and the position of the upper surface of the thermal oxide film 4b being the same position (height) is not intended to be exactly the same position, but the film thickness at the time of film formation. As a matter of course, manufacturing errors such as variations in the thickness and variations in the amount of removal during etching (about ± 10%) are included.

Embodiment 3
Here, a third example of a semiconductor device including two types of transistors having different gate oxide film thicknesses will be described. First, the manufacturing method will be described. As shown in FIG. 63, by performing a predetermined thermal oxidation process (first time), a thermal oxide film 2a is formed in the peripheral circuit region RA of the semiconductor substrate 1, and a thermal oxide film 2b is formed in the memory cell region RB. Is done. The thermal oxide films 2a and 2b have a thickness of about 15 nm. 63 represents the position of the surface of the semiconductor substrate 1 before the thermal oxidation treatment.

Next, a plasma nitridation process is performed on the semiconductor substrate 1. This nitriding treatment is performed under the condition that nitrogen does not reach the surface of the semiconductor substrate 1. As the nitriding conditions, for example, stage temperature: about 400 ° C., pressure: about 6.67 Pa, RF power: about 1.5 kW, Ar gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ gas flow rate: about 40 cm ³ Nitrogen plasma is generated under the condition of / min (40 sccm). Then, by exposing the semiconductor substrate 1 to the generated plasma for about 60 seconds, as shown in FIG. 64, nitrogen (nitrogen atoms) 50 are introduced into the thermal oxide film 2a in the peripheral circuit region RA, and the memory cell. In the region RB, nitrogen (nitrogen atoms) 50 is introduced into the thermal oxide film 2b.

  Next, by applying a photo resist (not shown) on the thermal oxide films 2a and 2b and performing a predetermined photoengraving process, as shown in FIG. 65, the thermal oxide film 2b located in the memory cell region RB. A resist pattern 70 is formed to cover the film. By performing predetermined etching using resist pattern 70 as a mask, as shown in FIG. 66, thermal oxide film 2a exposed in peripheral circuit region RA is removed. Thereafter, the resist pattern 70 is removed.

Next, as thermal oxidation conditions, for example, temperature: about 850 ° C., pressure: normal pressure, O ₂ gas flow rate: about 5500 cm ³ / min (5500 sccm), H ₂ gas flow rate: about 9900 cm ³ / min (9900 sccm) Then, by performing the thermal oxidation process (second time) for about 17 minutes and 30 seconds, as shown in FIG. 67, the thermal oxide film 3a is formed in the peripheral circuit region RA where the surface of the region of the semiconductor substrate 1 is exposed. . On the other hand, a thermal oxide film 3b is formed in the memory cell region RB. At this time, in the memory cell region RB, since nitrogen 50 is introduced into the thermal oxide film 2b, the thickness of the thermal oxide film 3b is smaller than that in the case where nitrogen is not introduced.

  In the second thermal oxidation process, the film thickness of the thermal oxide film formed in the peripheral circuit region RA becomes a desired film thickness by the second thermal oxidation process and the third thermal oxidation process described later. Thus, thermal oxidation conditions are set. In FIG. 67, the dotted line shown in the peripheral circuit region RA represents the position of the surface of the region of the semiconductor substrate 1 before the thermal oxidation treatment.

  Next, by applying a photoresist (not shown) on the thermal oxide films 3a and 3b and performing a predetermined photoengraving process, as shown in FIG. 68, the thermal oxide film 2a located in the peripheral circuit region RA. A resist pattern 71 is formed to cover the pattern. By performing predetermined etching using resist pattern 71 as a mask, as shown in FIG. 69, thermal oxide film 3b exposed in memory cell region RB is removed. Thereafter, the resist pattern 71 is removed.

Next, as thermal oxidation conditions, for example, temperature: about 800 ° C., pressure: normal pressure, O ₂ gas flow rate: about 1000 cm ³ / min (1000 sccm), H ₂ gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ As shown in FIG. 70, the thermal oxide film 3a grows in the peripheral circuit region RA by applying the thermal oxidation process (third time) for about 30 minutes at a gas flow rate of about 8900 cm ³ / min (8900 sccm). Thus, the thermal oxide film 4a is formed. On the other hand, in the memory cell region RB where the surface of the region of the semiconductor substrate 1 is exposed, the surface of the region of the semiconductor substrate 1 is oxidized to form the thermal oxide film 4b.

  In the third thermal oxidation process, thermal oxidation conditions are set so that the thermal oxide film 4b formed in the memory cell region RB has a desired film thickness. In FIG. 70, the dotted line shown in the peripheral circuit region RA represents the position of the interface between the thermal oxide film 3a before the thermal oxidation process and the surface of the region of the semiconductor substrate 1, and the dotted line shown in the memory cell region RB is The position of the surface of the area | region of the semiconductor substrate 1 before a thermal oxidation process is represented.

  By the second thermal oxidation process and the third thermal oxidation process, the step S between the peripheral circuit region RA and the memory cell region RB becomes about 11 nm. The value of the step S is sufficiently reduced as compared with the corresponding step of about 27 nm in the comparative example described above. Thus, in the peripheral circuit region RA, the thermal oxide film 4a is formed as the oxide film 9a that becomes the thicker gate oxide film. On the other hand, in the memory cell region RB, the thermal oxide film 4b is formed as an oxide film 9b that becomes the thinner gate oxide film.

  Thereafter, through the same steps as those shown in FIGS. 9 and 10, the silicon oxide film 16 is formed on the silicon nitride films 12a and 12b so as to fill the trenches 14a and 14b as shown in FIG. Is done. Next, as shown in FIG. 72, the silicon oxide film 16 is subjected to a chemical mechanical polishing process to remove the silicon oxide film 16 located on the upper surfaces of the silicon nitride films 12a and 12b. The upper surfaces of the films 12a and 12b are exposed. At this time, since the step S between the peripheral circuit region RA and the memory cell region RB is reduced as compared with the semiconductor device according to the comparative example, the silicon oxide film left unpolished in the memory cell region PB. 16 portion (polishing residue) is almost eliminated.

  Next, through a process similar to that shown in FIG. 13, as shown in FIG. 73, trench isolation region TA including silicon oxide film 16a filled in trench 14a is formed in peripheral circuit region RA, and the memory cell In the region RB, a trench isolation region TB including the silicon oxide film 16b filled in the trench 14b is formed.

  14 to 21, the gate electrode portion is patterned in the peripheral circuit region RA on the silicon nitride film 20 as shown in FIGS. 74 and 75, and the memory cell region RB. Then, a resist pattern 74 for patterning the gate electrode portion including the control gate electrode and the floating gate electrode is formed. Next, anisotropic etching is performed on the silicon nitride film 20 using the resist pattern 74 as a mask, thereby forming silicon nitride films 20a and 20b (see FIG. 77) as etching masks. Thereafter, the resist pattern 74 is removed.

  Next, anisotropic etching is performed on the polycide film 19, the ONO film 18 doped polysilicon films 17 a and 17 b, the polysilicon films 12 a and 12 b, etc. using the silicon nitride films 20 a and 20 b as a mask, so that FIGS. 76 and 77 are performed. As shown, the gate electrode portion 21 of the MOS transistor T1 is formed in the peripheral circuit region RA. The gate electrode portion 21 is constituted by a polysilicon film 11a, a doped polysilicon film 17a, and a polycide film 19a. Further, the doped polysilicon film 17a and the polycide film 19a are electrically connected through a portion where the ONO film 18 is removed.

  On the other hand, in memory cell region RB, gate electrode portion 24 including floating gate electrode portion 22 and control gate electrode portion 19b is formed. The floating gate electrode portion 22 is composed of the polysilicon film 11b and the doped polysilicon film 17b, and the control gate electrode 23 is composed of the polycide film 19b. Thus, the main part of the semiconductor device is formed.

  In the semiconductor device described above, the following effects can be obtained in addition to the effects obtained by the semiconductor device described above (Embodiment 1). That is, in the semiconductor device according to the present embodiment, nitrogen 50 is introduced so as not to reach the surface of semiconductor substrate 1 in the plasma nitriding process. Thereby, damage to the semiconductor substrate 1 can be reduced, and the reliability of the oxide films 4a and 4b serving as gate oxide films can be further improved.

Embodiment 4
In each of the above-described embodiments, the semiconductor device including two types of transistors having different gate oxide film thicknesses has been described. Next, a first example of a semiconductor device provided with three types of transistors having different gate oxide film thicknesses by applying a method for manufacturing two types of gate oxide films having different film thicknesses will be described. First, the manufacturing method will be described.

  As shown in FIG. 78, by performing a predetermined thermal oxidation process (first time), a thermal oxide film 2a is formed in the region RA1 (first region) in the peripheral circuit region RA of the semiconductor substrate 1, and the region RA2 ( A thermal oxide film 2b is formed in the third region). On the other hand, the thermal oxide film 2b is formed in the memory cell region RB (second region). The thermal oxide films 2a, 2b, and 2c have a thickness of about 15 nm. Peripheral circuit region RA indicates a region other than memory cell region RB. In this case, region RA1 is a region where, for example, a high breakdown voltage MOS transistor is formed, and region RA2 is a region where, for example, a low breakdown voltage MOS transistor is formed. It is said. 78 represents the position of the surface of the region of the semiconductor substrate 1 before the thermal oxidation treatment.

  Next, by applying a photo resist (not shown) on the thermal oxide films 2a to 2c and performing a predetermined photoengraving process, as shown in FIG. 79, the thermal oxide film 2a located in the peripheral circuit region RA is obtained. , 2c is formed. By performing predetermined etching using resist pattern 70 as a mask, as shown in FIG. 80, thermal oxide film 2b exposed in memory cell region RB is removed. Thereafter, the resist pattern 70 is removed.

Next, a plasma nitriding process (first time) is performed on the semiconductor substrate 1. As the nitriding conditions, for example, stage temperature: about 400 ° C., pressure: about 6.67 Pa, RF power: about 1.5 kW, Ar gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ gas flow rate: about 40 cm ³ Nitrogen plasma is generated under the condition of / min (40 sccm). Then, by exposing the semiconductor substrate 1 to the generated plasma for about 15 seconds, nitrogen (nitrogen atoms) 50 are introduced into the thermal oxide films 2a and 2c in the peripheral circuit region RA, as shown in FIG. In memory cell region RB, nitrogen (nitrogen atoms) 50 is introduced into the surface of the exposed region of semiconductor substrate 1. Thereby, silicon is nitrided and a nitride layer is formed on the surface of the region of the semiconductor substrate 1 in the memory cell region RB. The conditions for this plasma nitriding treatment (first time) are that the thermal oxide film formed in the memory cell region RB is desired as a gate oxide film by the second plasma nitriding treatment described later and the second thermal oxidation treatment. The film thickness is set to be.

  Next, a photoresist (not shown) is applied on the thermal oxide films 2a to 2c and subjected to a predetermined photoengraving process, so that it is located in the region RA1 in the peripheral circuit region RA as shown in FIG. A resist pattern 71 is formed to cover the thermal oxide film 2a. By performing predetermined etching using resist pattern 71 as a mask, thermal oxide film 2c exposed in region RA2 in peripheral circuit region RA is removed as shown in FIG. At this time, the nitrogen 50 introduced into the thermal oxide film 2c is also removed together with the thermal oxide film 2c. Thereafter, the resist pattern 71 is removed.

Next, a plasma nitriding process (second time) is performed on the semiconductor substrate 1. As the nitriding conditions, for example, stage temperature: about 400 ° C., pressure: about 6.67 Pa, RF power: about 1.5 kW, Ar gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ gas flow rate: about 40 cm ³ Nitrogen plasma is generated under the condition of / min (40 sccm). Then, by exposing the semiconductor substrate 1 to the generated plasma for about 15 seconds, as shown in FIG. 84, nitrogen (nitrogen atoms) 50 is introduced into the thermal oxide film 2a in the region RA1 of the peripheral circuit region RA, In the region RA2, nitrogen (nitrogen atoms) 50 is introduced into the surface of the exposed region of the semiconductor substrate 1. On the other hand, in the memory cell region RB, nitrogen (nitrogen atoms) 50 is introduced into the surface of the exposed region of the semiconductor substrate 1.

  Thereby, silicon is nitrided and a nitride layer is formed on the surface of the region of the semiconductor substrate 1 in the region RA2. In addition, in addition to the nitride layer formed by the first plasma nitriding process, a thicker nitride layer is formed by further nitriding silicon on the surface of the region of the semiconductor substrate 1 in the memory cell region RB. Become. The conditions for this plasma nitridation process (second time) are that the thermal oxide film formed in the region RA2 in the peripheral circuit region RA is a desired film thickness as a gate oxide film by a second thermal oxidation process described later. Is set to be

Next, as shown in FIG. 85, the thermal oxide film 2a exposed in the region RA1 is removed by performing predetermined etching. Next, as thermal oxidation conditions, for example, temperature: about 850 ° C., pressure: normal pressure, O ₂ gas flow rate: about 5500 cm ³ / min (5500 sccm), H ₂ gas flow rate: about 9900 cm ³ / min (9900 sccm) Then, by performing the thermal oxidation process (second time) for about 17 minutes and 30 seconds, as shown in FIG. 86, the surface of the exposed region of the semiconductor substrate 1 in the region RA1 in the peripheral circuit region RA is oxidized and heat is applied. Oxide film 3a is formed, and thermal oxide film 3c is formed in region RA2. On the other hand, a thermal oxide film 3b is formed in the memory cell region RB.

  At this time, a nitride layer is formed on the surface of the region of the semiconductor substrate 1 exposed in the region RA2, and a thicker nitride layer is formed on the surface of the region of the semiconductor substrate 1 exposed in the memory cell region RB. In the memory cell region RB, the surface oxidation of the region of the semiconductor substrate 1 is suppressed with respect to the region RA2. Thereby, the thermal oxide film 3b formed in the memory cell region RB is thinner than the thermal oxide film 3c formed in the region RA2. On the other hand, since no nitride layer is formed on the surface of the region of the semiconductor substrate 1 exposed in the region RA1, the thermal oxide film 3a formed in the region RA1 includes the region RA2 in which the nitride layer is formed and the memory cell region RB. It becomes thicker than the thermal oxide films 3c and 3b formed respectively. The conditions for the thermal oxidation process (second time) are set so that the thermal oxide film formed in the region RA1 of the peripheral circuit region RA has a desired thickness as a gate oxide film.

  The thickness of the thermal oxide film 3a thus formed is, for example, about 30 nm, the thickness of the thermal oxide film 3b is about 5 nm, and the thickness of the thermal oxide film 3c is about 10 nm. The step S between the thickest thermal oxide film 3a and the thinnest thermal oxide film 3b is about 13 nm. Thus, in the peripheral circuit region RA, in the region RA1, the thermal oxide film 3a is formed as the oxide film 9a that becomes the gate oxide film of the high breakdown voltage MOS transistor, and in the region RA2, the thermal oxide film 3c is formed as the gate oxide film of the low breakdown voltage MOS transistor. Is formed as an oxide film 9c. On the other hand, in the memory cell region RB, the thermal oxide film 3b is formed as an oxide film 9b that becomes a gate oxide film of the memory cell transistor. In FIG. 86, dotted lines respectively shown in region RA1, region RA2, and memory cell region RB represent the position of the surface of the region of semiconductor substrate 1 before the thermal oxidation process.

  Thereafter, through steps similar to those shown in FIGS. 9 and 10, the silicon oxide film 16 is formed on the silicon nitride films 12a to 12c so as to fill the trenches 14a to 14c, as shown in FIG. Is done. Next, as shown in FIG. 88, the silicon oxide film 16 is subjected to chemical mechanical polishing to remove the silicon oxide film 16 located on the upper surfaces of the silicon nitride films 12a to 12c. The upper surfaces of the films 12a to 12c are exposed. At this time, since the step between the peripheral circuit region RA and the memory cell region RB is reduced as compared with the case of a semiconductor device according to a comparative example to be described later, the silicon oxide that is left unpolished in the memory cell region PB. The film 16 portion (polishing residue) is almost eliminated.

  Next, through a process similar to the process shown in FIG. 13, as shown in FIG. 89, trench isolation region TA including silicon oxide film 16a filled in trench 14a is formed in peripheral circuit region RA, and A trench isolation region TC including the silicon oxide film 16c filled in the trench 14c is formed. On the other hand, in the memory cell region RB, a trench isolation region TB including the silicon oxide film 16b filled in the trench 14b is formed.

  Thereafter, the same steps as those shown in FIGS. 14 to 21 are performed. As shown in FIGS. 90 and 91, the gate electrode portion is patterned in the peripheral circuit region RA on the silicon nitride film 20 to form the memory cell region RB. Then, a resist pattern 74 for patterning the gate electrode portion including the control gate electrode and the floating gate electrode is formed. Next, anisotropic etching is performed on the silicon nitride film 20 using the resist pattern 74 as a mask, thereby forming silicon nitride films 20a to 20c (see FIG. 93) as etching masks. Thereafter, the resist pattern 74 is removed.

  Next, anisotropic etching is performed on the polycide film 19, the ONO film 18, the doped polysilicon films 17a to 17c, the polysilicon films 11a to 11c, and the like using the silicon nitride films 20a and 20b as masks, so that FIGS. As shown, in the peripheral circuit region RA, the gate electrode portion 21 of the high voltage MOS transistor T1 is formed in the region RA1, and the gate electrode portion 25 of the low voltage MOS transistor T3 is formed in the region RA2. The gate electrode portion 21 is constituted by the polysilicon film 11a, the doped polysilicon film 17a and the polycide film 19a, and the gate electrode portion 25 is constituted by the polysilicon film 11c, the doped polysilicon film 17c and the polycide film 19c. . The doped polysilicon films 17a and 17c and the polycide films 19a and 19c are electrically connected to each other through the portion from which the ONO film 18 is removed.

  On the other hand, in the memory cell region RB, the gate electrode portion 24 of the memory cell transistor T2 including the floating gate electrode portion 22 and the control gate electrode 23 is formed. The floating gate electrode portion 22 is composed of a polysilicon film 11c and a doped polysilicon film 17b, and the control gate electrode portion 19b is composed of a polycide film 19b. Thus, the main part of the semiconductor device is formed. In the semiconductor device according to the present embodiment, thermal oxidation treatment is performed on region RA1 that has not been subjected to plasma nitriding, region RA2 that has been subjected to plasma nitriding once, and region RB that has been subjected to plasma nitriding twice. The point is that the thermal oxide films 3a to 3c having different film thicknesses are formed by applying.

(Comparative example)
Next, the effect of the semiconductor device described above will be described in relation to a comparative example. First, a method for manufacturing a semiconductor device according to the comparative example will be described.

  As shown in FIG. 94, by performing thermal oxidation (first time), thermal oxide films 102a and 102c are formed in the peripheral circuit region RA on the main surface of the semiconductor substrate 101, and thermal oxide films are formed in the memory cell region RB. 102b is formed. In FIG. 94, dotted lines respectively shown in regions RA1, RA2, and RB indicate the position of the surface of the region of the semiconductor substrate 1 before the thermal oxidation process. Next, by performing a predetermined photoengraving process on the surfaces of the thermal oxide films 102a to 102c, as shown in FIG. 95, a resist pattern 170 covering the thermal oxide film 102a located in the area RA1 in the peripheral circuit area RA is formed. It is formed.

  By performing predetermined etching using resist pattern 170 as a mask, thermal oxide film 102c exposed in region RA2 in peripheral circuit region RA is removed and memory cell region RB is removed as shown in FIG. The exposed thermal oxide film 102b is removed. Thereafter, the resist pattern 170 is removed.

  Next, as shown in FIG. 97, by performing a predetermined thermal oxidation process (second time), the thermal oxide film 103a is formed in the region RA1 of the peripheral circuit region RA, and the thermal oxide film 103c in the region RA2. Is formed. On the other hand, in the memory cell region RB, a thermal oxide film 103b having a film thickness almost the same as that of the thermal oxide film 103c is formed. In FIG. 97, the dotted line shown in region RA1 represents the position of the interface between the thermal oxide film 102a before the thermal oxidation treatment and the surface of the semiconductor substrate 1 region. On the other hand, the dotted lines shown in region RA2 and region RB represent the position of the surface of the region of semiconductor substrate 1 before the thermal oxidation treatment.

  Next, by performing a predetermined photoengraving process on the surfaces of the thermal oxide films 103a to 103c, as shown in FIG. 98, the thermal oxide film 103a located in the region RA1 of the peripheral circuit region RA and the heat located in the region RA2 are processed. Resist patterns 171 covering oxide films 103c are formed. By performing predetermined etching using resist pattern 171 as a mask, as shown in FIG. 99, thermal oxide film 103b exposed in memory cell region RB is removed. Thereafter, the resist pattern 171 is removed.

  Next, as shown in FIG. 100, by performing a predetermined thermal oxidation process (third time), the thermal oxide film 104a is formed in the region RA1 of the peripheral circuit region RA and the thermal oxide film 104a in the region RA2. A thermal oxide film 104c thinner than the film thickness of is formed. On the other hand, a thermal oxide film 104b thinner than the thermal oxide film 104c is formed in the memory cell region RB.

  This thermal oxide film 104a is formed as an oxide film 109a that becomes the gate oxide film of the high voltage MOS transistor, and the thermal oxide film 104c is formed as an oxide film 109c that becomes the gate oxide film of the low voltage MOS transistor. On the other hand, the thermal oxide film 103b is formed as an oxide film 109b which becomes a gate oxide film of the memory cell transistor. Thus, the oxide film 9a is formed to a desired film thickness by three thermal oxidation processes, and the oxide film 9c is formed to a desired film thickness by two thermal oxidation processes. On the other hand, the oxide film 9b is formed in a desired film thickness by one thermal oxidation process.

  In particular, the oxide film 109a located in the region RA1 in the peripheral circuit region RA is removed by the thermal oxide film 102a formed by the first thermal oxidation process and the thermal oxide film 103a formed by the second thermal oxidation process. Instead, the thermal oxide film 104a having a desired film thickness is formed in the third thermal oxidation process. Therefore, the region thermally oxidized downward from the surface of the region of the semiconductor substrate 101 located in the region RA1 has a desired film thickness in the third thermal oxidation process after removing the thermal oxide film 102a and the thermal oxide film 103a. Compared with the case where the thermal oxide film 104a is formed, it is shallow.

  Therefore, even if the oxide films 109a to 109c have substantially the same thickness as the oxide films 9a to 9c of the semiconductor device according to the present embodiment, the region RA1 in which the oxide film 109a is formed A step (absolute step) SS with respect to the memory cell region RB where the oxide film 109b is formed is larger than that of the semiconductor device according to the present embodiment.

  Thereafter, through steps similar to those shown in FIGS. 9 and 10, the silicon oxide film 116 is formed on the silicon nitride films 112a to 112c so as to fill the trenches 114a to 114c as shown in FIG. Is done. Next, as shown in FIG. 102, the silicon oxide film 116 is subjected to chemical mechanical polishing to remove the silicon oxide film 116 located on the upper surfaces of the silicon nitride films 112a to 112c. The upper surfaces of the films 112a to 112c are exposed.

  At this time, in the region RA1 having a relatively high level difference, the portion of the silicon oxide film 116 located on the upper surface of the silicon nitride film 112a is removed, and the upper surface of the silicon nitride film 112a is exposed. On the other hand, in the memory cell region RB having a relatively low level difference, a portion of the silicon oxide film 116 located on the upper surface of the silicon nitride film 112b is not completely removed, and a polishing residue of the silicon oxide film 116 is generated. is there.

  Next, through a process similar to the process shown in FIG. 13, as shown in FIG. 103, in the peripheral circuit region RA, the trench isolation region TA including the silicon oxide film 116a filled in the trench 114a is formed. A trench isolation region TC including the silicon oxide film 116c filled in the trench 114c is formed. On the other hand, in the memory cell region RB, a trench isolation region TB including the silicon oxide film 116b filled in the trench 114b is formed.

  Here, in the region RA2 and the memory cell region RB, since the silicon oxide film 116 was not completely removed by the chemical mechanical polishing process, the heights of the trench isolation regions TC and TB from the upper surfaces of the polysilicon films 111c and 111b are increased. However, the height of the trench isolation region TA in the region RA1 is higher than the height from the upper surface of the polysilicon film 111a.

  Thereafter, the same steps as those shown in FIGS. 14 to 21 are performed. As shown in FIGS. 104 and 105, on the silicon nitride film 120, the gate electrode portion in each of the regions RA1 and RA2 in the peripheral circuit region RA. In the memory cell region RB, a resist pattern 174 for patterning the gate electrode portion including the control gate electrode portion and the floating gate electrode portion is formed. Next, anisotropic etching is performed on the silicon nitride film 120 using the resist pattern 174 as a mask, so that silicon nitride films 120a to 120c (see FIG. 107) as etching masks are formed. Thereafter, the resist pattern 174 is removed.

  Next, anisotropic etching is performed on the polycide film 119, the ONO film 118 doped polysilicon films 117a to 117c, the polysilicon films 111a to 111c, and the like using the silicon nitride films 120a to 120c as a mask, so that FIGS. As shown in FIG. 5, in the peripheral circuit region RA, the gate electrode portion 121 of the high voltage MOS transistor T1 is formed in the region RA1, and the gate electrode portion 125 of the low voltage MOS transistor T3 is formed in the region RA2. The gate electrode part 121 is constituted by a polysilicon film 111a, a doped polysilicon film 117a and a polycide film 119a, and the gate electrode part 125 is constituted by a polysilicon film 111c, a doped polysilicon film 117c and a polycide film 119c. . The doped polysilicon films 117a and 117c and the polycide films 119a and 119c are electrically connected to each other through the portion from which the ONO film 118 is removed.

  On the other hand, in the memory cell region RB, the gate electrode portion 124 of the memory cell transistor T2 including the floating gate electrode portion 122 and the control gate electrode portion 123 is formed. The floating gate electrode portion 122 is constituted by a polysilicon film 111b and a doped polysilicon film 117b, and the control gate electrode portion 123 is constituted by a polycide film 119b. Thus, the main part of the semiconductor device according to the comparative example is formed.

  In the semiconductor device according to the comparative example described above, in the state where the thermal oxide films 104a to 104c are formed as the oxide films 109a to 109c to be the gate oxide films, the region RA1 in the peripheral circuit region RA and the memory cell region RB The step SS is larger than the corresponding step S in the semiconductor device according to the present embodiment. Therefore, when the chemical mechanical polishing process is performed on the silicon oxide film 116 filling the trenches 114a to 114c, in the memory cell region RB having a relatively low level difference, the silicon oxide film 116 positioned on the upper surface of the silicon nitride film 112b. This portion may not be completely removed, and a polishing residue of the silicon oxide film 116 may be generated.

  Then, as already described, the doped polysilicon film 111b located immediately under the residue of the silicon nitride film remains without being removed, and the remaining portion of the doped polysilicon film 111b is electrically Short circuit may occur. Further, a residue such as the silicon oxide film 116 that is left without being removed becomes a foreign substance, which is one of the causes of the defect of the semiconductor device.

  In the region RA2 and the memory cell region RB, the height of the trench isolation region is higher than that in the region RA1. Therefore, when the polysilicon film is patterned, a residue of the polysilicon film is formed on the side surface of the portion protruding above the trench isolation regions TB and TC, which may cause a short circuit.

  In the semiconductor device according to the comparative example, defocusing occurs particularly in photolithography when the gate electrode portion is patterned due to the step SS between the region RA1 in the peripheral circuit region RA and the memory cell region RB. Sometimes. Therefore, for example, as shown in FIG. 105, a resist pattern 274 having a dimension different from the desired resist pattern 174 is formed, and as shown in FIG. 107, gate electrode portions 224 and 225 having a dimension different from the predetermined dimension are formed. Thus, the desired gate electrode portions 124 and 125 may not be formed.

  In contrast, in the semiconductor device according to the present embodiment, in the state where thermal oxide films 3a to 3c are formed as oxide films 9a to 9c to be gate oxide films, region RA1 in peripheral circuit region RA and the memory are particularly formed. The step S with respect to the cell region RB is about 13 nm, which is sufficiently reduced as compared with the step of the semiconductor device according to the comparative example.

  Thereby, when the silicon oxide film 16 filling the trenches 14a to 14c is subjected to the chemical mechanical polishing process, the residue of the silicon oxide film 16 is suppressed, and the residue of the silicon oxide film 16 is generated. An electrical short circuit like the semiconductor device according to the comparative example can be prevented. Further, residues that become foreign matters are reduced, so that defects in the semiconductor device can be reduced.

  Further, in the semiconductor device according to the comparative example, the bottom of the trench isolation region TA formed in the region RA1 in the peripheral circuit region RA and the bottom of the trench isolation region TB formed in the memory cell region RB are interfaces 110a and 110b. Corresponding to the position (height) relationship, the bottom of the trench isolation region TA is shallower than the bottom of the wrench isolation region TB or is located at substantially the same position (height). Therefore, there is a possibility that the margin of isolation breakdown voltage between the region RA1 of the peripheral circuit region RA where the high voltage MOS transistor is formed and the memory cell region RB where the memory cell transistor is formed is low.

  In contrast, in the semiconductor device according to the present embodiment, the interface 10a between the thermal oxide film 3a in the region RA1 of the peripheral circuit region RA and the surface of the region of the semiconductor substrate 1 is the thermal oxide film 3b in the memory cell region RB. The trench isolation region TA formed in the region RA1 is located at the bottom of the trench isolation region TB formed in the memory cell region RB by being positioned deeper than the interface 10b between the semiconductor substrate 1 and the surface of the semiconductor substrate 1 region. It will be located deeper than.

  Thereby, as compared with the semiconductor device according to the comparative example, the isolation breakdown voltage between the region RA1 in the peripheral circuit region RA to which a higher voltage is applied and the memory cell region RB to which a lower voltage is applied can be improved. .

  Further, in the semiconductor device according to the comparative example, the oxide film 109a in the region RA1 in the peripheral circuit region RA is formed by three thermal oxidation processes, and the oxide film 109c in the region RA2 is formed by two thermal oxidation processes. The oxide film 109b in the memory cell region RB is formed by one thermal oxidation process. In particular, in forming the oxide film 109a, first, a resist pattern is formed on the surface of the thermal oxide film 103a formed by the first thermal oxidation process, and the thermal oxide film 102 and the memory cell region formed in the region RA2. The thermal oxide film 102b formed on the RB is removed by wet etching. Then, a resist pattern is formed on the surface of the thermal oxide film 104a formed by the second thermal oxidation process, and the thermal oxide film 104b formed in the memory cell region RB is removed. Therefore, the oxide film 109a may be contaminated with a resist or an etching solution, and the reliability of the oxide film 109a as a gate oxide film may be impaired.

  In contrast, in the semiconductor device according to the present embodiment, oxide film 9a in region RA1, oxide film 9c in region RA2, and oxide film 9b in memory cell region RB in peripheral circuit region RA are subjected to two plasma nitriding processes. In this case, both are formed by the second thermal oxidation treatment, and the thermal oxidation treatment is formed by one thermal oxidation treatment. Thereby, the formation of the thermal oxide film to be the gate oxide film is simplified, the reliability of the gate oxide film can be ensured, and the amount of heat acting on the semiconductor device can be reduced.

  Furthermore, in the formation of the oxide film 9a in the region RA1 in the peripheral circuit region RA, the thermal oxide film 3a formed by the first thermal oxidation process and covered with the resist pattern 70 is removed, and the oxide film 9c in the region RA2 is formed. Also, the thermal oxide film 3c formed by the first thermal oxidation process and covered with the resist pattern 70 is removed. As a result, there is no risk of contamination of the oxide films 9a and 9c including the oxide film 9b by the resist and the etching solution, and the reliability of the oxide films 9a and 9c serving as the gate oxide films as compared with the semiconductor device according to the comparative example. Can be improved.

Embodiment 5
Next, a second example of a semiconductor device provided with three types of transistors having different gate oxide film thicknesses will be described. First, the manufacturing method will be described. As thermal oxidation conditions, for example, temperature: about 800 ° C., pressure: normal pressure, O ₂ gas flow rate: about 1000 cm ³ / min (1000 sccm), H ₂ gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ gas flow rate: As shown in FIG. 108, the thermal oxide film 2a is formed in the region RA1 of the peripheral circuit region RA by performing the thermal oxidation process (first time) for about 30 minutes at about 8900 cm ³ / min (8900 sccm). Then, a thermal oxide film 2c is formed in the region RA2. On the other hand, thermal oxide film 2b is formed in memory cell region RB. This thermal oxidation process is performed under the condition that the film thickness of the thermal oxide film formed in the region RA2 of the peripheral circuit region RA is a predetermined value as a gate oxide film by a plasma nitridation process described later and a second thermal oxidation process. The film thickness is set. In FIG. 108, dotted lines respectively shown in regions RA1 and RA2 and memory cell region RB represent the position of the surface of the region of semiconductor substrate 1 before the thermal oxidation treatment.

  Next, by applying a photoresist (not shown) on the thermal oxide films 2a to 2c and performing a predetermined photoengraving process, as shown in FIG. 109, the thermal oxide film 2a located in the peripheral circuit region RA. , 2c is formed. By performing predetermined etching using resist pattern 70 as a mask, thermal oxide film 2b exposed in memory cell region RB is removed as shown in FIG. Thereafter, the resist pattern 70 is removed.

Next, a plasma nitridation process is performed on the semiconductor substrate 1. As the nitriding conditions, for example, stage temperature: about 400 ° C., pressure: about 6.67 Pa, RF power: about 1.5 kW, Ar gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ gas flow rate: about 40 cm ³ Nitrogen plasma is generated under the condition of / min (40 sccm). Then, by exposing the semiconductor substrate 1 to the generated plasma for about 30 seconds, nitrogen (nitrogen atoms) 50 are introduced into the thermal oxide films 2a and 2c in the peripheral circuit region RA, as shown in FIG. In memory cell region RB, nitrogen (nitrogen atoms) 50 is introduced into the surface of the exposed region of semiconductor substrate 1.

  At this time, in the regions RA1 and RA2 of the peripheral circuit region RA, the nitrogen 50 stays in the thermal oxide films 2a and 2c and does not reach the interface between the thermal oxide film 2a and 2c and the surface of the semiconductor substrate 1 region. The surface of the region of the semiconductor substrate 1 is not nitrided. On the other hand, nitrogen is introduced into the surface of the region of the semiconductor substrate 1 exposed in the memory cell region RB, so that silicon is nitrided to form a nitride layer. The conditions for this plasma nitriding process are set so that the thermal oxide film formed in the memory cell region RB has a desired thickness as a gate oxide film by a second thermal oxidation process described later.

  Next, a photoresist (not shown) is applied on the thermal oxide films 2a to 2c and subjected to a predetermined photoengraving process, thereby positioning the region RA2 in the peripheral circuit region RA as shown in FIG. A resist pattern 71 is formed to cover the thermal oxide film 2c. By performing predetermined etching using resist pattern 71 as a mask, thermal oxide film 2a exposed in region RA1 in peripheral circuit region RA is removed as shown in FIG. At this time, the nitrogen 50 introduced into the thermal oxide film 2a is also removed together with the thermal oxide film 2a. On the other hand, in the memory cell region RB, since the nitrogen 50 is strongly bonded to silicon in the semiconductor substrate 1, the nitrogen 50 is not removed. Thereafter, the resist pattern 71 is removed.

Next, as thermal oxidation conditions, for example, temperature: about 850 ° C., pressure: normal pressure, O ₂ gas flow rate: about 5500 cm ³ / min (5500 sccm), H ₂ gas flow rate: about 9900 cm ³ / min (9900 sccm) As shown in FIG. 114, the thermal oxidation process (second time) is performed for about 17 minutes and 30 seconds, so that the thermal oxide film 3a is formed in the region RA1 and the thermal oxide film in the region RA2 as shown in FIG. 3c is formed. On the other hand, a thermal oxide film 3b is formed in the memory cell region RB.

  At this time, since nitrogen 50 is introduced into the region RA2 and the memory cell region RB, the surface oxidation of the regions of the respective semiconductor substrates 1 is suppressed. In the region RA2, nitrogen 50 is introduced into the thermal oxide film 2c, and in the memory cell region RB, a nitride layer is formed on the surface of the exposed region of the semiconductor substrate 1. As a result, the thermal oxide film 3c formed in the region RA2 is thicker than the thermal oxide film 3b formed in the memory cell region RB. On the other hand, since no nitride layer is formed on the surface of the region of the semiconductor substrate 1 exposed in the region RA1, the thermal oxide film 3a formed in the region RA1 includes the region RA2 into which nitrogen 50 is introduced and the memory cell region. It becomes thicker than the thermal oxide films 3c and 3b respectively formed on the RB. The conditions for the thermal oxidation process (second time) are set so that the thermal oxide film formed in the region RA1 of the peripheral circuit region RA has a desired thickness as a gate oxide film.

  The thickness of the thermal oxide film 3a thus formed is, for example, about 30 nm, the thickness of the thermal oxide film 3b is about 5 nm, and the thickness of the thermal oxide film 3c is about 10 nm. The step S between the thickest thermal oxide film 3a and the thinnest thermal oxide film 3b is about 13 nm. Thus, in the peripheral circuit region RA, in the region RA1, the thermal oxide film 3a is formed as the oxide film 9a that becomes the gate oxide film of the high breakdown voltage MOS transistor, and in the region RA2, the thermal oxide film 3c is formed as the gate oxide film of the low breakdown voltage MOS transistor. Is formed as an oxide film 9c. On the other hand, in the memory cell region RB, the thermal oxide film 3b is formed as an oxide film 9b that becomes a gate oxide film of the memory cell transistor. In FIG. 114, dotted lines respectively shown in the region RA1 and the memory cell region RB indicate the surface position of the region of the semiconductor substrate 1 before the thermal oxidation treatment, and a dotted line shown in the region RA2 is a thermal oxidation before the thermal oxidation treatment. The position of the interface between the film 2c and the surface of the region of the semiconductor substrate 1 is represented.

  Thereafter, the same process as that shown in FIGS. 9 and 10 is performed, and as shown in FIG. 115, silicon oxide film 16 is formed on silicon nitride films 12a-12c so as to fill trenches 14a-14c. Is done. Next, as shown in FIG. 116, the silicon oxide film 16 is subjected to a chemical mechanical polishing process to remove the silicon oxide film 16 located on the upper surfaces of the silicon nitride films 12a to 12c. The upper surfaces of the films 12a to 12c are exposed.

  Next, through a step similar to the step shown in FIG. 13, as shown in FIG. 117, in peripheral circuit region RA, trench isolation region TA including silicon oxide film 16a filled in trench 14a is formed, and A trench isolation region TC including the silicon oxide film 16c filled in the trench 14c is formed. On the other hand, in the memory cell region RB, a trench isolation region TB including the silicon oxide film 16b filled in the trench 14b is formed.

  14 to FIG. 21, the gate electrode portion is patterned in the peripheral circuit region RA on the silicon nitride film 20 as shown in FIGS. 118 and 119, and the memory cell region RB. Then, a resist pattern 74 for patterning the gate electrode portion including the control gate electrode portion and the floating gate electrode portion is formed. Next, anisotropic etching is performed on the silicon nitride film 20 using the resist pattern 74 as a mask, thereby forming silicon nitride films 20a to 20c (see FIG. 121) as etching masks. Thereafter, the resist pattern 74 is removed.

  Next, anisotropic etching is performed on the polycide film 19, the ONO film 18, the doped polysilicon films 17a to 17c, the polysilicon films 11a to 11c, and the like using the silicon nitride films 20a and 20b as a mask, so that FIGS. As shown, in the peripheral circuit region RA, the gate electrode portion 21 of the high voltage MOS transistor T1 is formed in the region RA1, and the gate electrode portion 25 of the low voltage MOS transistor T3 is formed in the region RA2. The gate electrode portion 21 is constituted by the polysilicon film 11a, the doped polysilicon film 17a and the polycide film 19a, and the gate electrode portion 25 is constituted by the polysilicon film 11c, the doped polysilicon film 17c and the polycide film 19c. . The doped polysilicon films 17a and 17c and the polycide films 19a and 19c are electrically connected to each other through the portion from which the ONO film 18 is removed.

  On the other hand, in the memory cell region RB, the gate electrode portion 24 of the memory cell transistor T2 including the floating gate electrode portion 22 and the control gate electrode portion 23 is formed. The floating gate electrode portion 22 is composed of a polysilicon film 11c and a doped polysilicon film 17b, and the control gate electrode portion 19b is composed of a polycide film 19b. Thus, the main part of the semiconductor device is formed.

  In the semiconductor device described above, the concentration of nitridation (degree of nitridation) varies depending on the number of plasma nitriding treatments, so that the region RA1 not subjected to plasma nitriding treatment, the region RA2 subjected to plasma nitriding treatment once, and the plasma By performing a predetermined thermal oxidation process (third time) on the region RB that has been subjected to the nitriding process twice, oxide films 9a to 9c having different film thicknesses are finally formed.

  On the other hand, in the semiconductor device according to the present embodiment, the region RA1 that has not been subjected to the plasma nitriding treatment, the region RA2 that has been subjected to the plasma nitriding treatment once on the oxide film 2c, and the surface of the region of the semiconductor substrate 1 are used. The point is that oxide films 9a to 9c having different film thicknesses are finally formed by performing a predetermined thermal oxidation process (second time) on the region RB to which the plasma nitriding process has been performed once. .

  That is, in the semiconductor device according to the present embodiment, in particular, the region RA2 and the memory cell region RB to be subjected to the plasma nitridation process are made different in oxidation resistance by the thermal oxidation process depending on the presence or absence of the oxide film. The film thickness of the oxide film 9c formed in the region RA2 with the oxide film 2c is made larger than the film thickness of the oxide film 9b formed in the memory cell region RB without the oxide film.

  As described above, in the semiconductor device according to the present embodiment, the region to be subjected to plasma nitriding (region RA2, memory cell region RB) and the region not to be subjected (region RA1) are formed, and the plasma nitriding is performed. Regarding the regions, by forming a region where the thermal oxide film is left (region RA2) and a region where the thermal oxide film is removed (memory cell region RB), the thickness of the oxide film finally formed in each region is increased. Have a difference.

  In the semiconductor device described above, the following effects can be obtained in addition to the effects obtained by the semiconductor device described above (Embodiment 4). That is, in the semiconductor device described above, the number of steps of plasma nitriding treatment can be reduced by one step compared to the semiconductor device described above, and the number of steps of removing the thermal oxide film can be reduced by one step, thereby reducing the number of steps. be able to.

Embodiment 6
Next, a third example of a semiconductor device provided with three types of transistors having different gate oxide film thicknesses will be described. First, the manufacturing method will be described. As shown in FIG. 122, by performing a predetermined thermal oxidation process (first time), thermal oxide film 2a is formed in region RA1 of peripheral circuit region RA of semiconductor substrate 1, and thermal oxide film 2b is formed in region RA2. It is formed. On the other hand, a thermal oxide film 2b is formed in memory cell region RB. The thermal oxide films 2a, 2b, and 2c have a thickness of about 15 nm. In particular, thermal oxide film 2a functions as a mask for region RA1 when plasma nitriding is performed. In FIG. 122, dotted lines respectively shown in region RA1, region RA2, and memory cell region RB represent the position of the surface of the region of semiconductor substrate 1 before the thermal oxidation process.

  Next, a photoresist (not shown) is applied on the thermal oxide films 2a, 2b, and 2c, and a predetermined photoengraving process is performed, so that a region RA1 in the peripheral circuit region RA is obtained as shown in FIG. A resist pattern 70 is formed so as to cover the thermal oxide film 2a located on the surface. By performing predetermined etching using resist pattern 70 as a mask, as shown in FIG. 124, thermal oxide film 2c exposed in region RA2 is removed and thermal oxidation exposed in memory cell region RB is removed. The film 2b is removed. Thereafter, the resist pattern 70 is removed.

Next, a plasma nitridation process is performed on the semiconductor substrate 1. As the nitriding conditions, for example, stage temperature: about 400 ° C., pressure: about 6.67 Pa, RF power: about 1.5 kW, Ar gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ gas flow rate: about 40 cm ³ Nitrogen plasma is generated under the condition of / min (40 sccm). Then, by exposing the semiconductor substrate 1 to the generated plasma for about 15 seconds, nitrogen (nitrogen atoms) 50 is introduced into the thermal oxide film 2a in the region RA1 of the peripheral circuit region RA as shown in FIG. At the same time, nitrogen (nitrogen atoms) 50 is introduced into the surface of the exposed region of the semiconductor substrate 1 in the region RA2. On the other hand, in the memory cell region RB, nitrogen (nitrogen atoms) 50 is introduced into the surface of the exposed region of the semiconductor substrate 1.

  At this time, in the region RA1 of the peripheral circuit region RA, the nitrogen 50 remains in the thermal oxide film 2a and does not reach the interface between the thermal oxide film 2a and the surface of the semiconductor substrate 1 region. The surface of the region is not nitrided. On the other hand, nitrogen is introduced into the surface of the region of the semiconductor substrate 1 exposed in each of the region RA2 and the memory cell region RB, so that silicon is nitrided to form a nitride layer. The conditions for this plasma nitriding process are that the thermal oxide film formed in the region RA2 of the peripheral circuit region RA is a desired film as a gate oxide film by the second and third thermal oxidation processes described later. It is set to be thick.

  Next, by performing predetermined etching, as shown in FIG. 126, thermal oxide film 2a exposed in region RA1 in peripheral circuit region RA is removed. At this time, the nitrogen 50 introduced into the thermal oxide film 2a is also removed together with the thermal oxide film 2a. On the other hand, in the region RA2 and the memory cell region RB, the nitrogen 50 is not removed because the nitrogen 50 is strongly bonded to the silicon in the semiconductor substrate 1.

Next, as thermal oxidation conditions, for example, temperature: about 850 ° C., pressure: normal pressure, O ₂ gas flow rate: about 5500 cm ³ / min (5500 sccm), H ₂ gas flow rate: about 9900 cm ³ / min (9900 sccm) Then, by performing the thermal oxidation process (second time) for about 15 minutes and 10 seconds, as shown in FIG. 127, in the peripheral circuit region RA, the thermal oxide film 3a is formed in the region RA1, and the thermal oxide film is formed in the region RA2. 3c is formed. On the other hand, a thermal oxide film 3b is formed in the memory cell region RB. In FIG. 127, dotted lines shown in regions RA1 and RA2 and memory cell region RB indicate the position of the surface of the region of semiconductor substrate 1 before the thermal oxidation treatment.

  Next, by applying a photoresist (not shown) on the thermal oxide films 3a to 3c and performing a predetermined photoengraving process, as shown in FIG. 128, the thermal oxide film 3a located in RA1 and the region RA2 A resist pattern 71 is formed so as to cover the thermal oxide film 3c located at the position. By performing predetermined etching using resist pattern 71 as a mask, thermal oxide film 3b exposed in memory cell region RB is removed as shown in FIG. At this time, the nitrogen 50 introduced into the thermal oxide film 3b is also removed together with the thermal oxide film 3b. Thereafter, the resist pattern 71 is removed.

Next, as thermal oxidation conditions, for example, temperature: about 800 ° C., pressure: normal pressure, O ₂ gas flow rate: about 1000 cm ³ / min (1000 sccm), H ₂ gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ As shown in FIG. 130, by performing thermal oxidation treatment (third time) for about 30 minutes under a gas flow rate of about 8900 cm ³ / min (8900 sccm), thermal oxidation is performed in the region RA1 in the peripheral circuit region RA. A film 4a is formed, and a thermal oxide film 4c is formed in the region RA2. On the other hand, a thermal oxide film 4b is formed in the memory cell region RB.

  At this time, in the memory cell region RB, the exposed surface of the semiconductor substrate 1 is oxidized to form a thermal oxide film 4b having a desired thickness. In the region RA2 of the peripheral circuit region RA, the thermal oxidation is suppressed by introducing nitrogen 50 into the thermal oxide film 3c, and the film thickness is smaller than that in the case where nitrogen is not introduced, and the thermal oxide film 4b. A thicker thermal oxide film 4c is formed. In the region RA1, the thermal oxide film 3c into which nitrogen is not introduced grows by thermal oxidation, and a thermal oxide film 4a thicker than the thermal oxide film 4c is formed. The conditions for this thermal oxidation treatment (third time) are set so that the thermal oxide film formed in the memory cell region RB has a desired thickness as a gate oxide film.

  The thickness of the thermal oxide film 4a formed in this way is, for example, about 30 nm, the thickness of the thermal oxide film 4b is about 5 nm, and the thickness of the thermal oxide film 4c is about 10 nm. In this case, the step S between the thickest thermal oxide film 4a and the thinnest thermal oxide film 4b is about 15 nm. Thus, in the peripheral circuit region RA, in the region RA1, the thermal oxide film 4a is formed as the oxide film 9a that becomes the gate oxide film of the high breakdown voltage MOS transistor, and in the region RA2, the thermal oxide film 4c is formed as the gate oxide film of the low breakdown voltage MOS transistor. Is formed as an oxide film 9c. On the other hand, in the memory cell region RB, the thermal oxide film 4b is formed as an oxide film 9b that becomes the gate oxide film of the memory cell transistor.

  In FIG. 130, the dotted line shown in the region RA1 represents the position of the interface between the thermal oxide film 3a before the thermal oxidation process and the surface of the region of the semiconductor substrate 1, and the dotted line shown in the region RA2 is the one before the thermal oxidation process. The position of the interface between the thermal oxide film 3c and the surface of the region of the semiconductor substrate 1 is represented. On the other hand, the dotted line of the memory cell region RB represents the position of the surface of the region of the semiconductor substrate 1 before the thermal oxidation treatment.

  Thereafter, through steps similar to those shown in FIGS. 9 to 22, the gate electrode portion 21 of the high voltage MOS transistor T1 is formed in the region RA1 in the peripheral circuit region RA as shown in FIGS. 131 and 132. Thus, the gate electrode portion 25 of the low breakdown voltage MOS transistor T3 is formed in the region RA2. The gate electrode portion 21 is constituted by the polysilicon film 11a, the doped polysilicon film 17a and the polycide film 19a, and the gate electrode portion 25 is constituted by the polysilicon film 11c, the doped polysilicon film 17c and the polycide film 19c. . The doped polysilicon films 17a and 17c and the polycide films 19a and 19c are electrically connected to each other through the portion from which the ONO film 18 is removed.

  On the other hand, in the memory cell region RB, the gate electrode portion 24 of the memory cell transistor T2 including the floating gate electrode portion 22 and the control gate electrode portion 23 is formed. The floating gate electrode portion 22 is composed of a polysilicon film 11c and a doped polysilicon film 17b, and the control gate electrode portion 23 is composed of a polycide film 19b. Thus, the main part of the semiconductor device is formed.

  In the semiconductor device described above, in the state where the thermal oxide films 4a to 4c are formed as the oxide films 9a to 9c to be the gate oxide films, in particular, the step between the region RA1 of the peripheral circuit region RA and the memory cell region RB is about 15 nm. Therefore, the step is sufficiently reduced as compared with the step of the semiconductor device according to the comparative example. As a result, similar to the semiconductor device (Embodiment 4) described above, the generation of a residue of the silicon oxide film 16 is suppressed when the chemical mechanical polishing process is performed on the silicon oxide film 16 filling the trenches 14a to 14c. Thus, it is possible to prevent an electrical short circuit like that in the semiconductor device according to the comparative example due to the generation of the residue of the silicon oxide film 16. Further, residues that become foreign matters are reduced, so that defects in the semiconductor device can be reduced. Furthermore, defocusing can be prevented from occurring in photolithography when patterning the gate electrode portion, and a desired gate electrode portion can be formed with high accuracy.

  Further, since the bottom of the trench isolation region TA formed in the region RA1 is located deeper than the bottom of the trench isolation region TB formed in the memory cell region RB, compared with the semiconductor device according to the comparative example. The isolation breakdown voltage between the region RA1 in the peripheral circuit region RA to which a higher voltage is applied and the memory cell region RB to which a lower voltage is applied can be improved.

  In the semiconductor device according to the present embodiment, the gate oxide film 9b in the memory cell region does not contain nitrogen. Therefore, the semiconductor device according to the present embodiment is particularly effective for a semiconductor device in which device characteristics such as reliability deteriorate due to the gate oxide film in the memory cell region containing nitrogen.

Embodiment 7
Next, a fourth example of a semiconductor device provided with three types of transistors having different gate oxide film thicknesses will be described. First, the manufacturing method will be described. As thermal oxidation conditions, for example, temperature: about 800 ° C., pressure: normal pressure, O ₂ gas flow rate: about 1000 cm ³ / min (1000 sccm), H ₂ gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ gas flow rate: By performing thermal oxidation treatment (first time) for about 30 minutes at about 8900 cm ³ / min (8900 sccm), as shown in FIG. 133, in the region RA1, the thermal oxide film 2a is formed in the region RA1. The thermal oxide film 2c is formed in the region RA2. On the other hand, thermal oxide film 2b is formed in memory cell region RB. In FIG. 133, dotted lines respectively shown in regions RA1 and RA2 and memory cell region RAB represent the position of the surface of the region of semiconductor substrate 1 before the thermal oxidation treatment.

Next, a plasma nitridation process is performed on the semiconductor substrate 1. As the nitriding conditions, for example, stage temperature: about 400 ° C., pressure: about 6.67 Pa, RF power: about 1.5 kW, Ar gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ gas flow rate: about 40 cm ³ Nitrogen plasma is generated under the condition of / min (40 sccm). Then, by exposing the semiconductor substrate 1 to the generated plasma for about 30 seconds, as shown in FIG. 134, nitrogen (nitrogen atoms) 50 is introduced into the thermal oxide film 2a in the region RA1 of the peripheral circuit region RA. At the same time, in the region RA2, nitrogen (nitrogen atoms) 50 is introduced into the thermal oxide film 2c. On the other hand, in the memory cell region RB, nitrogen (nitrogen atoms) 50 is introduced into the thermal oxide film 2b. The plasma nitriding process is performed in the region RA2 in the peripheral circuit region RA by performing the first thermal oxidation process and the third thermal oxidation process, which will be described later, the second and third thermal oxidation processes. The thermal oxide film is set to have a desired film thickness as a gate oxide film.

  Next, a photoresist (not shown) is applied on the thermal oxide films 2a to 2c and subjected to a predetermined photoengraving process, so that it is located in the region RA2 in the peripheral circuit region RA as shown in FIG. A resist pattern 70 is formed to cover the thermal oxide film 2c to be formed and to cover the thermal oxide film 2b located in the memory cell region RB. By performing predetermined etching using resist pattern 70 as a mask, thermal oxide film 2a exposed in region RA1 is removed as shown in FIG. Thereafter, the resist pattern 70 is removed.

Next, as thermal oxidation conditions, for example, temperature: about 850 ° C., pressure: normal pressure, O ₂ gas flow rate: about 5500 cm ³ / min (5500 sccm), H ₂ gas flow rate: about 9900 cm ³ / min (9900 sccm) Then, by performing the thermal oxidation process (second time) for about 15 minutes and 10 seconds, as shown in FIG. 137, in the peripheral circuit region RA, the thermal oxide film 3a is formed in the region RA1, and in the region RA2, the thermal oxide film is formed. 3c is formed. On the other hand, a thermal oxide film 3b is formed in the memory cell region RB.

  Next, by applying a photoresist (not shown) on the thermal oxide films 3a to 3c and performing a predetermined photoengraving process, as shown in FIG. 138, the thermal oxide film 3a and the area located in the area RA1 A resist pattern 71 is formed to cover the thermal oxide film 3c located at RA2. By performing predetermined etching using resist pattern 71 as a mask, as shown in FIG. 139, thermal oxide film 3b exposed in memory cell region RB is removed. Thereafter, the resist pattern 71 is removed.

Next, as thermal oxidation conditions, for example, temperature: about 800 ° C., pressure: normal pressure, O ₂ gas flow rate: about 1000 cm ³ / min (1000 sccm), H ₂ gas flow rate: about 1000 cm ³ / min (1000 sccm), N ₂ As shown in FIG. 140, by performing thermal oxidation treatment (third time) for about 30 minutes under a gas flow rate of about 8900 cm ³ / min (8900 sccm), thermal oxidation is performed in the region RA1 in the peripheral circuit region RA. A film 4a is formed, and a thermal oxide film 4c is formed in the region RA2. On the other hand, a thermal oxide film 4b is formed in the memory cell region RB.

  At this time, in the memory cell region RB, the exposed surface of the semiconductor substrate 1 is oxidized to form a thermal oxide film 4b having a desired thickness. In the region RA2 of the peripheral circuit region RA, the thermal oxidation is suppressed by introducing nitrogen 50 into the thermal oxide film 3c, and the film thickness is smaller than that in the case where nitrogen is not introduced, and the thermal oxide film 4b. A thicker thermal oxide film 4c is formed. In the region RA1, the thermal oxide film 3c into which nitrogen is not introduced grows by thermal oxidation, and a thermal oxide film 4a thicker than the thermal oxide film 4c is formed. The conditions for this thermal oxidation treatment (third time) are set so that the thermal oxide film formed in the memory cell region RB has a desired thickness as a gate oxide film.

  The thickness of the thermal oxide film 4a formed in this way is, for example, about 30 nm, the thickness of the thermal oxide film 4b is about 5 nm, and the thickness of the thermal oxide film 4c is about 10 nm. In this case, the step between the thickest thermal oxide film 4a and the thinnest thermal oxide film 4b is about 14 nm. Thus, in the peripheral circuit region RA, in the region RA1, the thermal oxide film 4a is formed as the oxide film 9a that becomes the gate oxide film of the high breakdown voltage MOS transistor, and in the region RA2, the thermal oxide film 4c is formed as the gate oxide film of the low breakdown voltage MOS transistor. Is formed as an oxide film 9c. On the other hand, in the memory cell region RB, the thermal oxide film 4b is formed as an oxide film 9b that becomes the gate oxide film of the memory cell transistor.

  Thereafter, through steps similar to those shown in FIGS. 9 to 22, the gate electrode portion 21 of the high voltage MOS transistor T1 is formed in the region RA1 in the peripheral circuit region RA as shown in FIGS. 141 and 142. Thus, the gate electrode portion 25 of the low breakdown voltage MOS transistor T3 is formed in the region RA2. The gate electrode portion 21 is constituted by the polysilicon film 11a, the doped polysilicon film 17a and the polycide film 19a, and the gate electrode portion 25 is constituted by the polysilicon film 11c, the doped polysilicon film 17c and the polycide film 19c. . The doped polysilicon films 17a and 17c and the polycide films 19a and 19c are electrically connected to each other through the portion from which the ONO film 18 is removed.

  On the other hand, in the memory cell region RB, the gate electrode portion 24 of the memory cell transistor T2 including the floating gate electrode portion 22 and the control gate electrode portion 23 is formed. The floating gate electrode portion 22 is composed of a polysilicon film 11c and a doped polysilicon film 17b, and the control gate electrode portion 23 is composed of a polycide film 19b. Thus, the main part of the semiconductor device is formed.

  In the semiconductor device described above, when the thermal oxide films 4a to 4c are formed as the gate oxide films 9a to 9c, in particular, the step between the region RA1 of the peripheral circuit region RA and the memory cell region RB is about 14 nm. The step is sufficiently reduced as compared with the step of the semiconductor device according to the example. As a result, similar to the semiconductor device (Embodiment 4) described above, the generation of a residue of the silicon oxide film 16 is suppressed when the chemical mechanical polishing process is performed on the silicon oxide film 16 filling the trenches 14a to 14c. Thus, an electrical short circuit such as that in the semiconductor device according to the comparative example caused by the residue of the silicon oxide film 16 can be prevented, and the residue that becomes a foreign substance is reduced, so that the defect of the semiconductor device is reduced. It can also be reduced. Furthermore, defocusing can be prevented from occurring in photolithography when patterning the gate electrode portion, and a desired gate electrode portion can be formed with high accuracy.

  Further, since the bottom of the trench isolation region TA formed in the region RA1 is located deeper than the bottom of the trench isolation region TB formed in the memory cell region RB, compared with the semiconductor device according to the comparative example. The isolation breakdown voltage between the region RA1 in the peripheral circuit region RA to which a higher voltage is applied and the memory cell region RB to which a lower voltage is applied can be improved.

  In the semiconductor device according to the present embodiment, the gate oxide film 9b in the memory cell region does not contain nitrogen. Therefore, the semiconductor device according to the present embodiment is particularly effective for a semiconductor device in which device characteristics such as reliability deteriorate due to the gate oxide film in the memory cell region containing nitrogen.

  In each of the above-described embodiments, the method of forming gate oxide films having different film thicknesses by utilizing the effect of suppressing thermal oxidation by plasma nitriding processing has been described. Here, as a summary, FIGS. 143 and 144 show the number of thermal oxidation processes for forming a gate oxide film of a transistor and the number of times that the gate oxide film is covered with a resist pattern, respectively.

  First, FIG. 143 shows the number of thermal oxidation treatments when two types of gate oxide films having different thicknesses are formed. First, in the case of the first embodiment, both are performed once in the peripheral circuit region RA and the memory cell region RB. In the case of the second embodiment, once in the peripheral circuit region RA and twice in the memory cell region RB. In the case of the third embodiment, it is twice in the peripheral circuit region RA and once in the memory cell region RB. On the other hand, in the comparative example, it is twice in the peripheral circuit area RA and once in the memory cell area RB.

  The number of times that the gate oxide film is covered with the resist pattern is also shown in FIG. First, in the case of the first embodiment, the number of times is zero in both the peripheral circuit region RA and the memory cell region RB. In the second embodiment, it is 0 in the peripheral circuit area RA and 1 in the memory cell area RB. In the case of the third embodiment, once in the peripheral circuit area RA and 0 in the memory cell area RB. On the other hand, in the comparative example, it is once in the peripheral circuit region RA and zero in the memory cell region RB.

  Next, FIG. 144 shows the number of thermal oxidation treatments when three types of gate oxide films having different thicknesses are formed. First, in the case of the fourth embodiment, each of the regions RA1, RA2 and memory cell region RB of the peripheral circuit region RA is performed once. In the case of the fifth embodiment, once in the region RA1 of the peripheral circuit region RA, twice in the region RA2, and once in the memory cell region RB. In the case of the sixth embodiment, both are performed twice in region RA1 and region RA2 of peripheral circuit region RA and once in memory cell region RB. In the case of the seventh embodiment, it is twice in the region RA1 of the peripheral circuit region RA, three times in the region RA2, and once in the memory cell region RB. On the other hand, in the comparative example, it is 3 times in the region RA1 of the peripheral circuit region RA, 3 times in the region RA2, and 1 time in the memory cell region RB.

  The number of times that the gate oxide film is covered with the resist pattern is also shown in FIG. In the case of the fourth embodiment, the number of times is zero in the region RA1, the region RA2 and the memory cell region RB of the peripheral circuit region RA. In the case of the fifth embodiment, the number of times is zero in the region RA1 of the peripheral circuit region RA, two times in the region RA2, and zero in the memory cell region RB. In the case of the sixth embodiment, the number of times is 1 in the region RA1 and the region RA2 of the peripheral circuit region RA, and 0 in the memory cell region RB. In the case of the seventh embodiment, once in the region RA1 of the peripheral circuit region RA, twice in the region RA2, and 0 in the memory cell region RB. On the other hand, in the comparative example, it is twice in the region RA1 of the peripheral circuit region RA, once in the region RA2, and zero in the memory cell region RB.

  In view of this result and the reliability as the gate oxide film, the number of times of the thermal oxidation treatment is the smallest, and the thermal oxide film is not covered with the resist pattern at all as described in the first and fourth embodiments. The method is considered desirable.

Embodiment 8
In each of the above-described embodiments, the method of forming gate oxide films having different film thicknesses by utilizing the effect of suppressing thermal oxidation by performing plasma nitriding treatment has been described. It is also possible to form gate oxide films having different thicknesses with reduced steps without performing plasma nitriding. Therefore, here, a method of forming two gate oxide films having different film thicknesses without performing plasma nitriding treatment will be described.

  First, as shown in FIG. 145, by performing a predetermined thermal oxidation process (first time), a thermal oxide film 2a is formed in the peripheral circuit region RA and a thermal oxide film 2b is formed in the memory cell region RB. . In FIG. 145, dotted lines shown in the peripheral circuit region RA and the memory cell region RB indicate the position of the surface of the region of the semiconductor substrate 1 before the thermal oxidation treatment.

  Next, by applying a photoresist (not shown) on the thermal oxide films 2a and 2b and applying a predetermined photoengraving process, as shown in FIG. 146, the thermal oxide film 2b located in the memory cell region RB is obtained. A resist pattern 70 is formed to cover the film. By performing predetermined etching using resist pattern 70 as a mask, as shown in FIG. 147, thermal oxide film 2a exposed in peripheral circuit region RA is removed. Thereafter, the resist pattern 70 is removed.

  Next, as shown in FIG. 148, by performing a predetermined thermal oxidation process (second time), a thermal oxide film 3a is formed on the surface of the region of the semiconductor substrate 1 exposed to the peripheral circuit region RA, and the memory cell. Thermal oxide film 2b located in region RB grows to form thermal oxide film 3b. In FIG. 148, the dotted line shown in the peripheral circuit region RA represents the position of the surface of the region of the semiconductor substrate 1 before performing the thermal oxidation process, and the dotted line shown in the memory cell region RB is before the thermal oxidation process. The position of the interface between the thermal oxide film 2b and the surface of the region of the semiconductor substrate 1 is represented.

  Next, by applying a photoresist (not shown) on the thermal oxide films 3a and 3b and performing a predetermined photoengraving process, as shown in FIG. 149, the thermal oxide film 3b located in the memory cell region RB. A resist pattern 71 is formed to cover the pattern. By performing predetermined etching using the resist pattern 71 as a mask, the thermal oxide film 3a exposed in the peripheral circuit region RA is removed as shown in the upper part of FIG. Thereafter, the resist pattern 71 is removed.

  Subsequently, a thermal oxide film (not shown) is formed on the surface of the region of the semiconductor substrate 1 exposed to the peripheral circuit region RA by performing a predetermined thermal oxidation process (third and subsequent times), and is positioned in the memory cell region RB. Forming a thermal oxide film (not shown) by growing the thermal oxide film 3b to be formed (step A), and then forming a resist pattern (not shown) covering the grown thermal oxide film in the memory cell region RB. Then, by repeating the step (step B) of removing the thermal oxide film formed on the surface of the region of the semiconductor substrate 1 exposed in the peripheral circuit region RA a predetermined number of times, as shown in the lower part of FIG. Then, a thermal oxide film 6a is formed on the surface of the region of the semiconductor substrate 1 exposed in the peripheral circuit region RA, and a thermal oxide film located in the memory cell region RB grows to form a thermal oxide film 6b.

  Next, by applying a photoresist (not shown) on the thermal oxide films 2a and 2b and performing a predetermined photoengraving process, as shown in FIG. 151, the thermal oxide film 6a located in the peripheral circuit region RA. A resist pattern 72 is formed to cover the pattern. By performing predetermined etching using resist pattern 72 as a mask, as shown in FIG. 152, thermal oxide film 6b exposed in memory cell region RB is removed. Thereafter, the resist pattern 72 is removed.

  Next, as shown in FIG. 153, a thermal oxide film 7a to be a gate oxide film 9a is formed on the surface of the region of the semiconductor substrate 1 exposed to the peripheral circuit region RA by performing a predetermined thermal oxidation process (final round). At the same time, a thermal oxide film 7b to be the gate oxide film 9b is formed on the surface of the region of the semiconductor substrate 1 exposed in the memory cell region RB. Thereafter, the main part of the semiconductor device shown in FIGS. 23 and 24 is formed through steps similar to those shown in FIGS. 8 to 23 described above.

  In the semiconductor device according to the above-described modification, the process A and the process B are repeated a predetermined number of times without performing the plasma nitridation process, whereby the thermal oxide film and the region of the semiconductor substrate 1 are separated in the peripheral circuit region RA. The position of the interface gradually becomes lower than the position of the interface between the thermal oxide film formed in the memory cell region RB and the region of the semiconductor substrate 1. Thereby, the position of the upper surface of the thick gate oxide film 9a formed in the peripheral circuit region RA and the position of the upper surface of the thin gate oxide film 9b formed in the memory cell region are substantially the same position (high Is).

  That is, the thermal oxidation (first region thermal oxidation) by the thermal oxidation process in the region of the semiconductor substrate 1 located in the peripheral circuit region RA (first region) is converted into the semiconductor substrate 1 located in the memory cell region RB (second region). The oxide film 9a (first oxide film) and the region of the semiconductor substrate 1 located immediately below the oxide film 9a are advanced to a region deeper than thermal oxidation (second region thermal oxidation) by thermal oxidation treatment in the region of The interface 10a (first interface) with the surface of the semiconductor substrate 1 is an interface 10b (the second oxide film) thinner than the oxide film 9a and the surface of the region of the semiconductor substrate 1 located immediately below the oxide film 9b ( It is formed at a position deeper than the second interface. As a result, the position of the upper surface of the oxide film 9a and the position of the upper surface of the oxide film 9b thinner than the oxide film 9a approach the same position, and the peripheral circuit region RA and the memory cell region RB The level difference is greatly reduced. As a result, as described in the first embodiment, it is possible to obtain the effects of reducing the residue of the silicon oxide film, reducing the defocus, and improving the isolation breakdown voltage.

  In each of the above-described embodiments, the flash memory including the memory cell transistor is described as an example of the semiconductor device. However, the manufacturing method described above is not limited to the flash memory, and includes transistors having different gate oxide film thicknesses. The present invention can be widely applied to various semiconductor devices.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. FIG. 2 is a cross-sectional view showing a step performed after the step shown in FIG. 1 in the same embodiment. FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 2 in the same embodiment. FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the same embodiment. FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the same embodiment. FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the same embodiment. FIG. 7 is a cross-sectional view showing the structure shown in FIG. 6 with the scale changed in the embodiment. FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the same embodiment. FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the same embodiment. FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the same embodiment. FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the same embodiment. FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the same embodiment. FIG. 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the same embodiment. FIG. 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the same embodiment. FIG. 15 is a cross-sectional view showing a step performed after the step shown in FIG. 14 in the same embodiment. FIG. 16 is a cross-sectional view showing a step performed after the step shown in FIG. 15 in the same embodiment. FIG. 17 is a cross-sectional view showing a step performed after the step shown in FIG. 16 in the same embodiment. FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the same embodiment. FIG. 19 is a cross-sectional view showing a step performed after the step shown in FIG. 18 in the same embodiment. FIG. 20 is a cross-sectional view showing a step performed after the step shown in FIG. 19 in the same embodiment. FIG. 21 is a cross-sectional view showing a step performed after the step shown in FIG. 20 in the same embodiment. FIG. 22 is another cross-sectional view in the step shown in FIG. 21 in the same embodiment. FIG. 22 is a cross-sectional view showing a step performed after the step shown in FIG. 21 in the same embodiment. FIG. 24 is another cross-sectional view in the step shown in FIG. 23 in the same embodiment. FIG. 10 is a cross-sectional view showing a step of a method of manufacturing a semiconductor device according to a comparative example in the embodiment. FIG. 26 is a cross-sectional view showing a step performed after the step shown in FIG. 25 in the same embodiment. FIG. 27 is a cross-sectional view showing a step performed after the step shown in FIG. 26 in the same embodiment. FIG. 28 is a cross-sectional view showing a step performed after the step shown in FIG. 27 in the same embodiment. FIG. 29 is a cross-sectional view showing the structure shown in FIG. 28 in different scales in the embodiment. FIG. 30 is a cross-sectional view showing a step performed after the step shown in FIG. 29 in the same embodiment. FIG. 31 is a cross-sectional view showing a step performed after the step shown in FIG. 30 in the same embodiment. FIG. 32 is a cross-sectional view showing a step performed after the step shown in FIG. 31 in the same embodiment. FIG. 33 is a cross-sectional view showing a step performed after the step shown in FIG. 32 in the same embodiment. FIG. 34 is a cross-sectional view showing a step performed after the step shown in FIG. 33 in the same embodiment. FIG. 35 is a cross-sectional view showing a step performed after the step shown in FIG. 34 in the same embodiment. FIG. 36 is a cross-sectional view showing a step performed after the step shown in FIG. 35 in the same embodiment. FIG. 37 is a cross-sectional view showing a step performed after the step shown in FIG. 36 in the same embodiment. FIG. 38 is a cross-sectional view showing a step performed after the step shown in FIG. 37 in the same embodiment. FIG. 39 is a cross-sectional view showing a step performed after the step shown in FIG. 38 in the same embodiment. FIG. 40 is a cross-sectional view showing a step performed after the step shown in FIG. 39 in the same embodiment. FIG. 41 is another cross-sectional view in the step shown in FIG. 40 in the same embodiment. FIG. 41 is a cross-sectional view showing a process performed after the process shown in FIG. 40 in the same embodiment. FIG. 43 is another cross-sectional view in the step shown in FIG. 42 in the same embodiment. In the same embodiment, it is sectional drawing which shows the problem of the semiconductor device which concerns on a comparative example. In the same embodiment, it is a graph which shows the relationship between plasma nitridation conditions and the film thickness of an oxide film. In the same embodiment, it is a graph which shows the relationship between plasma nitriding and the film thickness of a base oxide film. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 48 is a cross-sectional view showing a step performed after the step shown in FIG. 47 in the same embodiment. FIG. 49 is a cross-sectional view showing a step performed after the step shown in FIG. 48 in the same embodiment. FIG. 50 is a cross-sectional view showing a step performed after the step shown in FIG. 49 in the same embodiment. FIG. 52 is a cross-sectional view showing a step performed after the step shown in FIG. 50 in the same embodiment. FIG. 52 is a cross-sectional view showing a step performed after the step shown in FIG. 51 in the same embodiment. FIG. 53 is a cross-sectional view showing a step performed after the step shown in FIG. 52 in the same embodiment. FIG. 54 is a cross-sectional view showing a step performed after the step shown in FIG. 53 in the same embodiment. FIG. 55 is a cross-sectional view showing a step performed after the step shown in FIG. 54 in the same embodiment. FIG. 56 is a cross-sectional view showing a step performed after the step shown in FIG. 55 in the same embodiment. FIG. 57 is a cross-sectional view showing a step performed after the step shown in FIG. 56 in the same embodiment. FIG. 58 is a cross-sectional view showing a process performed after the process shown in FIG. 57 in the same Example. FIG. 59 is a cross-sectional view showing a process performed after the process shown in FIG. 58 in the same Example. FIG. 60 is another cross-sectional view in the step shown in FIG. 59 in the same embodiment. FIG. 60 is a cross-sectional view showing a step performed after the step shown in FIG. 59 in the same embodiment. FIG. 62 is another cross-sectional view in the step shown in FIG. 61 in the same embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. FIG. 64 is a cross-sectional view showing a step performed after the step shown in FIG. 63 in the same embodiment. FIG. 67 is a cross-sectional view showing a step performed after the step shown in FIG. 64 in the same embodiment. FIG. 66 is a cross-sectional view showing a step performed after the step shown in FIG. 65 in the same embodiment. FIG. 67 is a cross-sectional view showing a step performed after the step shown in FIG. 66 in the same embodiment. FIG. 68 is a cross-sectional view showing a process performed after the process shown in FIG. 67 in the same Example; FIG. 69 is a cross-sectional view showing a process performed after the process shown in FIG. 68 in the same Example. FIG. 70 is a cross-sectional view showing a step performed after the step shown in FIG. 69 in the same embodiment. FIG. 71 is a cross-sectional view showing a step performed after the step shown in FIG. 70 in the same embodiment. FIG. 72 is a cross-sectional view showing a process performed after the process shown in FIG. 71 in the same Example. FIG. 73 is a cross-sectional view showing a process performed after the process shown in FIG. 72 in the same Example. FIG. 74 is a cross-sectional view showing a step performed after the step shown in FIG. 73 in the same embodiment. FIG. 75 is another cross-sectional view in the step shown in FIG. 74 in the same embodiment. FIG. 75 is a cross-sectional view showing a step performed after the step shown in FIG. 74 in the same embodiment. FIG. 77 is another cross-sectional view in the step shown in FIG. 76 in the same embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. FIG. 79 is a cross-sectional view showing a step performed after the step shown in FIG. 78 in the same embodiment. FIG. 80 is a cross-sectional view showing a step performed after the step shown in FIG. 79 in the same embodiment. FIG. 81 is a cross-sectional view showing a step performed after the step shown in FIG. 80 in the same embodiment. FIG. 82 is a cross-sectional view showing a process performed after the process shown in FIG. 81 in the same Example. FIG. 83 is a cross-sectional view showing a step performed after the step shown in FIG. 82 in the same embodiment. FIG. 84 is a cross-sectional view showing a step performed after the step shown in FIG. 83 in the same embodiment. FIG. 85 is a cross-sectional view showing a step performed after the step shown in FIG. 84 in the same embodiment. FIG. 86 is a cross-sectional view showing a step performed after the step shown in FIG. 85 in the same embodiment. FIG. 89 is a cross-sectional view showing a step performed after the step shown in FIG. 86 in the same embodiment. FIG. 88 is a cross-sectional view showing a process performed after the process shown in FIG. 87 in the same Example. FIG. 89 is a cross-sectional view showing a step performed after the step shown in FIG. 88 in the same embodiment. FIG. 90 is a cross-sectional view showing a step performed after the step shown in FIG. 89 in the same embodiment. FIG. 91 is another cross-sectional view in the step shown in FIG. 90 in the same embodiment. FIG. 91 is a cross-sectional view showing a step performed after the step shown in FIG. 90 in the same embodiment. FIG. 93 is another cross-sectional view in the step shown in FIG. 92 in the same embodiment. FIG. 10 is a cross-sectional view showing a step of a method of manufacturing a semiconductor device according to a comparative example in the embodiment. FIG. 95 is a cross-sectional view showing a step performed after the step shown in FIG. 94 in the same embodiment. FIG. 96 is a cross sectional view showing a step performed after the step shown in FIG. 95 in the same embodiment. FIG. 97 is a cross-sectional view showing a step performed after the step shown in FIG. 96 in the same embodiment. FIG. 98 is a cross-sectional view showing a step performed after the step shown in FIG. 97 in the same embodiment. FIG. 99 is a cross-sectional view showing a step performed after the step shown in FIG. 98 in the same embodiment. FIG. 99 is a cross-sectional view showing a step performed after the step shown in FIG. 99 in the same embodiment. FIG. 100 is a cross-sectional view showing a process performed after the process shown in FIG. 100 in the same embodiment. FIG. 102 is a cross-sectional view showing a step performed after the step shown in FIG. 101 in the same embodiment. FIG. 103 is a cross-sectional view showing a step performed after the step shown in FIG. 102 in the same embodiment. FIG. 104 is a cross-sectional view showing a step performed after the step shown in FIG. 103 in the same embodiment. FIG. 103 is another cross-sectional view in the step shown in FIG. 104 in the same embodiment. FIG. 105 is a cross-sectional view showing a step performed after the step shown in FIG. 104 in the same embodiment. FIG. 107 is another cross-sectional view in the step shown in FIG. 106, in the embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention. 109 is a cross-sectional view showing a process performed after the process shown in FIG. 108 in the same Example. FIG. FIG. 110 is a cross sectional view showing a step performed after the step shown in FIG. 109 in the same embodiment. FIG. 112 is a cross-sectional view showing a step performed after the step shown in FIG. 110 in the same embodiment. FIG. 112 is a cross-sectional view showing a step performed after the step shown in FIG. 111 in the same embodiment. FIG. 113 is a cross-sectional view showing a step performed after the step shown in FIG. 112 in the same embodiment. FIG. 114 is a cross-sectional view showing a step performed after the step shown in FIG. 113 in the same embodiment. FIG. 115 is a cross sectional view showing a step performed after the step shown in FIG. 114 in the same embodiment. FIG. 116 is a cross sectional view showing a step performed after the step shown in FIG. 115 in the same embodiment. FIG. 117 is a cross-sectional view showing a process performed after the process shown in FIG. 116 in the embodiment. FIG. 118 is a cross-sectional view showing a step performed after the step shown in FIG. 117 in the same embodiment. FIG. 119 is another cross-sectional view in the step shown in FIG. 118 in the same embodiment. FIG. 118 is a cross-sectional view showing a process performed after the process shown in FIG. 118 in the same Example. FIG. 121 is another cross-sectional view in the step shown in FIG. 120 in the same embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention. FIG. 123 is a cross-sectional view showing a step performed after the step shown in FIG. 122 in the same embodiment. FIG. 124 is a cross-sectional view showing a step performed after the step shown in FIG. 123 in the same embodiment. FIG. 127 is a cross-sectional view showing a step performed after the step shown in FIG. 124 in the same embodiment. FIG. 126 is a cross-sectional view showing a step performed after the step shown in FIG. 125 in the same embodiment. FIG. 127 is a cross-sectional view showing a process performed after the process shown in FIG. 126 in the same Example. FIG. 128 is a cross-sectional view showing a step performed after the step shown in FIG. 127 in the same embodiment. FIG. 131 is a cross-sectional view showing a process performed after the process shown in FIG. 128 in the same Example. FIG. 131 is a cross-sectional view showing a step performed after the step shown in FIG. 129 in the same embodiment. FIG. 131 is a cross-sectional view showing a step performed after the step shown in FIG. 130 in the same embodiment. FIG. 132 is another cross-sectional view in the step shown in FIG. 131, in the embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 7 of this invention. FIG. 133 is a cross-sectional view showing a step performed after the step shown in FIG. 133 in the same embodiment. FIG. 135 is a cross-sectional view showing a step performed after the step shown in FIG. 134 in the same embodiment. FIG. 136 is a cross sectional view showing a step performed after the step shown in FIG. 135 in the same embodiment. FIG. 136 is a cross-sectional view showing a step performed after the step shown in FIG. 136 in the same embodiment. 137 is a cross-sectional view showing a step performed after the step shown in FIG. 137 in the same embodiment. FIG. 138 is a cross-sectional view showing a step performed after the step shown in FIG. 138 in the same embodiment. FIG. FIG. 140 is a cross-sectional view showing a step performed after the step shown in FIG. 139 in the same embodiment. FIG. 141 is a cross sectional view showing a step performed after the step shown in FIG. 140 in the same embodiment. FIG. 142 is another cross-sectional view in the step shown in FIG. 141 in the same embodiment. In the semiconductor device according to each embodiment of the present invention, a first diagram showing the number of thermal oxidation processes and the number of times a gate oxide film is covered with a resist pattern. In the semiconductor device concerning each embodiment of the present invention, it is the 2nd figure showing the number of times that a gate oxide film is covered with a resist pattern and the number of times of thermal oxidation processing. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 8 of this invention. FIG. 146 is a cross sectional view showing a step performed after the step shown in FIG. 145 in the same embodiment. FIG. 147 is a cross sectional view showing a step performed after the step shown in FIG. 146 in the same embodiment. FIG. 147 is a cross sectional view showing a step performed after the step shown in FIG. 147 in the same embodiment. FIG. 147 is a cross sectional view showing a step performed after the step shown in FIG. 148 in the same embodiment. FIG. 149 is a cross sectional view showing a step performed after the step shown in FIG. 149 in the same embodiment. FIG. 150 is a cross sectional view showing a step performed after the step shown in FIG. 150 in the same embodiment. FIG. 152 is a cross-sectional view showing a step performed after the step shown in FIG. 151 in the same embodiment. FIG. 151 is a cross-sectional view showing a step performed after the step shown in FIG. 152 in the same embodiment.

Explanation of symbols

  1 semiconductor device, 2a, 2b, 2c, 3a, 3b, 3c, 4a, 4b, 4c, 6a, 6b, 7a, 7b thermal oxide film, 9a, 9b, 9c oxide film, 10a, 10b, 10c interface, 11, 11a, 11b, 11c polysilicon film, 12, 12a, 12b, 12c silicon nitride film, 13a, 13b opening, 14a, 14b, 14c trench, 15a, 15b thermal oxide film, 16, 16a, 16b, 16c silicon oxide film 17, 17a, 17b, 17c doped polysilicon film, 18, 18a, 18b, 18c ONO film, 19, 19a, 19b, 19c polycide film, 20, 20a, 20b, 20c silicon nitride film, 21, 24, 25 Gate electrode part, 22 Floating gate electrode part, 23 Control gate electrode part, 50 Nitrogen.

Claims (16)

A plurality of first trench isolation regions formed in the first region of the main surface of the semiconductor substrate;
A first element formation region formed in a region of the semiconductor substrate sandwiched between one first trench isolation region and another first trench isolation region among the plurality of first trench isolation regions;
A plurality of second trench isolation regions formed in a second region of the main surface of the semiconductor substrate different from the first region;
A second element formation region formed in a region of the semiconductor substrate sandwiched between one second trench isolation region and another second trench isolation region among the plurality of second trench isolation regions;
A first oxide film formed on the surface of the region of the semiconductor substrate located in the first element formation region;
A first electrode portion formed on the first oxide film;
A second oxide film formed on the surface of the region of the semiconductor substrate located in the second element formation region;
A second electrode portion formed on the second oxide film;
With
The first oxide film is thicker than the second oxide film,
The first interface between the first oxide film and the surface of the region of the semiconductor substrate located immediately below the first oxide film is the surface of the semiconductor substrate located directly below the second oxide film and the second oxide film. At a position deeper than the second interface with the surface of the region,
The semiconductor device, wherein the first trench isolation region is formed deeper than the second trench isolation region.   The difference in height between the position of the upper surface of the first oxide film and the position of the upper surface of the second oxide film is based on the film thickness difference between the film thickness of the first oxide film and the film thickness of the second oxide film. The semiconductor device according to claim 1, which is also smaller.   The semiconductor device according to claim 2, wherein an upper surface of the first oxide film and an upper surface of the second oxide film are positioned at substantially the same height. The first electrode part is
A non-single crystalline silicon first conductive film;
And at least a second conductive film of non-single crystalline silicon formed on the first conductive film,
The interface between the first conductive film and the second conductive film is at a position lower than the upper surface of the first trench isolation region,
The second electrode part is
A third conductive film of non-single crystal silicon;
A non-single crystalline silicon fourth conductive film formed on the third conductive film,
4. The semiconductor device according to claim 1, wherein an interface between the third conductive film and the fourth conductive film is at a position lower than an upper surface of the second trench isolation region.   The semiconductor device according to claim 1, wherein the second oxide film contains a nitrogen atom. The second electrode part is
A lower electrode portion including the third conductive film and the fourth conductive film;
A dielectric film formed on the lower electrode portion;
The semiconductor device according to claim 1, further comprising an upper electrode portion formed on the dielectric film. A plurality of third trench isolation regions formed in a third region of the main surface of the semiconductor substrate different from the first region and the second region;
A third element formation region formed in a region of the semiconductor substrate sandwiched between one third trench isolation region and another third trench isolation region among the plurality of third trench isolation regions;
A third oxide film formed on the surface of the region of the semiconductor substrate located in the third element formation region;
A third electrode portion formed on the third oxide film,
The third oxide film is thicker than the second oxide film and thinner than the first oxide film,
A third interface between the third oxide film and the surface of the region of the semiconductor substrate located immediately below the third oxide film is shallower than the first interface and deeper than the second interface;
The semiconductor device according to claim 1, wherein the third trench isolation region is formed at a position shallower than the first trench isolation region and deeper than the second trench isolation region. By performing a predetermined thermal oxidation treatment, a first oxide film is formed in a predetermined first region on the main surface of the semiconductor substrate, and is thinner than the first oxide film in a second region different from the first region. An oxide film forming step of forming a second oxide film;
Forming a first element by forming a first trench isolation region in a portion of the first oxide film located in a predetermined region of the first region and a region of the semiconductor substrate located immediately below the portion of the first oxide film Forming a region, and forming a second trench isolation region in a portion of the second oxide film located in a predetermined region of the second region and a region of the semiconductor substrate located immediately below the portion of the second oxide film A trench isolation region forming step of forming a second element formation region;
Forming a first electrode portion on the surface of the region of the semiconductor substrate located in the first element formation region with the first oxide film interposed therebetween;
Forming a second electrode portion on the surface of the region of the semiconductor substrate located in the second element formation region with the second oxide film interposed therebetween,
In the oxide film forming step, at least the second region is subjected to plasma nitridation treatment to suppress the second region thermal oxidation due to the predetermined thermal oxidation treatment in the semiconductor substrate region located in the second region. The first region thermal oxidation by the predetermined thermal oxidation treatment in the region of the semiconductor substrate located in the first region is advanced to a region deeper than the second region thermal oxidation, and thereby the first oxide film and the The semiconductor substrate located immediately below the second oxide film and the second oxide film, the first interface with the surface of the region of the semiconductor substrate located directly below the first oxide film being thinner than the first oxide film Formed at a position deeper than the second interface with the surface of the region,
In the trench isolation region forming step, the first trench isolation region is formed to a position deeper than the second trench isolation region corresponding to the positional relationship between the first interface and the second interface. Method.   In the oxide film forming step, the difference in height between the position of the upper surface of the first oxide film and the position of the upper surface of the second oxide film is determined by determining the film thickness of the first oxide film and the film of the second oxide film. The method of manufacturing a semiconductor device according to claim 8, wherein the manufacturing method is smaller than a difference from the thickness.   10. The method of manufacturing a semiconductor device according to claim 9, wherein, in the oxide film forming step, the position of the upper surface of the first oxide film and the position of the upper surface of the second oxide film are made substantially the same position. The oxide film forming step includes
Forming a first thermal oxide film on the main surface of the semiconductor substrate by performing a first thermal oxidation process as one of the predetermined thermal oxidation processes;
Removing the portion of the first thermal oxide film located in the second region, leaving the portion of the first thermal oxide film located in the first region on the main surface of the semiconductor substrate; Exposing the surface of the region of the semiconductor substrate located in the region;
Performing a plasma nitriding process on the semiconductor substrate including the region of the semiconductor substrate exposed in the second region, leaving the portion of the first thermal oxide film located in the first region;
Exposing a surface of a region of the semiconductor substrate located in the first region by removing a portion of the first thermal oxide film located in the first region;
By performing a second thermal oxidation process as another one of the predetermined thermal oxidation processes, a second thermal oxide film is formed as the first oxide film on the surface of the region of the semiconductor substrate exposed to the first region. And forming a third thermal oxide film as the second oxide film on the surface of the region of the semiconductor substrate exposed to the second region. 11. The semiconductor device according to claim 8, Manufacturing method. The oxide film forming step includes
Forming a first thermal oxide film on the main surface of the semiconductor substrate by performing a first thermal oxidation process as one of the predetermined thermal oxidation processes;
By removing the portion of the thermal oxide film located in the second region, leaving the portion of the first thermal oxide film located in the first region on the main surface of the semiconductor substrate, Exposing the surface of the region of the semiconductor substrate that is located;
Performing a plasma nitriding process on the semiconductor substrate including the region of the semiconductor substrate exposed in the second region, leaving the portion of the first thermal oxide film located in the first region;
Removing a portion of the first thermal oxide film located in the first region to expose a surface of the region of the semiconductor substrate located in the first region;
By performing a second thermal oxidation process as another one of the predetermined thermal oxidation processes, a second thermal oxide film is formed on the surface of the region of the semiconductor substrate exposed in the first region, and the second thermal oxidation process is performed. Forming a third thermal oxide film on the surface of the region of the semiconductor substrate exposed in the region;
The surface of the region of the semiconductor substrate located in the first region is removed by removing the second thermal oxide film located in the first region while leaving the third thermal oxide film located in the second region. An exposure process;
The third thermal oxidation process is performed as another one of the predetermined thermal oxidation processes in a state where the third thermal oxide film located in the second area is left, so that the first thermal oxidation film is located in the first area. A fourth thermal oxide film is formed as the first oxide film on the surface of the semiconductor substrate region, and a fifth thermal oxide film is formed on the surface of the semiconductor substrate region located in the second region as the second oxide film. The manufacturing method of the semiconductor device in any one of Claims 8-10 including the process to form. The oxide film forming step includes
Forming a first thermal oxide film on the main surface of the semiconductor substrate by performing a first thermal oxidation process as one of the predetermined thermal oxidation processes;
Performing a plasma nitridation process on a portion of the first thermal oxide film located in the first region and a portion of the first thermal oxide film located in the second region;
By removing the portion of the first thermal oxide film located in the first region while leaving the portion of the first thermal oxide film located in the second region, the semiconductor substrate located in the first region is removed. Exposing the surface of the region;
The second thermal oxidation treatment is performed as another one of the predetermined thermal oxidation treatment with the portion of the first thermal oxidation film located in the second region left, and is exposed to the first region. Forming a second thermal oxide film on the surface of the region of the semiconductor substrate and forming a third thermal oxide film in the second region;
The surface of the region of the semiconductor substrate located in the second region by removing the third thermal oxide film located in the second region, leaving a portion of the second thermal oxide film located in the first region Exposing the step,
By applying a third thermal oxidation process as still another one of the predetermined thermal oxidation processes while leaving the portion of the second thermal oxide film located in the first area, Forming a fourth thermal oxide film as the first oxide film, and forming a fifth thermal oxide film as the second oxide film on the surface of the region of the semiconductor substrate exposed in the second region. Item 11. A method for manufacturing a semiconductor device according to any one of Items 8 to 10. The oxide film forming step includes
Third oxidation having a third film thickness smaller than the first film thickness and larger than the second film thickness in a third area different from the first area and the second area on the main surface of the semiconductor substrate. Forming a film;
Forming a third interface between the third oxide film and the surface of the region of the semiconductor substrate located immediately below the third oxide film at a position shallower than the first interface and deeper than the second interface; Including
In the trench isolation region forming step, the first oxide film is formed in the third oxide film portion located in a predetermined region of the third region and in the semiconductor substrate region located immediately below the third oxide film portion. Forming a third element formation region by forming a third trench isolation region shallower than the trench isolation region and deeper than the second trench isolation region;
14. The method according to claim 8, further comprising a step of forming a third electrode portion with the third oxide film interposed on a surface of a region of the semiconductor substrate located in the third element formation region. A method for manufacturing a semiconductor device. Oxidation that forms a first oxide film in a predetermined first region on the main surface of the semiconductor substrate and forms a second oxide film in a second region different from the first region by performing a predetermined thermal oxidation treatment A film forming step;
Forming a first element by forming a first trench isolation region in a portion of the first oxide film located in a predetermined region of the first region and a region of the semiconductor substrate located immediately below the portion of the first oxide film Forming a region, and forming a second trench isolation region in a portion of the second oxide film located in a predetermined region of the second region and a region of the semiconductor substrate located immediately below the portion of the second oxide film A trench isolation region forming step of forming a second element formation region;
Forming a first electrode portion on the surface of the region of the semiconductor substrate located in the first element formation region with the first oxide film interposed therebetween;
Forming a second electrode portion on the surface of the region of the semiconductor substrate located in the second element formation region with the second oxide film interposed therebetween,
In the oxide film forming step, the first region thermal oxidation by the predetermined thermal oxidation process in the region of the semiconductor substrate located in the first region is changed to the predetermined region in the region of the semiconductor substrate located in the second region. By proceeding to a region deeper than the second region thermal oxidation by thermal oxidation treatment, the first interface between the first oxide film and the surface of the region of the semiconductor substrate located immediately below the first oxide film is Forming at a position deeper than a second interface between the second oxide film thinner than the first oxide film and the surface of the region of the semiconductor substrate located immediately below the second oxide film;
In the trench isolation region forming step, the first trench isolation region is formed to a position deeper than the second trench isolation region corresponding to the positional relationship between the first interface and the second interface. Method. The oxide film forming step includes
Forming a first thermal oxide film on the main surface of the semiconductor substrate by performing a first thermal oxidation treatment;
The semiconductor substrate located in the first region by removing the portion of the first thermal oxide film located in the first region while leaving the portion of the first thermal oxide film located in the second region Exposing the surface of the region of
By subjecting the semiconductor substrate including the region of the semiconductor substrate exposed to the first region to a second thermal oxidation process while leaving a portion of the first thermal oxide film located in the second region, a semiconductor Forming a second thermal oxide film on the main surface of the substrate;
The semiconductor substrate located in the first region by removing the portion of the second thermal oxide film located in the first region while leaving the portion of the first thermal oxide film located in the second region Exposing the surface of the region of
By performing a third thermal oxidation process on the semiconductor substrate including the region of the semiconductor substrate exposed in the first region while leaving a portion of the first thermal oxide film located in the second region, a semiconductor is obtained. Forming a third thermal oxide film on the main surface of the substrate;
The semiconductor substrate located in the second region by removing the portion of the first thermal oxide film located in the second region while leaving the portion of the third thermal oxide film located in the first region Exposing the surface of the region of
By applying a fourth thermal oxidation process to the semiconductor substrate including the region of the semiconductor substrate exposed in the second region while leaving a portion of the third thermal oxide film located in the first region, Forming a third thermal oxide film in the first region as the first oxide film and forming a fourth thermal oxide film as the second oxide film on the surface of the region of the semiconductor substrate exposed in the second region; A method for manufacturing a semiconductor device according to claim 15, comprising:

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