JP2008016120A - Ferroelectric memory device - Google Patents

Abstract

Conventional main ferroelectric memories read and write data destructively, so that rewriting is required or a complicated control method is employed in order not to destroy data. Therefore, the control circuit is complicated and the cycle time for reading data is long, so that it is not easy to work in a general IC.
A ferroelectric latch circuit capable of holding, storing, and restoring state data independently using a ferroelectric element is used in a plurality of units, the data is not destroyed, and the state of the ferroelectric element is reflected. By adopting a control method for reading a signal from a latch circuit including a MOSFET, a high-speed, high-reliability nonvolatile ferroelectric memory device is configured.
[Selection] Figure 1

Description

  The present invention relates to a ferroelectric memory device which is a nonvolatile memory, which eliminates the problem of the lifetime due to the restriction on the number of times of reading of the memory element, reads data at high speed, and has a simple control method. Concerning configuration.

  In recent years, the importance of electrically writable and erasable nonvolatile memories in the memory field has increased. Further, it is often required to incorporate a nonvolatile circuit that can be written to and erased from a part of the integrated circuit.

  There are various types of nonvolatile memories, but ferroelectric memories are attracting attention from the viewpoints of high speed, low voltage characteristics, low power consumption, and the like. There are various specific configurations of the ferroelectric memory as shown in the following examples.

  An example of a ferroelectric memory is a ferroelectric capacitor that defines two states depending on the remanent polarization state inside the ferroelectric film, and two types of voltages having different polarities at the voltage exceeding the coercive electric field of the ferroelectric thin film at the time of writing. The internal polarization state of 1 or 0 is created by the application method, and after the storage state due to remanent polarization, the charge is taken out by applying a voltage higher than the coercive electric field of the ferroelectric thin film at the time of reading. There is a method for detecting the internal storage state. This method is simply shown in FIGS. 36, 38, 39, and 40. FIG.

  FIG. 36 is a cross-sectional view showing the structure of a ferroelectric capacitor. In FIG. 36, 3640 is a ferroelectric thin film made of an inorganic ferroelectric material, and 3641 and 3642 are electrodes made of metal. The ferroelectric capacitor shown by a broken line 3649 is constituted by a structure in which the ferroelectric thin film 3640 is sandwiched between the metal electrodes 3641 and 3642.

  FIG. 38 shows the polarization charge-applied voltage characteristics of the ferroelectric capacitor shown in FIG. In FIG. 38, curves passing through the characteristic points of 3801, 3802, 3803, 3804, 3805, 3806 are the voltage V applied between the first terminal 3641 and the second terminal 3642 of the ferroelectric capacitor of FIG. The characteristic of the polarization charge Q is represented. A characteristic point 3801 in FIG. 38 indicates a state in which a positive voltage V higher than that of the first terminal 3641 is applied to the second terminal 3642 in FIG. 36, and a characteristic point 3804 in FIG. 38 indicates that the first terminal 3641 in FIG. A state where a voltage V higher than 3642 is applied is shown. In the characteristic point 3801 and the characteristic point 3804 in FIG. 38, the internal polarization is positive / negative and reverse. When the potential difference between the first terminal and the second terminal of the ferroelectric capacitor that was in the state of the characteristic point 3801 is opened with 0, the internal polarization is stored as remanent polarization, and the state shown in the characteristic point 3802 is obtained. When the potential difference between the first terminal and the second terminal of the ferroelectric capacitor that was in the state of the characteristic point 3804 is opened with 0, the internal polarization is stored as remanent polarization and the state shown in the characteristic point 3805 is obtained. Therefore, the internal polarization charge of the ferroelectric capacitor and the applied voltage have hysteresis characteristics, and at the same time, the terminals at both ends of the ferroelectric capacitor are opened, and even if the voltage is set to 0, the residual polarization varies depending on the previous state. Have. It can be seen that this state corresponds to the characteristic point 3802 and the characteristic point 3805, and that nonvolatile data can be stored in the form of remanent polarization.

  In FIG. 38, the polarization charge at the characteristic point 3804 remains as remanent polarization even when the power is turned off as described above. However, the polarization charge at this time is not limited to this. The same polarization remains for a while even when the voltage is applied in the opposite direction. It disappears completely when the characteristic point 3806 is reached. The voltage at this time is called a coercive voltage.

  The states of internal polarization of the ferroelectric capacitors corresponding to the characteristic points 3801 to 3806 in FIG. 38 are schematically shown in FIGS. 39A to 39F, respectively. However, the applied voltage V in FIG. 38 is positive or negative with reference to the electrode of the upper capacitor in FIG. In FIG. 39, a ferroelectric capacitor surrounded by a circle inside two electrode plates and indicated by + and − represents a polarization charge, and a symbol indicated by + and − outside the electrode plate is simply It represents an electric charge. As can be seen from FIGS. 38 and 39, even when the voltage applied to the ferroelectric thin film becomes zero, the residual polarization inside the ferroelectric thin film remains different depending on the previous state and history. That is, in both the states of (B) and (E) of FIG. 39, the applied voltage is 0, but the polarity of the internal remanent polarization is completely reversed.

  Further, as shown in FIG. 38, when a voltage V (ΔVB) is applied between the terminals from the state where both terminals of the ferroelectric capacitor are opened, the characteristic point 3804 is moved. At this time, if the previous state is the characteristic point 3802, the charge of ΔQ1 shown in FIG. 38 is taken out, and if it is the state of the characteristic point 3805, the charge of ΔQ0 is taken out. From FIG. 38, it is apparent that ΔQ1 >> ΔQ0, so that the difference between the previous states stored as the remanent polarization can be determined by using an appropriate detection circuit, and can be used as data 1 or 0 or the like.

  It is assumed that the ferroelectric capacitor having the above structure and characteristics uses the symbol shown in FIG. 37 (a) or (b) as a symbol in the circuit diagram. Here, FIG. 37A is basically used in the case where the ferroelectric capacitor is used on a circuit exhibiting hysteresis characteristics. FIG. 37B is basically used when the ferroelectric capacitor is used on a circuit that does not exhibit hysteresis characteristics. In such a case, although it has the same structure as a ferroelectric capacitor, it does not exhibit hysteresis and simply functions and functions as an electrostatic capacitor having a large relative dielectric constant. Sometimes.

  FIG. 40 shows an example of a circuit configuration in which the above ferroelectric capacitor is actually performed. FIG. 40 is a circuit diagram showing a structure of a unit memory cell of a ferroelectric memory device that stores 1-bit nonvolatile data using one transistor and one ferroelectric capacitor. In FIG. 40, reference numeral 4011 denotes a ferroelectric capacitor, and 4012 denotes an N-type insulated gate field effect transistor (hereinafter also abbreviated as MOSFET. Note that MOSFET is a metal-oxide-semiconductor-field-effect-transistor). Reference numeral 4013 denotes a word line, which is connected to the gate electrode of the MOSFET 4012. Reference numeral 4014 denotes a bit line which is connected to an electrode serving as a source or drain of the MOSFET 4012. Reference numeral 4015 denotes a plate line connected to one end of the ferroelectric capacitor 4011. The other end of the ferroelectric capacitor 4011 is connected to the drain or source electrode of the MOSFET 4012. With the above circuit, the potential applied to the ferroelectric capacitor 4011 is supplied to the bit line 4014 and the plate line 4015, and the MOSFET 4012 is turned on (ON) and turned off (OFF) by the word line 4013, whereby the above-described charge write operation is performed. Read operation is performed. This method is a method generally called destructive reading because it takes out charges when reading data, that is, destroys the data.

  Further, there is a method called non-destructive reading using a method that does not destroy data when reading data. As an example, as shown in the cross-sectional view of FIG. 17 or the circuit diagram of FIG. 41, a ferroelectric thin film 1700 is provided at the gate portion of a field effect transistor, and a gate electrode 1701 and a substrate 1709 or a source electrode 1702 and a drain electrode are provided. After applying a voltage equal to or higher than the coercive voltage of the ferroelectric thin film to 1703 to cause polarization in the ferroelectric thin film 1700 and removing the applied voltage, the data is stored according to the state of the residual polarization, and the electric field is generated by the residual polarization. There is a method in which the charge induced in the channel of the effect transistor is different, the threshold voltage is different, and the current value flowing is different so that the direction of the written polarization is known, that is, the difference between 1 and 0 is detected. .

  A field effect transistor having a ferroelectric thin film in the gate portion may be abbreviated as MFSFET hereinafter. Note that the MFSFET is a combination of the initials of Metal-Ferroelectrics-Semiconductor-Field-Effect-Transistor.

  Now, a method of causing polarization in the ferroelectric thin film at the gate portion of the above-described field effect transistor and detecting a change in threshold voltage due to the residual polarization will be further described below.

  In FIG. 41, the MFSFET is surrounded by a broken line 4100. In the MFSFET 4100, a zero potential is applied to the gate electrode 4101 through the word line 4115, and a positive V potential equal to or higher than the coercive voltage is applied to the source electrode 4103 and the drain electrode 4104 through the first bit line 4113 and the second bit line 4114. The dielectric thin film has a positive polarity on the gate side and a negative polarity on the substrate side. Alternatively, a positive V potential higher than the coercive voltage is applied to the gate electrode 4101 through the word line 4115, and a zero potential is applied to the source electrode 4103 and the drain electrode 4104 through the first bit line 4113 and the second bit line 4114, and the ferroelectric thin film In addition, the negative electrode is polarized on the gate side and the positive electrode is polarized on the substrate side. A variation in the amount of current due to the difference in threshold voltage due to the difference in polarization is detected.

  Furthermore, as shown in FIG. 42, this method is a general method for arranging the MFSFETs on a matrix and controlling the word lines and bit lines to detect the data storage state of the MFSFETs to make a large capacity memory. is there. That is, in FIG. 42, MFSFETs such as 4201 are arranged in a matrix, and the word line 4205, the first bit line 4213, and the second bit line 4214 are used in common. A circuit for controlling the word line group and the bit line group of the memory cell array 4220 configured as described above is provided and controlled around the memory cell array.

  However, in this method, a ferroelectric thin film is provided under the gate electrode to store the remanent polarization, and in order to detect a difference in the stored data, a potential at which the transistor is turned on (ON) is applied to the gate electrode of the MFSFET. Therefore, it is necessary to provide a control system on the word line side and the bit line side so as not to erase stored data and to prevent malfunctions and erroneous writing in each MFSFET as a memory arranged in a matrix. is there.

  As an example of this, there is Patent Document 2 which describes a field effect transistor having a ferroelectric thin film in the gate portion.

JP-A-11-39882 JP 2004-153239 A

  However, the conventional ferroelectric memory has the following problems. 36, 38, 39, 40, or the method of destructive reading of the data shown in Patent Document 1, it is necessary to rewrite the lost data after reading. Therefore, since a write operation is performed after data is read, an excessively large number of control circuits and a non-negligible time are required, which affects access time and cycle time. Further, the increase in the number of times of writing by rewriting has a problem that the lifetime of the ferroelectric is shortened and the reliability as a device is lowered.

  In addition, a ferroelectric thin film is disposed on the gate electrode of a field effect transistor as shown in FIG. 17, FIG. 41, or Patent Document 2, and the ferroelectric material is interposed between the gate electrode and the drain electrode, the source electrode, or the substrate. A method in which a voltage higher than the coercive voltage of the thin film is applied to hold the data by the remanent polarization of the ferroelectric thin film, and the memory cells are arranged in a matrix and controlled by the peripheral circuit through the word line or bit line is a data error. In order to prevent writing and erroneous reading, the peripheral circuit is complicated and a circuit having a large number of elements is required. Further, even when the data is read nondestructively, the MFSFET is activated by applying a potential to the gate while preventing the data from being destroyed. Therefore, static random access memory (hereinafter abbreviated as SRAM. Compared to a general logic circuit using -Random-Access-Memory) or MOSFET, the read time becomes longer.

  From the above, it can be said that the conventional method described above is generally suitable for large-scale memories. However, a relatively small-capacity readable / writable nonvolatile memory is built in the integrated circuit, and a general logic can be used. When it is desired to use the circuit as if it were a circuit, the above-described conventional method had a large problem in the size of peripheral circuits, complicated control, and a long time required for reading and writing.

  Therefore, the present invention solves such problems, and the object of the present invention is a readable / writable non-volatile circuit and easy handling similar to that of a normal insulated gate field effect transistor circuit. It is another object of the present invention to provide a non-volatile circuit that can read data at high speed.

In order to solve the above-described problems and achieve the object of the present invention, each invention is configured as follows.
That is, the first invention includes a ferroelectric latch circuit that includes a ferroelectric element and can independently hold, store, and restore state data, a latch write circuit that writes data to the ferroelectric latch circuit, and the ferroelectric A latch read circuit for transmitting state data of the body latch circuit, a plurality of latch write circuits, and a latch control circuit for controlling the plurality of latch read circuits.

  The second invention defines the circuit configuration of the first invention as a ferroelectric memory block unit cell circuit, arranges the ferroelectric memory block unit cell circuits in a matrix, and transmits a row address signal. A line group, a bit line group for transmitting column address signals, a data line group for transmitting input data or output data, and a control signal line group for transmitting read and write control signals, The group is controlled by a row decoder control circuit, a column decoder control circuit, a read / write control circuit, and a data control circuit.

  According to a third invention, in the first or second invention, the ferroelectric latch circuit is configured by using a field effect transistor having a ferroelectric thin film at a gate portion.

  According to a fourth invention, in the first or second invention, the ferroelectric latch circuit is constituted by using two inverter circuits and a ferroelectric capacitor.

  A fifth invention is the first or second invention, wherein the number of the plurality of latch write circuits and the plurality of latch read circuits controlled simultaneously by the latch control circuit is a power of two. It is.

  According to a sixth aspect of the present invention, in the second aspect of the present invention, the input data line group and the output data line group of the ferroelectric memory block unit cell circuit group are shared.

  As described above, according to the present invention configured as described above, the polarization signal is not read out by operating the ferroelectric latch circuit each time, but the potential signal that already exists as the state of the ferroelectric latch circuit is used. Since reading is performed from the latch read circuit, the signal output is determined only by the response time of the MOSFET, and there is an effect that the speed becomes very high. In principle, there is an effect that a high-speed memory higher than SRAM can be obtained by a nonvolatile memory.

  In addition, as described above, the ferroelectric latch circuit is not directly read out, but the potential signal that already exists as a state is read out, so that there is no need for rewriting, and the lifetime of the ferroelectric becomes very long. is there.

  In addition, the portion including the ferroelectric has a separate control circuit in the cell as a ferroelectric memory unit cell circuit, and can be handled like a black box from the outside of the memory cell. Complicated control including common boosting and intermediate potential is unnecessary, and peripheral circuits such as row decoder control circuit, column decoder control circuit, read / write control circuit, and data control circuit can be configured with simple circuits and occupy an area. It has the effect of reducing the amount.

  In addition, since a field effect transistor or a ferroelectric capacitor having a ferroelectric thin film is used, the ferroelectric latch circuit can be configured with a small number of elements, operates at a low voltage, and has an effect of reducing power consumption.

  In addition, since the latch control circuit controls a plurality of the latch write circuits and the latch read circuits at the same time, the number of the latch control circuits is saved, and the degree of integration as a nonvolatile memory device is increased.

  Further, since the input data line group and the output data line group of the ferroelectric memory block unit cell circuit group are shared in some cases, there is an effect that the degree of integration as a nonvolatile memory device is further increased.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Circuit Configuration (1) of Embodiment 1 of the Ferroelectric Memory Device of the Present Invention)
FIG. 1 is a circuit diagram showing a first embodiment of a ferroelectric memory device according to the present invention. The circuit of FIG. 1 includes a ferroelectric element, a plurality of ferroelectric latch circuits capable of independently holding, storing, and restoring state data, and a plurality of latch write circuits for writing state data to the ferroelectric latch circuit. A plurality of latch read circuits for transmitting state data of the ferroelectric latch circuit; an address detection circuit; a plurality of the latch write circuits; and a latch control circuit for controlling the plurality of latch read circuits; It is composed of At the same time, a ferroelectric memory block unit cell circuit is formed in FIG.

  Although the details will be described later, the outline shown by a broken line 101 in FIG. 1 is the ferroelectric latch circuit, the inverter buffer circuit 102 with a control signal is the latch write circuit, and the inverter buffer circuit 103 with a control signal. Is the latch read circuit. The ferroelectric latch circuit 101, the latch write circuit 102, and the latch read circuit 103 are combined to form a ferroelectric latch unit circuit indicated by a one-dot chain line 120 in FIG. The ferroelectric latch unit circuits 121, 122, 123, 124, 125, 126, and 127 having the same configuration as the circuit 120 have a total of eight ferroelectric latch unit circuits. The NAND circuit 107 is an address detection circuit, and the configuration of the NAND circuit 107, the NOR circuit 104, the NOR circuit 105, and the inverter circuit 106 corresponds to the latch control circuit described above. The latch control circuit corresponds to the inside of the two-dot chain line 108 in FIG. The latch control circuit 108 includes eight ferroelectric latch unit circuits 120 to 127 through the control line 116 that is an output signal of the NOR circuit 104 and the control line 117 that is an output signal of the NOR circuit 105. I have control.

  In FIG. 1, a circuit surrounded by a broken line 101 or a circuit symbol shown in FIG. 4 represents a ferroelectric latch circuit that can hold, store, and restore the state data described above as a symbol. The function of the ferroelectric latch circuit 101 is an important circuit that supports the basis of the present invention, and is generally a circuit that is difficult to understand by the expression of symbols alone. Then, a ferroelectric transistor latch circuit or a ferroelectric capacitor latch circuit which is a configuration example thereof, an MFSFET which is an operation principle thereof, and the like will be described, and then the ferroelectric memory device of the present invention will be described again.

(Configuration and operating principle of ferroelectric latch circuit (1))
Various ferroelectric latch circuits that include ferroelectric elements and have the function of holding, storing and restoring state data independently can be considered, but field effect transistors with a ferroelectric thin film at the gate are used below. An example of the configuration of the conventional method and the method using a ferroelectric capacitor will be given.

  Here, a system using a field effect transistor (MFSFET) having a ferroelectric thin film in the gate portion is hereinafter referred to as a ferroelectric transistor latch circuit system.

  In addition, a method using a latch circuit with two inverter circuits and a ferroelectric capacitor is hereinafter referred to as a ferroelectric capacitor latch circuit method.

  First, the ferroelectric transistor latch circuit system will be described first, and then the ferroelectric capacitor latch circuit system will be described.

(Configuration and operating principle of ferroelectric transistor latch circuit system)
The configuration and operation principle of a ferroelectric transistor latch circuit system, which is a system using a field effect transistor (MFSFET) having a ferroelectric thin film in the gate portion, will be described below.

  First, the structure and operation principle of a field effect transistor (MFSFET) having a ferroelectric thin film of the gate portion used here will be described with reference to FIGS. 17, 20, 21, 22, and 23. FIG.

(Configuration and operation principle of MFSFET)
The MFSFET, which is a field effect transistor having a ferroelectric thin film in the gate portion, has been briefly described in the conventional example, but will be described in detail below.
FIG. 17 is a cross-sectional view taken along the source / drain direction of the channel portion of the MFSFET having N-type conductivity. In FIG. 17, reference numeral 1701 denotes a gate electrode made of metal, 1702 denotes a first electrode serving as a source or drain made of N + diffusion, and 1703 denotes a second electrode serving as a drain or source made of N + diffusion. Reference numeral 1709 denotes a silicon substrate. 1700 is a ferroelectric thin film made of PZTN. The ferroelectric thin film 1700 formed of PZTN having excellent crystallinity has a property that polarization occurs inside when a voltage is applied to both ends, and the polarization once generated is difficult to reverse, and has a hysteresis characteristic as shown in FIG. have. PZT and SBT have similar characteristics. However, PZTN has better remanent polarization and hysteresis squareness characteristics. PZT is a generic name for Pb (Zr, Ti) O3, PZTN is a generic name for a part of Ti in PZT replaced with Nb, and SBT is a generic name for SrBi2Ta2O9 or a composition close thereto. . In the following, in FIG. 17, the ferroelectric thin film will be described using a typical characteristic diagram of the most desirable PZTN, but PZT or SBT may be used, and the essential difference is not so large. When the ferroelectric thin film 1700 is used, platinum (Pt) is generally used as the metal electrode 1701.

  FIG. 38 described above also shows the polarization charge-applied voltage characteristics of the ferroelectric thin film PZTN1700 used in FIG. In FIG. 38, when a negative voltage higher than the coercive electric field is applied to the ferroelectric thin film, a characteristic point 3801 is obtained. When the applied voltage is removed, the characteristic point 3802 is obtained when the voltage is released, and an amount corresponding to the intersection of the vertical axes is remanent polarization. Held as. Further, when a positive voltage higher than the coercive voltage is applied, the state of the characteristic point 3804 is entered. Therefore, when the applied voltage is removed except for the applied voltage, a characteristic point 3805 is obtained, and an amount corresponding to the intersection of the vertical axes is retained as remanent polarization.

  As shown in FIG. 38, when a voltage higher than the coercive voltage is applied to the ferroelectric thin film 1700 in the MFSFET having the structure of FIG. 17, the ferroelectric thin film 1700 is polarized inside. For example, as shown in FIG. 20, when the gate electrode 2001 becomes a drain electrode or a source electrode with zero potential through the gate electrode terminal 2004 and 2002 and 2003 have a + V potential through the electrode terminals 2005 and 2006, the ferroelectric as shown in FIG. The thin body film 2000 causes positive internal polarization on the gate electrode 2001 side, and negative internal polarization on the 2002 and 2003 sides which become the drain electrode or the source electrode. This polarization works in a direction to suppress the induction of electrons in the channel portion 2009 as an N-type field effect transistor. That is, the threshold voltage of the N-type MFSFET is increased.

  Further, as shown in FIG. 21, if the gate electrode 2001 becomes + V potential through the gate electrode terminal 2104 and becomes the drain electrode or source electrode 2002, 2003 becomes zero potential through the electrode terminals 2105, 2106, the ferroelectric thin film of FIG. In 2100, the gate electrode 2001 side is negative and the drain electrode or source electrode 2002, 2003 side has positive internal polarization. This polarization induces electrons in the channel portion 2109 as an N-type field effect transistor. In the case of the N type, it acts in a direction in which a path channel through which electrons flow is easily formed. That is, the threshold voltage of the N-type MFSFET is lowered. In FIG. 21, the upper portion of the channel portion 2109 is expressed by a plurality of broken lines, which represents a state in which electrons are induced in the channel portion as a result of the polarization of the ferroelectric thin film.

  FIG. 38 shows the relationship between the voltage V applied to the ferroelectric thin film and the internal polarization charge Q. From the general relationship of Q = CV where the capacitance is C, the change in MOS capacitance is read from FIG. I can take it. Further, the change in the threshold voltage of the MOSFET is related to the change in the MOS capacitance. Therefore, in FIG. 38, the threshold voltage of the N-type MFSFET changes greatly in the vicinity of the coercive voltage at which the characteristic curve changes greatly. This corresponds to the fact that the threshold voltage of the field effect transistor changes depending on the direction and magnitude of the internal polarization of the ferroelectric thin film of the MFSFET. In FIG. 38, the voltage when the characteristic curve changes in the vicinity of the coercive voltage is an amount of change that sufficiently affects the operating voltage of the field effect transistor. Since the remanent polarization at the characteristic points 3802 and 3805 is sufficiently large, the threshold voltage of the MFSFET in which the remanent polarization is preserved when the power is turned off is also preserved as a large difference.

  FIGS. 22 and 23 show the polarization of the ferroelectric thin films 2200 and 2300 and the carrier induction of the channel portions 2209 and 2309 when a gate voltage is applied when a P-type MFSFET is used. In the case of a P-type MFSFET, as shown in FIG. 22, when the gate electrode 2201 side is at 0 potential, hole (hole) carriers are induced in the channel portion, and the threshold voltage is equivalently reduced in absolute value, and current flows easily. Become. Further, as shown in FIG. 23, when the gate electrode 2201 is at + V potential, the threshold voltage is equivalently increased in absolute value, and it becomes difficult to conduct.

Next, a configuration example of a ferroelectric transistor latch circuit using these MFSFETs will be given.
(Configuration Example 1 of Ferroelectric Transistor Latch Circuit)
FIG. 16 is a circuit diagram showing a first configuration example of a ferroelectric transistor latch circuit used in the present invention.
In FIG. 16, reference numerals 1601 and 1603 denote N-type conductivity type field effect transistors (MFSFETs) having a ferroelectric thin film in the gate portion. Reference numerals 1602 and 1604 denote P-type conductivity type field effect transistors (MFSFETs) having a ferroelectric thin film in the gate portion.

  The source electrode of the N-type MFSFET 1601 is connected to the negative power supply terminal having the potential of VSS, the source electrode of the P-type MFSFET 1602 is connected to the positive power supply terminal having the potential of VDD, the gate electrode of the N-type MFSFET 1601 and the P-type MFSFET 1602. Are connected to each other to form a first input / output terminal 1605. The drain electrode of the N-type MFSFET 1601 and the drain electrode of the P-type MFSFET 1602 are connected to each other. As described above, the N-type MFSFET 1601 and the P-type MFSFET 1602 constitute a first inverter circuit.

  The source electrode of the N-type MFSFET 1603 is connected to the negative power supply terminal having the potential of VSS, the source electrode of the P-type MFSFET 1604 is connected to the positive power supply terminal having the potential of VDD, and the gate electrode of the N-type MFSFET 1603 and the P The gate electrode of the type MFSFET 1604 is connected to each other and serves as a second input / output terminal 1606. The drain electrode of the N-type MFSFET 1603 and the drain electrode of the P-type MFSFET 1604 are connected to each other. As described above, the N-type MFSFET 1603 and the P-type MFSFET 1604 constitute a second inverter circuit.

  The drain electrodes of the N-type MFSFET 1601 and the P-type MOSFET 1602 constituting the first inverter circuit are connected to the second input / output terminal 1606, and the drain electrodes of the N-type MFSFET 1603 and the P-type MFSFET 1604 constituting the second inverter circuit are The first input / output terminal 1605 is connected, and the first inverter circuit and the second inverter circuit constitute a latch circuit.

  In the above configuration, the first inverter circuit and the second inverter circuit are configured to be the same or symmetrical in the layout pattern, and the characteristics of each MFSFET of each PN are the same in the corresponding elements.

  In FIG. 16, since the N-type MFSFET 1601 and the P-type MFSFET 1602 constitute the first inverter circuit, when a positive high potential is applied to the gate portion, the drain electrode becomes a negative low potential, and the N-type MFSFET 1601 is turned on (ON At the same time, the ferroelectric thin film in the gate portion is polarized in the direction of a low threshold voltage that facilitates conduction. In addition, the P-type MFSFET 1602 is turned off (OFF), and at the same time, the ferroelectric thin film in the gate portion is polarized in the direction of a higher threshold voltage that is turned off.

  In addition, since the N-type MFSFET 1603 and the P-type 1604 constitute the second inverter circuit, when a positive high potential is applied to the gate portion, the drain electrode becomes a negative low potential, and the N-type MFSFET 1603 is turned on. At the same time, the ferroelectric thin film in the gate portion is polarized in a direction toward a low threshold voltage that facilitates conduction. In addition, the P-type MFSFET 1604 is turned off (OFF), and at the same time, the ferroelectric thin film in the gate portion is polarized in the direction of a higher threshold voltage that is turned off.

  The first inverter circuit composed of the N-type MFSFET 1601 and the P-type MFSFET 1602 and the second inverter circuit composed of the N-type MFSFET 1603 and the PMFSFET type 1604 constitute a latch circuit in which the respective inputs and outputs are separated from each other. When one input / output terminal 1605 becomes a positive high potential VDD, the second input / output terminal 1606 becomes a negative low potential VSS. Accordingly, at this time, the ferroelectric thin film in the gate portion is polarized so that the N-type MFSFET 1601 and the P-type MFSFET 1604 are turned on (ON) and become a threshold voltage that is more easily conducted. In addition, the ferroelectric thin film in the gate portion is polarized so that the N-type MFSFET 1603 and the P-type MFSFET 1602 are turned off (OFF) and the threshold voltage is further turned off.

  Further, when the first input / output terminal 1605 becomes a negative low potential VSS, the second input / output terminal 1606 becomes a positive high potential VDD. Therefore, at this time, the ferroelectric thin film in the gate portion is polarized so that the N-type MFSFET 1601 and the P-type MFSFET 1604 are turned off and become a threshold voltage that is turned off. In addition, the ferroelectric thin film in the gate portion is polarized so that the N-type MFSFET 1603 and the P-type MFSFET 1602 are turned on (ON) and become a threshold voltage that is more easily conducted.

  As described above, when the power supply is cut off regardless of whether the input / output terminal of the latch circuit of FIG. 16 is positive or negative, the ferroelectric thin film of the gate portion of each MFSFET is reflected so that the state of each MFSFET of the latch circuit at that time is reflected. It is memorized as remanent polarization. Therefore, although there are two stable states for the latch circuit, when the power is turned on again, each MFSFET has a residual polarization and a threshold voltage bias that reflect the previous state. Return.

  As described above, it has been found that the nonvolatile data is held and restored by the ferroelectric transistor latch circuit of FIG. 16, but when the held data is read from the latch circuit of FIG. 16, the input / output terminal 1605 or the input / output terminal The potential of 1606 may be read. At this time, the MFSFETs 1601, 1602, 1603, 1604 and the like do not need to perform special operations. When new data is written to the latch circuit, a positive high potential VDD or a negative low potential VSS with low impedance may be applied to the input / output terminal 1605 or the input / output terminal 1606. When new signal data is added with low impedance, the latch circuit is determined in a state corresponding to the new signal data, and the internal polarization of the ferroelectric in the gate portions such as MFSFETs 1601, 1602, 1603, and 1604 is also changed accordingly.

  Therefore, the configuration of FIG. 16 realizes a nonvolatile latch circuit capable of reading and writing using a ferroelectric transistor.

  18 and 19 simply represent the polarization in each stable state of the latch circuit described above and the state of the induced carrier as a schematic diagram. FIG. 18 shows the case where the input / output terminal 1605 has a positive high potential VDD in the circuit of FIG. 16, and FIG. 19 shows the case where the input / output terminal 1606 has a positive high potential VDD in the circuit of FIG.

(Configuration example 2 of ferroelectric transistor latch circuit)
FIG. 24 is a circuit diagram showing a second configuration example of the ferroelectric transistor latch circuit used in the present invention. In FIG. 24, 2402 and 2404 are P-type MOSFETs, which are used instead of the P-type MFSFETs 1602 and 1604 in FIG. The other elements have the same configuration in FIG. 24 and FIG.

  Also in the circuit of FIG. 24, since the N-type MFSFETs 2401 and 2403 are used, the polarization reflecting the potential state is written, stored as the residual polarization even when the power is turned off, and the residual polarization reflecting the previous state after the power is turned on again. Since the threshold voltage is biased, the stable state before the power is turned off is restored.

(Configuration Example 3 of Ferroelectric Transistor Latch Circuit)
FIG. 25 is a circuit diagram showing a third configuration example of the ferroelectric transistor latch circuit used in the present invention. In FIG. 25, 2501 and 2503 are N-type MOSFETs, which are used in place of the N-type MFSFETs 1601 and 1603 in FIG. The other elements have the same configuration in FIG. 25 and FIG.

  Also in the circuit of FIG. 25, since the P-type MFSFETs 2502 and 2504 are used, the polarization reflecting the potential state is written, stored as the residual polarization even when the power is turned off, and the residual polarization reflecting the previous state after the power is turned on again. Since the threshold voltage is biased, the stable state before the power is turned off is restored.

(Configuration and operating principle of ferroelectric capacitor latch circuit system)
Next, a method using a latch circuit with two inverters and a ferroelectric capacitor as a ferroelectric latch circuit will be described. This method is hereinafter referred to as a ferroelectric capacitor latch circuit.

  There are various ferroelectric capacitor latch circuits, but a configuration example is shown below.

(Configuration example 1 of a ferroelectric capacitor latch circuit)
FIG. 26 is a circuit diagram showing a first example of a ferroelectric capacitor latch circuit.
In FIG. 26, reference numerals 261 and 262 denote ferroelectric capacitors. Reference numeral 263 denotes an N-type insulated gate field effect transistor (MOSFET), and reference numeral 265 denotes a P-type MOSFET. The source electrode of the N-type MOSFET 263 is connected to a negative power supply terminal having a potential of VSS, the source electrode of the P-type MOSFET 265 is connected to a positive power supply terminal having a potential of VDD, and the N-type MOSFET 263 and the P-type MOSFET 265 are respectively connected. The gate electrode is connected to each other, and the drain electrode is also connected to each other. The N-type MOSFET 263 and the P-type MOSFET 265 constitute an inverter circuit 2635.

  264 is an N-type MOSFET, and 266 is a P-type MOSFET. The source electrode of the N-type MOSFET 264 is connected to a negative power supply terminal having a potential of VSS, the source electrode of the P-type MOSFET 266 is connected to a positive power supply terminal having a potential of VDD, and the N-type MOSFET 264 and the P-type MOSFET 266 are respectively connected. The gate electrode is connected to each other, and the drain electrode is also connected to each other. The N-type MOSFET 264 and the P-type MOSFET 266 constitute an inverter circuit 2646.

  The output of the inverter circuit 2635 is connected to the input of the inverter circuit 2646 through resistance means 2697 formed of polysilicon. The output of the inverter circuit 2646 is connected to the input of the inverter circuit 2635 through the resistance means 2698 made of the polysilicon. As described above, the inverter circuit 2635 and the inverter circuit 2646 form a latch circuit.

  The output of the inverter circuit 2635 is connected to the input / output terminal 267 through the resistance means 2695. The ferroelectric capacitor 261 has a first terminal connected to the input / output terminal 267 and a second terminal connected to the input of the inverter circuit 2635. One end of the capacitor 2691 is connected to the input / output terminal 267, and the other end is connected to the positive power supply terminal VDD. One end of the capacitor 2693 is connected to the second terminal of the ferroelectric capacitor 261, and the other end is connected to the negative power supply terminal VSS.

  The output of the inverter circuit 2646 is connected to the input / output terminal 268 via the resistance means 2696. The ferroelectric capacitor 262 has a first terminal connected to the input / output terminal 268 and a second terminal connected to the input of the inverter circuit 2646. One end of the capacitor 2692 is connected to the input / output terminal 268 and the other end is connected to the positive power supply terminal VDD. One end of the capacitor 2694 is connected to the second terminal of the ferroelectric capacitor 262, and the other end is connected to the negative power supply terminal VSS.

  In the above, the ferroelectric capacitors 261 and 262, the N-type MOSFETs 263 and 264, the P-type MOSFETs 265 and 266, the capacitors 2691 and 2692, the capacitors 2693 and 2694, the resistance means 2695 and 2696, and the resistance means 2697 and 2698 have the same shape, respectively. Yes, the same characteristics. In addition, it is desirable that the layout pattern in which the above elements are arranged and connected is also the same or symmetrical.

  Since the inverter circuit 2635 and the inverter circuit 2646 constitute a latch circuit as described above, the latch circuit has two stable states. That is, the input / output terminal 267 is −VSS corresponding to a low potential, the input / output terminal 268 is + VDD corresponding to a high potential, and the input / output terminal 267 is + VDD corresponding to a high potential. 268 is a second state of −VSS corresponding to a low potential.

FIG. 27 is a circuit diagram that expresses FIG. 26 functionally and easily. FIG. 28 shows a stable state when power is supplied in the circuit diagram of FIG. (281A) in FIG. 28 shows the first state, and (282A) shows the second state. That is, in the first state, the input / output terminal 267 is −VSS corresponding to a low potential, and the input / output terminal 268 is + VDD corresponding to a high potential. In the second state, the input / output terminal 267 is + VDD corresponding to a high potential, and the input / output terminal 268 is −VSS corresponding to a low potential. Now, the ferroelectric capacitors 261 and 262 shown in FIGS. 26 and 27 cause polarization inside due to the potential state in this state. The states of polarization at this time are represented by the respective states of (281A) showing the first state and (282A) showing the second state in FIG. 28, and the polarization states inside the ferroelectric capacitor in each state are expressed. That is, in the situation where the input / output terminal 267 is −VSS and the input / output terminal 268 is + VDD, the ferroelectric capacitors 261 and 262 are positive in the capacitor side on the input / output terminal 267 side and the capacitor electrode on the input / output terminal 268 side. The side causes negative polarity polarization inside the ferroelectric thin film. Further, in the situation where the input / output terminal 267 is + VDD and the input / output terminal 268 is −VSS, the ferroelectric capacitors 261 and 262 have a negative polarity on the capacitor side on the input / output terminal 267 side and a capacitor on the input / output terminal 268 side. On the electrode side, positive polarity polarization occurs inside the ferroelectric thin film.
Next, a case where the power is turned off will be described. In the polarization described above, when the power is turned off in FIG. 26, the polarization charge amount decreases, but the residual polarization at characteristic points 3802 and 3805 in FIG. 38 remains and is stored. FIG. 28 (281B) and (282B) show the state of internal polarization when the power is cut off, that is, when the input / output terminals 267 and 268 are both at the ground potential of zero. In the circuit diagram of FIG. 26, -VSS, which is a negative power source, is used as a ground potential. Now, after turning off the power, the potential of each circuit settles to the ground potential after a while. However, as described above, the internal polarization of the ferroelectric capacitor is stored as remanent polarization.

  Next, the case where the power is turned on again will be described. The capacitors 2691 and 2692 in FIG. 26 have a charge of 0 when the power is turned off. Since one end of the capacitor is connected to the positive power supply terminal + VDD, the input / output terminals 267 and 268 try to follow the potential on the positive power supply terminal + VDD side when the power is turned on again. In other words, the input / output terminals 267 and 268 of the ferroelectric capacitors 261 and 262 try to follow the potential on the positive power supply terminal + VDD side. On the other hand, the capacitors 2693 and 2694 are zero in charge when the power is turned off, and one end of the capacitor is connected to the negative power supply terminal -VSS, so that the ferroelectric capacitors 261 and 262 are turned on when the power is turned on again. The terminal on the opposite side of the input / output terminal attempts to follow the potential on the negative power supply terminal -VSS side.

Actually, if the capacitances of the ferroelectric capacitors 261 and 262 are Cf, the capacitances of the capacitors 2691 and 2692 are C1, and the capacitances of the capacitors 2893 and 2694 are C2, the ferroelectric capacitors 261 and 262 The potential V1 of the input / output terminals 267 and 268, which are one ends, is
V1 = VDD.C1 (Cf + C2) / (C2Cf + C1C2 + C1Cf)
It becomes.
The potential V2 at the other end of the ferroelectric capacitors 261 and 262 is
V2 = VDD. (C1Cf) / (C2Cf + C1C2 + C1Cf)
It becomes. Therefore, the potentials of V1 and V2 at the time of power-on change depending on how the values of Cf, C1, and C2 are selected. However, as an extreme example, in the case of Cf << C1 and Cf << C2, V1≈VDD And V2≈0. That is, the ferroelectric capacitors 261 and 262 can be applied with a potential close to + VDD at one end and −VSS (zero potential) at the other end when the power is turned on. Therefore, a voltage close to the voltage between the power supplies + VDD is applied to both ends of the ferroelectric capacitor electrode.

  This corresponds to applying the voltage V to the ferroelectric capacitor at the characteristic point 3802 or 3805 where the voltage between the electrodes is 0 in the diagram of FIG. At this time, if the residual polarization corresponds to the characteristic point 3805, the amount of change in charge is small, and if it is 3802, the amount of change in charge is large. Here, a small amount of fluctuation in charge means that there is little fluctuation in potential at the other electrode of the electrode to which a potential is applied, and a large amount of fluctuation in charge means that the other end of the electrode to which a potential is applied. This means that the potential fluctuation at the electrode is large.

  Accordingly, when the power is turned on again, the input / output terminals 267 and 268 operate as if + VDD is applied due to the action of the capacitors 2691 and 2692. At this time, the internal polarization of the ferroelectric capacitor 261 or 262 is changed to the input / output. In the electrode on the terminal 267 or 268 side, the negative remanent polarization, that is, the one that induces a positive charge outside the electrode corresponds to the characteristic point 3805 in FIG. Few. Further, the characteristic point 3802 of FIG. 38 shows that the internal polarization of the ferroelectric capacitor 261 or 262 induces a positive remanent polarization, that is, a negative charge outside the electrode, at the input / output terminal 267 or 268 side electrode. The charge transfer is large and the potential fluctuation at the other end is also large.

  Therefore, for example, when the power is turned on again with residual polarization as shown in FIG. 28 (281B), + VDD is applied to the electrode on the input / output terminal 267 side of the ferroelectric capacitor 261 due to the action of the capacitor 2691. At this time, the electrode on the input / output terminal 267 side of the ferroelectric capacitor 261 induces a positive remanent polarization, that is, a negative charge outside the electrode in the state of (261B). In this state, the amount of charge transfer is relatively large and the potential fluctuation is large. Therefore, the other end of the ferroelectric capacitor 261 greatly fluctuates from 0 potential to the positive potential side, and a large positive potential is applied to the input terminal of the inverter circuit 2635.

  On the other hand, due to the action of the capacitor 2692, similarly, the electrode on the input / output terminal 268 side of the ferroelectric capacitor 262 acts as if + VDD is applied, but at this time, the input / output of the ferroelectric capacitor 262 is performed. In the state of (261B), the electrode on the terminal 268 side has negative remanent polarization, that is, a state in which positive charge is induced outside the electrode, so that the amount of moving charge is relatively small and the potential fluctuation is small. Therefore, the other end of the ferroelectric capacitor 262 hardly fluctuates from 0 potential, and a potential close to 0 potential is applied to the input terminal of the inverter circuit 2646. Thus, a relatively large positive potential is applied to the input terminal of the inverter circuit 2635, and a potential that is relatively close to 0 potential is applied to the input terminal of the inverter circuit 2646. As a result, the latch circuit including the inverter circuits 2635 and 2646 settles to a stable state in which the input / output terminal 267 becomes −VSS (0 potential) and the input / output terminal 268 becomes + VDD. This is the state (281A) before the power is turned off. That is, it means that the state before power-off is restored after power-on again.

  Actually, Cf, C1, and C2 are values that cannot be ignored. Therefore, V1 has a potential lower than + VDD, V2 has a potential higher than 0, and the voltage between the electrodes of the ferroelectric capacitors 261 and 262 is + VDD. Although only a lower voltage is applied, it is clear from FIGS. 38 and 39 that there is a difference in charge amount due to the difference in remanent polarization, which is sufficient for the symmetrically configured latch circuit to select the original state. It becomes biased.

  When the power is turned on again in the second state (282B) in FIG. 28 with residual polarization, the capacitor 2691 causes the electrode on the input / output terminal 267 side of the ferroelectric capacitor 261 to be applied. It operates as if it is operated with a potential close to + VDD. At this time, the electrode on the input / output terminal 267 side of the ferroelectric capacitor 261 has negative residual polarization, that is, outside the electrode in the state of (281B). Since the positive charge is induced, the potential fluctuation is small. Therefore, the other end of the ferroelectric capacitor 11 hardly fluctuates from 0 potential, and a potential close to 0 potential is applied to the input terminal of the inverter circuit 2635.

  On the other hand, due to the action of the capacitor 2692, the electrode on the input / output terminal 268 side of the ferroelectric capacitor 262 acts as if it is operated by applying a potential close to + VDD. At this time, the ferroelectric capacitor 262 is operated. In the state of (282B), the electrode on the input / output terminal 268 side has a positive remanent polarization, that is, a state in which a negative charge is induced outside the electrode, and therefore the potential fluctuation is large. Accordingly, the other end of the ferroelectric capacitor 262 greatly fluctuates from the 0 potential to the positive potential side, and a large positive potential is applied to the input terminal of the inverter circuit 2646. Thus, a potential that is relatively close to 0 potential is applied to the input terminal of the inverter circuit 2635, and a relatively large positive potential is applied to the input terminal of the inverter circuit 2646. As a result, the latch circuit including the inverter circuits 2635 and 2646 settles to a stable state in which the input / output terminal 267 becomes + VDD and the input / output terminal 268 becomes −VSS (0 potential). This is the state (282A) before the power is turned off. That is, it means that the state before power-off is restored after power-on again.

  As described above, in any of the two stable states, the state is restored to the state before the power is turned off after the power is turned on again by the residual polarization of the ferroelectric capacitor. FIG. 28 shows the respective potentials and polarization states of the circuit at the time of stabilization before the power-off described above, and the respective potentials and polarization states of the circuit at the time of power-off. The relationship of returning to the state before cutting is schematically expressed.

  Note that resistance means 2695, 2696, 2697, and 2698 are provided in FIG. 26 so that the above operation proceeds as intended and promptly. In other words, after the power is turned on again, in a transient short time when the latch circuit goes to the state before the power is turned off, the charge read from the ferroelectric capacitor is prevented from being dissipated to other than the input terminal of the inverter circuit, This prevents unnecessary charges and potentials from entering from other paths.

  The structure of the ferroelectric capacitors 261 and 262 in FIGS. 26 and 27 has the structure shown in FIG. In FIG. 36, the above-described PZTN, PZT, and SBT are suitable for the ferroelectric thin film 3640. Among these, PZTN is more desirable because it has a large residual polarization and hysteresis characteristics with good squareness. In addition, platinum (Pt) is generally used for the metal electrodes 3641 and 3642 in FIG.

  As described above, it has been found that the nonvolatile data is held and restored by the ferroelectric capacitor latch circuit of FIG. 26. However, when the held data is read from the latch circuit of FIG. 26, the input / output terminal 267 or the input / output terminal is read. What is necessary is to read the potential of 268. At this time, the ferroelectric capacitors 261 and 263 do not need to perform special operations, and data is not destroyed. When new data is written to the latch circuit, a positive high potential VDD or a negative low potential VSS with low impedance may be applied to the input / output terminal 267 or the input / output terminal 268. When new signal data is added at a low impedance, the latch circuit is determined in a state corresponding to the new signal data, and the internal polarization of the ferroelectric capacitors 261 and 262 is also changed accordingly.

  Therefore, the configuration of FIG. 26 realizes a nonvolatile latch circuit capable of reading and writing using a ferroelectric capacitor.

(Configuration example 2 of ferroelectric capacitor latch circuit)
FIG. 29 is a circuit diagram showing a second configuration example of the ferroelectric capacitor latch circuit. In FIG. 29, reference numerals 261 and 262 denote ferroelectric capacitors. Reference numeral 263 denotes an N-type MOSFET, and reference numeral 265 denotes a P-type MOSFET. The source electrode of the N-type MOSFET 263 is connected to a negative power supply terminal having a potential of VSS, the source electrode of the P-type MOSFET 265 is connected to a positive power supply terminal having a potential of VDD, and the N-type MOSFET 263 and the P-type MOSFET 265 are respectively connected. The gate electrode is connected to each other, the drain electrode is also connected to each other, and the N-type MOSFET 263 and the P-type MOSFET 265 constitute an inverter circuit 135.

  264 is an N-type MOSFET, and 266 is a P-type MOSFET. The source electrode of the N-type MOSFET 264 is connected to a negative power supply terminal having a potential of VSS, the source electrode of the P-type MOSFET 266 is connected to a positive power supply terminal having a potential of VDD, and the N-type MOSFET 264 and the P-type MOSFET 266 are respectively connected. The gate electrode is connected to each other, and the drain electrode is also connected to each other. The N-type MOSFET 264 and the P-type MOSFET 266 constitute an inverter circuit 2646.

  The output of the inverter circuit 2635 is connected to the input of the inverter circuit 2646. The output of the inverter circuit 2646 is connected to the input of the inverter circuit 2635. As described above, the inverter circuit 2635 and the inverter circuit 2646 form a latch circuit.

  The output of the inverter circuit 2635 is connected to the input / output terminal 267. The ferroelectric capacitor 261 has a first terminal connected to the input / output terminal 267 and a second terminal connected to the input of the inverter circuit 2635. One end of the capacitor 2691 is connected to the input / output terminal 267, and the other end is connected to the positive power supply terminal VDD. One end of the capacitor 2693 is connected to the second terminal of the ferroelectric capacitor 261, and the other end is connected to the negative power supply terminal VSS.

  The output of the inverter circuit 2646 is connected to the input / output terminal 268. The ferroelectric capacitor 262 has a first terminal connected to the input / output terminal 268 and a second terminal connected to the input of the inverter circuit 2646. One end of the capacitor 2692 is connected to the input / output terminal 268 and the other end is connected to the positive power supply terminal VDD. One end of the capacitor 2694 is connected to the second terminal of the ferroelectric capacitor 262, and the other end is connected to the negative power supply terminal VSS.

  In the above, the ferroelectric capacitors 261 and 262, the N-type MOSFETs 263 and 264, the P-type MOSFETs 265 and 266, the capacitors 2691 and 2692, and the capacitors 2693 and 2694 have the same shape and the same characteristics. In addition, it is desirable that the layout pattern in which the above elements are arranged and connected is also the same or symmetrical.

  The configuration of FIG. 29 is a configuration in which the resistance means 2695, 2696, 2697, and 2698 in the circuit of FIG. 26 are omitted, and the other configurations are the same as the circuit of FIG. 29, the output impedance of the inverter circuit 2635 is increased by changing the channel lengths of the N-type MOSFET 263 and the P-type MOSFET 265, and the function of the resistance means 2695 of FIG. Yes. Similarly, the function of the resistance means 2696 in FIG. In addition, the resistance means 2697 and 2698 in FIG. 26 are substituted with polysilicon used for the gate electrodes of the MOSFETs 263, 264, 265, and 266 in FIG. 29 to have substantial functions. Therefore, in FIG. 29, the resistance means 2695, 2696, 2697, and 2698 in FIG. 2 are not on the circuit diagram, but the function of the resistance means is substituted to provide a ferroelectric capacitor latch circuit similar to the circuit in FIG. Has function. In the case of FIG. 29, there is an effect that an area occupied by the layout pattern can be reduced.

(Configuration example 3 of a ferroelectric capacitor latch circuit)
FIG. 30 is a circuit diagram showing a third configuration example of the ferroelectric capacitor latch circuit.
In FIG. 30, reference numerals 261 and 262 denote ferroelectric capacitors. Reference numeral 263 denotes an N-type MOSFET, and reference numeral 265 denotes a P-type MOSFET. The source electrode of the N-type MOSFET 263 is connected to a negative power supply terminal having a potential of VSS, the source electrode of the P-type MOSFET 265 is connected to a positive power supply terminal having a potential of VDD, and the N-type MOSFET 263 and the P-type MOSFET 265 are respectively connected. The gate electrode is connected to each other, and the drain electrode is also connected to each other. The N-type MOSFET 263 and the P-type MOSFET 265 constitute an inverter circuit 2635.

  264 is an N-type MOSFET, and 266 is a P-type MOSFET. The source electrode of the N-type MOSFET 264 is connected to a negative power supply terminal having a potential of VSS, the source electrode of the P-type MOSFET 266 is connected to a positive power supply terminal having a potential of VDD, and the N-type MOSFET 264 and the P-type MOSFET 266 are respectively connected. The gate electrode is connected to each other, and the drain electrode is also connected to each other. The N-type MOSFET 264 and the P-type MOSFET 266 constitute an inverter circuit 2646.

  The output of the inverter circuit 2635 is connected to the input of the inverter circuit 2646 through the resistance means 2697. The output of the inverter circuit 2646 is connected to the input of the inverter circuit 2635 through the resistance means 2698. As described above, the inverter circuit 2635 and the inverter circuit 2646 form a latch circuit.

  The output of the inverter circuit 2635 is connected to the input / output terminal 267 through the resistance means 2695. The ferroelectric capacitor 261 has a first terminal connected to the input / output terminal 267 and a second terminal connected to the input of the inverter circuit 2635. One end of the high dielectric capacitor 3091 is connected to the input / output terminal 267, and the other end is connected to the positive power supply terminal VDD. One end of the high-dielectric capacitor 3093 is connected to the second terminal of the ferroelectric capacitor 261, and the other end is connected to the negative power supply terminal VSS.

  The output of the inverter circuit 2646 is connected to the input / output terminal 268 via the resistance means 2696. The ferroelectric capacitor 262 has a first terminal connected to the input / output terminal 268 and a second terminal connected to the input of the inverter circuit 146. One end of the high dielectric capacitor 3092 is connected to the input / output terminal 268, and the other end is connected to the positive power supply terminal VDD. One end of the high-dielectric capacitor 3094 is connected to the second terminal of the ferroelectric capacitor 262, and the other end is connected to the negative power supply terminal VSS.

  Note that the ferroelectric capacitors 261 and 262 are represented by the symbols in FIG. 37A, and the high-dielectric capacitors 3091, 3092, 3093, and 3094 are represented by the symbols in FIG. The ferroelectric capacitors 261 and 262 and the high-dielectric capacitors 3091, 3092, 3093, and 3094 have the same structure as shown in FIG. 36. However, there may be a difference in whether a high dielectric capacitor having a high relative dielectric constant is obtained. Here, the high dielectric capacitors 3091, 3092, 3093, and 3094 are structurally identical to the ferroelectric capacitors, but one end of the capacitor is connected to the positive power supply terminal VDD or the negative power supply terminal VSS. This is a usage in which the positive / negative of the potential between the terminals is not reversed, and therefore the hysteresis characteristic is not exhibited. Therefore, the symbol in FIG. 37 (b) is used.

  Compared with the circuit configuration of FIG. 26, the circuit configuration of FIG. 30 is obtained by replacing the capacitors 2691, 2692, 2693, and 2694 in FIG. 26 with high dielectric capacitors 3091, 3092, 3093, and 3094, respectively, in FIG. Other than that, FIG. 26 and FIG. 30 have the same configuration. In FIG. 26, capacitors 2691, 2692, 2693, and 2694 preferably have large capacitance values that can be compared with the ferroelectric capacitors 261 and 262. At this time, when a nitride material containing silicon dioxide (SiO2) or nitrogen generally used as a capacitor is sandwiched between metal electrodes, the relative permittivity of the substance is compared with the relative permittivity of the ferroelectric. It is very small and requires a large area. Therefore, in FIG. 30, a high dielectric capacitor having a large relative dielectric constant is used to reduce the occupied area. As described above, the high dielectric capacitors 3091, 3092, 3093, and 3094 in FIG. 30 are actually formed in the same structure as the ferroelectric capacitors 261 and 262. The circuit of FIG. 30 has an effect that the occupied area is reduced because the capacitors 2691, 2692, 2693, and 2694 of the circuit of FIG. 26 become the high dielectric capacitors 3091, 3092, 3093, and 3094 in FIG.

(Configuration example 4 of ferroelectric capacitor latch circuit)
FIG. 32 is a circuit diagram showing a fourth configuration example of the ferroelectric capacitor latch circuit.
In FIG. 32, reference numerals 261 and 262 denote ferroelectric capacitors. Reference numeral 263 denotes an N-type MOSFET, and reference numeral 265 denotes a P-type MOSFET. The source electrode of the N-type MOSFET 263 is connected to a negative power supply terminal having a potential of VSS, the source electrode of the P-type MOSFET 265 is connected to a positive power supply terminal having a potential of VDD, and the N-type MOSFET 263 and the P-type MOSFET 265 are respectively connected. The gate electrode is connected to each other, and the drain electrode is also connected to each other. The N-type MOSFET 263 and the P-type MOSFET 265 constitute an inverter circuit 2635.

  264 is an N-type MOSFET, and 266 is a P-type MOSFET. The source electrode of the N-type MOSFET 264 is connected to a negative power supply terminal having a potential of VSS, the source electrode of the P-type MOSFET 266 is connected to a positive power supply terminal having a potential of VDD, and the N-type MOSFET 264 and the P-type MOSFET 266 are respectively connected. The gate electrode is connected to each other, and the drain electrode is also connected to each other. The N-type MOSFET 264 and the P-type MOSFET 266 constitute an inverter circuit 2646.

  The output of the inverter circuit 2635 is connected to the input of the inverter circuit 2646 through a transmission gate resistance means 3297 comprising a P-type MOSFET 3254 and an N-type MOSFET 3253. The output of the inverter circuit 2646 is connected to the input of the inverter circuit 2635 through a transmission gate resistance means 3298 composed of a P-type MOSFET 3252 and an N-type MOSFET 3251. As described above, the inverter circuit 2635 and the inverter circuit 2646 form a latch circuit.

  The output of the inverter circuit 2635 is connected to the input / output terminal 267 through the resistance means 2695. The ferroelectric capacitor 261 has a first terminal connected to the input / output terminal 267 and a second terminal connected to the input of the inverter circuit 2635. One end of the capacitor 2691 is connected to the input / output terminal 267, and the other end is connected to the positive power supply terminal VDD. One end of the capacitor 2693 is connected to the second terminal of the ferroelectric capacitor 261, and the other end is connected to the negative power supply terminal VSS.

  The output of the inverter circuit 2646 is connected to the input / output terminal 268 via the resistance means 2696. The ferroelectric capacitor 262 has a first terminal connected to the input / output terminal 268 and a second terminal connected to the input of the inverter circuit 2646. One end of the capacitor 2692 is connected to the input / output terminal 268 and the other end is connected to the positive power supply terminal VDD. One end of the capacitor 2694 is connected to the second terminal of the ferroelectric capacitor 262, and the other end is connected to the negative power supply terminal VSS.

  In FIG. 26, the resistance means 2695, 2696, 2697, and 2698 are used in FIG. 26. In FIG. 32, transmission gates 3297 and 3298 using P-type MOSFETs and N-type MOSFETs are used as the resistance means 2697 and 2698. Note that the gate electrodes of the P-type MOSFETs 3252 and 3254 are connected to VSS, and the gate electrodes of the N-type MOSFETs 3251 and 3253 are connected to VDD. The other structure is the same in FIG. 26 and FIG.

  FIG. 31 shows a general transmission gate circuit configuration. In FIG. 31, 3151 is an N-type MOSFET, and 3152 is a P-type MOSFET. The source or drain electrodes of the N-type MOSFET 3151 and the P-type MOSFET 3152 are connected to each other, one end being a terminal 3153 and the other end being a terminal 3154. The gate electrode of the N-type MOSFET 3151 is connected to VDD, the gate electrode of the P-type MOSFET 3152 is connected to VSS, and both are turned on. The P-type MOSFET 3152 easily transmits a high-potential side signal potential, and the N-type MOSFET 3151 easily transmits a low-potential signal potential. Therefore, since the N-type MOSFET 3151 and the P-type MOSFET 3152 are connected in parallel, a signal on the low potential side and a signal on the high potential side are transmitted.

  In FIG. 32, as described above, transmission gates 3297 and 3298 made of MOSFET are used as resistance means. In the case of resistance means by MOSFET, it is easy to maintain the magnitude relationship with the impedance of the inverter circuit by MOSFETs 263, 265 and 264, 266, and it is easy to configure resistance means of appropriate impedance, and it is easy to make high resistance, so small occupation There is an effect that it can be formed with an area.

(Configuration Example 5 of Ferroelectric Capacitor Latch Circuit)
FIG. 33 is a circuit diagram showing a fifth configuration example of the ferroelectric capacitor latch circuit.
In FIG. 33, reference numerals 261 and 262 denote ferroelectric capacitors. Reference numeral 263 denotes an N-type MOSFET, and reference numeral 265 denotes a P-type MOSFET. The source electrode of the N-type MOSFET 263 is connected to a negative power supply terminal having a potential of VSS, the source electrode of the P-type MOSFET 265 is connected to a positive power supply terminal having a potential of VDD, and the N-type MOSFET 263 and the P-type MOSFET 265 are respectively connected. The gate electrode is connected to each other, and the drain electrode is also connected to each other. The N-type MOSFET 263 and the P-type MOSFET 265 constitute an inverter circuit 2635.

  264 is an N-type MOSFET, and 266 is a P-type MOSFET. The source electrode of the N-type MOSFET 264 is connected to a negative power supply terminal having a potential of VSS, the source electrode of the P-type MOSFET 266 is connected to a positive power supply terminal having a potential of VDD, and the N-type MOSFET 264 and the P-type MOSFET 266 are respectively connected. The gate electrode is connected to each other, and the drain electrode is also connected to each other. The N-type MOSFET 264 and the P-type MOSFET 266 constitute an inverter circuit 2646.

  The output of the inverter circuit 2635 is connected to the input of the inverter circuit 2646 through a transmission gate resistance means 3297 comprising a P-type MOSFET 3254 and an N-type MOSFET 3253. The output of the inverter circuit 2646 is connected to the input of the inverter circuit 2635 through a transmission gate resistance means 3298 composed of a P-type MOSFET 3252 and an N-type MOSFET 3251. As described above, the inverter circuit 2635 and the inverter circuit 2646 form a latch circuit.

  The output of the inverter circuit 2635 is connected to the input / output terminal 267. The ferroelectric capacitor 261 has a first terminal connected to the input / output terminal 267 and a second terminal connected to the input of the inverter circuit 2635. One end of the high dielectric capacitor 3091 is connected to the input / output terminal 267, and the other end is connected to the positive power supply terminal VDD. One end of the high-dielectric capacitor 3093 is connected to the second terminal of the ferroelectric capacitor 261, and the other end is connected to the negative power supply terminal VSS.

  The output of the inverter circuit 2646 is connected to the input / output terminal 268. The ferroelectric capacitor 262 has a first terminal connected to the input / output terminal 268 and a second terminal connected to the input of the inverter circuit 2646. One end of the high dielectric capacitor 3092 is connected to the input / output terminal 268, and the other end is connected to the positive power supply terminal VDD. One end of the high-dielectric capacitor 3094 is connected to the second terminal of the ferroelectric capacitor 262, and the other end is connected to the negative power supply terminal VSS.

  The configuration of FIG. 33 is the basic configuration excluding the resistance means 2695 and 2696 of FIG. 26, the point that high dielectric capacitors 3091, 3092, 3093, and 3094 are used for the capacitor of FIG. 30, and the resistance means 3297 of FIG. 3298 is a combination of features using a transmission gate made of MOSFET. Therefore, the basic operation and function as the ferroelectric capacitor latch circuit are the same as those of the configuration examples 1, 2, 3, and 4 described above. By taking advantage of each feature, the occupation area is reduced while ensuring stable operation, and a practical configuration is achieved.

  In FIG. 33, there is no equivalent to the resistance means 2695 and 2696 in FIG. 26. However, if there are resistance means 3297 and 3298 by the transmission gate in FIG. 32, the resistance means 2695 and 2696 can be effectively omitted. Is possible.

  In FIG. 33, high-dielectric capacitors 3091, 3092, 3093, and 3094 are formed in the same structure as the ferroelectric capacitors 261 and 262.

(Configuration Example 6 of Ferroelectric Capacitor Latch Circuit)
FIG. 34 is a circuit diagram showing a sixth configuration example of the ferroelectric capacitor latch circuit. FIG. 34 is obtained by omitting the capacitor 2693 and the capacitor 2694 from the configuration of FIG. Capacitors 2693 and 2694 always have a small amount of parasitic capacitance, and may be sufficient in terms of characteristics. In such a case, the circuit diagram of FIG. 34 may be used.

(Configuration Example 7 of Ferroelectric Capacitor Latch Circuit)
FIG. 35 is a circuit diagram showing a seventh configuration example of the ferroelectric capacitor latch circuit. FIG. 35 is obtained by omitting capacitors 2691, 2692, 2693, and 2694 and resistance means 2695, 2696, 2697, and 2698 from the configuration of FIG. Capacitors are parasitic capacitances, and resistance means are parasitic resistances, which are always small, and may be sufficient in terms of characteristics. In such a case, the circuit diagram of FIG. 35 may be used.

(Circuit Configuration (2) of Embodiment 1 of the Ferroelectric Memory Device of the Present Invention)
Returning to FIG. 1, Example 1 of the circuit of the ferroelectric memory device according to the present invention will be described.

  The configuration and function of the ferroelectric latch circuit 101 in FIG. 1 have been described above. Next, another circuit in FIG. 1 will be described. In FIG. 1, reference numerals 102 and 103 denote inverter buffer circuits with control signals. The symbols and specific configuration of the inverter buffer circuit with control signal are shown in FIGS. 2 and 3, respectively.

  FIG. 3 shows a circuit configuration of an inverter buffer circuit with a control signal. In FIG. 3, 321 and 322 are N-type MOSFETs, and 323 and 324 are P-type MOSFETs. The source electrode of the N-type MOSFET 321 is connected to the negative power supply terminal −VSS, and the source electrode of the P-type MOSFET 324 is connected to the positive power supply terminal + VDD. The gate electrodes of the N-type MOSFET 322 and the P-type MOSFET 323 are connected to each other as an input signal terminal 331, and the drain electrodes are connected to each other as an output signal terminal 332. The source electrode of the N-type MOSFET 322 is connected to the drain electrode of the N-type MOSFET 321. The source electrode of the P-type MOSFET 323 is connected to the drain electrode of the P-type MOSFET 324. The control signal terminal 333 is connected to the gate electrode of the N-type MOSFET 321, the control signal terminal 333 is connected to the input terminal of the inverter circuit 325, and the output terminal of the inverter circuit 325 is connected to the gate electrode of the P-type MOSFET 324. ing. With the above configuration, when the control signal terminal 333 is at a high potential (High), the potential of the inverted signal of the data signal of the input signal terminal 331 is output from the output signal terminal 332. Note that when the control signal terminal 333 is at a low potential (Low), the output signal terminal 332 is in a floating state.

  FIG. 1 illustrates a configuration in which there are eight ferroelectric latch unit circuits 120 to 127, but the configuration is expanded to simplify the explanation of the operation and to other configurations. In order to show the basic circuit, first, FIG. 11 shows a case where only one ferroelectric latch unit circuit is 120, and its operation and function will be described.

  In FIG. 11, the data input signal terminal 111 is connected to the input signal terminal of the inverter buffer circuit 102 with control signal, and the output signal terminal of the inverter buffer circuit 102 with control signal is the first input terminal of the ferroelectric latch circuit 101. It is connected to the output terminal and also connected to the input signal terminal of the inverter buffer circuit 103 with control signal. The output of the NOR circuit (non-OR circuit) 104 is connected to the control signal terminal of the inverter buffer circuit 102 with control signal. The output of the NOR circuit 105 is connected to the control signal terminal of the inverter buffer circuit with control signal 103. The first input gate and the second input gate of the NAND circuit (non-logical product circuit) 107 are input signal terminals 114 and 115, respectively. The data control signal terminal 113 and the output terminal of the NAND circuit 107 are connected to the second input gate and the first input gate of the NOR circuit 105, respectively. The data control signal terminal 113 is connected to the input terminal of the inverter circuit 106, and the output terminal of the inverter circuit 106 and the output terminal of the NAND circuit 107 are connected to the second input gate and the first input gate of the NOR circuit 104, respectively. It is connected.

  With the above configuration, if either of the input signal terminals 114 and 115 is a low potential (Low) signal, the outputs of the NOR circuit 104 and the NOR circuit 105 are both low potential (Low), and the inverter buffer with a control signal is provided. The output signals of both the circuits 102 and 103 are in a floating state. That is, since the ferroelectric latch circuit 101 is in a disconnected state, the data remains stored as a residual polarization in the ferroelectric thin film even when the power is turned off. Return to the data state before the power is turned off. That is, it is a non-volatile latch circuit.

  Further, when both the input signal terminals 114 and 115 are at a high potential (High) and the data control signal terminal 113 is at a high potential (High), the output of the NOR circuit 104 becomes a high potential (High). The attached inverter buffer circuit 102 is activated, and the data at the data input signal terminal 111 is written into the ferroelectric latch circuit 101. In order to write the data at the data input signal terminal 111 to the ferroelectric latch circuit 101, the output impedance of the inverter buffer circuit with control signal 102 is sufficiently higher than the impedance of the input / output terminal of the ferroelectric latch circuit 101. Set to a low value.

  Further, when both the input signal terminals 114 and 115 are at a high potential (High) and the data control signal terminal 113 is at a low potential (Low), the output of the NOR circuit 105 becomes a high potential (High). The attached inverter buffer circuit 103 is activated, and the data of the ferroelectric latch circuit 101 is read to the data output signal terminal 112. At the time of this reading, since the ferroelectric latch circuit 101 does not change the signal, there is no signal delay related to the state change of the ferroelectric, and this operation is the response of the inverter buffer circuit 103 with a control signal. Because it depends only on sex, it is done at high speed.

  In the configuration of FIG. 11, the inverter buffer circuit with control signal 102 corresponds to the latch write circuit and the inverter buffer circuit 103 with control signal corresponds to the latch read circuit from the above-described operations and functions. Further, it can be seen that a circuit in which the NAND circuit 107, the inverter circuit 106, and the NOR circuits 104 and 105 are combined corresponds to a latch control circuit.

  In the configuration of FIG. 11, there is only one inverter buffer circuit 102 that is a latch write circuit, inverter buffer circuit 103 that is a latch read circuit, and ferroelectric latch circuit 101. . Here, the latch write circuit 102, the latch read circuit 103, and the ferroelectric latch circuit 101 are collectively defined as a ferroelectric latch unit circuit. In FIG. 11, the ferroelectric latch unit circuit is surrounded by an alternate long and short dash line 120. An internal circuit surrounded by a two-dot chain line including the NAND circuit 107, the inverter circuit 106, and the NOR circuits 104 and 105 is defined as a latch control circuit as described above. Further, when the number of the ferroelectric latch unit circuits 120 is one as shown in FIG. 11, the number of the data input terminals DI and the data output terminals DO is one, so the symbols of the entire circuit of FIG. 11 are as shown in FIG. Become.

  In FIG. 1, the ferroelectric latch unit circuit is expanded to eight. Accordingly, in FIG. 1, a total of eight ferroelectric latch unit circuits 120, 121, 122, 123, 124, 125, 126, and 127 are used for one latch control circuit 108. The eight ferroelectric latch unit circuits 120 to 127 have data input signal terminals DI1 to DI7, data output signal terminals DO1 to DO8, and 101 ferroelectric latches. Eight pieces of data are stored in the circuit, and are input / output as necessary by the control signals 116 and 117 of the latch control circuit 108. In FIG. 1, as compared with FIG. 11, eight ferroelectric latch unit circuits 120 to 127 are collectively controlled by one latch control circuit 108, so that the control efficiency is good and the chip area when an integrated circuit is formed. Is efficient and the degree of integration is high.

  1 is expressed as a symbol shown in FIG. 5 as a ferroelectric memory block unit cell circuit. An embodiment using a plurality of ferroelectric memory block unit cell circuits will be described below. In the symbols in FIG. 5, eight data input signal terminals are expressed as DI0 to DI7, and eight data output signal terminals are expressed as DO0 to DO7.

(Embodiment 2 of a ferroelectric memory device of the present invention)
FIG. 6 is a circuit block diagram showing a second embodiment of the ferroelectric memory device of the present invention. A plurality of ferroelectric memory block unit cell circuits represented by the symbols in FIG. 5 are arranged in a matrix and used efficiently. In FIG. 6, reference numeral 620 denotes a ferroelectric memory block unit cell circuit, and the same ferroelectric memory block unit cell circuits are arranged in a matrix. A specific configuration example of the ferroelectric memory block unit cell circuit 620 is the circuit configuration shown in FIG. In FIG. 6, 651 is a word line, and there are a plurality of lines per row. 652 is a bit line, and there are a plurality of bit lines per column. A specific ferroelectric latch unit circuit is selected from the ferroelectric memory block unit cell circuits arranged in a matrix by the plurality of word lines 651 and bit lines 652. Specifically, the word line 651 in FIG. 6 is connected to the first gate 114 of the NADN circuit 107 in FIG. 1, and the bit line 652 in FIG. 6 is connected to the second gate 115 of the NAND circuit 107 in FIG. Therefore, only the ferroelectric memory block unit cell circuit at the address where the plurality of word lines 651 and bit lines 652 in FIG. 6 are combined with a high potential (High) signal is activated. Reference numeral 653 in FIG. 6 denotes a control signal line for controlling reading and writing of data in the ferroelectric memory block unit cell circuit. In the circuit of FIG. 1, the control signal line 653 is connected to the control signal terminal 113 and selects whether reading or writing is performed at a low potential (Low) or a high potential (High). In FIG. 6, reference numeral 654 denotes a data input line composed of 8 units, and a plurality of bundles are arranged for each column. In FIG. 1, eight data input lines 654 are connected to DI0 and DI1, DI2, DI3, DI4, DI5, DI6, and DI7 of the data input signal terminal 111, respectively, and supply input data signals to be written. 655 in FIG. 6 is a data output line composed of 8 units, and a plurality of these bundles are arranged for each column. In FIG. 1, the eight data output lines 655 are connected to DO0 and DO1, DO2, DO3, DO4, DO5, DO6, and DO7 of the data output signal terminal 112, respectively, and transmit the read output data signal. . In FIG. 6, reference numeral 641 denotes a row decoder control circuit, which selects and controls a plurality of word lines 651 by an address. A column decoder control circuit 642 selects and controls a plurality of bit lines 652 by an address. Reference numeral 643 denotes a read / write control circuit which controls signals according to the case where data is read and the case where data is written. A data input / output control circuit 644 transmits and receives input data and output data via a data input line and a data output line.

  With the above configuration, nonvolatile signal data of the ferroelectric memory block unit cell circuit is read / written at the address designated by the row decoder control circuit 641 and the column decoder control circuit 642, and eight data are read / written to the read / write control circuit. Based on the signal 643, data is transmitted to and received from the data input / output control circuit 644 to control the ferroelectric memory device.

(Effect of Embodiment 2)
Since the ferroelectric memory device having the above configuration uses a ferroelectric latch circuit, it is nonvolatile. In addition, when reading, a signal is not given to the ferroelectric each time and it is not read, but the signal state of the ferroelectric latch circuit that is already in a stable state is only seen through the MOSFET. The reading is very fast and has a long lifetime. In the case of writing, it is only necessary to determine the state of the latch circuit by the MFSFET or MOSFET inherent in the ferroelectric latch circuit, and the polarization of the ferroelectric thin film is continuously performed once the state of the latch circuit is determined. There is no need to wait until the polarization of the ferroelectric thin film is completely completed, and it is determined by the response time of the latch circuit of the MFSFET or MOSFET, and the writing becomes very fast. The ferroelectric memory unit cell circuit 621 may be controlled by a simple digital signal such as a low potential (Low) or a high potential (High), and a high-voltage boosted signal or an intermediate potential that is often found in a nonvolatile memory. Does not require a signal. Therefore, the row decoder control circuit 641 and the column decoder control circuit 642 may be simple circuits, have a small number of elements, occupy a small area, and can operate at high speed. Further, since the output signal of the ferroelectric memory unit cell circuit 620 is a logic circuit potential such as a simple low potential (Low) or a high potential (High), a minute signal that is likely to be in a nonvolatile memory is detected. A signal detection circuit such as a high-sensitivity sense amplifier is not required. Therefore, the data input / output control circuit 644 may have a simple circuit configuration, has a small number of elements, occupies a small area, can operate at high speed, and consumes less power.

  For the above reasons, high-speed operation is faster than SRAM. When a small-capacity memory is embedded in an integrated circuit (LSI), a non-volatile memory with high SRAM speed is incorporated. There is a comparable effect.

  Further, as described above, eight ferroelectric latch unit circuits from 120 to 127 are collectively controlled by one latch control circuit 108, so that the control efficiency is good and the chip area efficiency when integrated circuit is further increased. Well, the degree of integration is high.

(Embodiment 3 of the ferroelectric memory device of the present invention)
FIG. 7 is a circuit block diagram showing a third embodiment of the ferroelectric memory device of the present invention. In FIG. 7, the data input signal line and the data output signal line are shared, and the efficiency of the occupied area of the chip is further improved.

  In FIG. 6, the data input line 654 and the data output line 655 are provided separately, but in FIG. 7, the data input / output control circuit 744 is provided with a circuit having a switching function, and the data input / output line 754 is used as the data input / output line 754. The input line 654 and the data output line 655 are combined.

(Embodiment 4 of the ferroelectric memory device of the present invention)
FIG. 8 is a circuit diagram showing a fourth embodiment of the ferroelectric memory device of the present invention. In the circuit of FIG. 1, eight ferroelectric latch unit circuits 120 are configured, whereas in FIG. 8, four ferroelectric latch unit circuits 120 are configured. Other configurations are the same. When data is configured in units of 4 bits, the circuit configuration of FIG. 8 is less wasteful and has the effect of reducing noise and power consumption during operation.

  FIG. 9 represents the circuit of FIG. 8 as a symbol of a ferroelectric memory block unit cell circuit. In the symbols in FIG. 8, four data input signal terminals are expressed as DI0 to DI3, and four data output signal terminals are expressed as DO0 to DO3.

(Embodiment 5 of a ferroelectric memory device according to the present invention)
FIG. 10 is a circuit block diagram showing a fifth embodiment of the ferroelectric memory device of the present invention. In FIG. 10, a plurality of ferroelectric memory block unit cell circuits represented by the symbols of FIG. 9 which is the circuit configuration of FIG. 8 are arranged in a matrix.

  In FIG. 10, reference numeral 1020 denotes a ferroelectric memory block unit cell circuit, and the same ferroelectric memory block unit cell circuits are arranged in a matrix. The data input signal line 1054 is a bundle of four, and the data output signal line 1055 is also a bundle of four. The other row decoder 641, column decoder 642, and read / write control circuit 643 are basically the same as those in FIG. The data input / output control circuit 1044 of FIG. 10 has the same basic configuration as the data input / output control circuit 644 of FIG. 6 except that the control unit of the number of data input lines and data output lines to be controlled is changed. is there.

  FIG. 10 shows an embodiment suitable for 4-bit data.

(Other embodiments)
The present invention is not limited to the above embodiment. Here are some examples:

(Other embodiment A)
The ferroelectric latch unit circuit 120 used in the present invention has an input / output terminal at one end of the ferroelectric latch circuit 101 as an output terminal of the inverter buffer circuit 102 with a control signal in FIG. 1, FIG. 8, and FIG. It is connected to the input terminal of the inverter buffer circuit 103 with signal. At this time, when viewed from the ferroelectric latch circuit 101, the signal line is connected to only one of the two input / output terminals, and parasitic capacitance is added. This is originally not desirable for the ferroelectric latch circuit 101 which should ensure circuit symmetry. FIG. 14 shows a countermeasure example in consideration of this point.

  14 has the same circuit configuration as that of FIG. 11 except for the signal line 1418 in FIG. In FIG. 14, the input / output terminal at one end of the latch circuit 101 is connected to the output terminal of the inverter buffer circuit with control signal 1402 and the input terminal of the inverter buffer circuit with control signal 1403. The input / output terminal at the other end of the latch circuit 101 is connected to a dummy signal line 1418. The signal line 1418 is in a floating state and has no meaning on the signal. The signal line 1418 is connected to the latch circuit 101 by adding the parasitic capacitance of the signal line 1418 to ensure symmetry as the parasitic capacitance, and the signal state when the power is turned off when the latch circuit 101 is turned on. This is to prevent malfunction when returning to the state.

(Other embodiment B)
FIG. 15 shows another method for securing the symmetry of the ferroelectric latch circuit described in the other embodiment A.
In FIG. 15, the ferroelectric latch circuit 1501 connects the output terminal of the inverter buffer circuit 102 with control signal and the input terminal of the inverter buffer circuit 103 with control signal to the first input / output terminal as described above in FIG. However, in FIG. 15, it is the same that the output terminal of the inverter buffer circuit with control signal 1502 is connected to the first input / output terminal, but the second input / output terminal of the ferroelectric latch circuit 1501 is connected to the control signal. The inverter buffer circuit 1503 is connected to the input terminal. In this connection method, since both the first input / output terminal and the second input / output terminal of the ferroelectric latch circuit 1501 are used, it is easy to balance the parasitic capacitance and to prevent malfunction. In FIG. 15, as described above, as a result of using the first input / output terminal and the second input / output terminal of the ferroelectric latch circuit 1501, the data output signal terminal 1512 becomes the inverted signal of the data input signal terminal 1511. Become. If the data is adjusted in consideration of the correctness of the data, the ferroelectric latch circuit 1501 having good symmetry can be realized in FIG. 15, and good characteristics can be secured.

(Other embodiment C)
1, 6, and 7 show examples of data handling units of 8 bits, and FIGS. 8 and 10 show examples of 4 bits, but not limited to these bits, 16 bits, 32 bits, or In general, a bit configuration of a power of 2 is possible and convenient.

(Other embodiment D)
In FIG. 1, FIG. 8, FIG. 11, FIG. 14 and FIG. 15, the ferroelectric latch circuits are arranged in rows and columns and controlled by X and Y address signals, but the row decoder control circuit 641 of FIG. When all the word lines 651 and bit lines 652 supplied from the column decoder control circuit 642 are set to a low potential (Low), all the ferroelectric memory block unit cell circuits 620 are inactivated, so that the row decoder control circuit 641 and the column decoder control circuit 642 can also have a virtual chip select function.

(Other embodiment E)
In FIG. 1, FIG. 8, FIG. 11, FIG. 14, and FIG. 15, the ferroelectric latch circuits are arranged in a matrix and controlled by X and Y address signals, but they are not necessarily address signals. A circuit configuration which is simply a signal for activating the ferroelectric latch circuit is also possible.

(Other embodiment F)
In the above description, the MOSFET is described as the device mainly constituting the circuit. However, if the circuit can be constituted, the MOSFET is not necessarily required. It may be a bipolar element, a TFT, or an organic transistor. Also in the case of MOSFET, not only a silicon (Si) substrate but also GaAs or SiGe may be used for the substrate.

1 is a circuit diagram showing a first embodiment of a ferroelectric memory device according to the present invention; The symbol figure of the inverter buffer circuit with a control signal used in the ferroelectric memory device of this invention. The circuit diagram of the inverter buffer circuit with a control signal used in the ferroelectric memory device of this invention. FIG. 3 is a symbol diagram of a ferroelectric latch circuit used in the ferroelectric memory device of the present invention. The symbol figure at the time of seeing the 1st Embodiment of the ferroelectric memory device of this invention as a ferroelectric memory block unit cell circuit. The circuit block diagram which shows the 2nd Example of the ferroelectric memory device of this invention. The circuit block diagram which shows the 3rd Example of the ferroelectric memory device of this invention. The circuit diagram which shows the 4th Example of the ferroelectric memory device of this invention. The symbol figure at the time of considering the 4th Embodiment of the ferroelectric memory device of this invention as a ferroelectric memory block unit cell circuit. FIG. 9 is a circuit block diagram showing a fifth embodiment of a ferroelectric memory device according to the present invention. 1 is a circuit diagram showing a first example of a basic configuration of a ferroelectric memory device according to the present invention. The symbol figure at the time of seeing the example of a basic composition of the ferroelectric memory device of this invention as a ferroelectric memory block unit cell circuit. The circuit block diagram which shows the 2nd example of the basic composition of the ferroelectric memory device of this invention. The circuit diagram which shows the 3rd example of the basic composition of the ferroelectric memory device of this invention. The circuit diagram which shows the 4th example of the basic composition of the ferroelectric memory device of this invention. 1 is a circuit diagram showing a first configuration example of a ferroelectric transistor latch circuit used in a ferroelectric memory device of the present invention. Sectional drawing cut | disconnected in the source / drain direction in the channel part for showing the structural example of MFSFET used for this invention. The schematic diagram which shows the mode of the polarization of the 1st state in the 1st structural example of the ferroelectric transistor latch circuit used for this invention. The schematic diagram which shows the mode of the polarization of the 2nd state in the 1st structural example of the ferroelectric transistor latch circuit used for this invention. Sectional drawing which shows the 1st polarization state of the ferroelectric thin film of N type MFSFET used for this invention. Sectional drawing which shows the 2nd polarization state of the ferroelectric thin film of N type MFSFET used for this invention. Sectional drawing which shows the 1st polarization state of the ferroelectric thin film of P-type MFSFET used for this invention. Sectional drawing which shows the 2nd polarization state of the ferroelectric thin film of P-type MFSFET used for this invention. The circuit diagram which shows the 2nd structural example of the ferroelectric transistor latch circuit used in the ferroelectric memory device of this invention. The circuit diagram which shows the 3rd structural example of the ferroelectric transistor latch circuit used in the ferroelectric memory device of this invention. 1 is a circuit diagram showing a first configuration example of a ferroelectric capacitor latch circuit used in a ferroelectric memory device of the present invention. FIG. 3 is a circuit diagram illustrating a first configuration example of a ferroelectric capacitor latch circuit used in the ferroelectric memory device of the present invention in terms of functions. The schematic diagram showing each electric potential and polarization state at the time of power supply in the circuit of the 1st example of composition of a ferroelectric capacitor latch circuit used in the present invention at the time of power supply off. The circuit diagram which shows the 2nd structural example of the ferroelectric capacitor | condenser latch circuit used in the ferroelectric memory device of this invention. The circuit diagram which shows the 3rd structural example of the ferroelectric capacitor | condenser latch circuit used in the ferroelectric memory device of this invention. 1 is a circuit diagram showing a configuration example of a transmission gate circuit used in a ferroelectric memory device of the present invention. The circuit diagram which shows the 4th structural example of the ferroelectric capacitor | condenser latch circuit used in the ferroelectric memory device of this invention. The circuit diagram which shows the 5th structural example of the ferroelectric capacitor | condenser latch circuit used in the ferroelectric memory device of this invention. The circuit diagram which shows the 6th structural example of the ferroelectric capacitor | condenser latch circuit used in the ferroelectric memory device of this invention. The circuit diagram which shows the 7th structural example of the ferroelectric capacitor | condenser latch circuit used in the ferroelectric memory device of this invention. Sectional drawing which shows the structure of the conventional ferroelectric capacitor used for this invention. The circuit symbol figure which shows the symbol of the ferroelectric capacitor and high dielectric capacitor which are used for the past and this invention. The characteristic view which shows the typical hysteresis characteristic of the applied voltage and polarization charge of the ferroelectric thin film used for the past and this invention. The schematic diagram which shows the state of the applied voltage and polarization charge of the ferroelectric thin film used for the past and this invention. The circuit diagram which shows the 1st example of the structure of the memory cell used for the conventional ferroelectric memory device. The circuit diagram which shows the 2nd example of the structure of the memory cell used for the conventional ferroelectric memory device. The circuit diagram which shows the structural example of the memory cell array used for the conventional ferroelectric memory device.

Explanation of symbols

101, 1401, 1501 ... Ferroelectric latch circuit, 102, 103, 1402, 1403, 1502, 1503 ... Inverter buffer circuit with control signal, 104, 105, 1404, 1405, 1504, 1505 ... NOR circuit, 106, 325 1406, 1506, 2635, 2646 ... inverter circuit, 107, 1407, 1507 ... NAND circuit, 108 ... latch control circuit, 111, 1411, 1511 ... data input signal terminal, 112, 1412, 1512 ... data output signal terminal, 113, 1413, 1513 ... Data control signal terminal, 114, 115, 331, 1414, 1415, 1514, 1515 ... Input signal terminal, 120, 121, 122, 123, 124, 125, 126, 127 ... Ferroelectric latch unit circuit, 261,2 2, 3649, 4011 ... Ferroelectric capacitor, 3091, 3092, 3093, 3094 ... High dielectric capacitor, 263, 264, 321, 322, 2501, 2503, 3151, 3251, 3253, 4012 ... N-type MOSFET, 265 266, 323, 324, 2402, 2404, 3152, 3252, 3254 ... P-type MOSFETs, 267, 268, 1605, 1606, 2405, 2406, 2505, 2506, 3153, 3154 ... input / output terminals, 332 ... output signal terminals, 333: Control signal terminal, 620, 1020, 1320 ... Ferroelectric memory unit cell circuit, 641 ... Row decoder control circuit, 642 ... Column decoder control circuit, 643 ... Read / write control circuit, 644, 744, 1044, 1344 ... Data input Output control times , 651, 4013, 4115, 4205 ... word line, 652, 4014, 4113, 4114, 4213, 4214 ... bit line, 116, 117, 653 ... control signal line, 654, 1054, 1354 ... data input line, 655, 1055 , 1355 ... Data output line, 754 ... Data input / output line, 1601, 1603, 2401, 2403, 4100, 4201 ... N-type MFSFET, 1602, 1604, 2502, 2504 ... P-type MFSFET, 1700, 2000, 2100, 2200, 2300, 3640... Ferroelectric thin film, 1701, 2001, 2201... Gate electrode, 1702, 1703, 2002, 2003... N + diffusion source or drain electrode, 1709, 2009, 2109, 2209, 2309. 2004, 2104, 2204, 2304, 4101 ... gate electrode terminal, 2005, 2006, 2105, 2106, 2205, 2206, 2305, 2306, 4103, 4104 ... drain electrode source or source electrode terminal, 2202, 2203 ... P + Electrodes to be diffusion source or drain, 2691, 2692, 2693, 2694... Capacitors, 2695, 2696, 2697, 2698... Resistance elements, 3297, 3298... Transmission gates, 3641, 3642 ... ferroelectric capacitor electrodes, 3801, 3802 , 3803, 3804, 3805, 3806, characteristic points, 4015, plate line, 4220, memory cell array.

Claims (6)

A ferroelectric latch circuit including a ferroelectric element and capable of holding, storing, and restoring state data independently;
A latch write circuit for writing data to the ferroelectric latch circuit;
A latch read circuit for transmitting state data of the ferroelectric latch circuit;
A plurality of latch write circuits and a latch control circuit for controlling the plurality of latch read circuits;
A ferroelectric memory device characterized by comprising: A ferroelectric latch circuit that includes a ferroelectric element and can hold, store, and restore state data independently, a latch write circuit that writes data to the ferroelectric latch circuit, and state data of the ferroelectric latch circuit A ferroelectric memory block unit cell circuit comprising: a latch read circuit for transmitting; an address detection circuit; and a latch control circuit for controlling the plurality of latch write circuits and the plurality of latch read circuits;
A plurality of ferroelectric memory block unit cell circuits, a ferroelectric memory block unit cell circuit group arranged in a matrix;
A word line group for transmitting a row address signal of the ferroelectric memory block unit cell circuit group;
A bit line group for transmitting an address signal of a column of the ferroelectric memory block unit cell circuit group;
A control signal line group for controlling reading and writing of data in the ferroelectric memory block unit cell circuit group;
A data line group composed of a plurality of units for transmitting input data or output data of the ferroelectric memory block unit cell circuit group; and
A row decoder control circuit for selectively specifying the row address of the ferroelectric memory block unit cell circuit group via the word line group;
A column decoder control circuit for selecting and specifying a column address of the ferroelectric memory block unit cell circuit group via the bit line group;
A read / write control circuit for controlling writing and reading to and from the ferroelectric memory block unit cell circuit group;
A data input / output control circuit for controlling input / output data to / from the ferroelectric memory block unit cell circuit group;
A ferroelectric memory device comprising: In claim 1 or claim 2,
A ferroelectric memory device, wherein the ferroelectric latch circuit uses a field effect transistor having a ferroelectric thin film at a gate portion. In claim 1 or claim 2,
2. A ferroelectric memory device according to claim 1, wherein the ferroelectric latch circuit uses two inverter circuits and a ferroelectric capacitor. In claim 1 or claim 2,
2. The ferroelectric memory device according to claim 1, wherein each of the plurality of latch write circuits and the plurality of latch read circuits controlled by the latch control circuit is a power of two. In claim 2,
A ferroelectric memory device characterized in that an input data line and an output data line of the ferroelectric memory block unit cell circuit group are shared.

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