JP2008011559A - Multiple differential transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To implement differential transmission of a 3-bit information signal by three signal lines in order to suppress the occurrence of noise and reduce further data signal lines. <P>SOLUTION: In a signal transmitter for a multiplex differential transmission system that comprises the signal transmitter, a signal receiver, and a transmission path comprised of a first to a third signal line, a first to a third differential driver each transmits a first to a third output signal and their inverted first to third output signal in response to bit information signals, and combines the first output signal and inverted third signal for transmission to a first signal line. Furthermore, the first to third differential driver each combines the second output signal and inverted first output signal for transmission to a second signal line, and combines the third output signal and inverted third output signal for transmission to the first signal line. A first to a third differential driver of the signal receiver each detects polarity of termination voltage generated at termination resistors that are connected between adjacent signal lines and outputs bit information signals. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multiplex differential transmission system that differentially transmits a 3-bit bit information signal via a signal transmission path composed of three signal lines.

  In recent years, in flat panel displays typified by liquid crystal televisions and plasma televisions, the signal speed for transferring image information has been increased as the image quality increases from VGA (Video Graphics Array) to XGA (eXtended Graphics Array). Yes. Therefore, a low-amplitude differential transmission method has come to be used as a high-speed digital data transmission method.

  This transmission method is a transmission method in which signals having opposite phases are transmitted through one balanced cable or two signal line patterns formed on a printed circuit board. Features include low noise, strong resistance to external noise, low voltage amplitude, high-speed data transmission, and the like, and the introduction of the high-speed transmission technique is progressing particularly in the display field.

Japanese Patent No. 3507687. JP-A-4-230147.

  The differential transmission method has many merits in the high-speed transmission as described above compared with the normal single-ended transmission method. However, since two signal lines are required for one data bit transmission, in order to realize multi-bit transmission, there are problems such as an increase in the number of signal lines and an increase in the signal line area on the printed circuit board. Had. For this reason, it has become a big issue in realizing further high-speed transmission in the future.

  With respect to this problem, for example, in the differential data transmission method disclosed in Patent Document 1, two data bit transmissions are performed using three lines (conventional data lines) by using one line as a complementary data line. The differential transmission method requires four wires), and has achieved a reduction in data signal lines, but the signals flowing through the three wires are not balanced and the radiation noise is larger than in normal differential transmission. There were problems such as becoming.

  Further, in Patent Document 2, differential transmission of a 3-bit bit information signal is performed using three signal lines. However, there is a limitation that output signals of all three differential drivers must be different, and 3 Since all three bits cannot transmit the states of 0 and 1, and only 6 states can be transmitted from 3 bits (8 states) except for the states of all 0 and 1 bits, There was a big problem.

  The first object of the present invention is to solve the above-mentioned problems, to suppress the generation of noise and to further reduce the number of data signal lines, and to perform differential transmission of a 3-bit bit information signal to a three-line signal. An object of the present invention is to provide a multiple differential transmission system that can be realized by a line, and a signal transmitter and a signal receiver used in the multiple differential transmission system.

  The second object of the present invention is to solve the above-described problems, to suppress the generation of noise, and to further reduce the number of data signal lines. And a signal transmitter and a signal receiver used in the multiple differential transmission system, and a signal transmitter and a signal receiver used for the multiple differential transmission system.

A signal transmitter according to a first invention is
A multiple differential transmission system comprising: a signal transmitter; a signal receiver; and a signal transmission path including first, second, and third signal lines connecting between the signal transmitter and the signal receiver. In the signal transmitter for
A first differential driver for transmitting a first output signal and an inverted first output signal that is a phase inverted signal of the first output signal in response to the first bit information signal;
A second differential driver for transmitting a second output signal and an inverted second output signal that is a phase inverted signal of the second output signal in response to the second bit information signal;
A third differential driver that transmits a third output signal and an inverted third output signal that is a phase inverted signal of the third output signal in response to the third bit information signal;
The first output signal and the inverted third output signal are combined and transmitted to the first signal line, and the second output signal and the inverted first output signal are combined and transmitted to the second signal line. Then, the third output signal and the inverted third output signal are combined and transmitted to the first signal line.

  In the signal transmitter, the first output signal, the inverted first output signal, the second output signal, the inverted second output signal, the third output signal, and the inverted third output signal, Have the same binary signal voltage.

  In the signal transmitter, the first output signal, the inverted first output signal, the second output signal, and the inverted second output signal have the same binary signal voltage. In addition, the third output signal and the inverted third output signal have different binary signal voltages.

A signal receiver according to a second aspect of the present invention is a signal transmission comprising a signal transmitter, a signal receiver, and first, second and third signal lines connecting the signal transmitter and the signal receiver. A signal receiver for a multiplex differential transmission system with a path,
The polarity of a termination voltage generated in a first termination resistor connected between the first signal line and the second signal line is detected, and the detection result is output as a first bit information signal. A first differential receiver;
The polarity of the termination voltage generated in the second termination resistor connected between the second signal line and the third signal line is detected, and the detection result is output as a second bit information signal. A second differential receiver;
The polarity of the termination voltage generated in the third termination resistor connected between the third signal line and the first signal line is detected, and the detection result is output as a third bit information signal. And a third differential receiver.

  In the signal receiver, the signal receiver receives each output signal from the signal transmitter.

Further, in the signal receiver that receives each output signal from the signal transmitter, it is determined whether or not the absolute value of the third termination voltage generated in the third termination resistor exceeds a predetermined threshold voltage. Comparing means to
First, second, and third bit information output from the first, second, and third differential receivers, respectively, when the absolute value of the third termination voltage does not exceed a predetermined threshold voltage While outputting a signal, when the absolute value of the third termination voltage exceeds a predetermined threshold voltage, the third bit information signal output from the third differential receiver is changed to the first, second and Control means for outputting as a third bit information signal,
The absolute value of the binary signal voltage of the third output signal is set to be larger than half of the absolute value of the binary signal voltage of the first output signal, and the threshold voltage is the same as that of the first output signal. The third output signal is set to be larger than the absolute value of the difference between the binary signal voltages.

Furthermore, in the signal receiver that receives each output signal from the signal transmitter,
Comparing means for determining whether or not the absolute value of the second termination voltage generated in the second termination resistor exceeds a predetermined threshold voltage;
First, second, and third bit information output from the first, second, and third differential receivers, respectively, when the absolute value of the second termination voltage does not exceed a predetermined threshold voltage When the absolute value of the second termination voltage exceeds a predetermined threshold voltage while the signal is output, the third bit information signal output from the third differential receiver is changed to the first, second and Control means for outputting as a third bit information signal,
The absolute value of the binary signal voltage of the third output signal is set to be larger than half the absolute value of the binary signal voltage of the first output signal.

  A multiple differential transmission system according to a third aspect of the present invention includes the signal transmitter and the signal receiver.

  According to the multiplex differential transmission system according to the present invention, differential transmission of a 3-bit bit information signal is possible with three signal lines, and the number of signals is less than in the prior art while suppressing an increase in noise. Multi-bit differential transmission is possible using a line.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

First embodiment.
FIG. 1 is a block diagram showing a configuration of a multiple differential transmission system according to a first embodiment of the present invention. In FIG. 1, the multiple differential transmission system according to the first embodiment is configured by connecting a signal transmitter 10 and a signal receiver 20 via a signal transmission path 30. The signal transmitter 1
(A) a differential driver 11 that outputs a first output signal S11a and an inverted first output signal S11b that is a phase inverted signal in response to a bit information signal B1 having a high level or a low level;
(B) in response to a bit information signal B2 having a high level or a low level, a differential driver 12 that outputs a second output signal S12a and an inverted second output signal S12b that is a phase inverted signal thereof;
(C) A differential driver 13 that outputs a third output signal S13a and an inverted third output signal S13b that is a phase inverted signal thereof in response to a bit information signal B3 having a high level or a low level. The binary voltage levels of the output signals are equal to each other at ± 1 [V], and the differential drivers 11, 12, and 13 operate so as to transmit each output signal at the rising timing of the clock CLK.

  The signal transmission path 30 includes signal lines 31, 32, and 33. Here, the first output signal S <b> 11 a from the differential driver 11 and the inverted third output signal S <b> 13 b from the differential driver 13 are combined and sent to the signal line 31. Also, the second output signal S12a from the differential driver 12 and the inverted first output signal S11b from the differential driver 11 are combined and then sent to the signal line 32. Further, the third output signal S13a from the differential driver 13 and the inverted second output signal S12b from the differential driver 12 are combined and sent to the signal line 33.

  Each of the signal receivers 20 is a bit information determination unit (consisting of a comparator that determines whether or not the termination voltages V1, V2, and V3 are negative, as will be described later with reference to FIG. 7). The differential receivers 21, 22, 23, the clock recovery circuit 24, and the three termination resistors 41, 42, 43 are configured. A termination resistor 41 is connected between the signal line 31 and the signal line 32, and the method of the current flowing through the termination resistor 41 or the polarity of the termination voltage V 1 generated in the termination resistor 41 is detected by the differential receiver 21. A termination resistor 42 is connected between the signal line 32 and the signal line 33, and the method of the current flowing through the termination resistor 42 or the polarity of the termination voltage V <b> 2 generated in the termination resistor 42 is detected by the differential receiver 22. Further, a termination resistor 43 is connected between the signal line 33 and the signal line 31, and the method of the current flowing through the termination resistor 43 or the polarity of the termination voltage V 3 generated in the termination resistor 43 is detected by the differential receiver 23. The clock recovery circuit 24 includes a rise detection circuit and a PLL circuit, and regenerates a clock CLK having a predetermined cycle by detecting a rising edge of a transmission signal transmitted to the three signal lines 31, 32, and 33. And output to each differential receiver 21, 22, 23. Each differential receiver 21, 22, 23 executes bit information determination at the rising edge of the input clock CLK, as will be described later, and outputs bit information signals B1, B2, B3, respectively.

  FIG. 2 shows the signal waveforms of the output signals S11a, S11b, S12a, S12b, S13a, and S13b of the differential drivers 11, 12, and 13 in FIG. 1, the definition of the current direction or the polarity of the signal voltage, and the bit information to be assigned. FIG. 3 is a waveform diagram showing the relationship, and FIG. 3 shows the signal waveforms of the signal voltages Vs1, Vs2, and Vs3 of the transmission signal transmitted through the signal lines 31, 32, and 33 of the signal transmission path 30 of FIG. It is a wave form diagram which shows a relationship. Each differential receiver 21, 22, 23 outputs the output signal shown in FIG. 2 according to the input bit information signal. At this time, the signal transmission is performed according to the input 3-bit bit information signal. Signal voltages Vs1, Vs2, and Vs3 of transmission signals transmitted through the signal lines 31, 32, and 33 of the path 30 are as shown in FIG.

  4 shows the relationship between bit information transmitted in the multiplex differential transmission system of FIG. 1 and signal voltages Vs1, Vs2, and Vs3 of transmission signals transmitted through the signal lines 31, 32, and 33 of the signal transmission path 30. FIG. 5 is a circuit diagram showing an equivalent circuit of the signal transmitter 10 and the signal lines 31, 32, 33 for explaining the signal voltages Vs1, Vs2, Vs3 of the signal lines 31, 32, 33 of FIG. FIG. Here, the signal voltages Vs1, Vs2, and Vs3 of the signal lines 31, 32, and 33 will be described with reference to FIGS.

Signal voltages V _i1 and V _i2 from two differential drivers (11, 12; 12, 13; 13, 11) are superimposed on each signal line 31, 32, 33. The internal resistance of each differential driver 11, 12, 13 is r, and the impedance of the termination resistors 41, 42, 43 of the signal receiver 20 is Z (the input impedance of the differential receivers 21, 22, 23 is infinite ( And the signal voltage Vs generated on each signal line 31, 32, 33 is expressed by the following equation.

  Here, since r << Z, it is approximately expressed by the following equation.

  FIG. 6 is a diagram showing the relationship between bit information transmitted in the multiple differential transmission system of FIG. 1 and the polarities of the termination voltages V1, V2, and V3 of the termination resistors 41, 42, and 43 of the signal receiver 30. .

  As apparent from FIG. 6, the current difference is caused by the potential difference (termination voltage of the termination resistors 41, 42, and 43) generated between a pair of adjacent signal lines when superimposed on the three signal lines 31, 32, and 33. By determining the direction or polarity of the termination voltage, it is possible to decode the bit information signals output by the differential drivers 11, 12, and 13 in 6 states other than when all bits are 0 and all bits are 1. It is. In addition, the signal voltage applied to each signal line 31, 32, 33 of the signal transmission path 30 is 0 in total when any bit information signal is transmitted, and is radiated from each signal line 31, 32, 33. Since the noises cancel each other, transmission with less noise is possible as in the normal differential transmission method.

  FIG. 7 is a flowchart showing bit information determination processing executed by each differential receiver 21, 22, 23 of the signal receiver 20 of FIG.

  In FIG. 7, first, in step S <b> 1, whether or not the direction of the current flowing through each termination resistor 41, 42, 43 is negative by each differential receiver 21, 22, 23 or whether each termination resistor 41, 42, 43 is It is determined whether or not the termination voltage Vi (i = 1, 2, 3) is negative. If YES, the process proceeds to step S2 and 0 is set in the bit information Bi. If NO, the process proceeds to step S3 and 1 is set in the bit information Bi. Then, the bit information determination process ends.

Second embodiment.
FIG. 8 is a block diagram showing a configuration of a multiple differential transmission system according to the second embodiment of the present invention. In FIG. 8, the multiple differential transmission system according to the second embodiment is configured by connecting a signal transmitter 10 </ b> A and a signal receiver 20 </ b> A via a signal transmission path 30. Similar to the first embodiment, the signal transmitter 10A includes three differential drivers 11, 12, 13A, and the connection method between the differential drivers 11, 12, 13A and the signal lines 31, 32, 33 is as follows. As in the first embodiment, the binary voltage levels of the output signals of the differential driver 11 and the differential driver 12 are equal to ± 1 [V], but the binary voltage level of the output signal of the differential driver 13 is It is ± 1.5 [V], and its absolute value is set higher than that of the differential drivers 11 and 12.

  The signal receiver 20A is switched and controlled in conjunction with the comparator 25 having the threshold voltage source 44 and the output signal from the comparator 25, as compared with the signal receiver 20 according to the first embodiment. It is characterized by further comprising changeover switches 26 and 27 and an absolute value calculator 28. In the second embodiment, after the absolute value calculator 28 detects the termination voltage V3 of the termination resistor 43, the absolute value calculator 28 calculates the absolute value | V3 | and outputs a voltage signal indicating the absolute value | V3 | Output to. The comparator 25 compares the absolute value | V3 | of the termination voltage V3 with the threshold voltage Vth from the threshold voltage source 44, and when | V3 |> | Vth | , 27, the changeover switches 26, 27 are switched to the contact a side. On the other hand, when | V3 | ≦ | Vth |, a low-level control signal is output to the changeover switches 26, 27. , 27 are switched to the contact b side. Each differential receiver 21, 22, 23 executes bit information determination at the rising edge of the input clock CLK, as will be described later, and outputs bit information signals B1, B2, B3, respectively. Here, when the changeover switches 26 and 27 are switched to the contact a side (the processing of steps S21 to S23 is executed when YES in step S11 of FIG. 12), the bit information signal from the differential receiver 21 B1 is output through the contact a side of the changeover switch 26, the bit information signal B2 from the differential receiver 22 is output through the contact a side of the changeover switch 27, and the bit information signal B3 from the differential receiver 23 is Output as is. On the other hand, when the changeover switches 26 and 27 are switched to the contact b side (NO in step S11 in FIG. 12, the processing in steps S12 to S14 is executed). Bit information signal B3 from the differential receiver 23 The bit information signal having the determination result (000 or 111) is output as the bit information signals B1, B2, and B3.

When the absolute values of the binary signal voltages of the output signals of the differential drivers 11, 12, and 13 are Vd1, Vd2, and Vd3, the setting condition (Vd3> Vd1 (for example, Vd1 = Vd2 = 1) according to the second embodiment. .0 [V]; Vd3 = 1.5 [V]) is a method for distinguishing the bit information signals 000 and 111 from all other bit information signals, and can be executed under the following conditions: .
(1) | Vd1 | = | Vd2 |
(2) When | Vd3 | ≠ | Vd1 |: Vd3 = Vd1, if the bit information signals 000 and 111 are sent, the potential difference between the signal lines becomes 0 and determination is impossible.
(3) When | Vd3 | ≠ | 3Vd1 |: Vd3 = 3Vd1, sending the bit information signals 010 to 101 causes 0 in the potential difference between the signal lines and makes determination impossible.
(4) | Vd3 |> | Vd1 | / 2: Since the threshold value | Vth |
(5) | Vd1-Vd3 | <| Vth |: a threshold value condition. As a result, only the comparator 25 and the absolute value calculator 28 can make the determination.

  In the first setting example, the threshold value Vth is set to satisfy 0.5 [V] <Vth <1.0 [V], for example, Vth = 0.8 [V].

  FIG. 9 is a signal waveform diagram showing signal waveforms of the output signals S11a, S11b, S12a, S12b, S13a, and S13b of the differential drivers 11, 12, and 13A shown in FIG. FIG. 10 is a waveform diagram showing the relationship between the signal waveforms of the signal voltages Vs1, Vs2, and Vs3 of the transmission signal transmitted through the signal lines 31, 32, and 33 of the signal transmission line 30 of FIG. is there. Further, FIG. 11 shows bit information transmitted in the multiplex differential transmission system of FIG. 8, signal voltages Vs1, Vs2, Vs3 of transmission signals transmitted through the signal lines 31, 32, 33, and each of the signal receivers 30. It is a figure which shows the relationship between termination voltage V1, V2, V3 of termination | terminus resistance 41,42,43 and its polarity.

  As described above, the signal voltage level of only one differential driver 13 is set to a value different from the signal voltage level of the other differential drivers 11 and 12, and the circuit elements 25 to 28 forming all bit compensation circuits are provided. Thus, it is possible to decode the bit information signals in all eight states including the case where all bits are 0 and all bits are 1. In addition, the signal voltage applied to each signal line 31, 32, 33 of the signal transmission path 30 is 0 in total when any bit information signal is transmitted, and is radiated from each signal line 31, 32, 33. Since the noises cancel each other, transmission with less noise is possible as in the normal differential transmission method.

  FIG. 12 is a flowchart showing a first embodiment of bit information determination processing executed by the differential receivers 21, 22, 23 and the comparator 25 of the signal receiver 20 in the multiplex differential transmission system of FIG.

  In FIG. 12, first, in step S11, the comparator 25 determines whether or not the absolute value | V3 | of the termination voltage V3 of the termination resistor 43 exceeds the threshold value Vth. In the present embodiment, | V1-V3 | <| Vth | is preset in accordance with the above threshold value condition (| Vd1-Vd3 | <| Vth |). If NO in step S11, the process proceeds to step S12. If YES, the process proceeds to step S21, and the termination voltages Vi (i = 1, 2) of the termination resistors 41, 42, and 43 are detected by the differential receivers 21, 22, and 23. , 3) whether or not the polarity is negative. If YES, the process proceeds to step S22 to set 0 to the bit information signal Bi. If NO, the process proceeds to step S23 and 1 is set to the bit information signal Bi. Set. Then, the bit information determination process ends. In step S12, it is determined whether or not the termination voltage V3 of the termination resistor 43 is negative. If YES, the process proceeds to step S13, and all bit information signals B1, B2, and B3 are set to 0. Proceeding to S14, all bit information signals B1, B2 and B3 are set to 1. Then, the bit information determination process ends.

Modified example of the second embodiment.
FIG. 13 is a block diagram showing a configuration of a multiple differential transmission system according to a modification of the second embodiment of the present invention. As shown in FIG. 13, the modification of the second embodiment includes a signal receiver 20B instead of the signal receiver 20A, as shown in FIG. Instead of the changeover switches 26 and 27, a decoding processor 50 is provided which has a program memory 50a and executes the bit information determination processing (stored in advance in the program memory 50a) of FIG. . The absolute value calculator 28 detects the termination voltage V2 of the termination resistor 42, calculates its absolute value | V2 | = | V1 + V3 |, and outputs a signal indicating the calculation result to the non-inverting input terminal of the comparator 25. Output.

According to the modification of the second embodiment, the bit information signals 000 and 110 and 111 and 000 are distinguished from each other, and can be executed under the following conditions.
(1) | Vd1 | = | Vd2 |
(2) When | Vd3 | ≠ | Vd1 |: Vd3 = Vd1, if bit information 000, 111 is sent, the potential difference between the signal lines becomes 0 and determination is impossible.
(3) When | Vd3 | ≠ | 3Vd1 |: Vd3 = 3Vd1, if bit information 010 to 101 is sent, 0 is generated in the potential difference between the signal lines, and determination is impossible.
(4) | Vd1-Vd3 | <| Vth |: a threshold value condition. As a result, only the comparator 25 and the absolute value calculator 28 can make the determination. In FIG. 13, the absolute value calculator 28 calculates the absolute value | V2 | of the termination voltage V2 and outputs it to the comparator 25.

  In FIG. 13, the decoding processor 50 is constituted by, for example, a CPU or a DSP, and is programmed based on each signal from the differential receivers 21, 22, 23 and the comparator 25 in synchronization with the clock from the clock recovery circuit 24. By executing the bit information determination process of FIG. 14 stored in the memory 50a, the decoding process is executed to generate and output bit information signals B1, B2, and B3.

  FIG. 14 is a flowchart showing a second embodiment of bit information determination processing executed by the decoding processor 50 of the signal receiver 20 in the multiplex differential transmission system of FIG. In FIG. 14, steps S21 to S23 are processes executed by the differential receivers 21, 22, and 23, step S24 is a process executed by the decoding processor 50 alone, and steps S11 to S14 are the differential receivers 23. And processing executed by the comparator 25.

  In FIG. 14, first, it is determined by each differential receiver 21, 22, 23 whether or not the polarity of the termination voltage Vi (i = 1, 2, 3) of each termination resistor 41, 42, 43 is negative. If YES, the process proceeds to step S22, and 0 is set to the bit information signal Bi. If NO, the process proceeds to step S23, and after 1 is set to the bit information signal Bi, the process proceeds to step S24. In step S24, it is determined whether or not the bit information signals B1, B2, and B3 are 000, 001, 110, or 111. If YES, the process proceeds to step S11. If NO, the bit information determination process ends. To do. In step S11, the comparator 25 determines whether or not the absolute value | V2 | = | V1 + V3 | of the termination voltage V2 of the termination resistor 43 exceeds the threshold value Vth. In this modification, | V1−V3 | <| Vth | is preset in accordance with the above threshold value condition (| Vd1−Vd3 | <| Vth |). If NO in step S11, the process proceeds to step S12. If YES, the bit information determination process ends. In step S12, it is determined whether or not the termination voltage V3 of the termination resistor 43 is negative. If YES, the process proceeds to step S13, and all bit information signals B1, B2, and B3 are set to 0. Proceeding to S14, all bit information signals B1, B2 and B3 are set to 1.

Third embodiment.
FIG. 15 shows the bit information transmitted in the multiple differential transmission system according to the third embodiment of the present invention (only the setting conditions are different using the configuration of FIG. 8) and the signal lines 31, 32, and 33. 4 is a diagram showing the relationship between signal voltages Vs1, Vs2, and Vs3 of transmission signals to be transmitted, termination voltages V1, V2, and V3 of termination resistors 41, 42, and 43 of the signal receiver 30 and their polarities. The third embodiment differs from the second embodiment only in setting conditions, and Vd3> Vd1 (for example, when Vd1 = Vd2 = 1.0 [V]; Vd3 = 0.8 [V]) It is characterized by being set. The apparatus configuration uses the multiple differential transmission system of FIG.

  FIG. 16 shows a third example of bit information determination processing executed by the differential receivers 21, 22, 23 and the comparator 25 of the signal receiver 20 in the multiple differential transmission system according to the third embodiment. It is a flowchart. In the bit information determination process in FIG. 16, the process in step S13 and the process in step S14 are simply switched compared to the bit information determination process in FIG. The third embodiment configured as described above has the same functions and effects as those of the second embodiment.

Modified example of the third embodiment.
FIG. 17 shows bits executed by the decoding processor 50 of the signal receiver 20 in the multiple differential transmission system according to the modification of the third embodiment of the present invention (only the setting conditions are different using the configuration of FIG. 13). It is a flowchart which shows the 4th Example of an information determination process. Here, the apparatus configuration uses the multiple differential transmission system of FIG. In the bit information determination process of FIG. 17, the process of step S13 and the process of step S14 are simply switched compared to the bit information determination process of FIG. The modification of the third embodiment configured as described above has the same function and effect as the modification of the second embodiment.

  As described above in detail, according to the multiple differential transmission system according to the present invention, differential transmission of a 3-bit bit information signal can be performed by three signal lines, and an increase in noise is suppressed, and Thus, multi-bit differential transmission is possible using fewer signal lines than in the prior art. In particular, the multiplex differential transmission system of the present invention can be used as a multi-bit transmission for a display for realizing a higher image quality than before and a high-speed transmission method in a device that needs to be miniaturized.

It is a block diagram which shows the structure of the multiple differential transmission system which concerns on the 1st Embodiment of this invention. FIG. 1 shows the relationship between the signal waveforms of the output signals S11a, S11b, S12a, S12b, S13a, and S13b of each differential driver 11, 12, and 13 in FIG. It is a waveform diagram. FIG. 3 is a waveform diagram showing a relationship between signal waveforms of signal voltages Vs1, Vs2, and Vs3 of transmission signals transmitted via signal lines 31, 32, and 33 of the signal transmission path 30 of FIG. 1 and assigned bit information. FIG. 3 is a diagram showing a relationship between bit information transmitted in the multiple differential transmission system of FIG. 1 and signal voltages Vs1, Vs2, and Vs3 of signal lines 31, 32, and 33 of a signal transmission line 30; FIG. 3 is a circuit diagram showing an equivalent circuit of the signal transmitter 10 and each signal line 31, 32, 33 for explaining the signal voltages Vs1, Vs2, Vs3 of the signal lines 31, 32, 33 of FIG. FIG. 2 is a diagram illustrating a relationship between bit information transmitted in the multiple differential transmission system of FIG. 1 and polarities of termination voltages V1, V2, and V3 of termination resistors 41, 42, and 43 of the signal receiver 30; 2 is a flowchart showing bit information determination processing executed by each differential receiver 21, 22, 23 of the signal receiver 20 of FIG. It is a block diagram which shows the structure of the multiple differential transmission system which concerns on the 2nd Embodiment of this invention. FIG. 9 is a signal waveform diagram showing signal waveforms of output signals S11a, S11b, S12a, S12b, S13a, and S13b of the differential drivers 11, 12, and 13A of FIG. FIG. 9 is a waveform diagram showing a relationship between signal waveforms of signal voltages Vs1, Vs2, and Vs3 of transmission signals transmitted via signal lines 31, 32, and 33 of the signal transmission path 30 of FIG. 8 and assigned bit information. The bit information transmitted in the multiplex differential transmission system of FIG. 8, the signal voltages Vs1, Vs2, and Vs3 of the transmission signal transmitted through the signal lines 31, 32, and 33, and the termination resistors 41 and 42 of the signal receiver 30, respectively. , 43 is a diagram showing the relationship between the terminal voltages V1, V2, V3 and their polarities. 9 is a flowchart showing a first example of bit information determination processing executed by each differential receiver 21, 22, 23 and comparator 25 of the signal receiver 20 in the multiple differential transmission system of FIG. It is a block diagram which shows the structure of the multiple differential transmission system which concerns on the modification of the 2nd Embodiment of this invention. It is a flowchart which shows the 2nd Example of the bit information determination process performed by the decoding processor 50 of the signal receiver 20 in the multiplex differential transmission system of FIG. Bit information transmitted in the multiple differential transmission system according to the third embodiment of the present invention (only the setting conditions differ using the configuration of FIG. 8) and transmission signals transmitted through the signal lines 31, 32, 33 FIG. 4 is a diagram showing the relationship between the signal voltages Vs1, Vs2, and Vs3, the termination voltages V1, V2, and V3 of the termination resistors 41, 42, and 43 of the signal receiver 30 and their polarities. 12 is a flowchart showing a third example of bit information determination processing executed by each differential receiver 21, 22, 23 and comparator 25 of the signal receiver 20 in the multiple differential transmission system according to the third embodiment. . Bit information determination processing executed by the decoding processor 50 of the signal receiver 20 in the multiple differential transmission system according to the modification of the third embodiment of the present invention (only the setting conditions differ using the configuration of FIG. 13). It is a flowchart which shows the 4th Example of this.

Explanation of symbols

10, 10A ... Signal transmitter,
11, 12, 13, 13A ... differential driver,
20, 20A, 20B ... signal receiver,
21, 22, 23 ... differential receiver,
24. Clock recovery circuit,
25 ... comparator,
26, 27 ... changeover switch,
28: Absolute value calculator,
30: Signal transmission path,
31, 32, 33 ... signal lines,
41, 42, 43 ... termination resistors,
44... Threshold voltage source,
50: Decoding processor,
50a: Program memory.

Claims (3)

A multiple differential transmission system comprising: a signal transmitter; a signal receiver; and a signal transmission path including first, second, and third signal lines connecting between the signal transmitter and the signal receiver. In the signal transmitter for
A first differential driver for transmitting a first output signal and an inverted first output signal that is a phase inverted signal of the first output signal in response to the first bit information signal;
A second differential driver for transmitting a second output signal and an inverted second output signal that is a phase inverted signal of the second output signal in response to the second bit information signal;
A third differential driver that transmits a third output signal and an inverted third output signal that is a phase inverted signal of the third output signal in response to the third bit information signal;
The first output signal and the inverted third output signal are combined and transmitted to the first signal line, and the second output signal and the inverted first output signal are combined and transmitted to the second signal line. And the third output signal and the inverted third output signal are combined and transmitted to the first signal line. A multiple differential transmission system comprising: a signal transmitter; a signal receiver; and a signal transmission path including first, second, and third signal lines connecting between the signal transmitter and the signal receiver. A signal receiver for receiving each output signal from the signal transmitter according to claim 1,
The polarity of a termination voltage generated in a first termination resistor connected between the first signal line and the second signal line is detected, and the detection result is output as a first bit information signal. A first differential receiver;
The polarity of the termination voltage generated in the second termination resistor connected between the second signal line and the third signal line is detected, and the detection result is output as a second bit information signal. A second differential receiver;
The polarity of the termination voltage generated in the third termination resistor connected between the third signal line and the first signal line is detected, and the detection result is output as a third bit information signal. A signal receiver comprising a third differential receiver. A signal transmitter according to claim 1;
A multiple differential transmission system comprising the signal receiver according to claim 2.

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