JP2008011461A - Bit soft decision likelihood calculation method and receiver in maximum likelihood detection - Google Patents

Abstract

The present invention relates to a bit soft decision likelihood calculation method and receiving apparatus in maximum likelihood detection, and reduces the amount of calculation processing in calculating bit soft decision likelihood.
A maximum likelihood symbol is detected using a Euclidean distance between an estimated symbol of a received signal and a received symbol as a determination index, and a searched flag is written in a search situation memory 1-47 for each bit value of the maximum likelihood symbol. The determination index is written in the bit likelihood memory 1-48. Next, the opponent symbol candidates are selected from the estimated symbols other than the maximum likelihood symbol in ascending order of the determination index, the bit values are checked, and the searched flag is written in the search status memory 1-47 for the conflicting bit values. At the same time, the determination index is written in the bit likelihood memory 1-48. The search status memory 1-47 is referred to check whether or not the search for all the bit values is completed. When the search for all the bit values is completed, the process is terminated. If there is an unsearched bit value, the next conflict symbol candidate is selected. Repeat the same process.
[Selection] Figure 1

Description

  The present invention relates to a bit soft decision likelihood calculation method and receiving apparatus in maximum likelihood detection, and in a digital modulation / demodulation communication system using multi-level modulation, during decoding processing in maximum likelihood detection (MLD). The present invention relates to a method for calculating a soft decision likelihood for each bit of a received signal required for the above and a receiving apparatus including the calculating means.

  Maximum likelihood detection (MLD) is an effective means as a multi-input multi-output (MIMO) channel separation method. In digital modulation / demodulation, communication data (bit sequence) is mapped to modulation symbols in accordance with a modulation scheme, and reception symbol data is demodulated on the receiving side and decoded into original communication data (bit sequence).

  FIG. 9 shows an outline of a receiving apparatus based on the maximum likelihood detection of the multiple input multiple output (MIMO) system. A multi-input multi-output (MIMO) receiver receives radio signals transmitted from a plurality of transmitting antennas and transmitted through a propagation path by the plurality of receiving antennas, and outputs them from the radio unit 9-1 of each receiving antenna. The channel estimation unit 9-2 estimates the channel characteristics of the propagation path based on the received signal, and the maximum likelihood detection unit 9-3 includes the channel characteristics H obtained from the channel estimation unit 9-2, a replica of the transmission signal, Is used to generate an estimated symbol of the received signal, and one maximum likelihood symbol is detected from the estimated symbols using the squared Euclidean distance between the actually received received symbol Rx and the estimated symbol as a determination index.

  The estimated symbol detected here is the maximum likelihood as a received symbol, but the likelihood for each bit mapped to the estimated symbol is still unknown. Therefore, in order to obtain the likelihood for each bit, the estimated symbol at the shortest distance is selected for each bit value from the estimated symbols mapped with bit values different from the bit values mapped to the maximum likelihood symbol for each bit value. Then, the difference of the square root (Euclidean distance from the received symbol) of the determination index of each of the opposite symbol and the maximum likelihood symbol is calculated.

  The difference between the Euclidean distances is output as a soft decision likelihood for each bit to the error correction unit 9-4, and the error correction unit 9-4 uses the soft decision likelihood for each bit and receives it by turbo decoding or the like. Signal decoding and error correction are performed. This bit soft decision likelihood is also called a log likelihood ratio (LLR). A soft decision gain is obtained by using this bit soft decision likelihood for decoding for error correction.

  Hereinafter, a calculation example of the bit soft decision likelihood (log likelihood ratio LLR) is shown. Here, the bit of interest is bit I. The bit value at the I-th bit position of each bit value (mapped bit value, either 0 or 1 code) of the maximum likelihood symbol hard-decided by the Euclidean distance from the received symbol is hard-decided, and the bit value Is determined as one side of bit value candidates of bit I. As an example, if the hard decision value of bit I is 1 and the Euclidean distance of the maximum likelihood symbol is 0.3, the negative bit soft decision likelihood (log likelihood ratio LLR) of bit I is 0.3. Calculated.

  Next, an estimation symbol having a bit value different from (a conflict with) the hard decision value of bit I is selected from the survival estimation symbols excluding the maximum likelihood symbol. Then, among these estimated symbols, the estimated symbol of the minimum Euclidean distance is selected as an opposing symbol. As an example, if the hard decision value of bit I of the opposing symbol is 0 and the Euclidean distance of the opposing symbol is 0.4, the positive bit soft decision likelihood (log likelihood ratio LLR) of bit I is 0.4. Is calculated.

  The bit soft decision likelihood (log likelihood ratio LLR) sent to the decoding unit is a negative bit soft decision likelihood (log likelihood ratio LLR) and a plus bit soft decision likelihood (log likelihood ratio LLR), respectively. Is the likelihood calculated by subtracting the square root of √0.3−√0.4 = −0.08 in the above example. This is repeated for the number of bits mapped to the maximum likelihood symbol, and further for the number of antennas in the MIMO (MISO) scheme.

Thus, in order to calculate the bit soft decision likelihood (log likelihood ratio LLR), the bit value is referred to for each bit, and the shortest of the estimated symbols having the bit value opposite to the bit value of the maximum likelihood symbol is selected. It is necessary to repeatedly perform an operation of selecting confrontation symbols of distances and subtracting the Euclidean distances of those symbols. This process is performed by the maximum likelihood detection (MLD), the number of final surviving symbols, the number of symbols, and the MIMO method. It increases in proportion to the number of antennas. This processing amount is expressed by the following equation.
Processing amount = number of final surviving symbols x number of symbols bits x number of antennas

  As a prior art document related to the present invention, Patent Document 1 below discloses that one symbol of each modulated signal is detected using a detection method different from likelihood detection for a plurality of modulated signals transmitted from a plurality of antennas. Demodulate partial bits of multiple bits that make up, reduce candidate signal points using the demodulated partial bits, and perform maximum likelihood detection based on the Euclidean distance between the reduced candidate signal points and reception points Thus, a technique for improving error rate characteristics with a relatively small circuit scale is described in which only a part of bits that are difficult to error is obtained by a partial bit demodulator and another bit is obtained by a likelihood detector.

Patent Document 2 below describes a technique for reducing the amount of computation and improving reception characteristics by reducing transmission signal vector candidates in the maximum likelihood detection method using spatial filtering by an ordered sequential decoding method. Has been.
Japanese Unexamined Patent Publication No. 2005-184779 JP 2005-269383 A

  As described above, in the maximum likelihood detection (MLD) in the MIMO scheme, in order to calculate the bit soft decision likelihood (log likelihood ratio LLR), the final number of surviving symbols, the number of symbol bits, and the transmission of the MIMO scheme The amount of calculation processing increases in proportion to the number of antennas. The object of the present invention is to reduce this throughput.

  The bit soft decision likelihood calculation method of the present invention detects a maximum likelihood symbol from an estimated symbol using the Euclidean distance between the estimated symbol of the received signal and the received symbol as a determination index, and is mapped to the maximum likelihood symbol. In the bit soft decision likelihood calculation method for calculating the soft decision likelihood of each bit value, a searched flag is written in a search status memory for each bit value mapped to the maximum likelihood symbol, and each bit A first step of writing a determination index for a value in a bit likelihood memory, and a symbol having a smaller determination index from among estimated symbols mapped to bit values different from the bit values mapped to the maximum likelihood symbol A second step of selecting each of the opposing symbol candidates one by one in order, and mapping to the opposing symbol candidate When a bit value different from each bit value mapped to the maximum likelihood symbol is detected, a searched flag is written in the search status memory for the bit value, and each bit value is A third step of writing the determination index for the bit likelihood memory into the bit likelihood memory, and checking whether or not the searched flag is written for all bit values in the search status memory, and searching for all bit values The process is terminated when a completed flag is written, and the second step and the third step are repeatedly executed when there is a bit value for which a searched flag is not yet written. And a step.

  In addition, an upper limit is set in advance for the number of symbols to be selected as an opposing symbol candidate in the second step, and it is determined whether the number of symbols to be selected as an opposing symbol candidate exceeds the upper limit, and the upper limit is set. The method includes a fifth step of terminating the processing when exceeding.

  Further, the receiver of the present invention detects the maximum likelihood symbol from the estimated symbol using the Euclidean distance between the estimated symbol of the received signal and the received symbol as a determination index, and each bit value mapped to the maximum likelihood symbol. In a receiver comprising bit soft decision likelihood calculating means for calculating the soft decision likelihood of the search signal, a search status memory for storing a search processing status for each bit value mapped to each estimated symbol of the received signal, A bit likelihood memory for storing a minimum determination index for each bit value mapped to the estimated symbol, and for each bit value mapped to the maximum likelihood symbol, a flag that has been searched for in the search status memory A first means for writing a determination index for each bit value into the bit likelihood memory; and a map for the maximum likelihood symbol. Second means for sequentially selecting symbols having a smaller determination index as confronting symbol candidates one by one from among estimated symbols mapped with bit values different from each of the pinged bit values; When the mapped bit value is examined and a bit value different from each bit value mapped to the maximum likelihood symbol is detected, a searched flag is written in the search status memory for the bit value, and each A third means for writing a determination index for a bit value in the bit likelihood memory, and checking whether or not a flag that has been searched for in the search status memory is written for all the bit values. If the searched flag is written, the processing ends and the bit value for which the searched flag has not been written yet. If present, and having a fourth means for repeating functions to the second means and the third means.

  Further, an upper limit is set in advance for the number of symbols to be selected as the opposing symbol candidate, and it is determined whether or not the number of symbols to be selected as the opposing symbol candidate exceeds the upper limit, and processing is performed when the upper limit is exceeded. The present invention is characterized in that a fifth means for terminating the processing is provided.

  Further, the estimated symbol and the received symbol of the received signal are a combination of a plurality of symbols transmitted by a plurality of antennas, and soft decision of each bit value mapped to each symbol is made with respect to the combination of the plurality of symbols. The likelihood is calculated.

  According to the present invention, a confronted symbol is selected from the surviving symbols in ascending order of the determination index with respect to the maximum likelihood symbol, and when the confronting bit value is detected, the retrieved flag is written in the retrieval status memory. Thus, the search for the remaining symbols can be stopped at the stage where all the conflicting bit values have been searched before all the surviving symbols are examined, so that the processing amount can be reduced.

  When a maximum likelihood symbol is detected, all the bit values mapped to the maximum likelihood symbol are hard-decided as 0 or 1, and a searched flag for the bit value is written in the search status memory so that all symbols Since half of the bit values mapped to are already searched in one process, the conflicting bit values can be searched efficiently.

  In addition, the search status is retained in the search status memory and the bit likelihood memory, and the processing is terminated within a predetermined time limit by stopping the processing by cutting off the number of symbols to be selected as the opponent symbol candidates at a predetermined upper limit value. be able to. Therefore, power consumption can be reduced when processing is performed using a DSP (Digital Signal Processor) or the like.

  In the calculation of the bit soft decision likelihood, since the present invention searches for the conflict symbol candidates in order from the smallest determination index, even if the search is terminated at the stage where the search for all the conflict symbol candidates is not completed, Will not have a major impact. Further, the present invention can be similarly applied to survival symbols that are narrowed down by maximum likelihood detection (MLD) using QR decomposition or the like for survival symbols by complete maximum likelihood detection (MLD).

  FIG. 1 shows a receiving apparatus for performing bit soft decision likelihood calculation according to the present invention. As shown in the figure, the receiving apparatus includes a radio unit 1-2 that receives a radio signal via a receive antenna unit 1-1 having a plurality of receive antennas, and a received signal received by the radio unit 1-2. Are provided with a channel estimation unit 1-3 for estimating channel characteristics of the propagation path, the radio unit 1-2 receives the received symbol Rx, and the channel estimation unit 1-3 detects the channel characteristic H of the propagation path using maximum likelihood detection (MLD). Output to part 1-4.

  A maximum likelihood detection (MLD) unit 1-4 includes a replica generation unit 1- that generates an estimated symbol HTx of a received signal based on a channel characteristic H obtained from the channel estimation unit 1-3 and a replica of the transmission signal Tx. 41, a Euclidean distance calculation unit 1-42 that calculates a difference between the actually received received symbol Rx and the estimated symbol HTx, and a symbol bitmap memory 1-43 that stores a bit value mapped to the transmission symbol A symbol combination memory 1-44 that stores combinations of symbols transmitted by a plurality of antennas, and a Euclidean distance memory 1-45 that stores the square of the Euclidean distance calculated by the Euclidean distance calculation unit 1-42 as a determination index. With.

  Furthermore, in the present invention, as a bit soft decision likelihood calculation unit in the maximum likelihood detection (MLD) unit 1-4, a symbol combination selection unit and bit likelihood selection unit 1-46, a search situation memory 1-47, a bit likelihood A memory 1-48 and a bit likelihood calculating unit 1-49 are provided. The bit soft decision likelihood (log likelihood ratio LLR) output from the bit likelihood calculation unit 1-49 is input to the error correction unit 1-5, and the error correction unit 1-5 performs soft decision for each bit. Using the likelihood, the received signal is decoded and error correction is performed by turbo decoding or the like.

  The search status memory 1-47 prepares a storage area for 1 bit for storing whether or not the search has been completed for each bit value mapped to the symbol in order to store the search processing status for the number of bits of the estimated symbol. . When the symbol modulation method is 16QAM, 4 bits are prepared for each bit value of one symbol, and storage areas for the number of transmission antennas are prepared.

  Focusing on the fact that the Euclidean distance from which the bit soft decision likelihood (log likelihood ratio LLR) is calculated is calculated for a symbol (a combination of a plurality of symbols), and by efficiently selecting a symbol to be calculated The processing amount of bit soft decision likelihood (log likelihood ratio LLR) calculation is reduced. The procedure for calculating the bit soft decision likelihood (log likelihood ratio LLR) according to the present invention will be described below.

  (1) Select and extract candidate symbols to be calculated in ascending order of Euclidean distance. In this case, it is optional to sort all the symbol candidates in advance in ascending order of the Euclidean distance, or to select and extract one by one in the order of decreasing Euclidean distance when sequentially extracting the symbol candidates as the process proceeds. The symbol with the smallest Euclidean distance is the maximum likelihood symbol.

(2) For the maximum likelihood symbol, one symbol having the next smallest Euclidean distance is selected as an opposing symbol candidate.
(3) The above-mentioned conflict symbol candidate search status memory 1-47 is examined, and only the bits for which information indicating unsearched (for example, 0) is stored in the search status memory 1-47 are processed. When a candidate bit has a bit value (opposite bit value) opposite to the value of each bit of the maximum likelihood symbol, the Euclidean distance is stored in the bit likelihood memory 1-48 of the bit value as an opposing symbol. At the same time, a flag (for example, 1) indicating that the search has been completed is stored in the search status memory 1-47 that stores the search processing status of the bit.

  (4) The entire searched status is checked based on the search status memory 1-47. If all the search status memories 1-47 are in the searched status, the search process is terminated, and a flag indicating unsearched is the search status. If it remains in the memory 1-47 (that is, if there are one or more 0s indicating unsearched), the process (3) is continued.

  (5) The above processes (2) to (4) are performed in units of one symbol, and are repeated for the last surviving symbols in order from the smallest Euclidean distance as symbol candidates.

  The present invention obtains the maximum likelihood symbol combination and its likelihood by an arbitrary maximum likelihood detection (MLD) technique, and then performs bit soft decision so that the bit opposite to the bit value mapped to the maximum likelihood symbol combination. When searching for symbol combinations to which values are mapped, by searching while searching the search status memory 1-47, and by introducing a search frequency upper limit value α, which will be described later, early termination is possible and processing is performed. The amount is to be reduced. The present invention can be similarly applied to a single symbol and a combination of a plurality of symbols.

  FIG. 2 shows a process flowchart for executing the above search procedure. The processing flow will be described with reference to FIG. By performing maximum likelihood detection (MLD) in the maximum likelihood detection (MLD) unit 1-4, the determination index (Euclidean distance) of each symbol (a plurality of symbol combinations) is Euclid corresponding to each symbol (a plurality of symbol combinations). The data is stored in the distance memory 1-45, sorted in descending order of the determination index, and the maximum likelihood symbol is selected (step 2-1). A plurality of symbol combinations are simply referred to as symbols for the sake of simplicity.

  For each bit value mapped to the maximum likelihood symbol (either 0 or 1, that is, one bit value), the determination index (Euclidean distance) of the maximum likelihood symbol is stored in the bit likelihood memory 1-48. (Step 2-2). Then, for each bit value in which the determination index (Euclidean distance) is stored, a searched mark (for example, 1) is stored in a search status memory 1-47 that stores a bit likelihood search status (step 2-3). ). At this time, half of the search status memory 1-47 is marked as searched.

  Next, in order to search for a symbol (opposite symbol) having the smallest determination index (Euclidean distance) among symbols having different bit values from the maximum likelihood symbol, Step 2-4 and Step 2-5 And in step 2-12, the counter symbol candidates are selected in order from the one with the smallest determination index (Euclidean distance), and the bit value is examined. In step 2-4, the upper limit of the number of symbols to be selected as an opposing symbol candidate is set as the maximum value α.

  Next, in order to check whether or not the likelihood search has been completed for each bit value of the selected confronting symbol candidate, a bit is obtained by step 2-6, step 2-7, and step 2-10. The search status memory 1-47 is confirmed in order of position. The search status memory 1-47 checks the next bit position without doing anything for the bit value marked as searched.

  When the search status memory 1-47 detects a bit value that is not marked as searched, the determination index (Euclidean distance) of the symbol is stored as an opposite likelihood in the bit likelihood memory 1-48 corresponding to the bit value. (Step 2-8), the searched mark (for example, 1) is stored in the search status memory 1-47 corresponding to the bit value (Step 2-9).

  In Step 2-10, it is determined whether or not the search has been performed up to the last bit position (MAX) of one conflict symbol candidate. If the search has not been completed up to the last bit position (MAX), the process goes to Step 2-6. Returning, the same processing is repeated for the next bit position. When the search is completed up to the last bit position (MAX), all bit search statuses in the search status memory 1-47 are confirmed (step 2-11), and searched marks are stored for all bit values. If it is detected that the process has been performed, the process is terminated.

  If it is detected in step 2-11 that there is an unsearched one for all bit values of all symbol candidates, it is determined whether or not the number of symbols selected as the opposing symbol candidate exceeds the upper limit α. If the upper limit value α is exceeded, the process ends. If the upper limit value α is not exceeded, the process returns to step 2-4, and the same applies to the symbol having the next smallest determination index value. Repeat the process.

  The upper limit α of the number of symbols to be selected as the conflict symbol candidate is set to an arbitrary number of calculations according to the constraint time of the likelihood calculation, etc., independently of the maximum likelihood detection (MLD) symbol candidate narrowing number. By limiting the number of calculations, the processing time for likelihood calculation can be shortened. If the upper limit α is set to the same value as the number of surviving symbol combinations of maximum likelihood detection (MLD), the likelihood calculation is performed over all surviving symbol combinations of maximum likelihood detection (MLD).

  Below, the calculation process of the bit soft decision likelihood (log likelihood ratio LLR) by this invention is demonstrated using a specific example. FIG. 3A shows a determination index association table storing the determination index and the mapped bit value for each symbol combination. The table is configured by combining the symbol bitmap memory 1-43, the symbol combination memory 1-44, and the Euclidean distance memory 1-45 of FIG. The calculation of the determination index of the surviving symbol combination in maximum likelihood detection (MLD) includes a method of comparing all symbol combinations or a method of reducing the number of searches using QR decomposition. It may be used.

  The determination index association table shown in FIG. 3A shows a state of sorting in ascending order of determination index values. The symbol modulation method is 16QAM, and each symbol (TX1, TX2,..., TXn) has a bit value of 2 bits each as an in-phase component bit (I bit) and a quadrature component bit (Q bit). It is mapped. The determination index is a square Euclidean distance, and the smaller the value, the greater the likelihood.

  FIG. 3B shows an initial state of the search status memory 1-47. For the bit polarities (bit values) 0 and 1 of the symbols (TX1, TX2,..., TXn) in FIG. It is assumed that unsearched is stored as flag logical value 0 and searched is stored as flag logical value 1, and in the initial state, flag logical value 0 indicating unsearched is stored for all bit polarities (bit values). The

  FIG. 3 shows the initial state of the bit likelihood memory 1-48 that stores bit soft decision likelihood corresponding to each bit value, and shows the bit polarity (bit) of each symbol (TX1, TX2,..., TXn) in FIG. With respect to 0) and 1), the initial value z is written as the determination index value (real number) in the initial state. As the initial value z, 0, an average value of the Euclidean distance of each symbol, or the like can be used.

  The processing procedure from the initial state shown in FIG. 3 will be described below. The maximum likelihood symbol combination with the smallest determination index is selected from the determination index association table of FIG. In this example, the symbol combination of determination index 3 at address 0 is selected as the maximum likelihood symbol combination. This selection is performed by the symbol combination selection unit and bit likelihood selection unit 1-46 of FIG.

  An area of the bit likelihood memory 1-48 corresponding to the bit value (0/1) mapped to the maximum likelihood symbol combination at the address 0 is determined as a write address, and the bit value of the bit likelihood memory 1-48 The determination index read from the determination index / bit value storage table of FIG. 3A is written in the corresponding area of (0/1). The processing at this time is shown in FIG. The upper table in FIG. 4A shows the stored contents in the initial state before writing, and the lower table shows the stored contents after writing. In this procedure, the determination index 3 is written in the shaded area in the lower part of FIG.

  The search status memory 1-47 also has a searched flag (1) in the area corresponding to the bit value (0/1) mapped to the maximum likelihood symbol combination, which is the same area as the bit likelihood memory 1-48. ) Is written. The processing at this time is shown in FIG. The upper table of FIG. 4B shows the stored contents in the initial state before writing, and the lower table shows the stored contents after writing. In this procedure, as shown in the lower part of FIG. 4B, 1 is written to the searched bit value (bit polarity). At this time, half of the search status memory 1-47 is marked as searched. These processes are performed in cooperation with the symbol combination selection unit and bit likelihood selection unit 1-46 of FIG. The same applies to the following processing.

  Next, a process of sequentially searching for conflict symbol candidates is performed. From the determination index association table of FIG. 3A, the second highest symbol combination after the maximum likelihood symbol combination at address 0 is selected. In the case of the example shown in the figure, the data is the symbol combination data of address 1. The determination index and bit value are shown in FIG. Of this data, the write area of the search status memory 1-47 is determined by each bit value (0/1).

  FIG. 5B shows the contents stored in the search status memory 1-47 in this process. The upper row shows the stored content before writing, and the lower row shows the stored content after writing. The write area of the search status memory 1-47 corresponding to each bit value (0/1) is shown with an underline in the upper table of FIG.

  If flag 1 indicating that the search has already been performed has been written in the write area indicated by the underline, the next bit is checked, the bit in which flag 0 indicating that the search has not been performed is detected, and the bit has been searched The flag 1 indicating is written. The flag 1 to be written at this time is shown with an underline in the lower table of FIG.

  For the bit in which the flag 0 indicating unsearched is written, the determination index of the symbol candidate shown in FIG. 5A is written in the bit likelihood memory 1-48 as shown in FIG. 5C. . FIG. 5C shows the storage contents before writing of this processing in the upper row, and the storage contents after writing in the lower row. As shown in the lower table of FIG. 5C, the determination index 8 is written in the same storage area as the underlined area of FIG. 5B.

  Then, all the stored contents of the search status memory 1-47 shown in FIG. 5B are checked, and it is checked whether or not the flag 1 indicating that the search has been completed is stored in all. If the flag 1 indicating that the search has been completed is stored in all, the process ends before reaching the designated number of symbol combinations. Otherwise, the same processing is repeated for the next symbol candidate. In the example shown in FIG. 5B, since the flag 0 indicating unsearched still remains, the processing is continued.

  FIG. 6 shows processing for the symbol combination with the third determination index. For the third symbol combination, the third symbol combination is selected from the determination index association table of FIG. 3A in the same manner as the processing for the second symbol combination. In the case of the example shown in the figure, the symbol combination data of the determination index 10 at address 2 is used. This determination index and bit value are shown in FIG. Of this data, the write area of the search status memory 1-47 is determined by each bit value (0/1).

  FIG. 6B shows the stored contents of the search status memory 1-47 in the processing at this time. The upper row shows the stored content before writing, and the lower row shows the stored content after writing. The write area of the search status memory 1-47 corresponding to each bit value (0/1) is shown in the upper table of FIG. 6B with an underline.

  If flag 1 indicating that the search has already been performed has been written in the write area indicated by the underline, the next bit is checked, the bit in which flag 0 indicating that the search has not been performed is detected, and the bit has been searched The flag 1 indicating is written. The flag 1 to be written at this time is shown with an underline in the lower table of FIG.

  For the bit in which the flag 0 indicating unsearched is written, the determination index of the symbol candidate shown in FIG. 6A is written in the bit likelihood memory 1-48 as shown in FIG. 6C. . FIG. 6C shows the storage contents before writing of this process in the upper row, and the storage contents after writing in the lower row. As shown in the lower table of FIG. 6C, the determination index 10 is written in the same storage area as the underlined area of FIG. 6B.

  Then, all the stored contents of the search status memory 1-47 shown in FIG. If the flag 1 indicating that the search has been completed is stored in all, the processing is terminated before the designated symbol combination number α is reached. Otherwise, the same processing is repeated for the next symbol candidate until the calculation number limit value α is reached.

  An example of the determination index finally stored in the bit likelihood memory 1-48 is shown in FIG. From this determination index, the soft decision likelihood (log likelihood ratio LLR) of each bit is calculated as shown in FIG. The bit soft decision likelihood (log likelihood ratio LLR) is obtained by subtracting the plus log likelihood ratio (square root of the determination index for bit value 1) from the negative log likelihood ratio (square root of the determination index for bit value 1). Is calculated by

  Note that the above-described calculation frequency limit value α is normally the number of surviving symbol combinations of maximum likelihood detection (MLD). The calculation processing amount of the bit soft decision likelihood (log likelihood ratio LLR) can be reduced by setting the calculation number limit value α to a value smaller than the number of surviving symbol combinations of maximum likelihood detection (MLD). In the present invention, since the candidate symbols are selected as the opposing symbol candidates in order from the one with the smallest determination index for the surviving symbol combination, the calculation frequency limit value α is provided, and the bit soft decision likelihood (log likelihood ratio LLR) calculation process There is no big error even if you abort the process.

  The specific example of the processing amount reduction effect by this invention is shown below. Here, the modulation method is 16QAM, the MIMO method with two transmitting antennas and two receiving antennas, and maximum likelihood detection (MLD) using QR decomposition, and narrowed down to 16 symbols (symbol combinations) by symbol soft decision. An example of likelihood calculation processing when performing the above will be described.

  FIG. 8A shows an example of the worst case in which the processing amount is not reduced, and FIG. 8B shows an example in which the processing amount is significantly reduced. The description in the column of each table in FIG. 8 includes, from the left, the final number of surviving symbols, the distance of the opposing symbol (determination index), the search status flag of each bit of the first antenna symbol, and the symbol of the second antenna The search status flag of each bit of, and the address of the opposing symbol when sorted by distance (determination index) are shown.

  In the example shown in FIG. 8 (a), the search status flag of each bit of the second antenna remains 0111 until the end, and not all have been searched (all 1). The worst example in which processing was performed is shown. This is because even if all 15 confrontation symbols narrowed down by QR decomposition or the like are searched, bit confrontation candidates for the maximum likelihood symbol are not prepared. The amount of calculation in this case is the number of final surviving symbols × the number of bits in the symbol × the number of transmitting antennas = 15 × 4 × 2 = 120.

  On the other hand, in the example shown in FIG. 8B, the search status flag of each bit of the first and second antennas becomes 1111 when the sixth conflict symbol (the seventh when the hard decision symbol is included) is searched. In this way, the process can be terminated when all the search is completed (all 1). This is because all the bit conflict candidates for the maximum likelihood symbol are prepared at the stage of searching for the sixth conflict symbol. The calculation amount in this case is the number of processing symbols × the number of bits in the symbol × the number of transmission antennas = 6 × 4 × 2 = 48, and the calculation amount is greatly reduced as compared with the case (a).

It is a figure which shows the receiver which performs the bit soft decision likelihood calculation by this invention. 5 is a process flowchart for executing a search procedure according to the present invention. It is a figure which shows the initial state of a determination parameter | index correlation table, a search condition memory, and a bit likelihood memory. It is a figure which shows the search condition memory at the time of maximum likelihood symbol search, and a bit likelihood memory. It is a figure which shows the search condition memory and bit likelihood memory at the time of a 1st conflict symbol candidate search. It is a figure which shows the search condition memory and bit likelihood memory at the time of a 2nd opposition symbol candidate search. It is a figure which shows the bit likelihood memory at the time of a process end, and a bit soft decision likelihood. It is a figure which shows the specific example of the processing amount reduction effect by this invention. It is a figure which shows the outline | summary of the receiver by the maximum likelihood detection of a multiple input multiple output (MIMO) system.

Explanation of symbols

1-1 receiving antenna unit 1-2 radio unit 1-3 channel estimation unit 1-4 maximum likelihood detection (MLD) unit 1-41 replica generation unit 1-42 Euclidean distance calculation unit 1-43 symbol bitmap memory 1-44 Symbol combination memory 1-45 Euclidean distance memory 1-46 Symbol combination selection unit and bit likelihood selection unit 1-47 Search status memory 1-48-bit likelihood memory 1-49-bit likelihood calculation unit 1-5 Error correction unit

Claims (5)

A bit for detecting the maximum likelihood symbol from the estimated symbol and calculating the soft decision likelihood of each bit value mapped to the maximum likelihood symbol using the Euclidean distance between the estimated symbol of the received signal and the received symbol as a determination index In the soft decision likelihood calculation method,
For each bit value mapped to the maximum likelihood symbol, a first flag is written to the search status memory, and a determination index for the bit value is written to the bit likelihood memory.
A second step of sequentially selecting, as an opposing symbol candidate, symbols one by one from among estimated symbols in which bit values different from the bit values mapped to the maximum likelihood symbol are mapped;
A bit value mapped to the candidate for conflict symbol is examined, and when a bit value different from each bit value mapped to the maximum likelihood symbol is detected, a searched flag is written in the search status memory for the bit value. And a third step of writing a determination index for each bit value to the bit likelihood memory;
It is checked whether or not the searched flag is written in all the bit values in the search status memory, and when the searched flag is written in all the bit values, the process is finished, and still A fourth step of repeatedly executing the second step and the third step when there is a bit value in which a searched flag is not written;
A bit soft decision likelihood calculation method in maximum likelihood detection.   An upper limit is set in advance for the number of symbols to be selected as the opposing symbol candidate in the second step, and it is determined whether or not the number of symbols to be selected as the opposing symbol candidate exceeds the upper limit. The bit soft decision likelihood calculation method according to claim 1, further comprising a fifth step of occasionally terminating the process. A bit for detecting the maximum likelihood symbol from the estimated symbol and calculating the soft decision likelihood of each bit value mapped to the maximum likelihood symbol using the Euclidean distance between the estimated symbol of the received signal and the received symbol as a determination index In a receiver equipped with a soft decision likelihood calculation means,
A search status memory for storing a search processing status for each bit value mapped to each estimated symbol of the received signal; a bit likelihood memory for storing a minimum determination index for each bit value mapped to each estimated symbol; With
A first means for writing a searched flag in the search status memory for each bit value mapped to the maximum likelihood symbol, and writing a determination index for each bit value in the bit likelihood memory;
A second means for sequentially selecting, as an opposing symbol candidate, one symbol at a time from the estimated symbols in which bit values different from the bit values mapped to the maximum likelihood symbol are mapped;
When the bit value mapped to the conflict symbol candidate is examined and a bit value different from each bit value mapped to the maximum likelihood symbol is detected, a flag that has been searched for in the search status memory is set for the bit value. A third means for writing and writing a determination index for each bit value to the bit likelihood memory;
It is checked whether or not the searched flag is written in all the bit values in the search status memory, and when the searched flag is written in all the bit values, the process is finished, and still A fourth means for repeatedly functioning the second means and the third means when there is a bit value in which a searched flag is not written;
A receiver comprising:   An upper limit is set in advance for the number of symbols to be selected as the opposing symbol candidate, and it is determined whether or not the number of symbols to be selected as the opposing symbol candidate exceeds the upper limit, and the processing is terminated when the upper limit is exceeded. The receiver according to claim 3, further comprising fifth means.   The estimated symbol and the received symbol of the received signal are a combination of a plurality of symbols transmitted by a plurality of antennas, and the soft decision likelihood of each bit value mapped to each symbol with respect to the combination of the plurality of symbols The receiver according to claim 3, wherein the receiver is calculated.

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