JP2008010704A - Thermoelectric device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thermoelectric device capable of providing a small size, a high integration, and a high reliability. <P>SOLUTION: A plurality of strip n-type impurity regions 3a and a plurality of strip p-type impurity regions 3b are formed in a single crystal silicon layer 3 on the surface of an SOI substrate 4. An insulating layer 6 is formed on the single crystal silicon layer 3 including the n-type and the p-type impurity regions 3a, 3b. A trench groove comprising a connection hole 6a and an interconnection groove 6b is formed in the insulating layer 6, and interconnection patterns 7a, 7b are formed in the trench groove. Respective one ends in a longitudinal direction of the n-type and the p-type impurity regions 3a, 3b are connected through the interconnection pattern 7b, and the other end of the n-type impurity region 3a (the p-type impurity region 3b) is connected to the other adjacent p-type impurity region 3b (the n-type impurity region 3a) through the interconnection pattern 7a. A concave opening part 9a is formed to the other end side (an interconnection pattern 7a side) of the n-type and the p-type impurity regions 3a, 3b from the upper surface of the insulating layer 6. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a thermoelectric device, and more particularly to a thermoelectric device that generates power using a temperature difference in a thermoelectric material by the Seebeck effect.

  Conventionally, a thermoelectric conversion element (thermoelectric device) using the Seebeck effect is known as an element that converts thermal energy into electric energy (see, for example, Patent Document 1).

  In the above-mentioned Patent Document 1, the thermoelectric material is formed in a plane shape in a direction perpendicular to the temperature gradient, and the temperature difference in the thermoelectric material is reduced by arranging a heat insulating material on the upstream or downstream side of the temperature gradient of the thermoelectric material. A method for securing and generating electricity has been proposed.

FIG. 10 is a cross-sectional view schematically showing the structure of a conventional thermoelectric device disclosed in Patent Document 1. In the conventional thermoelectric device, the N-type thermoelectric material 102 and the P-type thermoelectric material 103 are alternately arranged on the quartz glass substrate 101. After the Ag electrode 104 is formed between the thermoelectric materials, every other polyurethane foam sheet 105 is formed on the Ag electrode 104 as a heat insulating material. By placing this thermoelectric device in an environment with a temperature gradient (an environment in which the heat flow flows from the quartz glass substrate 101 side to the foamed polyurethane sheet 105 side), between the part where heat radiation is hindered by the foamed polyurethane sheet 105 and the other part. An electromotive force is obtained by generating a temperature difference.
JP 7-11345 A

  By the way, the conventional thermoelectric device has a large structure, and in recent years, miniaturization and high integration of the thermoelectric device are strongly demanded. In order to realize this, it is necessary to form a thermoelectric device on a semiconductor substrate (for example, a silicon substrate) using a semiconductor manufacturing process. However, in the prior art, the temperature difference is caused only by the foamed polyurethane sheet, but the current foamed polyurethane sheet has a heat-resistant temperature of about 80 ° C., and thus a reliability evaluation test in a semiconductor manufacturing process (for example, a high temperature storage test 85). ° C) cannot pass and pass, and the reliability of the thermoelectric device cannot be ensured.

  The present invention has been made in view of such circumstances, and its purpose is to produce a temperature difference in the thermoelectric material, and to achieve downsizing and high integration in a thermoelectric device that generates electric power and to improve its reliability. It is to provide a thermoelectric device that can be enhanced.

  In order to solve the above-described problems, a thermoelectric device according to the present invention includes an N-type member and a P-type member provided in a strip shape on the surface of a semiconductor substrate, and a semiconductor substrate including the N-type member and the P-type member. An N-type member and a P-type member are connected to one end in the longitudinal direction, and cooling means is provided on the other end side of the N-type member and the P-type member. And

  According to the present invention, since the portion is cooled by the cooling means provided on the other end side of the N-type member and the P-type member, the temperature of the other end of the N-type member and the P-type member is set to the N-type member and the P-type. It can be made lower than one end of the member. As a result, a temperature difference is generated in each of the strip-shaped N-type member and P-type member, and an electromotive force can be generated.

In the above structure, the cooling means is a concave first opening provided so as to face the semiconductor substrate from the upper surface side of the insulating layer. By doing in this way, since the part is exposed to air | atmosphere (air) by the 1st opening part provided in the other end side of the N-type member and the P-type member, the other end of the N-type member and the P-type member The temperature can be lowered compared to one end of the N-type member and the P-type member. In particular, when the thermoelectric device is arranged in a temperature environment in which the temperature on the upper surface side is lower than the lower surface side (back surface side), the first opening provided on the other end side of the N-type member and the P-type member Therefore, the temperature of the other end of the N-type member and the P-type member can be lowered more effectively. As a result, a temperature difference is generated in each of the strip-shaped N-type member and P-type member, and an electromotive force can be generated.

  In the above configuration, the first opening is preferably provided with the N-type member and the P-type member exposed in the opening. In this case, the joint part of the other end of the N-type member and the P-type member (specifically, the joint part of the N-type member and the second wiring pattern and the joint part of the P-type member and the second wiring pattern). Is easily affected by the temperature of the atmosphere (air) in the opening and is cooled more effectively, so that the temperature difference between the N-type member and the P-type member can be expanded. As a result, a larger electromotive force can be generated.

  In order to solve the above-mentioned problem, another thermoelectric device according to the present invention is configured such that one end of each of the N-type member and the P-type member is exposed through the first wiring pattern provided exposed from the surface of the insulating layer. The other end of each of the N-type member and the P-type member is connected to a second wiring pattern that is exposed from the surface of the insulating layer, and the cooling means has an exposed area that is greater than that of the first wiring pattern. The second wiring pattern is provided so as to be larger. By doing so, the second wiring pattern is more strongly affected by the temperature of the atmosphere (air), and the joint portion between the second wiring pattern and the N-type member and P-type member is cooled more effectively. Is done. As a result, the temperature difference between the N-type member and the P-type member can be increased, and a larger electromotive force can be generated.

  In the above configuration, an insulating protective layer may be further provided so as to cover the first wiring pattern. In this case, since the influence of the temperature of the atmosphere (air) is reduced by the insulating protective layer in the first wiring pattern, the temperature difference between the other end in the N-type member and the P-type member can be expanded. A large electromotive force can be generated.

  In order to solve the above-described problem, still another thermoelectric device according to the present invention includes an N-type member and a P-type thermoelectric device arranged in a temperature environment in which the temperature on the lower surface side (back surface side) is higher than that on the upper surface side. In the lower region on one end side of the mold member, a concave second opening is further provided from the lower surface side of the semiconductor substrate. By doing in this way, since the part is exposed to a high temperature environment by the 2nd opening part provided in the downward area | region of the one end side of a N-type member and a P-type member, the temperature of the one end of a N-type member and a P-type member Can be further increased. As a result, the temperature difference between the N-type member and the P-type member can be increased, and a larger electromotive force can be generated.

  According to the present invention, in a thermoelectric device that generates a temperature difference in a thermoelectric material and generates power, it is possible to provide a thermoelectric device that can be downsized and highly integrated, and can increase its reliability. Can do.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic top view showing the configuration of the thermoelectric device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line XX of the thermoelectric device of FIG.

  The thermoelectric device according to the first embodiment includes a strip-like single crystal silicon layer 3 in an SOI (Silicon on Insulator) substrate 4 composed of a P-type silicon substrate 1, a buried oxide film 2, and a single crystal silicon layer 3. A plurality of N-type impurity regions 3 a and P-type impurity regions 3 b are alternately formed. In the single crystal silicon layer 3, an STI (Shallow Trench Isolation) region 5 reaching the buried oxide film 2 is formed. N-type impurity region 3a and P-type impurity region 3b are electrically separated by STI region 5. The SOI substrate 4 is an example of the “semiconductor substrate” of the present invention, the N-type impurity region 3a is an example of the “N-type member” of the present invention, and the P-type impurity region 3b is an example of the “P-type member” of the present invention.

  An insulating layer 6 made of a silicon oxide film or the like is formed on the upper surface of the single crystal silicon layer 3 including the N-type impurity region 3a and the P-type impurity region 3b. The insulating layer 6 is formed with a trench groove including a connection hole 6a and a wiring groove 6b, and a conductor portion (wiring patterns 7a and 7b) made of copper (Cu) is embedded in the trench groove.

  N-type impurity region 3a and P-type impurity region 3b are connected to conductor portions (wiring patterns 7a and 7b) through connection holes 6a formed thereon. Alternatingly formed N-type impurity regions 3a and P-type impurity regions 3b are joined at adjacent ends to different types of adjacent impurity regions so as to be electrically in series. Specifically, one end (one end) in the longitudinal direction of the N-type impurity region 3a and the P-type impurity region 3b is connected via the wiring pattern 7b, and the N-type impurity region 3a (P-type impurity region 3b) is connected. ) Is connected to another adjacent P-type impurity region 3b (N-type impurity region 3a) via a wiring pattern 7a. The wiring pattern 7a is an example of the “second wiring pattern” in the present invention, and the wiring pattern 7b is an example of the “first wiring pattern” in the present invention.

  The wiring pattern 7a is connected to terminals A and B for extracting the electromotive force (voltage) generated in the N-type impurity region 3a and the P-type impurity region 3b to the outside. The wiring pattern 7b is covered with an insulating protective film 8 made of a silicon nitride film or the like. The insulating protective film 8 is an example of the “insulating protective layer” in the present invention.

A concave opening 9a is formed from the upper surface of the insulating layer 6 in the region on the other end side (wiring pattern 7a side) of the N-type impurity region 3a and the P-type impurity region 3b. Opening 9a is provided in a straight line along the other ends of N-type impurity region 3a and P-type impurity region 3b. The opening width of the opening 9a is about 1000 nm. The bottom of the opening 9a is provided to reach the P-type silicon substrate 1 in the SOI substrate 4, and the side walls of the N-type impurity region 3a and the P-type impurity region 3b are exposed in the opening 9a. The opening 9a is an example of the “cooling means” or “first opening” in the present invention.
(Production method)
3 and 4 are cross-sectional views for explaining the manufacturing process of the thermoelectric device according to the first embodiment of the present invention.

  As shown in FIG. 3A, an SOI (Silicon on Insulator) substrate 4 composed of a P-type silicon substrate 1, a buried oxide film 2, and a single crystal silicon layer 3 is prepared. The layer thickness of the single crystal silicon layer 3 is 10 to 200 nm, more preferably 100 nm. The thickness of the buried oxide film 2 is 10 to 200 nm, more preferably 100 nm.

  As shown in FIG. 3B, an STI region 5 reaching the buried oxide film 2 is formed in the single crystal silicon layer 3 of the SOI substrate 4. The single crystal silicon layer 3 is separated into regions that are electrically partitioned by the STI region 5.

As shown in FIG. 3C, resist masks (not shown) for forming the N-type impurity region 3a and the P-type impurity region 3b are respectively formed on the SOI substrate 4, and N is formed using an ion implantation method. A type impurity and a P type impurity are introduced into the region. Both impurities are introduced so as to be alternately arranged in a strip shape as shown in FIG. As the ion implantation conditions, in the case of an N-type impurity, for example, phosphorus (P) is implanted at an acceleration energy of 10 to 30 keV and an implantation amount of 1 to 5 × 10 ¹⁵ cm ⁻² . In the case of a P-type impurity, for example, boron (B) is implanted at an acceleration energy of 10 to 30 keV and an implantation amount of 1 to 5 × 10 ¹⁵ cm ⁻² . After both the impurities are implanted and the resist mask is removed, the region into which the N-type impurity and the P-type impurity are introduced is activated by heat treatment (700 to 900 ° C., 30 minutes, N ₂ atmosphere). Thereby, an N-type impurity region 3a and a P-type impurity region 3b are formed.

  As shown in FIG. 3D, an insulating layer 6 made of a silicon oxide film is formed by plasma CVD (Chemical Vapor Deposition) on an SOI substrate 4 provided with an N-type impurity region 3a and a P-type impurity region 3b. Form. The thickness of the insulating layer 6 is about 1000 nm.

  Next, as shown in FIG. 4A, a trench groove including a connection hole 6a (dimension: about 500 nm) and a wiring groove 6b is formed in the insulating layer 6 by using a photolithography technique and an etching technique. The depth of the connection hole 6a and the wiring groove 6b is about 500 nm.

  As shown in FIG. 4B, a barrier metal film (not shown) made of tantalum nitride (TaN) and a copper film (not shown) serving as a seed layer for electrolytic plating are formed on the entire insulating layer 6 including the trench groove. Are formed in this order by sputtering. Then, a copper film is embedded in the trench groove using an electrolytic plating method. Subsequently, unnecessary portions of the copper film and the barrier metal film are sequentially polished and removed by a CMP (Chemical Mechanical Polishing) method. As a result, conductor portions (wiring patterns 7 a and 7 b) embedded in the insulating layer 6 are formed so as to penetrate the insulating layer 6. In this embodiment, the conductor portions (wiring patterns 7a and 7b) are formed in the insulating layer 6 by using the dual damascene method shown in FIGS. 4A and 4B. However, the single damascene method is repeated. The conductor portions (wiring patterns 7a and 7b) may be formed.

  As shown in FIG. 4C, an insulating protective film 8 made of a silicon nitride film is formed on the entire insulating layer 6 and conductor portions (wiring patterns 7a and 7b) by using a plasma CVD method. Thereafter, unnecessary portions of the insulating protective film 8 are removed by using a photolithography technique and an etching technique. Thereby, the insulating protective film 8 that selectively covers only the wiring pattern 7b is formed.

  Finally, as shown in FIG. 2, the insulating layer 6 is formed in a predetermined region on the other end side (wiring pattern 7a side) of the N-type impurity region 3a and the P-type impurity region 3b by using a photolithography technique and an etching technique. A concave opening 9a reaching the P-type silicon substrate 1 from the upper surface of the substrate is formed. The opening 9a is provided in a straight line along the other ends of the N-type impurity region 3a and the P-type impurity region 3b, and the opening width of the opening 9a is about 1000 nm. As a result, N-type impurity region 3a and P-type impurity region 3b are exposed in opening 9a.

  Through these steps, the thermoelectric device of the first embodiment is manufactured.

  Hereinafter, the structure having an opening in the vicinity of the other end side of the thermoelectric material (N-type impurity region 3a, P-type impurity region 3b) is effective in causing a temperature difference in the thermoelectric material with reference to FIG. I will explain.

FIG. 5 is a simulation result showing the relationship between the depth of the opening in the thermoelectric device and the temperature difference in the thermoelectric material. In this simulation, the thickness of the SOI substrate 4 is 10 μm, the length of the thermoelectric material (N-type impurity region 3a or P-type impurity region 3b) in the longitudinal direction is 10 μm, the thickness of the insulating layer 6 is 1 μm, the connection hole 6a and The depth of the wiring groove 6b is 0.5 μm, and the width of the opening 9a is 1 μm. Further, the external temperature on the upper surface side (the upper surface side of the insulating layer 6) of the thermoelectric device is 25 ° C., and the external temperature on the lower surface side (the lower surface side of the SOI substrate 4) is 35 ° C. The opening 9a is provided from the upper surface of the insulating layer 6, and the depth of the opening 9a is based on the position of the upper surface of the insulating layer 6 (upper surface of the conductor portions (wiring patterns 7a and 7b)) (zero). .

  As is clear from FIG. 5, it is understood that a temperature difference is generated at both ends in the longitudinal direction of the thermoelectric material by arranging the opening 9 a in the vicinity of the other end side of the thermoelectric material. In particular, when the depth of the opening 9a is 0.5 μm or more, the temperature difference increases rapidly. For example, when reaching the surface of the SOI substrate 4 (depth 1 μm), the temperature difference is about 0.5 ° C. When reaching the P-type silicon substrate 1 in the substrate 4, the temperature difference is about 0.9 ° C. This is because the opening 9a is provided from the upper surface side of the insulating layer 6 so that the temperature in the opening 9a becomes the external temperature 25 ° C. on the upper surface side of the insulating layer 6, and the other end of the thermoelectric material (specifically, the thermoelectric This is because the joint portion between the material and the conductor portion is affected by the external temperature (25 ° C.) through the opening 9a.

According to the thermoelectric device of the first embodiment described above, the following effects can be obtained.
(1) Since the portions are cooled by the cooling means provided on the other end side of the N-type impurity region 3a and the P-type impurity region 3b, the temperature at the other end of the N-type impurity region 3a and the P-type impurity region 3b is set to N It can be made lower than one end of each of the type impurity region 3a and the P type impurity region 3b. As a result, a temperature difference occurs in each of the strip-shaped N-type impurity region 3a and P-type impurity region 3b, and an electromotive force can be generated by the Seebeck effect.
(2) Since the portion is exposed to the atmosphere (air) by the concave opening 9a provided from the upper surface side of the insulating layer 6 toward the SOI substrate 4, the other ends of the N-type impurity region 3a and the P-type impurity region 3b Can be made lower than one end of the N-type member and the P-type member. In particular, when the thermoelectric device is arranged in a temperature environment in which the temperature on the upper surface side is lower than that on the lower surface side (back surface side), the portion is exposed to the low temperature environment by the opening 9a, so the N-type impurity region 3a. And the temperature at the other end of the P-type impurity region 3b can be lowered more effectively. As a result, a temperature difference occurs in each of the strip-shaped N-type impurity region 3a and P-type impurity region 3b, and an electromotive force can be generated by the Seebeck effect.
(3) The bottom of the opening 9a reaches the SOI substrate 4, and the N-type impurity region 3a and the P-type impurity region 3b are exposed in the opening 9a. The junction part at the other end of the region 3b (specifically, the junction part between the N-type impurity region 3a and the wiring pattern 7a and the junction part between the P-type impurity region 3b and the wiring pattern 7a) is the atmosphere in the opening 9a ( The temperature difference between the N-type impurity region 3a and the P-type impurity region 3b can be increased because the air is easily affected by the temperature of the air) and is cooled more effectively. As a result, a larger electromotive force can be generated.
(4) By providing the insulating protective film 8 so as to cover the wiring pattern 7b formed on one end side of the N-type impurity region 3a and the P-type impurity region 3b, the external temperature (atmosphere) to the wiring pattern 7b due to the heat insulation effect Since the influence of (temperature) is reduced, temperature change (cooling) at one end side of the N-type impurity region 3a and the P-type impurity region 3b is suppressed. As a result, the temperature difference between the other end in the N-type impurity region 3a and the P-type impurity region 3b can be increased, and a larger electromotive force can be generated.
(5) Thermoelectric materials (N-type impurity region 3a, P-type impurity region 3b) using the same lithography technique, etching technique, film forming technique, ion implantation technique, CMP polishing technique, and the like as in the case of manufacturing a general semiconductor device. ) And electrodes (wiring patterns 7a and 7b) can be formed, and the thermoelectric device can be easily downsized and highly integrated.
(6) Since a thermoelectric device can be formed using a semiconductor manufacturing process, the thermoelectric materials (N-type impurity region 3a and P-type impurity region 3b) are highly integrated and arranged in series (or in parallel). Thus, the electromotive force (power generation amount) per unit area can be increased.
(7) It is possible to generate electric power by generating a temperature difference in the thermoelectric material without adopting polyurethane foam as in the conventional thermoelectric device.

(Second Embodiment)
6 is a schematic top view showing the configuration of the thermoelectric device according to the second embodiment of the present invention, and FIG. 7 is a cross-sectional view of the thermoelectric device of FIG. 6 along the line XX. The difference from the first embodiment is that the exposed area of the wiring pattern 7 c provided exposed from the surface of the insulating layer 6 is formed larger than the wiring pattern 7 b. The rest is the same as in the first embodiment. The formation of the exposed area of the wiring pattern 7c larger than that of the wiring pattern 7b is an example of the “cooling unit” in the present invention.

According to the thermoelectric device of the second embodiment, the following effects can be obtained in addition to the effects described in the first embodiment.
(8) The wiring pattern 7c is provided such that the exposed area of the wiring pattern 7c provided exposed from the surface of the insulating layer 6 is larger than the wiring pattern 7b provided exposed from the surface of the insulating layer 6. Is more strongly affected by the temperature of the atmosphere (air), and the joint portion between the wiring pattern 7c and the N-type impurity region 3a and the P-type impurity region 3b is more effectively cooled. As a result, the temperature difference in the N-type impurity region 3a and the P-type impurity region 3b can be increased, and a larger electromotive force can be generated.

(Third embodiment)
FIG. 8 is a schematic top view showing the configuration of the thermoelectric device according to the third embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line XX of the thermoelectric device of FIG. A difference from the first embodiment is that a concave opening 9b is provided from the lower surface side of the SOI substrate 4 in a lower region on one end side (wiring pattern 7b side) of the N-type impurity region 3a and the P-type impurity region 3b. It is that you are. The rest is the same as in the first embodiment. The opening 9b is an example of the “second opening” in the present invention.

  The opening 9b of the third embodiment is formed by performing additional processing on the thermoelectric device manufactured in the first embodiment. Specifically, the buried oxide film 2 is reached from the back side of the P-type silicon substrate 1 to one end side (wiring pattern 7b side) of the N-type impurity region 3a and the P-type impurity region 3b by using a photolithography technique and an etching technique. A concave opening 9b is formed.

According to the thermoelectric device of the third embodiment, the following effects can be obtained in addition to the effects described in the first embodiment.
(9) When the thermoelectric device is placed in a temperature environment where the temperature on the lower surface side (back surface side) is higher than that on the upper surface side, one end side of the N-type impurity region 3a and P-type impurity region 3b (wiring pattern 7b side) Since that portion is exposed to a high temperature environment by the opening 9b provided in the lower region, the temperature at one end of the N-type impurity region 3a and the P-type impurity region 3b can be further increased. As a result, the temperature difference in the N-type impurity region 3a and the P-type impurity region 3b can be increased, and a larger electromotive force can be generated.

  In the second embodiment, the example in which the exposed areas of the wiring patterns 7a and 7c are different in the state where the opening 9a is provided as the cooling means is shown. However, the present invention is not limited to this. The opening 9a may not be provided in the thermoelectric device, and only the difference in the exposed areas of the wiring patterns 7a and 7c may be generated. In this case as well, an electromotive force can be generated by generating a temperature difference in the thermoelectric material (N-type impurity region 3a and P-type impurity region 3b).

In the third embodiment, the example in which the opening 9b on the lower surface side of the thermoelectric device is provided together with the opening 9a on the upper surface side is shown. However, the present invention is not limited thereto, and for example, the opening on the lower surface side of the thermoelectric device. Only 9b may be used. In this case as well, an electromotive force can be generated by generating a temperature difference in the thermoelectric material (N-type impurity region 3a and P-type impurity region 3b).

  In the above embodiment, the example in which the insulating protective film 8 is provided so as to selectively cover only the wiring pattern 7b has been described. However, the present invention is not limited to this, and for example, the insulating protective film 8 is not provided in the thermoelectric device. Also good. Further, the insulating protective film 8 may be provided on the entire surface including the wiring pattern 7a. In these cases, effects other than the above (4) can be enjoyed.

  In the above embodiment, an example in which only the thermoelectric device is provided on the semiconductor substrate (SOI substrate 4) has been shown. However, the present invention is not limited to this, and for example, a semiconductor device such as an LSI for controlling the thermoelectric device is formed. A thermoelectric device may be provided on the formed semiconductor substrate. In this case, a miniaturized thermoelectric module is provided.

  In the above-described embodiment, an example in which the thermoelectric material (N-type impurity region 3a and P-type impurity region 3b) is provided in the semiconductor substrate (SOI substrate 4) using an ion implantation method has been described, but the present invention is not limited thereto. Instead, for example, an N-type polysilicon film and a P-type polysilicon film may be formed on a semiconductor substrate (P-type silicon substrate) by using a low pressure CVD method.

1 is a schematic top view showing a configuration of a thermoelectric device according to a first embodiment of the present invention. Sectional drawing along the XX line of the thermoelectric apparatus of FIG. (A)-(D) The schematic sectional drawing for demonstrating the manufacturing process of the thermoelectric apparatus which concerns on 1st Embodiment. (A)-(C) The schematic sectional drawing for demonstrating the manufacturing process of the thermoelectric apparatus which concerns on 1st Embodiment. The simulation result which shows the relationship between the depth of the opening part in a thermoelectric apparatus, and the temperature difference of a thermoelectric material. The schematic top view which shows the structure of the thermoelectric apparatus which concerns on 2nd Embodiment of this invention. Sectional drawing along the XX line of the thermoelectric apparatus of FIG. The schematic top view which shows the structure of the thermoelectric apparatus which concerns on 3rd Embodiment of this invention. Sectional drawing along the XX line of the thermoelectric apparatus of FIG. Sectional drawing which showed the structure of the conventional thermoelectric apparatus roughly.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate, 2 ... Embedded oxide film, 3 ... Single crystal silicon layer, 4 ... SOI substrate, 5 ... STI region, 6 ... Insulating layer, 6a ... Connection hole, 6b ... wiring groove, 7a, 7b ... wiring pattern, 8 ... insulating protective film, 9a ... opening

Claims (6)

An N-type member and a P-type member provided in a strip shape on the surface of the semiconductor substrate;
An insulating layer provided on the semiconductor substrate including the N-type member and the P-type member;
With
One end of each of the N-type member and the P-type member in the longitudinal direction is connected,
A thermoelectric device in which cooling means is provided on the other end side of the N-type member and the P-type member.   2. The thermoelectric device according to claim 1, wherein the cooling means is a concave first opening provided to face the semiconductor substrate from an upper surface side of the insulating layer.   The thermoelectric device according to claim 2, wherein the first opening is provided with the N-type member and the P-type member exposed in the opening. One end of each of the N-type member and the P-type member is connected via a first wiring pattern provided exposed from the surface of the insulating layer,
The other end of each of the N-type member and the P-type member is connected to a second wiring pattern that is exposed from the surface of the insulating layer.
2. The thermoelectric device according to claim 1, wherein the cooling unit is the second wiring pattern provided such that an exposed area is larger than the first wiring pattern.   The thermoelectric device according to claim 4, further comprising an insulating protective layer so as to cover the first wiring pattern. In a thermoelectric device arranged in a temperature environment in which the temperature on the lower surface side is higher than that on the upper surface side,
5. The recessed second opening is further provided from the lower surface side of the semiconductor substrate in a lower region on one end side of the N-type member and the P-type member. Thermoelectric device.

Images