JP2008010640A - Compound semiconductor switch circuit device - Google Patents

Abstract

A switch circuit device in which FETs are connected in multiple stages in series cannot perform direct current inspection of each FET, and needs to be selected by high-frequency measurement before shipment.
In a switch circuit device in which a switching element on a first main surface of a substrate and an electrode pad on a second main surface are connected by a via hole penetrating the substrate and a vertical metal layer on its inner wall, all FETs are connected. An inspection electrode pad is provided on the second main surface so that the electrode can be inspected, and DC inspection of each FET is performed using the external terminal electrode pad and the inspection electrode pad. This eliminates the need for sorting by high-frequency measurement before shipment, and reduces the man-hours for measurement. Since the inspection electrode pad is not provided with a bump electrode serving as an external terminal, and a small area is sufficient, an increase in chip size can be avoided. Further, since the wiring on the mounting substrate and the inspection electrode pad are sufficiently separated from each other, leakage of a high frequency signal can be prevented.
[Selection] Figure 2

Description

  The present invention relates to a compound semiconductor switch circuit device, and more particularly to a compact compound semiconductor switch circuit device that does not require a high-frequency characteristic test.

  In a switch circuit device used for antenna switching of a third generation mobile phone terminal, it is necessary to connect FETs in three stages in series in order to pass a signal of about 26 dBm. This switch circuit device is called SPDT, uses a total of six FETs, and has five external terminals, a common input terminal IN, output terminals OUT1 and OUT2, and control terminals Ctl-1 and Ctl-2.

  FIG. 13 is a circuit diagram showing an example of a conventional compound semiconductor switch circuit device. As shown in FIG. 13, the switch circuit device includes a first FET group F1 and a second FET group F2 in which three FETs are connected in series. The source electrode (or drain electrode) of the FET 1-1 of the first FET group F1 and the source electrode (or drain electrode) of the FET 2-1 of the second FET group F2 are connected to the common input terminal IN, and The gate electrodes of the three FETs of the FET group F1 are connected to the common first control terminal Ctl-1 through resistors, respectively, and the three gate electrodes of the second FET group F2 are connected to the second through the resistors, respectively. To the control terminal Ctl-2. Further, the drain electrode (or source electrode) of the FET 1-3 in the first FET group F1 is connected to the first output terminal OUT1, and the drain electrode (or source electrode) of the FET 2-3 in the second FET group F2 is connected. This is connected to the second output terminal OUT2. The control signals applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals, and the FET group on the side to which the H level signal is applied is turned on and applied to the common input terminal IN. The input signal thus transmitted is transmitted to one of the output terminals. The resistors are arranged for the purpose of preventing high-frequency signals from leaking through the gate electrode with respect to the DC potential of the control terminals Ctl-1 and Ctl-2 that are AC grounded.

  In the switch circuit device constituted by the multi-stage FET as described above, a method of performing a DC test of each FET by an inspection terminal connected to each FET is also known.

  FIG. 14 shows a switch circuit device capable of DC inspection of all FETs.

On the surface of the chip, electrode pads connected to external terminals (common input terminal IN, output terminals OUT1 and OUT2, control terminals Ctl-1 and Ctl-2) used by the user, and DC inspection terminals C1-1 and C1- 2, electrode pads connected to C2-1 and C2-2 are arranged. Then, all the electrodes of the FET constituting the switch circuit device are led out to the outside by the external terminal and the DC inspection terminal. The external terminal and the DC inspection terminal are the conductive pattern 2 provided on the back surface of the ceramic substrate (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 2004-254086

  The switch circuit device needs to guarantee the user three characteristics of insertion loss, isolation, and output power as high-frequency characteristics. However, if the DC inspection can be performed for all FETs constituting the switch circuit device, Can be guaranteed.

  Here, in the SPDT switch having one stage of FET, the source electrode, drain electrode, and gate electrode of the two FETs 1 and 2 are all led out to the outside, so the DC characteristics of both FETs can be inspected. it can. That is, in the SPDT switch having one stage of FET, the above-described high frequency characteristics can be guaranteed by direct current inspection of the FET, so that the inspection of the high frequency characteristics can be omitted.

  However, in the multistage switch circuit device as shown in FIG. 13, the drain electrode of FET1-1 and the source electrode of FET1-2, the drain electrode of FET1-2 and the source electrode of FET1-3, the drain electrode of FET2-1 and the FET2- 2 source electrode, drain electrode of FET2-2, and source electrode of FET2-3 are not led out. In other words, since all the electrodes of each FET are not derived to the outside, the direct current inspection of all the FETs cannot be performed completely. Therefore, it is impossible to check whether each FET is in accordance with the specifications, and to select all non-defective products and defective products.

  Therefore, in order to guarantee the above-described high frequency characteristics, it is necessary to inspect the high frequency characteristics separately from the DC inspection. Since the high-frequency characteristic inspection device is different from the direct-current inspection device, not only the high-frequency characteristic inspection time is added as the measurement man-hour, but also the time for transporting the measured element from the direct-current inspection device to the high-frequency characteristic inspection device. Is also added. Accordingly, the inspection man-hours are greatly increased, and an investment for an expensive high-frequency characteristic inspection device is required. Therefore, the depreciation is added and the total cost is greatly increased.

  Therefore, as shown in FIG. 14, there is a method in which an inspection terminal is provided in addition to the external terminal used by the user, and the source electrodes and drain electrodes of all the FETs are led to the outside using these terminals. As a result, DC inspection can be performed for each FET, and high-frequency characteristic inspection can be omitted.

  However, in this case, there is a problem that the number of inspection terminals is increased in addition to the terminals (external terminals) that the user actually uses as the terminals of the switch circuit device, and the package size is increased.

  In this method, the inspection terminal is not used by the user, and is not connected to any wiring or the like on the mounting board of the user set. However, since the inspection terminal is connected to the source and drain electrodes of all FETs on the chip, the potential vibrates at a high frequency due to a high frequency signal. That is, there is a problem in that interference occurs between the inspection terminal and the adjacent wiring on the mounting board of the user's set, and the high-frequency signal leaks.

  The present invention has been made in view of the above-mentioned various circumstances. First, switching is made up of a compound semiconductor substrate and a FET group provided on the first main surface of the substrate and having a plurality of FETs connected in series. An element, a first electrode pad provided on a second main surface of the substrate and connected to a part of an electrode of the FET and an external terminal of the switching element; and the FET provided on a second main surface of the substrate. A second electrode pad connected to the other electrode, and provided from the first main surface to the second main surface of the substrate, to connect the FET to the first electrode pad and the second electrode pad, respectively. This problem is solved by providing the conductive means.

  Second, a compound semiconductor substrate, a switching element provided on a first main surface of the substrate, and configured by an FET group in which a plurality of FETs having a source electrode, a drain electrode, and a gate electrode are connected in series, and the substrate A common input terminal, an output terminal and a control terminal of the switching element provided on the second main surface, and a part of the electrodes of the FET and the common input terminal and output terminal provided on the second main surface of the substrate. And a first electrode pad connected to each of the control terminals, a second electrode pad provided on the second main surface of the substrate and connected to another electrode of the FET, and a second electrode pad from the first main surface of the substrate. The problem is solved by including the FET and conductive means for connecting the first electrode pad and the second electrode pad, which are provided to reach the main surface.

  According to the present invention, the following effects can be obtained.

  First, a flip-chip switch circuit device is provided in which an external terminal electrode pad connected to an external terminal used by a user and an inspection electrode pad are provided on the back surface of the chip. Then, direct FET inspection is performed by directly probing the external terminal electrode pad and the inspection electrode pad. In other words, the electrode pad to which all the source electrodes and drain electrodes of the multi-stage FET are connected is arranged on the back surface of the chip, and the gate electrode is connected to the control terminal, so that direct current inspection using all three electrodes for the desired FET is possible. It becomes. Therefore, sorting by high frequency measurement is not required before shipment.

  Conventionally, the inspection device for high frequency characteristics is a separate device from the direct current inspection device. Therefore, the measurement man-hour is not only added to the high frequency characteristic inspection time, but also the measured element from the direct current inspection device to the high frequency characteristic inspection device. Time to carry is also added. Accordingly, the inspection man-hours are greatly increased, and an investment for an expensive high-frequency characteristic inspection device is required. Therefore, the depreciation is added and the total cost is greatly increased.

  However, according to the embodiment of the present invention, it is not necessary to prepare an expensive high-frequency measuring instrument in the production line, and man-hours for high-frequency measurement are not required.

  Second, since direct current inspection is performed by directly probing the external terminal electrode pad and the inspection electrode pad, it is not necessary to lead the inspection electrode pad to the outside as the inspection terminal. That is, the bump electrode is provided on the external terminal electrode pad, but the bump electrode is not provided on the inspection electrode pad. The inspection electrode pad need only have an area that can be contacted by the probe for direct current inspection, and can be made sufficiently smaller than the external terminal electrode pad. Therefore, it can be arranged in the gap between the external terminal electrode pads, and the conventional chip size can be maintained.

  In addition, since the bump electrode is not provided on the inspection electrode pad, it is not in contact with the mounting board of the user's set and is separated from the substrate surface. Therefore, even when a high-frequency signal propagates to the inspection electrode pad by connecting to the source electrode and the drain electrode, the high-frequency signal does not leak to adjacent wirings on the mounting substrate.

  An embodiment of the present invention will be described in detail with reference to FIGS. In the present embodiment, an example of a compound semiconductor switch circuit device will be described using an SP3T (Single Pole Throw Throw) having three switching elements.

  First, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a diagram showing an example of SP3T, and is a schematic circuit diagram in which a circuit diagram integrated on one chip and an electrode pad are shown.

  The switch circuit device of this embodiment includes a compound semiconductor substrate, a switching element, an external terminal, a first electrode pad, a second electrode pad, and a conductive means.

  The switching element is provided on the first main surface of the substrate 1 and is configured by an FET group in which a plurality of FETs are connected in series. The external terminals are a common input terminal IN, a first output terminal OUT1, a second output terminal OUT2, a third output terminal OUT3, a first control terminal Ctl1, a second control terminal Ctl2, and a third control terminal Ctl3. Some electrodes are connected.

  The first electrode pad and the second electrode pad are provided on the second main surface S2 of the substrate 1. The first electrode pad 31 is provided with a bump electrode (not shown here) serving as an external terminal.

  Further, the second electrode pad 32 is directly connected to another electrode of the FET that is not connected to the first electrode pad 31. The first electrode pad 31 and a part of the FET electrode, and the second electrode pad 32 and the other electrode of the FET are respectively provided by conductive means provided from the first main surface of the substrate 1 to the second main surface. Connected.

  The switch circuit device includes a first FET group F1, a second FET group F2, and a third FET group F3, which are FETs connected in series in three stages and serve as switching elements. Further, the source electrode (or drain electrode) of the FET at one end of the first FET group F1, the source electrode (or drain electrode) of the FET at one end of the second FET group F2, and the FET at one end of the third FET group F3 Source electrodes (or drain electrodes) are connected to the common input terminal IN. In addition, the gate electrodes of the three FETs of the first FET group F1 are connected to the first control terminal Ctl1 through the first control resistor CR1, respectively, and the three gate electrodes of the second FET group F2 are respectively connected to the second control terminal Ctl1. The resistor CR2 is connected to the second control terminal Ctl2. The three gate electrodes of the third FET group F3 are connected to the third control terminal Ctl3 through the third control resistor CR3.

  A part of the first control resistor CR1 is composed of resistors VR1-1, VR1-2, VR1-3 connected to the respective gate electrodes of the first FET group F1, and a part of the second control resistor CR2 is the second control resistor CR2. The resistors VR2-1, VR2-2, and VR2-3 are connected to the gate electrodes of the FET group F2. A part of the third control resistor CR3 is a resistor VR3 that is connected to the gate electrodes of the third FET group F3. -1, VR3-2 and VR3-3.

  Furthermore, the drain electrode (or source electrode) of the FET at the other end of the first FET group F1 is connected to the first output terminal OUT1. Further, the drain electrode (or source electrode) of the FET at the other end of the second FET group F2 is connected to the second output terminal OUT2, and the drain electrode (or source electrode) of the FET at the other end of the third FET group F3 is connected. This is connected to the third output terminal OUT3. In the FET, the source electrode and the drain electrode are equivalent and will be described below using any one, but the same applies even if they are interchanged.

  FET group in which one of the control signals applied to the first, second and third control terminals Ctl1, Ctl2, Ctl3 is a combination of H level and the other is L level, and the H level signal is applied Is turned ON, and a high-frequency analog signal input to the common input terminal IN is transmitted to one of the output terminals. The resistors are arranged for the purpose of preventing leakage of high-frequency signals via the gate electrodes with respect to the DC potentials of the control terminals Ctl1, Ctl2, and Ctl3 that are AC grounded.

  Hereinafter, the common input terminal IN, the first control terminal Ctl1, the second control terminal Ctl2, the third control terminal Ctl3, and the first output terminal OUT1, which are derived to the outside and used on the user side in this switch circuit device, The output terminal OUT2 and the third output terminal OUT3 are referred to as external terminals of the switch circuit device.

  Each external terminal is connected to an external terminal electrode pad that is the first electrode pad 31. The external terminal electrode pads 31 are the common input terminal pad I, the first control terminal pad C1, the second control terminal pad C2, the third control terminal pad C3, the first output terminal pad O1, the second output terminal pad O2, 3 output terminal pad O3.

  Furthermore, in this embodiment, in addition to the external terminal electrode pad 31, the six test electrode pads CK1-1, CK1-2, CK2-1, CK2-2, CK3-1, and CK3-2 are the second electrode pads 32. Is provided. As will be described in detail later, the source electrode or drain electrode that is not directly connected to the external terminal electrode pad 31 in each FET is connected to the inspection electrode pad 32, whereby all the FET electrodes are inspected as finished products. Possible electrode pads can be supplied.

  For example, the first FET group F1 side will be described. The drain electrode of FET1-1 and the source electrode of FET1-2 are connected, and these electrodes are connected to a common inspection electrode pad CK1-1. Further, the drain electrode of the FET 1-2 and the source electrode of the FET 1-3 are connected, and these electrodes are connected to a common inspection electrode pad CK1-2. The source electrode of the FET 1-1 is connected to the common input terminal pad I and led out, and the drain electrode of the FET 1-3 is connected to the first output terminal pad O1 and led out. Further, the gate electrodes of the three FETs are commonly connected to the first control terminal pad C1 and led out to the outside.

  That is, all the source electrodes, gate electrodes, and drain electrodes of the FETs constituting the first FET group F1 are connected to either the external terminal electrode pad 31 or the inspection electrode pad 32.

  Since the second FET group F2 and the third FET group F3 are the same as the first FET group F1, detailed description thereof will be omitted, but in the second FET group F2, the FET 2-1, FET 2-2, All source electrodes, gate electrodes, and drain electrodes of the FET 2-3 are connected to the common input terminal pad I, the second control terminal pad C2, the second output terminal pad O2, and the inspection electrode pads CK2-1 and CK2-2. The

  In the third FET group F3, all the source electrodes, gate electrodes, and drain electrodes of the FET 3-1, FET 3-2, and FET 3-3 are connected to the common input terminal pad I, the third control terminal pad C3, and the third control terminal pad C3. The output terminal pad O3 and the inspection electrode pads CK3-1 and CK3-2 are connected.

  Thus, by connecting the electrodes of all the FETs to the external terminal electrode pad 31 or the inspection electrode pad 32, a complete DC inspection can be performed on each FET. As a result, the high frequency characteristic inspection of the switch circuit device can be ensured without the high frequency characteristic inspection. The reason will be described below.

  As described above, the switch circuit device needs to guarantee to the user three characteristics of insertion loss, isolation, and output power as high-frequency characteristics. First, the insertion loss has a strong correlation with the ON resistance of the FET. That is, if the ON resistance is inspected by direct current inspection of the FET, the insertion loss can be guaranteed to the user without measuring the insertion loss itself. Next, the isolation is poor when the leakage current (Igss) of the FET is large. If the leakage current (Igss) is equal to or less than a predetermined value, there is almost no production variation of the isolation. In other words, isolation can be selected as a non-defective product or a defective product by direct current inspection of the FET. Furthermore, the output power has a strong correlation between the FET IDSS and the pinch-off voltage. That is, if the IDSS and the pinch-off voltage of the FET are inspected by direct current inspection of the FET, the output power can be guaranteed to the user without measuring the output power itself.

  In the embodiment of the present invention, the common input terminal IN, the first control terminal Ctl-1, the second control terminal Ctl-2, the third control terminal Ctl-3, the first output terminal OUT1, the second output terminal OUT2, In addition to the external terminal electrode pad 31 connected to the three output terminals OUT3, an inspection electrode pad 32 is provided, and all the electrodes of the multi-stage connection FET constituting the switch circuit device are either the external terminal electrode pad 31 or the inspection electrode pad 32. That is, by probing the external terminal electrode pad 31 and the inspection electrode pad 32, the ON resistance, Igss, IDSS, and pinch-off voltage of each FET can be inspected, and high-frequency characteristics can be ensured only by direct current inspection. .

  FIG. 2 is a plan view of a switch circuit device in which the circuit of FIG. 1 is integrated on one chip. In the present embodiment, the switching element is disposed on the first main surface (front surface) S1 of the GaAs substrate 1, and all of the switching elements are connected to the second main surface (back surface) S2 facing the first main surface S1. Electrode pads are arranged. FIG. 2 is a diagram in which plan views of the first main surface S1 and the second main surface S2 are superimposed.

  Three FET groups serving as switching elements are arranged on the first main surface S1 of the GaAs substrate 1. The first FET group F1 includes, for example, three FETs, FET1-1, FET1-2, and FET1-3, each having a source electrode, a drain electrode, and a gate electrode, connected in series. The second FET group F2 is formed by connecting FET2-1, FET2-2, and FET2-3 in series. The third FET group F3 is formed by connecting FET3-1, FET3-2, and FET3-3 in series.

  A first control resistor CR1, a second control resistor CR2, and a third control resistor CR3 are connected to the nine gate electrodes constituting each FET group.

  A surface ohmic metal layer (AuGe / Ni / Au) 10s which is a first metal layer and is in ohmic contact with the first main surface S1 of the substrate 1 forms a source electrode, a drain electrode and the like of each FET. FIG. 2 is not shown because it overlaps the surface wiring metal layer (Ti / Pt / Au) 30 s which is the third metal layer.

  The wiring of the second metal layer indicated by the dotted line on the first main surface of the substrate 1 is a gate metal layer (for example, Pt / Mo) 20 formed simultaneously with the formation of the gate electrode of each FET, and is indicated by the solid line. The surface wiring metal layer 30s forms a wiring for connecting each element.

  External terminal electrode pads 31 and inspection electrode pads 32 are provided on the second main surface S2. The external terminal electrode pad 31 includes a common input terminal pad I, a first output terminal pad O1, a second output terminal pad O2, a third output terminal pad O3, a first control terminal pad C1, a second control terminal pad C2, and a third. The control terminal pad C3 is a common input terminal IN, a first output terminal OUT1, a second output terminal OUT2, a third output terminal OUT3, a first control terminal Ctl1, a second control terminal Ctl2, and a third control, respectively. Connect to terminal Ctl3. On the other hand, the test electrode pads CK1-1, CK1-2, CK2-1, CK2-2, CK3-1, CK3-2 are external terminals (common input terminal IN, first output terminal OUT1, second output terminal OUT2, The third output terminal OUT3, the first control terminal Ctl1, the second control terminal Ctl2, and the third control terminal Ctl3) are not directly connected.

  All the electrode pads are provided on the second main surface (back surface) S2 facing the first main surface (front surface) S1, and are connected to the electrodes of the FETs by conductive means.

  FIG. 3 is a plan view showing the first main surface S1.

  Since the first FET group F1, the second FET group F2, and the third FET group F3 have the same configuration, the following description will mainly focus on the first FET group F1. The FET 1-1 is a source electrode 35 in which three comb-like surface wiring metal layers 30s extending from the upper side are connected to a common input terminal pad I (not shown here) provided on the second main surface S2. Below this is a source electrode formed of a surface ohmic metal layer. Further, the three comb-like surface wiring metal layers 30s extending from the lower side are the drain electrodes 36 of the FET 1-1, and the drain electrode formed of the surface ohmic metal layer is below this. Both electrodes are arranged in a shape in which comb teeth are engaged, and a gate electrode 27 formed of the gate metal layer 20 is arranged in the shape of five comb teeth therebetween.

  In the FET 1-2, the three source electrodes 35 extending from the upper side are connected to the drain electrode 36 of the FET 1-1.

  A switch circuit device in which FETs are connected in series in multiple stages is a high output switch circuit device because it can withstand a larger voltage amplitude when the FET group is OFF, as compared with a switch circuit device having one FET. In general, the source electrode 35 and the drain electrode 36 serving as the connection portion CP between the FET 1-1 and the FET 1-2 are merely passing points of a high-frequency signal and do not need to be led out to the outside. That is, it does not become an external terminal used by the user and is not connected to the electrode pad 31 for external terminals.

  However, in the present embodiment, the source electrode 35 and the drain electrode 36 that are the connection portions CP of the FETs are connected to a pad for direct current inspection. That is, an inspection electrode pad CK1-1 (not shown here) is provided on the second main surface S2, and the drain electrode 36 of the FET 1-1 and the source electrode 35 of the FET 1-2 are connected. That is, a via hole 55 penetrating the substrate 1 is provided below the surface wiring metal layer 30 s of the connection portion CP corresponding to the inspection electrode pad CK 1-1, and the vertical metal layer 65 is formed on at least the side wall of the via hole 55. Provide.

  Further, the three drain electrodes 36 extending from the lower side of the FET 1-2 are connected to the source electrode 35 of the FET 1-3. There is a surface ohmic metal layer under both electrodes. These are arranged in a shape in which comb teeth are engaged, and a gate electrode 27 formed of the gate metal layer 20 is arranged in the shape of five comb teeth in the meantime. The drain electrode 36 and the source electrode 35, which are the connection portions CP of the FET 1-2 and FET 1-3, are also only high-frequency signal passing points and generally do not need to be led out to the outside, so they are not connected to the external terminal electrode pads 31. .

  In the present embodiment, the via hole 55 and the vertical metal layer 65 are also provided below the surface wiring metal layer 30s of the connection portion CP between the FET1-2 and FET1-3. The vertical metal layer 65 is connected to the inspection electrode pad CK1-2 (not shown) provided on the second main surface S2. Thereby, the drain electrode 36 and the source electrode 35 which become the connection part CP of the FET1-2 and the FET1-3 can also be inspected.

  In the FET 1-3, three comb-like surface wiring metal layers 30 s extending from the upper side are the source electrodes 35, and below this are the source electrodes formed by the surface ohmic metal layers. Further, three comb-like surface wiring metal layers 30s extending from the lower side are drain electrodes 36 connected to an output terminal pad O1 (not shown) provided on the second main surface S2, below which a surface ohmic is formed. There is a drain electrode formed of a metal layer. Both electrodes are arranged in a shape in which comb teeth are engaged, and a gate electrode 27 formed of the gate metal layer 20 is arranged in the shape of five comb teeth therebetween. Each gate electrode 27 is bundled with comb teeth by a gate wiring 21 which is also formed of the gate metal layer 20.

  The operation region 100 is a region in which, for example, an n-type impurity is selectively ion-implanted into the GaAs substrate 1 like a one-dot chain line, and the source region and the drain region, which are high-concentration n-type impurity regions, are included in the operation region 100. Selectively formed.

  A via hole 55 penetrating the substrate 1 is also provided around the substrate 1. The via hole 55 is disposed on the second main surface S2 and is provided corresponding to the common input terminal pad I and the first to third output terminal pads O1 to O3 through which high-frequency signals propagate. Further, at least the side wall of the via hole 55 is covered with the vertical metal layer 65, whereby the first to third FET groups F1 to F3, the common input terminal pad I, and the first to third output terminal pads O1 to O3. Is connected.

  A conductive region 155 is provided along each vertical metal layer 65. The conductive region 155 is an n-type impurity region 155 (hereinafter referred to as a vertical n + type region 155) provided from the first main surface S1 to the second main surface S2 of the substrate 1. The vertical n + type regions 155 are arranged adjacent to each other and are arranged between the vertical metal layers 65 through which different high-frequency signals propagate. This can prevent a high-frequency signal leaking between the vertical metal layers 65, which will be described later.

Further, a floating conductive region 170 is provided on the surface of the first main surface S1 of the substrate 1 between the first FET group F1, the second FET group F2, and the third FET group F3. The floating conductive region 170 is an n-type impurity region provided in an island shape without any potential applied from the outside, and the impurity concentration is about 1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ .

  In the region where the FETs are connected in series, that is, in the connection portion CP between the FET 1-1 and FET 1-2 and the FET 1-2 and FET 1-3, the surface wiring metal is formed on the nitride film (not shown) provided on the surface of the substrate 1. Layer 30s extends. In the region where the first FET group F1 and the second FET group F2 are adjacent, the surface wiring metal layers 30s are close to each other on the nitride film. Since a high-frequency analog signal propagates to the surface wiring metal layer 30s, the underlying nitride film becomes a capacitive component, and the high-frequency signal passes through the nitride film and reaches the semi-insulating substrate 1.

  Further, the semi-insulating substrate 1 functions as a dielectric, charge and discharge due to the high-frequency signal leaking in the semi-insulating substrate 1 occurs, and the high-frequency signal leaks between the adjacent surface wiring metal layers 30s. Similarly, in the region between the conduction region (for example, the operation region 100) on the first FET group F1 side and the conduction region (for example, the operation region 100) on the second FET group F2 side in the semi-insulating substrate 1, a high frequency signal is similarly applied. As a result, charging and discharging of electric charges occur, and leakage of high-frequency signals occurs between adjacent conductive regions. However, by disposing the floating conductive region 170 as shown in the figure, the semi-insulating substrate 1 does not work as a continuous uniform dielectric, and even when a high-frequency signal leaks into the semi-insulating substrate 1, It is possible to prevent leakage of high-frequency signals due to charge / discharge of charges between adjacent surface wiring metal layers 30s and between conduction regions.

  The gate wirings 21 of the FET 1-1, FET1-2, and FET1-3 are connected to the resistor VR1 (resistors VR1-1, VR1-2, VR1-3) outside the operation region 100, respectively. The resistor VR1 is another conductive region provided from the first main surface S1 to the second main surface S2 of the substrate 1, and is specifically an n-type impurity region having a resistance value of about 10 KΩ. The resistor VR1 (hereinafter referred to as the vertical resistor VR1) is wired on the second main surface S2 and connected to the first control terminal pad C1 (not shown). That is, the vertical resistor VR1 is a conductive means for connecting the gate wiring 21 of each FET and the first control terminal pad C1, and is a resistor constituting a part of the first control resistor CR1 (not shown).

  Similarly, the gate wiring 21 of the second FET group F2 is connected to the vertical resistor VR2 (resistors VR2-1, VR2-2, VR2-3), and the gate wiring 21 of the third FET group F3 is also connected to the vertical resistor VR3. (Resistors VR3-1, VR3-2, VR3-3).

  4 is a cross-sectional view taken along the line aa in FIG.

  A p− type region 13 and an n type channel layer 12 are provided on a non-doped GaAs substrate 1, and high concentration n + type impurity regions for forming a source region 18 and a drain region 19 are provided on both sides thereof. A gate electrode 27 forms a Schottky junction with the channel layer 12. The periphery of the gate electrode 27 is covered with a nitride film 60s serving as a passivation film. The source region 18 and the drain region 19 are provided with a source electrode 15 and a drain electrode 16 formed of the surface ohmic metal layer 10s. Further, a nitride film 60sa is provided thereon, and the source electrode 35 and the drain electrode 36 formed of the surface wiring metal layer 30s through the opening of the nitride film 60sa are connected to the source electrode 15 and the drain electrode 16 in the first layer. Contact. The surface wiring metal layer 30s constituting the connection point CP of the FET 1-1, FET 1-2, and FET 1-3 extends on the nitride film 60sa. Further, the surface wiring metal layers 30s of adjacent FET groups (for example, the first FET group F1 and the second FET group F2) are arranged close to each other on the nitride film 60sa (see FIGS. 2, 3, and 6). ). The surface of the substrate 1 is covered with a nitride film 60sb serving as a jacket coat film.

  FIG. 5 is a plan view of the second main surface S2.

  All electrode pads, that is, the external terminal electrode pads 31 and the inspection electrode pads 32 are arranged on the second main surface S2. For example, in the peripheral portion of the chip, the common input terminal pad I, the first control terminal pad C1, the second control terminal pad C2, the third control terminal pad C3, the first output terminal pad O1, the second output terminal pad O2, the third Seven external terminal electrode pads 31 of the output terminal pad O3 are arranged. Then, six inspection electrode pads CK1-1, CK1-2, CK2-1, CK2-2, CK1-3, and CK2-3 are arranged inside them. Each electrode pad is formed of a back surface wiring metal layer 30r having the same configuration as that of the front surface wiring metal layer 30s.

  Via holes 55 are provided corresponding to the common input terminal pad I and the first to third output terminal pads O1 to O3 through which the high-frequency signal propagates, and the inspection electrode pad 32, respectively. The layer 65 is electrically connected to the common input terminal pad I, the first to third output terminal pads O1 to O3, and the inspection electrode pad 32. Here, an example is shown in which the via hole 55 is provided so as to overlap the electrode pad, and the vertical metal layer 65 on the side wall of the via hole 55 is directly connected to the electrode pad. However, a wiring connecting to the electrode pad is provided on the second main surface S2. The wiring and the via hole 55 may be overlapped and connected to the vertical metal layer 65 on the side wall of the via hole 55. Alternatively, one wiring (or electrode pad) and a plurality of via holes 55 may be overlapped, and the vertical metal layer 65 provided on the side wall of each via hole 55 may be connected to one wiring (or electrode pad).

  A vertical n + type region 155 that penetrates the substrate 1 is arranged along each vertical metal layer 65. By providing the vertical n + type region 155, a depletion layer extending from the vertical metal layer 65 to the inside of the substrate 1 can be blocked, so that different high frequency signals propagate and prevent high frequency signals leaking between adjacent vertical metal layers 65. it can.

  Further, vertical resistors VR1, VR2, and VR3 are provided corresponding to the first to third control terminal pads C1 to C3 to which the DC potential (high-frequency GND potential) is applied. The vertical resistors VR1, VR2, and VR3 extend from the first main surface S1 to the second main surface S2, and are connected to the first to third control terminal pads C1 to C3. For example, in the first FET group F1, the vertical resistor VR1-1 is directly connected to the first control terminal pad C1, and the vertical resistors VR1-2 and VR1-3 are connected to the first control terminal pad via the back surface wiring W. Connect to C1. The back surface wiring W is formed by a back surface wiring metal layer 30r constituting each electrode pad.

  All external terminal electrode pads 31 are provided with bump electrodes 112 as shown by broken lines. The bump electrode 112 is a solder ball, for example, and serves as an external terminal of the switch circuit device. The bump electrode 112 has a diameter of, for example, 300 μm, and the external terminal electrode pad 31 has a sufficient area (for example, 320 μm × 320 μm) for connecting the bump electrode 112.

  On the other hand, the bump electrode 112 is not provided on the inspection electrode pad 32. The inspection electrode pad 32 is an electrode pad for performing a direct current inspection, and it is sufficient to secure an area that can be contacted by the probe. That is, the terminal used by the user is not connected to the inspection electrode pad 32. The area of the inspection electrode pad 32 is sufficiently smaller than the area of the external terminal electrode pad 31, for example, 30 μm × 30 μm.

  Furthermore, a back surface n + type region 130r, which is an n + type impurity region, is provided on the surface of the second main surface S2 of the substrate 1 to which each electrode pad contacts. These protrude from the electrode pads and are provided around these electrodes.

The impurity concentration of the back surface n + -type region 130r is 1 × 10 ¹⁷ cm ⁻³ to 50 × 10 ¹⁷ cm ⁻³ , and a depletion layer extending to the substrate 1 through each electrode pad can be suppressed, and isolation can be improved.

  Further description will be given with reference to FIG. 6 is a cross-sectional view taken along the line bb of FIGS. 2, 3, and 5, and the first FET group F1 will be described. The same applies to the second FET group F2 and the third FET group F3. It is.

  All electrode pads are provided on the second main surface (back surface) S2 facing the first main surface (front surface) S1, and are connected to the electrodes of the FETs through conductive means. The conductive means is a via hole 55 having at least a side wall covered with a metal layer 65, or a vertical resistance VR.

  In the first output terminal pad O1 and the inspection electrode pads CK1-1 and CK1-2, the corresponding via holes 55 reach the second main surface S2 from the first main surface S1 of the substrate 1 and penetrate the substrate 1. Provided. Here, the via hole 55 is provided so as to overlap with the corresponding electrode pad. The surface wiring metal layer 30s is a metal layer constituting the second source electrode 35 and the drain electrode 36 in the first FET group F1, and the back surface wiring metal layer 30r constituting each electrode pad is a surface wiring metal layer. It is a metal layer having the same configuration as 30 s.

  The sidewall of the via hole 55 is covered with the vertical metal layer 65. Here, the case where the vertical metal layer 65 is filled in the via hole 55 is shown, but it is sufficient that at least the side wall of the via hole 55 is covered. Thereby, for example, the drain electrode 36 of the FET 1-3 and the first output terminal pad O 1 are electrically connected by the vertical metal layer 65. Further, the drain electrode 36 of the FET 1-1 not connected to the external terminal and the source electrode 35 of the FET 1-2 are connected to the inspection electrode pad CK1-1 at the connection point CP, and are not connected to the external terminal. 36 and the source electrode 35 of the FET 1-3 are connected to the inspection electrode pad CK1-2 at the connection point CP (see FIG. 3).

  The vertical metal layer 65 is in contact with the surface wiring metal layer 30s and the back surface wiring metal layer 30r through the surface ohmic metal layer 10s and the back surface ohmic metal layer 10r, respectively, for improving the ohmic property with the substrate. . The surface ohmic metal layer 10s is a metal layer constituting the first source electrode 15 and the drain electrode 16 of each FET. The back ohmic metal layer 10r is a metal layer having the same configuration as that of the front ohmic metal layer 10s. The front ohmic metal layer 10 s and the back ohmic metal layer 10 r may be larger than the via hole 55.

  The surface wiring metal layer 30s is in contact with the surface ohmic metal layer 10s through an opening provided in the nitride film 60sa serving as a passivation film. The surface wiring metal layer 30s is covered with a nitride film 60sb serving as a jacket coat film.

  Similarly, the back wiring metal layer 30r is in contact with the back ohmic metal layer 10r through an opening provided in the nitride film 60ra serving as a passivation film. The back wiring metal layer 30r is covered with a nitride film 60rb serving as a jacket coat film.

  However, the vertical metal layer 65, the front surface wiring metal layer 30s and the back surface wiring metal layer 30r are not necessarily in contact with each other via the front surface ohmic metal layer 10s and the back surface ohmic metal layer 10r, but are directly in contact with each other. Also good.

  The common input terminal pad I, the first output terminal pad O1, the second output terminal pad O2, the third output terminal pad O3, the first control terminal pad C1, the second control terminal pad C2, and the third control terminal pad C3 are By providing each of the bump electrodes 112, the common input terminal IN, the first output terminal OUT1, the second output terminal OUT2, the third output terminal OUT3, the first control terminal Ctl1, the second control terminal Ctl2, Connected to the third control terminal Ctl3. Further, the inspection electrode pads CK1-1, CK1-2, CK2-1, CK2-2, CK3-1, and CK3-2 are source electrodes that are not directly connected to the external terminal electrode pad 31 in each FET. 35 or the drain electrode 36.

  Further, when the vertical metal layers 65 that propagate different high-frequency signals are arranged adjacent to each other like the first output terminal pad O1 and the inspection electrode pad CK1-2, the vertical n + type region 155 is formed between them. Deploy. This will be described below.

  A high frequency analog signal propagates between the common input terminal pad I and the first output terminal pad O1 (the same applies to the second output terminal pad O2 and the third output terminal pad O3). Further, for example, the vertical metal layer 65 connected to the first output terminal pad O <b> 1 forms a Schottky junction with the substrate 1 in the via hole 55.

  In FIG. 6, the potential of the first output terminal pad O1 changes from time to time due to the propagating high frequency signal, that is, the potential of the vertical metal layer 65a connected to the first output terminal pad O1 also changes from time to time. Even on the same metal wiring, the high-frequency signal has different potentials before and after propagating a certain distance, because the phase is different if the position is different. Further, although the inspection electrode pads CK1-2 are not connected to external terminals, the vertical metal layer 65b is connected to the source electrode 35 or the drain electrode 36 of the FET. That is, the potential of the vertical metal layer 65b changes every moment due to the high-frequency signal propagating.

  In this way, when the vertical metal layers 65a and 65b through which different high-frequency signals propagate are arranged adjacent to each other, if the separation distance is short, for example, the depletion that spreads from the Schottky junction by the vertical metal layer 65a to the substrate 1 The layers reach the adjacent vertical metal layer 65b, and a high frequency signal leaks between them. The depletion layer extends from the lower one of the vertical metal layers 65a and 65b toward the higher one. Therefore, when the vertical metal layer 65b has a lower potential, a depletion layer spreads from the Schottky electrode formed by the vertical metal layer 65b toward the vertical metal layer 65a.

  Therefore, in the present embodiment, when the vertical metal layers 65a and 65b that are respectively connected to the electrode pads and propagate different high-frequency signals are disposed adjacent to each other, the vertical n + region 155 is disposed therebetween.

The impurity concentration of the vertical n + type region 155 is 1 × 10 ¹⁷ cm ⁻³ to 50 × 10 ¹⁷ cm ⁻³ , and is an n + type impurity region formed by ion implantation or the like. Therefore, unlike the substrate 1 which is not doped with impurities, the depletion layer hardly spreads in the vertical n + type region 155.

The substrate 1 is a semi-insulating substrate having a specific resistance of 1 × 10 ⁷ Ω · cm or more and 1 × 10 ⁹ Ω · cm or less. On the other hand, the specific resistance of an insulator such as glass, ceramic, rubber, oxide film and nitride film is 1 × 10 ¹⁰ Ω · cm or more. That is, the semi-insulating substrate 1 is a semiconductor and is essentially different from an insulator.

  That is, even when a depletion layer extends in the horizontal direction from the vertical metal layers 65 a and 65 b to the substrate 1, the vertical n + type region 155 can prevent the depletion layer from reaching the adjacent vertical metal layer 65. Therefore, it is possible to prevent a high frequency signal leaking between the adjacent vertical metal layers 65a and 65b, and to improve the isolation of the switch circuit device.

  The vertical n + type region 155 can be separated from the vertical metal layer 65 and disposed between the adjacent vertical metal layers 65 to improve isolation. However, in this case, there may be a restriction on the pattern by providing the vertical n + type region 155.

  Therefore, in this embodiment, the vertical n + type region 155 that contacts the outside of each vertical metal layer 65 is provided. As a result, the vertical n + type region 155 is always disposed between the adjacent vertical metal layers 65, and the depletion layer extending in any direction can be prevented from spreading. That is, there is no restriction on the pattern by providing the vertical n + type region 155, which is suitable when the pattern is dense.

  Further, a vertical n + region 155 that contacts the vertical metal layer 65 and a separated vertical n + region 155 may be provided between the adjacent vertical metal layers 65. As a result, the effect of preventing leakage of high-frequency signals is increased, and leakage of high-frequency signals with higher power can be prevented.

  Further, the surface ohmic metal layer 10s, the gate metal layer 20, the surface wiring metal layer 30s, the back surface ohmic metal layer 10r, and the back surface wiring metal layer 30r are in contact with the surfaces of the first main surface S1 and the second main surface S2 of the substrate 1. Are provided with a front surface n + region 130s and a back surface n + region 130r. These protrude from each metal layer and are provided around each metal layer. This suppresses a depletion layer extending from the Schottky junction formed between each metal layer and the substrate 1 to the substrate 1. That is, it is possible to prevent a high frequency signal from leaking between conductive regions (metal layers and impurity regions) arranged close to each other and improve isolation.

  That is, both the front surface n + -type region 130 s and the back surface n + -type region 130 r are preferably arranged in a pattern larger than the contact area between each electrode pad or each wiring and the surface of the substrate 1.

  The front surface n + -type region 130 s and the back surface n + -type region 130 r are metal layers (surface ohmic metal layer 10 s, back ohmic metal layer 10 r, surface wiring metal layer 30 s, back surface wiring metal layer 30 r, or gate wiring 21. However, the present invention is not limited to this and may be connected to the metal layer in a state where a direct current flows (hereinafter referred to as DC connection). That is, it may be provided so as to protrude from the metal layer at the lower peripheral portion of these metal layers, or may be provided around the metal layer at a distance of about 5 μm or less from the metal layer.

  Next, the vertical resistor VR will be described with reference to the vertical resistor VR1-1 in FIG.

  The gate wiring 21 in which the gate electrodes 27 of the FET 1-1 are bundled is connected to the vertical resistor VR1-1 through the surface wiring metal layer 30s and the surface ohmic metal layer 10s outside the operation region 100. The surface wiring metal layer 30s is in contact with the surface ohmic metal layer 10s and the gate wiring 21 through an opening provided in the nitride film 60sa. The surface wiring metal layer 30s is covered with a nitride film 60sb.

  The vertical resistor VR1-1 is provided to reach the second main surface S2 from the first main surface S1, and is connected to the back wiring metal layer 30r via the back ohmic metal layer 10r on the surface of the second main surface S2. Back wiring metal layer 30r is in contact with back ohmic metal layer 10r through an opening provided in nitride film 60ra, and the surface of back wiring metal layer 30r is covered with nitride film 60rb. The back wiring metal layer 30r is a part of the first control terminal pad C1.

The vertical resistors VR1-2 and VR1-3 have substantially the same configuration as that of the vertical resistor VR1-1. However, the back surface wiring metal layer 30r is a part of the back surface wiring W, and the first control terminal is interposed therethrough. Connect to pad C1. A bump electrode 112 serving as the first control terminal Ctl1 is connected to the first control terminal pad C1. The vertical resistor VR1 has an area of about several μm ^{2 on} the surface of the first main surface S1 or the second main surface S2, and has a resistance value of about 10 KΩ. The vertical resistor VR1 and the back surface wiring W constitute a part of the first control resistor CR1 (see FIGS. 2, 3, and 5).

  For the same reason as the vertical n + type region 155, the surface of the first main surface S1 and the second main surface S2 are provided with a front surface n + type region 130s and a back surface n + type region 130r to improve isolation. The surface n + -type region 130 s is provided continuously and below the surface ohmic metal layer 10 s and the gate wiring 21. Further, the back surface n + type region 130r is provided so as to protrude from the back surface ohmic metal layer 10r.

  The control resistance of the switch circuit device requires a high resistance value of 5 KΩ or more. Therefore, in the conventional structure, for example, as shown in FIG. 14, it is necessary to route the control resistor on the chip surface in order to obtain a predetermined resistance value, which prevents the miniaturization of the chip.

  However, according to the present embodiment, the vertical resistor VR1 can be formed using the thickness of the substrate 1 in the vertical direction. As a result, the area occupied by the first control resistor CR1 on the chip surface can be reduced, so that the chip can be downsized.

  Further, since the vertical resistor VR1 and other conductive regions (for example, the vertical n + region 155) have the same structure and can be formed in the same process, a new man-hour for forming the vertical resistor VR1 is added. Can be implemented.

  Although description is omitted, the vertical resistors VR2 and VR3 have the same configuration as the vertical resistor VR1.

  In FIG. 6, the vertical n + type region 155 is also provided between the vertical resistor VR1-1 and the adjacent vertical metal layer 65 (in this case, for example, the vertical metal layer 65 connected to the inspection electrode pad CK1-1). And good.

  The vertical resistor VR1-1 (similar to other vertical resistors) is an impurity diffusion region, and no junction is formed with the semi-insulating substrate 1. The depletion layer is generated from the junction when a reverse bias is applied to the junction, and the spread distance increases as the reverse bias voltage applied to the junction increases. Therefore, no depletion layer is generated from the side surface of the vertical resistor VR1-1.

  On the other hand, the inspection terminal pad CK1-1 is connected to the junction between the FET 1-1 and the FET 1-2 through which a high-frequency signal propagates as described above. Therefore, a depletion layer spreads from the Schottky junction between the vertical metal layer 65 connected to the inspection terminal pad CK1-1 and the substrate 1. Here, as described above, the potential of the high-frequency signal propagating through the vertical metal layer 65 and the potential applied to the first control terminal pad C1 change from moment to moment. A depletion layer is formed from the vertical metal layer 65 to the substrate 1 only when the potential of the high-frequency signal propagating through the vertical metal layer 65 connected to the inspection electrode pad CK1-1 is lower than the potential of the first control terminal pad C1. Spread.

  For example, when the control signal of the first control terminal pad C1 changes at 3V / 0V, the DC bias potential of the inspection electrode pad CK1-1 is about 2.4V. Since a high-frequency signal propagates to the inspection electrode pad CK1-1, the actual potential of the inspection electrode pad CK1-1 changes around 2.4 V according to the high-frequency signal level. For example, when the first control terminal pad C1 is 3V, it is natural that a time zone in which the test electrode pad CK1-1 has a lower potential than the first control terminal pad C1 occurs. In this time zone, the depletion layer from the vertical metal layer 65 connected to the inspection electrode pad CK1-1 may reach the first control terminal pad C1 (or the vertical resistor VR1-1 connected thereto). In this case, a high-frequency signal propagating to the inspection electrode pad CK1-1 leaks as a high-frequency signal to the first control terminal pad C1, which has a GND potential (hereinafter referred to as a high-frequency GND potential), and the insertion loss increases.

  In such a case, the vertical n + type region 155 is disposed between the vertical metal layer 65 through which the high-frequency signal propagates and the vertical resistor VR having the high-frequency GND potential (or DC potential). Thereby, since the spread of the depletion layer from the vertical metal layer 65 can be suppressed, a high-frequency signal leaking to the adjacent vertical resistor VR (conduction region) can be prevented. The vertical n + type region 155 is provided in contact with the vertical metal layer 65 in FIG. 6, but is disposed between the vertical resistor VR <b> 1-1 and the vertical metal layer 65 so as to be separated from the vertical metal layer 65. May be.

  For example, if there are two vertical metal layers 65 connected to the first control resistor CR1 and the second control resistor CR2, respectively, and they are adjacent to each other, it is necessary to provide a vertical n + region 155 between them. There is no. For example, when the potentials of the two are different, the depletion layer may spread from the lower potential to the higher potential and reach the vertical metal layer on the higher potential side. At this time, a leak current of about several nA flows. However, even if such a leakage current flows between the first control terminal Ctl1 and the second control terminal Ctl2, for example, it does not affect the switching of the switch circuit device. Further, since a high frequency does not propagate to a DC terminal such as a control terminal, a high frequency signal does not leak from the control terminal, and high frequency characteristics such as insertion loss and isolation are not deteriorated. Therefore, when the adjacent vertical metal layers 65 are both at DC potential, there is no need to provide the vertical n + -type region 155 between them.

  7 and 8 are views showing the via hole 55 and the vertical metal layer 65. FIG.

  FIG. 7A is the same as FIG. 6 and shows a case where the vertical metal layer 65 is filled in the via hole 55. The front surface n + type region 130s and the back surface n + type region 130r are connected to the front surface wiring metal layer 30s and the back surface wiring metal layer 30r in a direct current manner, and are provided so as to protrude from these metal layers. For example, when the surface wiring metal layer 30s is connected to the surface n + type region 130s via the surface ohmic metal layer 10s as in the first to third output terminal pads O1 to O3 shown in FIG. is there.

  The vertical n + type region 155 is provided to reach the second main surface S2 from the first main surface S1 by implanting and diffusing impurities into the substrate 1 on the side wall of the via hole 55. Then, it is continuous with the front surface n + type region 130s and the back surface n + type region 130r. In such a case, the thickness d of the vertical n + type region 155 may be about several thousand mm.

  By bringing the vertical n + region 155 into contact with the vertical metal layer 65, the vertical n + region 155 can suppress the spread of the depletion layer extending in any direction from the vertical metal layer 65.

  FIG. 7B shows a case where the vertical n + type region 155 is separated from the vertical metal layer 65 and disposed between the adjacent vertical metal layers 65. The vertical n + region 155 may be disposed between the vertical metal layers 65 through which different high-frequency signals propagate, and may not be in contact with the vertical metal layer 65 as shown in FIG.

  Further, as shown in FIG. 7C, the vertical metal layer 65 may be provided so as to cover only the side wall without filling the via hole 55.

  FIG. 8 is different from FIG. 7 in the shape of the via hole 55. In the case of FIG. 7, the via hole 55 is a trench type formed by anisotropic etching, but FIG. 8 is a shape etched in a mortar shape. Also in this case, the vertical metal layer 65 may be filled in the via hole 55 (FIG. 8A), or may be provided so as to cover only the side wall of the via hole 55 (FIG. 8B). ).

  As shown in FIG. 7B, the vertical n + type region 155 may be disposed between the adjacent vertical metal layers 65 so as to be separated from the vertical metal layer 65.

  Further, two adjacent vertical metal layers 65 (and via holes 55) do not have to have the same shape, and one of them may be a vertical resistance VR.

  9 and 10 show a second embodiment. The second embodiment is a case of a switch circuit device using a HEMT (High Electron Mobility Transistor) as a switching element. The plan view is the same as that of the first embodiment. 9 is a cross-sectional view of the operation region 100 (corresponding to the cross-section along line aa in FIG. 3), and FIG. 10 is a cross-sectional view of the via hole 55, the vertical metal layer 65, and the vertical resistor (bb in FIG. 2). It corresponds to a line cross section). In addition, description is abbreviate | omitted about the structure similar to 1st Embodiment.

  As shown in FIG. 9, the substrate 1 is formed by laminating a non-doped buffer layer 132 on a semi-insulating GaAs substrate 131, and an n + type AlGaAs layer 133 serving as an electron supply layer, a channel (electron travel) layer, and the buffer layer 132. A non-doped InGaAs layer 135 and an n + -type AlGaAs layer 133 serving as an electron supply layer are sequentially stacked. A spacer layer 134 is disposed between the electron supply layer 133 and the channel layer 135.

The buffer layer 132 is a high-resistance layer to which no impurity is added, and its film thickness is about several thousand Å. On the upper electron supply layer 133, for example, a non-doped AlGaAs layer 141 is stacked to ensure a predetermined breakdown voltage and pinch-off voltage. A chemically stable stable layer (n + type or non-doped InGaP layer) 140 is disposed thereon, and an n + type GaAs layer 137 serving as a cap layer is laminated on the uppermost layer. A high concentration impurity is added to the cap layer 137, and the impurity concentration is about 1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ .

For the electron supply layer 133, the non-doped AlGaAs layer 141, and the spacer layer 134, a material having a band gap larger than that of the channel layer 135 is used. Further, an n-type impurity (for example, Si) is added to the electron supply layer 133 to about 2 × 10 ¹⁸ cm ⁻³ to 4 × 10 ¹⁸ cm ⁻³ .

  With such a structure, electrons generated from the donor impurity of the n + -type AlGaAs layer that is the electron supply layer 133 move to the channel layer 135 side, and a channel serving as a current path is formed. As a result, electrons and donor ions are spatially separated with the heterojunction interface as a boundary. Electrons travel through the channel layer 135, but since donor ions are not present in the channel layer 135, the influence of Coulomb scattering is very small and high electron mobility can be obtained.

The operating region 100 of the HEMT is separated from other regions as shown by a one-dot chain line by an insulating region 50 reaching the buffer layer 132. The insulating region 50 is not electrically completely insulated, but is an insulated region in which carrier traps are provided in the epitaxial layer by ion implantation of impurities (boron, hydrogen or oxygen). In other words, impurities are present in the insulating region 50 as an epitaxial layer, but are inactivated by, for example, B + ion implantation for insulation. The specific resistance of the insulating region 50 is 1 × 10 ⁷ Ω · cm or more and 1 × 10 ⁹ Ω · cm or less. On the other hand, the specific resistance of insulators such as glass, ceramic, rubber, oxide film and nitride film is 1 × 10 ¹⁰ Ω · cm or more. The insulating region 50 is a semiconductor and is essentially different from an insulator.

  A source region 137 s and a drain region 137 d are provided by partially removing the cap layer 137 to which the high concentration impurity is added in the operation region 100. A source electrode 15 and a drain electrode 16 formed of a surface ohmic metal layer 10s are connected to the source region 137s and the drain region 137d, and a source electrode 35 and a drain electrode 36 are formed on the upper layer thereof by a surface wiring metal layer 30s. .

  Further, in the operation region 100 of the first main surface S1, the cap layer 137 and the stable layer 140 where the gate electrode 27 is disposed are removed by etching, the non-doped AlGaAs layer 141 is exposed, and the gate metal layer 20 is shot. The gate electrode 27 is formed by key connection. The gate electrode 27 is formed by depositing Pt / Po. After deposition, a part of the lowermost layer metal (Pt) is embedded in the non-doped AlGaAs layer 41 by heat treatment. For this reason, a high breakdown voltage characteristic can be obtained.

The HEMT epitaxial structure includes a cap layer 137. Since the impurity concentration of the cap layer 137 is as high as about 1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ^{−3, the} region where the cap layer 137 is disposed is functionally high concentration (n + type). It can be said that this is an impurity region.

  As shown in FIG. 10, each electrode pad is provided on the second main surface S2 by the backside wiring metal layer 30r. The substrate 1 is the same as that shown in FIG. Corresponding to each electrode pad, via holes 55 penetrating the substrate 1 are provided from the first main surface S1 to the second main surface S2. At least the side wall of the via hole 55 is covered with the vertical metal layer 65, whereby the external terminal electrode pad 31 (here, the first output terminal pad O1, the first control terminal pad C1) and a part of the switching element (HEMT). The electrodes are connected. Further, the inspection electrode pad 32 (in this case, the inspection electrode pads CK1-1 and CK1-2) and the external terminal electrode pad 31 are directly connected to other electrodes of switching elements that are not connected. And all the electrodes of FET which comprise a switching element can be test | inspected with the pad connected to 2nd main surface S2.

  A vertical n + type region 155 that contacts the vertical metal layer 65 is provided by ion implantation or the like. The vertical n + type region 155 has a conductive region adjacent to the non-doped buffer layer 132 and the semi-insulating substrate 131 in the depth direction of the buffer layer 132 and the semi-insulating substrate 131 (other vertical types). n + type region 155, vertical metal layer 65 and vertical resistance VR). Further, a portion located in the doped semiconductor layer above the buffer layer 132 is separated from other adjacent conductive regions by providing an insulating region 50 in a desired pattern. Further, as shown in FIG. 7B, the vertical n + type region 155 may be separated from the vertical metal layer 65.

  In the HEMT, the surface n + type region 130 s for improving isolation is also separated by the insulating region 50, and is constituted by a semiconductor layer including the cap layer 137. On the other hand, the back surface n + type region 130r is formed by ion-implanting impurities into the surface of the second main surface S2.

  The same applies when the vertical metal layer 65 connected to the first to third control resistors CR1 to CR3 is provided.

  The gate wiring 21 is provided on the non-doped AlGaAs layer 141 similarly to the gate electrode 27, and a part of the lowermost layer metal (Pt) is embedded in the non-doped AlGaAs layer 141. The surface ohmic metal layer 10s is provided on the cap layer 137, and the surface wiring metal layer 30s is in contact with the gate wiring 21 and the surface ohmic metal layer 10s through an opening provided in the nitride film 60sa serving as a passivation film. A nitride film 60sb serving as a jacket coat film is provided so as to cover them.

The vertical resistor VR (here, the vertical resistor VR1-1) is a conductive region that reaches the second main surface S2 from the first main surface S1, and has an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ to 50 × 10 ¹⁷ cm ^{−. 3} is an n-type impurity region to which ³ n-type impurities are added by ion implantation or the like.

  The vertical resistor VR constituting the first control resistor CR1 (same as the second control resistor CR2 and the third control resistor CR3) secures a cross-sectional shape having a desired resistance value, and is separated from other regions by the insulating region 50. To be separated.

  Further, the front surface n + -type region 130 s and the back surface n + -type region 130 r are metal layers (surface ohmic metal layer 10 s, back ohmic metal layer 10 r, surface wiring metal layer 30 s, back surface wiring metal layer 30 r, or gate wiring 21, which are in contact therewith However, it may be provided so as to protrude beyond the metal layer at the lower peripheral part of these metal layers. Further, it may be provided around the metal layer at a distance of about 5 μm or less from the metal layer.

  Next, with reference to FIG. 11, a method of direct current inspection according to the present embodiment will be described. The direct current inspection is performed on each FET of the chip shown in FIG.

  FIG. 11 shows the second main surface S2. In the direct current inspection, the probe 118 is brought into direct contact with the external terminal electrode pad 31 and the inspection electrode pad 32 on the second main surface S2, a desired direct current bias is applied, and current or voltage is measured. FIG. 11 shows a case where the probe 118 is in contact with only the first control terminal pad C1 and the inspection electrode pad CK1-1 in order to avoid complexity, but in reality, all the external terminal electrode pads 31 and the inspection electrode pads are in contact with each other. 32 are simultaneously in contact with separate probes 118, each individually corresponding to 32. That is, at the same time, a total of 13 probes 118 are in contact with the corresponding electrode pads. As described above, the external terminal electrode pad 31 and the inspection electrode pad 32 are connected to all the source electrodes, drain electrodes, and gate electrodes of the FET provided on the first main surface S1.

  That is, the electrode pad to which all the source electrodes and drain electrodes of the multi-stage FET are connected is arranged on the back surface of the chip, and the gate electrode is connected to the control terminal. Therefore, by selecting the external terminal electrode pad 31 and the inspection electrode pad 32 for applying and measuring the bias by a measurement program as appropriate, the DC inspection using all three electrodes (for all items) for the desired FET is performed. Can do.

  Thereby, in this embodiment, the drain electrode of FET1-1, the source electrode of FET1-2, the drain electrode of FET1-2, the source electrode of FET1-3, and the drain electrode of FET2-1, which cannot be probing conventionally, Probe to FET2-2 source electrode, FET2-2 drain electrode and FET2-3 source electrode, FET3-1 drain electrode and FET3-2 source electrode, FET3-2 drain electrode and FET3-3 source electrode 118 can be contacted. Therefore, DC inspection of all FETs constituting the switching circuit can be performed.

  By measuring the ON resistance of all the FETs by this direct current inspection, it is possible to guarantee the insertion loss of the switch circuit device to the user. Further, the isolation of the switch circuit device can be guaranteed by measuring the leakage current (Igss) of the FET. Further, by measuring the IDSS and pinch-off voltage of the FET, the output power of the switch circuit device can be guaranteed to the user.

  A mounting example of the semiconductor chip of this embodiment will be described with reference to a cross-sectional view of FIG.

  The semiconductor chip 100 of this embodiment is mounted by flip chip. That is, the bump electrode 112 serving as an external terminal is formed on the external terminal electrode pad 31 formed by the back surface metal layer 30r provided on the second main surface S2. The bump electrode 112 is provided by, for example, solder, and the bump electrode 112 is fixed to the conductive pattern 120 provided on the mounting board 110 of the user set.

  The external terminal electrode pad 31 is used on the user side, and requires an area of at least about 320 μm × 320 μm in order to sufficiently reduce the soldering connection resistance and ensure a predetermined connection strength. On the other hand, the inspection terminal pad 32 is not used on the user side and can be made sufficiently smaller than the external terminal electrode pad 31. Specifically, it is only for use in DC inspection before shipment, and it is sufficient that the probe 118 for DC inspection can be touched. Therefore, an area of about 30 μm × 30 μm is sufficient.

  Therefore, the inspection electrode pads 32 can be arranged in the gaps between the external terminal electrode pads 31, and the conventional chip size can be maintained. Further, since direct current inspection is performed by directly probing the external terminal electrode pad and the inspection electrode pad, it is not necessary to lead the inspection electrode pad 32 to the outside as the inspection terminal.

  That is, since the test electrode pad 32 is not provided with the bump electrode 112, it is not in contact with the mounting board 110 of the user set as shown in FIG. 12, and can be separated from the surface of the mounting board 110 by at least several tens of μm or more. . Therefore, even when a high frequency signal propagates to the inspection electrode pad 32 by connecting to the source electrode and drain electrode of each FET, the high frequency signal is applied to the conductive pattern 120 such as the adjacent wiring on the mounting substrate 110 of the user. Will not leak.

  In general flip chips, solder bumps are provided on electrode pads provided on the first main surface S1 of the chip and mounted on a mounting board 110 of a user's set. However, on the first main surface of the chip, elements such as FETs that propagate high-frequency signals are integrated on one surface, and these elements and the mounting substrate 110 of the user set face each other. For this reason, complex high-frequency signal interference occurs between these elements and the mounting board 110 of the set, which deteriorates the high-frequency characteristics.

  However, in the structure of the present application, the second main surface S2 of the chip faces the mounting board 110 of the set. In addition to the external terminal electrode pad 31 used as a terminal, the second main surface has only six test electrode pads 32 having a small area of about 30 μm × 30 μm, in addition to the external terminal electrode pad 31 used as a terminal. is there. That is, there is no interference of a high frequency signal between the chip and the mounting substrate, which has occurred in a conventional flip chip, and there is no deterioration in high frequency characteristics.

  The SP3T switch circuit device has been described above as an example, but the configuration of the switch circuit device is not limited to the above example, and switches having different numbers of input ports and output ports, such as SPDT, SP4T, SP7T, DPDT, DP4T, and DP7T. It may be a circuit device or may be provided with a logic circuit. Furthermore, a shunt FET that prevents leakage of high-frequency signals may be connected to the off-side output terminal.

It is a circuit diagram for demonstrating this invention. It is a top view for demonstrating this invention. It is a top view for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is a top view for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is a top view for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is a circuit diagram for demonstrating a prior art. It is a top view for demonstrating a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 10s Surface ohmic metal layer 10r Back side ohmic metal layer 12 Channel layer 15, 35 Source electrode 16, 36 Drain electrode 27 Gate electrode 18, 137s Source region 19, 137d Drain region 20 Gate metal layer 21 Gate wiring 30s Surface wiring metal layer 30r Back surface metal layer 31 External terminal electrode pad 32 Inspection electrode pad 55 Via hole 65 Vertical metal layer 112 Bump electrode 118 Probe 130s Surface n + type region 130r Back surface n + type region 170 Floating conduction region 131 GaAs substrate 132 Buffer layer 133 Electron Supply layer 134 Spacer layer 135 Channel layer 137 Cap layer 140 Stable layer 141 Non-doped layer 155 Vertical n + type region 50 Insulating region 60 sa, 60 sb, 60 ra, 60 rb, 60 s, 6 0r Nitride film 100 Operating region VR1, VR2, VR3, VR Vertical resistance IN Common input terminal Ctl1 First control terminal Ctl2 Second control terminal Ctl3 Third control terminal OUT1 First output terminal OUT2 Second output terminal OUT3 Second output terminal I common input terminal pad C1 first control terminal pad C2 second control terminal pad C3 third control terminal pad O1 first output terminal pad O2 second output terminal pad O3 third output terminal pad CR control resistor CR1 first control resistor CR2 2nd control resistance CR3 3rd control resistance F1 1st switching element F2 2nd switching element F3 3rd switching element W Back surface wiring

Claims (10)

A compound semiconductor substrate;
A switching element constituted by a group of FETs provided on the first main surface of the substrate and having a plurality of FETs connected in series;
A first electrode pad provided on the second main surface of the substrate and connected to a part of the electrodes of the FET and an external terminal of the switching element;
A second electrode pad provided on the second main surface of the substrate and connected to the other electrode of the FET;
Conductive means provided from the first main surface of the substrate to the second main surface, for connecting the FET and the first electrode pad and the second electrode pad, respectively.
A compound semiconductor switch circuit device comprising:   2. The compound semiconductor switch circuit device according to claim 1, wherein the second electrode pad is not connected to the external terminal.   2. The compound semiconductor switch circuit device according to claim 1, wherein the external terminal is a bump electrode, and the bump electrode is provided on the second main surface. A compound semiconductor substrate;
A switching element that is provided on the first main surface of the substrate and is configured by an FET group in which a plurality of FETs having a source electrode, a drain electrode, and a gate electrode are connected in series;
A common input terminal, an output terminal and a control terminal of the switching element provided on the second main surface of the substrate;
A first electrode pad provided on the second main surface of the substrate and connected to a part of the electrodes of the FET and the common input terminal, output terminal and control terminal;
A second electrode pad provided on the second main surface of the substrate and connected to the other electrode of the FET;
Conductive means provided from the first main surface of the substrate to the second main surface, for connecting the FET and the first electrode pad and the second electrode pad, respectively.
A compound semiconductor switch circuit device comprising:   5. The compound semiconductor switch circuit device according to claim 4, wherein the common input terminal, the output terminal, and the control terminal are bump electrodes.   5. The compound semiconductor switch circuit device according to claim 1, wherein the second electrode pad is smaller than the first electrode pad. 6.   The compound semiconductor switch circuit device according to claim 1, wherein the second electrode pad is an inspection electrode pad.   At least two of the conductive means include a via hole that penetrates the substrate and is provided corresponding to the first electrode pad and the second electrode pad, and a metal layer provided on at least a side wall of the via hole. 5. The compound semiconductor switch circuit device according to claim 1, wherein the compound semiconductor switch circuit device is characterized in that:   9. The compound semiconductor switch circuit device according to claim 8, further comprising a conductive region provided between the adjacent metal layers and extending from the first main surface to the second main surface.   5. The compound semiconductor switch circuit device according to claim 4, wherein the conductive means connected to the control terminal is a conductive region reaching from the first main surface to the second main surface.

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