JP2008008759A - Calibration board set, semiconductor testing device, and calibration method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a calibration board set for performing calibration to drivers and comparators corresponding to a plurality of test devices. <P>SOLUTION: This calibration board set is equipped with drivers DR for generating a test signal synchronized with a clock signal, and comparators CP for comparing synchronously a result signal from a device with a strobe signal. The board set is also equipped with the first board 50A including device domains R1, R2 corresponding to a test device of some kind and adjacent to the first direction and device domains R3, R4 corresponding to a test device of another kind and adjacent to the second direction orthogonal to the first direction, for adjusting either phase of a clock signal and a strobe signal in the domains R1, R2 based on the other, and adjusting either phase of a clock signal and a strobe signal in the domains R3, R4 based on the other; and with the second board 50B for acquiring a phase difference between each clock signal or a phase difference between each strobe signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a calibration board set, a semiconductor test apparatus, and a calibration method. For example, a calibration board set, a semiconductor test apparatus, and a calibration for adjusting operation timings of drivers and comparators constituting pin electronics of a semiconductor test apparatus Regarding the method.

  The pin electronics of the semiconductor test apparatus includes a driver that applies a signal to the device under test and a comparator that determines the logic of the signal output from the device under test in response to this signal. The driver outputs a test signal synchronized with the input clock signal. The comparator determines the logic of the output signal from the device under test in synchronization with the strobe signal.

  In the initial state of the semiconductor test apparatus, the time length of the signal path for each input / output pin of the device under test varies. For this reason, the timing of outputting the test signal from the driver and the timing of determination by the comparator are deviated from the expected timing. In order to correct this deviation, timing calibration is performed before testing the device under test.

Conventional calibration first adjusts the phase of the clock signal and the strobe signal for a driver / comparator pair, and then the phase of the clock signal between multiple drivers or the phase of the strobe signal between multiple comparators. (See Patent Document 1).
International Publication No. 02/101404 Pamphlet

  However, in the conventional calibration, a driver and a comparator corresponding to one device under test are calibrated, but a driver and a comparator corresponding to a plurality of adjacent devices under test are not calibrated. That is, conventionally, since the unit of the tester pin is fixed to the device under test unit, the phases of the clock signal and the strobe signal are not corrected by the calibration between the plurality of devices under test.

  Usually, a predetermined number of special pins used for testing high-speed operation or the like among tester pins are provided corresponding to the device under test. Therefore, the conventional semiconductor test apparatus has a problem that the test cannot be performed by changing the number of special pins.

  In order to solve the above problems, the present invention provides a calibration board set, a semiconductor test apparatus, and a calibration method capable of performing calibration on drivers and comparators corresponding to a plurality of devices under test.

A calibration board set according to an embodiment of the present invention includes a driver that generates a test signal synchronized with a clock signal for a plurality of devices under test, and the plurality of devices under test output based on the test signals. A calibration board set for calibrating a semiconductor test apparatus including a comparator for comparing a result signal in synchronization with a strobe signal,
First and second device regions arranged to correspond to a certain type of device under test and adjacent to each other in the first direction, and to another type of device under test and to the first direction And third and fourth device regions arranged adjacent to each other in a second direction orthogonal to each other, and each of the first and second device regions is based on one of the clock signal and the strobe signal. And a first calibration board for adjusting the other phase based on one of the clock signal and the strobe signal in each of the third and fourth device regions. When,
Second calibration for obtaining a relative phase difference between the clock signals corresponding to each of the plurality of drivers, or a relative phase difference between the strobe signals corresponding to each of the plurality of comparators. And an action board.

  The first calibration board and the second calibration board set include a reference terminal connected to an element that inputs one of the clock signal or the strobe signal serving as a reference, and the clock signal or the adjustment target. You may provide the some adjustment terminal connected to the element which inputs the other of the said strobe signal, and the node which electrically connects between the said reference terminal and these adjustment terminals.

A semiconductor test apparatus according to an embodiment of the present invention generates a test signal synchronized with a clock signal for a plurality of devices under test, and the plurality of devices under test output based on the test signals. A semiconductor test apparatus comprising a comparator for comparing a result signal in synchronization with a strobe signal,
First and second device regions arranged to correspond to a certain type of device under test and adjacent to each other in the first direction, and to another type of device under test and to the first direction And third and fourth device regions arranged adjacent to each other in a second direction orthogonal to each other, and each of the first and second device regions is based on one of the clock signal and the strobe signal. The other phase is adjusted, and each of the third and fourth device regions corresponds to a device under test adjacent to the device under test on the basis of one of the clock signal or the strobe signal. A first calibration board for adjusting the other phase of the clock signal or the strobe signal;
Second calibration for obtaining a relative phase difference between the clock signals corresponding to each of the plurality of drivers, or a relative phase difference between the strobe signals corresponding to each of the plurality of comparators. And an action board.

  The first calibration board and the second calibration board set include a reference terminal connected to an element that inputs one of the clock signal or the strobe signal serving as a reference, and the clock signal or the adjustment target. You may provide the some adjustment terminal connected to the element which inputs the other of the said strobe signal, and the node which electrically connects between the said reference terminal and these adjustment terminals.

  The semiconductor test apparatus may further include a storage unit that stores a phase difference between the clock signal and the strobe signal in the first to fourth device regions.

A calibration method according to an embodiment of the present invention includes: a driver that generates a test signal synchronized with a clock signal for a plurality of devices under test; and the plurality of devices under test output based on the test signals. A calibration method for adjusting a semiconductor test apparatus including a comparator that compares a result signal in synchronization with a strobe signal using a calibration board,
The phase of the other of the first and second device regions corresponding to a certain type of device under test and arranged adjacent to each other in the first direction is adjusted based on one of the clock signal and the strobe signal. And the clock signal in each of the third and fourth device regions corresponding to other types of devices under test and arranged adjacent to each other in a second direction orthogonal to the first direction. Or adjusting the other phase with reference to one of the strobe signals;
Obtaining a relative phase difference between the clock signals corresponding to each of the plurality of drivers, or a relative phase difference between the strobe signals corresponding to each of the plurality of comparators. Yes.

The calibration method is based on the form of the device under test.
Step A: adjusting the phase of each of the clock signal and the strobe signal in the first and second device regions based on the relative phase difference;
Step B: adjusting the phase of each of the clock signal and the strobe signal in the third and fourth device regions based on the relative phase difference;
The method further includes the step of selectively executing either step A or step B.

  The calibration method may simultaneously adjust the other phase with reference to one of the plurality of clock signals or the plurality of strobe signals.

  The calibration method simultaneously acquires a relative phase difference between the clock signals corresponding to each of the plurality of drivers or a relative phase difference between the strobe signals corresponding to each of the plurality of comparators. May be.

  According to the present invention, the calibration board set, the semiconductor test apparatus, and the calibration method can calibrate drivers and comparators corresponding to a plurality of adjacent devices under test.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

  FIG. 1 is a conceptual diagram of a calibration board and a semiconductor test apparatus to be subjected to timing calibration according to an embodiment of the present invention. The semiconductor test apparatus includes a semiconductor test apparatus main body 10 (hereinafter also simply referred to as the main body 10) and a workstation (WS) 40 in order to perform a predetermined test on a device under test (not shown). I have.

  The workstation 40 controls a whole series of test operations such as a function test and a timing calibration operation, and has an interface function between the user and the main body 10.

  The main body 10 performs various tests on the device under test by executing a test program transferred from the workstation 40. In addition, the main body 10 performs timing calibration by executing a dedicated program transferred from the workstation 40. For this purpose, the main body 10 includes a tester control unit (TP) 12, a timing generator (TG) 14, a pattern generator (PG) 16, a data selector (DS) 18, a format control unit (FC) 20, and a storage unit 21. And pin electronics 22.

  The tester control unit 12 is connected to each component such as the timing generator 14 via the bus BUS. The tester control unit 12 executes the test program transferred from the workstation 40, thereby performing control necessary for various test operations or calibration operations on the respective components such as the timing generator 14.

  The timing generator 14 sets a basic period of the test operation and generates various timing edges included in the basic period. The pattern generator 16 generates a data pattern input to each pin of the device under test. The data selector 18 associates various pattern data output from the pattern generator 16 with each pin of the device under test that inputs the pattern data. The format control unit 20 performs waveform control on the device under test based on the pattern data selected by the data selector 18 and the timing edge generated by the timing generator 14.

  The pin electronics 22 is used to establish a physical interface between the device under test and the main body 10. The pin electronics 22 generates signals that are actually input / output between the device under test and the main body 10 based on the clock signal CLK and the strobe signal STB generated by the waveform control of the format control unit 20. For this purpose, the pin electronics 22 includes n drivers DR and n comparators CP for each device under test. Here, n is an integer. The n drivers DR and n comparators CP are provided in the same number as the number of devices under test that can be tested simultaneously.

  The driver DR performs a test signal generation operation in synchronization with the clock signal CLK output from the format control unit 20, and changes the output signal from a low level to a high level when the clock signal CLK rises. The driver output signal may be designed to fall in synchronization with the rising edge of the clock signal, and the driver output signal to rise in synchronization with the falling edge of the clock signal.

  The comparator CP performs a comparison operation in synchronization with the strobe signal STB output from the format control unit 20, and determines the logic of the signal input from the corresponding pin of the device under test when the strobe signal STB is input. . Note that the comparator CP may perform a comparison operation in synchronization with the rising edge of the strobe signal STB, or may perform a comparison operation in synchronization with the falling edge of the strobe signal.

  One driver DR and one comparator CP form a pair and correspond to one input / output pin of the device under test. Thus, the driver DR and the comparator CP are provided corresponding to each input / output pin of the device under test.

  The semiconductor test apparatus according to the present embodiment can test a plurality of devices under test simultaneously, and includes the same pin electronics for each device under test.

  Furthermore, the performance board 30 is mounted on the main body 10. The pin electronics 22 is connected to the calibration board 50A or 50B via the performance board 30. The calibration boards 50A and 50B have special internal wiring for performing timing calibration, and have different wirings.

  FIG. 2 is a wiring diagram showing the internal configuration of the first calibration board 50A. The first calibration board 50A includes a first device region R1 (hereinafter also simply referred to as a region R1) corresponding to a first device under test (not shown), and a first device adjacent to the first device under test. And a second device region R2 (hereinafter also simply referred to as region R2) corresponding to two devices under test (not shown). Further, the first calibration board 50A has a third device region R3 (hereinafter simply referred to as region R3) corresponding to a third and fourth device under test of a different type from the first and second devices under test. And a fourth device region R4 (hereinafter also simply referred to as region R4). Regions R1 and R2 are adjacent in the first direction. The regions R3 and R4 are adjacent to a second direction orthogonal to the first direction.

  In the region R1, terminals 1a to na and terminals 1b to nb are provided, and in the region R2, terminals 1c to nc and terminals 1d to nd are provided. Terminals 1a to na correspond to drivers used for testing the first device under test, and terminals 1b to nb correspond to comparators used for testing the first device under test. Terminals 1c to nc correspond to drivers used for testing the second device under test, and terminals 1d to nd correspond to comparators used for testing the second device under test.

  The node N1 connects the terminal 1b and the terminals 1a, 4a, 7a, 10a,... (N-2) a in the region R1. The node N2 connects the terminal 1d and the terminals 1c, 4c, 7c, 10c,... (N-2) c in the region R2. The node N3 connects the terminal 2d and the terminals 2a, 5a, 2c, and 5c in the region R3. Further, the node N4 connects the terminal 8d and the terminals 8a, 11a, 8c, and 11c in the region R4. Similarly, the node Nm connects the terminal (n-4) d and the terminals (n-4) a, (n-1) a, (n-4) c, and (n-1) c.

  In the first calibration board 50A, the terminals are conceptually divided into groups of three columns. Group 1 includes terminals 1a-3a, 1b-3b, 1c-3c and 1d-3d. Group 2 includes terminals 4a-6a, 4b-6b, 4c-6c and 4d-6d. Similarly, the group (n / 3) includes terminals (n-2) a to na, (n-2) b to nb, (n-2) c to nc, and (n-2) d to nd.

  In the present embodiment, the terminals 1b and 1d are connected to the terminals included in each group one by one in the regions R1 and R2, respectively. The terminal 2d is connected to the terminals 2a, 2c, 5a and 5c included in the region R3 and included in each of a plurality of adjacent groups. The terminal 8d is connected to the terminals 8a, 8c, 11a and 11c included in the region R4 and included in each of a plurality of adjacent groups.

  Here, it should be noted that not only the wirings are provided only in the regions R1 and R2, but also the wirings extending over both the regions R1 and R2 are provided in the regions R3 and R4. Thus, the present embodiment is not limited to the clock signals and strobe signals in the regions R1 and R2 corresponding to a certain type of device under test, but also the clock signals in the regions R3 and R4 corresponding to other types of devices under test and The strobe signal can be adjusted.

  FIG. 3 is a wiring diagram showing the internal configuration of the second calibration board 50B. The second calibration board 50B also includes regions R1 to R4. The arrangement of the terminals 1a to na, 1b to nb, 1c to nc, and 1d to nd is the same as that of the first calibration board 50A. Further, the terminals of the second calibration board 50B are divided into groups 1 to (n / 3) as in the case of the first calibration board 50A.

  However, in the second calibration board 50B, the terminals in the regions R1 and R2 are connected, but the terminal between the regions R1 and R2 is not connected. For example, in the region R1, the node N1a connects the terminals 1a to 3a and 1b to 3b, and connects the node N2a terminals 4a to 6a and 4b to 6b. Similarly, the node N (n / 3) a connects the terminals (n-2) a to na and (n-2) b to nb. In the region R2, the node N1b connects the terminals 1c to 3c and 1d to 3d, and connects the node N2b terminals 4c to 6c and 4d to 6d. Similarly, the node N (n / 3) b connects the terminals (n-2) c to nc and (n-2) d to nd. By using the second calibration board 50B, the phases of the respective clock signals and strobe signals in the regions R1 to R4 can be adjusted for each group.

  In the first calibration board 50A, it is preferable that the time length of the wiring from the driver to the comparator is equal. Also in the second calibration board 50B, it is preferable that the time length of the wiring from the driver to the comparator is equal. The wiring time length means the wiring length converted into the signal delay time. The signal delay time indicates, for example, the RC delay of the wiring. In the first and second calibration boards 50A and 50B, when the wiring time length from the driver to the comparator is different, it is necessary to correct the difference in the wiring time length of each node.

  The first and second calibration boards 50A and 50B are used to execute timing calibration of the semiconductor test apparatus as one calibration board set.

  FIG. 4 is a conceptual diagram showing a connection relationship between the first calibration board 50A, the driver DR, and the comparator CP at the time of calibration. FIG. 5 is a conceptual diagram showing a connection relationship between the second calibration board 50B, the driver DR, and the comparator CP at the time of calibration. At the time of calibration, the terminals 1a to na are connected to drivers DR1a to DRna that apply test signals to the first device under test. The terminals 1b to nb are connected to comparators CP1b to CPnb that perform an operation of comparing output signals from the first device under test. The terminals 1c to nc are connected to drivers DR1c to DRnc that apply a test signal to the second device under test. The terminals 1d to nd are connected to comparators CP1d to CPnd that perform an operation of comparing output signals from the first device under test.

  FIG. 6 is a flowchart of a calibration method using the calibration board sets 50A and 50B according to the present embodiment. The calibration method according to the present embodiment will be described with reference to FIGS.

  First, the first calibration board 50A is set on the performance board 30 (S100). The first calibration board 50A may be set manually or may be set using a dedicated robot. The tester control unit 12 adjusts the phase of the clock signal for each node of the calibration board 50A with reference to the strobe signal (step 101). The adjustment in step S101 is performed by observing the level of the output signal when the strobe signal is output (rises) and the comparison operation by the comparator is performed while gradually changing the rising timing of the clock signal. By this observation, the phase of the clock signal when the level of the output signal of the comparator is inverted can be obtained. Thereby, the phase of the clock signal can be adapted to the phase of the strobe signal.

  First, test signals from the drivers DR1a, DR4a, DR7a, DR10a,... DR (n-2) a are output to the comparator CP1b via the node N1, respectively. Thereby, the test signal from the drivers DR1a, DR4a, DR7a, DR10a,... DR (n-2) a can be adapted to the strobe signal to the comparator CP1b. That is, the phase of the clock signal input to these drivers DR1a, DR4a, DR7a, DR10a,... DR (n-2) a is adapted with reference to the phase of the strobe signal to the comparator CP1b. At this time, the terminal 1b of the calibration board 50A is a reference terminal, and the terminals 1a, 4a,... (N-2) a are adjustment terminals. The reference terminal is a terminal on a calibration board connected to a comparator or driver that inputs a strobe signal or a clock signal as a reference. The adjustment terminal is a terminal on a calibration board connected to a driver or a comparator that inputs a clock signal or strobe signal to be adjusted.

  FIG. 7 is a conceptual diagram showing in more detail the operation of adjusting the phase of the clock signal in step S101. In FIG. 7, DR1a, DR4a,... DR (n-2) a indicate timings of test signals output from the drivers DR1a, DR4a,. N1 in FIG. 7 indicates the timing at which the test signal output from the drivers DR11, DR14,... DR1 (n−2) according to each clock signal reaches the node N1. 7 indicates the timing at which the test signals output from the drivers DR1a, DR4a,... DR (n-2) a arrive at the comparator CP1b via the node N1, respectively.

  The tester control unit 12 shifts the phase of the clock signal CLK1a while fixing the phase of the strobe signal STB1b input to the comparator CP1b (that is, the timing for performing the comparison operation). Thereby, the rising timing of the output signal from the driver DR1a is adjusted so as to match the rising timing of the strobe STB1b. Next, the tester control unit 12 shifts the phase of the clock signal 4a while fixing the phase of the strobe signal STB1b. Thereby, the rising timing of the output signal from driver DR4a is adjusted to match the rising timing of strobe STB1b. Similarly, the adjustment is repeated, and the output signal from the driver DR (n−2) a is also adapted to the rising timing of the strobe STB1b. Thus, the phase of the test signal output from one driver (DR1a, DR4a,... DR (n-2) a) among the three drivers included in each group is the strobe signal STB input to the comparator CP1b. Are sequentially adapted on the basis of the phase.

  The clock signals input to the drivers DR1c, DR4c,... DR (n-2) c connected to the node N2 have the phase of the test signal from the drivers DR1c, DR4c,. It is adjusted to match the phase of the input strobe signal. This adjustment is the same as the adjustment of the clock signal related to the node N1 described above. At this time, the terminal 1d of the calibration board 50A is a reference terminal, and the terminals 1c, 4c,... (N-2) c are adjustment terminals.

  The clock signals for the nodes N3 to Nm are also adjusted in the same manner as the clock signals for the nodes N1 and N2. However, the adjustment of the clock signals related to the nodes N1 and N2 is adjustment in the regions R1 and R2, respectively, but the adjustment of the clock signals related to the nodes N3 to Nm is adjustment in the regions R3, R4.

  More specifically, with respect to the node N3, the tester control unit 12 fixes the phase of the strobe signal input to the comparator CP2d (that is, the timing for performing the comparison operation) and the clock input to the driver DR2a in the region R3. Shift the phase of the signal. Thereby, the rising timing of the output signal from the driver DR2a is adjusted so as to match the rising timing of the strobe signal. Similarly, the clock signals input to the drivers DR5a, DR2c and DR5c in the region R3 connected to the node N3 match the phase of the strobe signal input to the comparator CP2d from the phase of the test signal from these drivers. To be adjusted. At this time, the terminal 2d of the calibration board 50A is a reference terminal, and the terminals 2a, 5a, 2c and 5c are adjustment terminals.

  The clock signals input to the drivers connected to the nodes N4 to Nm are adjusted so that the phases of the test signals from these drivers match the phases of the strobe signals input to the comparators CP8d, CP14d, CP20d,. Is done. Since these adjustments are the same as the adjustment of the clock signal related to the node N3, the description thereof is omitted.

  In the present embodiment, the adjustment related to the node N1 and the adjustment related to the node N2 may be executed in parallel, or may be executed sequentially at different timings. The adjustment regarding the nodes N3 to Nm may be executed in parallel, or may be executed in order at different timings. The calibration time can be shortened by performing the adjustment for the node N1 and the adjustment for the node N2 in parallel and / or the adjustment for the nodes N3 to Nm in parallel. However, when the calibration is executed with respect to the same node, that is, when the reference terminals are the same, the calibration needs to be sequentially performed on a plurality of adjustment terminals.

  Next, the second calibration board 50B is set on the performance board 30 (S102). The tester control unit 12 acquires the phase difference of the strobe signal for each node of the calibration board 50B (S103). Hereinafter, the measurement operation of the phase difference of the strobe signal related to the node N1a will be described.

  FIG. 8 is a conceptual diagram showing the phase measuring operation of the strobe signal with reference to the clock signal CLK1a. The tester control unit 12 measures the phase difference between the strobe signals STB2b and STB3b input to the comparators CP2b and CP3b with reference to the phase of the clock signal CLK1a input to the driver DR1a with respect to the node N1a of the calibration board 50B. Since the clock signal CLK1a and the strobe signal STB1b have the same phase, this measurement is a measurement of the relative phase difference between the strobe signal STB1b and the strobe signals STB2b and STB3b (the relative phase difference between the strobe signals).

  This measurement can be performed by scanning the phase of the strobe signal STB within a predetermined range with the phase of the clock signal CLK1a being fixed. Specifically, the rising timing of the signal output from the driver DR1a corresponding to the clock signal CLK1a and input to the comparator CP via the node N1a is gradually changed until the level of the output signal of the comparator CP is inverted. Let The amount of change when the phase of the strobe signal is changed in this way corresponds to the phase difference of the strobe signal to be measured. This measurement is performed for each of the comparators CP2b and CP3b. However, this measurement may be performed simultaneously on each of the comparators CP2b and CP3b in order to shorten the measurement time.

  For example, it is assumed that the phase difference T1 between the clock signal CLK1a and the strobe signal STB2b and the phase difference T2 between the clock signal CLK1a and the strobe signal STB3b are acquired by this measurement. Since the clock signal CLK1a is adapted to the strobe signal STB1b in step S101, the phase difference between the clock signal CLK1a and the strobe signal STB1b is zero. Therefore, there is no need to measure the phase difference between the clock signal CLK1a and the strobe signal STB1b in step S103.

  FIG. 9 is a conceptual diagram showing the phase measuring operation of the strobe signal with reference to the clock signal CLK2a. The tester control unit 12 measures the phase difference of the strobe signal STB1b input to the comparator CP1b with respect to the node N1a of the calibration board 50B with reference to the phase of the clock signal CLK2a input to the driver DR2a. By this measurement, for example, the phase difference T3 between the clock signal CLK2a and the strobe signal STB1b is acquired.

  Since the phase difference between the clock signal CLK2a and the strobe signals STB2b and STB3b can be relatively calculated from T1 to T3, it is not necessary to measure these phase differences in step S103. Of course, these phase differences may be measured.

  FIG. 10 is a conceptual diagram showing a phase difference measuring operation between the clock signal CLK3a and the strobe signal STB1b.

  The tester control unit 12 measures the phase difference between the clock signal CLK3a input to the driver DR3a and the strobe signal STB1b input to the comparator CP1b with respect to the node N1a of the calibration board 50B. By this measurement, for example, the phase difference T4 between the clock signal CLK3a and the strobe signal STB1b is acquired.

  Next, the tester control unit 12 determines a correction value using the acquired phase difference of each strobe signal (S104). Using the phase differences T1 to T4 obtained in step S103, the phase difference between the clock signal and the strobe signal related to the node N1a is determined as follows. The phase difference between the clock CLK1a and the strobe signal STB1b is almost zero. The phase difference between the clock signal CLK1a and the strobe signal STB2b is T1. The phase difference between the clock CLK1a and the strobe signal STB3b is T2. That is, the phase difference between the strobe signal STB1b and the strobe signal STB2b is T1, and the phase difference between the strobe signal STB1b and the strobe signal STB3b is T2.

  The phase difference between the clock CLK2a and the strobe signal STB1b is T3. The phase difference between the clock CLK3a and the strobe signal STB1b is T4.

  Also for the nodes N2a to N (n / 3) a and the nodes N1b to N (n / 3) b, the phase difference is acquired (S103) and the correction value is determined (S104) in the same manner as the node N1. As a result, the phase difference between the clock signal and the strobe signal and the phase difference between the strobe signals for all the nodes of the second calibration board 50B are acquired. Note that the measurement of the phase difference regarding the nodes N1 to N (n / 3) a and the nodes N1b to N (n / 3) b may be performed simultaneously on each node. Thereby, the measurement time of a phase difference can be shortened.

  Note that the phases of the clock signals CLK2a, CLK5a, CLK2c, and CLK5c are adapted to the phase of the strobe signal STB2d in the region R2 in step S101. Thereby, all the relative phase differences between the clock signal and the strobe signal at the node N1a, the node N2a, the node N1b, and the node N2b in the region R3 are found. The same applies to the region R4. Therefore, all the relative phase differences between the clock signal and the strobe signal in each region in the regions R1 to R4 are found. However, the phase difference between the device regions is not necessary. The phase difference of each node or the phase difference of each device region may be measured in parallel. Thereby, the calibration time can be shortened.

  Information on the relative phase difference between the clock signal and the strobe signal in each of the regions R1 to R4 is stored in the data file or the storage unit 21. When testing the device, information on these phase differences is read out and used.

  The tester control unit 12 corrects the phase of the strobe signal according to the type of device under test (S105). Further, the tester control unit 12 corrects the phase of the clock signal in accordance with the type of device under test (S106). For example, when testing a type of device adapted to the regions R1 and R2, the clock signal and the strobe signal are adjusted according to the phase difference in the nodes N1a to N (n / 3) a corresponding to the region R1, and the region The clock signal and the strobe signal are adjusted according to the phase difference at the nodes N1b to N (n / 3) b corresponding to R2. Adjustment of the phase difference between the regions R1 and R2 is unnecessary.

  On the other hand, for example, when testing a device of a type adapted to the region R3, R4, the clock signal and the strobe signal are adjusted according to the phase difference in the nodes N1a, N1b, N2a, N2b corresponding to the region R3, and The clock signal and the strobe signal are adjusted according to the phase difference at the nodes N3a, N3b, N4a, and N4b corresponding to R4. Adjustment of the phase difference between the regions R3 and R4 is not necessary.

  As described above, in the present embodiment, the phase correction of the strobe signal and the clock signal can be performed in accordance with various forms of the device under test. For example, the semiconductor test apparatus can perform a test by changing the number of special pins used for testing high-speed operation or the like.

  Note that the phase difference in this specification is obtained by correcting the difference in the time length of the wiring when the time length of the wiring from the driver to the comparator is different in the first and second calibration boards 50A and 50B. The phase difference is shown.

  In this embodiment, the terminals in three rows are made into one group, but the terminals in two rows or less may be made into one group, or the terminals with more than four rows may be made into one group.

  In the present embodiment, the calibration board 50A is applied and then the calibration 50B is applied. However, the application order of the calibration boards 50A and 50B may be reversed.

  In the present embodiment, device regions subsequent to the regions R1 and R2 may be further adjacent in the first direction. Further, the device region following the regions R3 and R4 may be further adjacent to the group (n / 3) in the second direction.

  In this embodiment, the number of pins of the device under test in the regions R1 and R2 is different from the number of pins of the device under test in the regions R3 and R4. However, the number of pins in the regions R1 and R2 and the regions R3 and R4 may be equal.

1 is a conceptual diagram of a calibration board and a semiconductor test apparatus that is a target of timing calibration according to an embodiment of the present invention. The wiring diagram which shows the internal structure of 50 A of 1st calibration boards. The wiring diagram which shows the internal structure of the 2nd calibration board 50B. The conceptual diagram which shows the connection relation of the 1st calibration board 50A, driver DR, and comparator CP at the time of calibration. The conceptual diagram which shows the connection relationship with the 2nd calibration board 50B, the driver DR, and the comparator CP at the time of calibration. The flowchart of the calibration method using the calibration board sets 50A and 50B by this embodiment. The conceptual diagram which shows the adjustment operation | movement of the phase of a clock signal in step S101. The conceptual diagram which shows the measurement operation | movement of the phase of the strobe signal on the basis of the clock signal CLK1a. The conceptual diagram which shows the measurement operation | movement of the phase of the strobe signal on the basis of the clock signal CLK2a. The conceptual diagram which shows the measurement operation | movement of the phase difference of clock signal CLK3a and strobe signal STB1b.

Explanation of symbols

50A ... First calibration board 50B ... Second calibration boards 1a-na, 1b-nb, 1c-nc, 1d-nd ... Terminals N1-Nm, N1a-N (n / 3) a, N1b-N (N / 3) b: Nodes DR1a to DRna, DR1b to DRnb, DR1c to DRnc, DR1d to DRnd ... Drivers CP1a to CPna, CP1b to CPnb, CP1c to CPnc, CP1d to CPnd ... Comparator CLK ... Clock STB ... Strobe

Claims (9)

A driver for generating a test signal synchronized with a clock signal for a plurality of devices under test, and a comparator for comparing the result signals output from the plurality of devices under test in synchronization with a strobe signal based on the test signals A calibration board set for calibrating a semiconductor test apparatus provided,
First and second device regions arranged to correspond to a certain type of device under test and adjacent to each other in the first direction, and to another type of device under test and to the first direction And third and fourth device regions arranged adjacent to each other in a second direction orthogonal to each other, and each of the first and second device regions is based on one of the clock signal and the strobe signal. And a first calibration board for adjusting the other phase based on one of the clock signal and the strobe signal in each of the third and fourth device regions. When,
Second calibration for obtaining a relative phase difference between the clock signals corresponding to each of the plurality of drivers, or a relative phase difference between the strobe signals corresponding to each of the plurality of comparators. Calibration board set with a calibration board. The first calibration board and the second calibration board set are:
A reference terminal connected to an element that inputs one of the clock signal or the strobe signal serving as a reference;
A plurality of adjustment terminals connected to an element that inputs the other of the clock signal or the strobe signal to be adjusted;
The calibration board set according to claim 1, further comprising a node that electrically connects the reference terminal and the plurality of adjustment terminals. A driver for generating a test signal synchronized with a clock signal for a plurality of devices under test, and a comparator for comparing the result signals output from the plurality of devices under test in synchronization with a strobe signal based on the test signals A semiconductor test apparatus comprising:
First and second device regions arranged to correspond to a certain type of device under test and adjacent to each other in the first direction, and to another type of device under test and to the first direction And third and fourth device regions arranged adjacent to each other in a second direction orthogonal to each other, and each of the first and second device regions is based on one of the clock signal and the strobe signal. The other phase is adjusted, and each of the third and fourth device regions corresponds to a device under test adjacent to the device under test on the basis of one of the clock signal or the strobe signal. A first calibration board for adjusting the other phase of the clock signal or the strobe signal;
Second calibration for obtaining a relative phase difference between the clock signals corresponding to each of the plurality of drivers, or a relative phase difference between the strobe signals corresponding to each of the plurality of comparators. Semiconductor test equipment equipped with an operation board. The first calibration board and the second calibration board set are:
A reference terminal connected to an element that inputs one of the clock signal or the strobe signal serving as a reference;
A plurality of adjustment terminals connected to an element that inputs the other of the clock signal or the strobe signal to be adjusted;
The semiconductor test apparatus according to claim 3, further comprising a node that electrically connects the reference terminal and the plurality of adjustment terminals.   5. The semiconductor test apparatus according to claim 3, further comprising a storage unit that stores a phase difference between the clock signal and the strobe signal in the first to fourth device regions. A driver for generating a test signal synchronized with a clock signal for a plurality of devices under test, and a comparator for comparing the result signals output from the plurality of devices under test in synchronization with a strobe signal based on the test signals A calibration method for adjusting a semiconductor test apparatus provided using a calibration board,
The phase of the other of the first and second device regions corresponding to a certain type of device under test and arranged adjacent to each other in the first direction is adjusted based on one of the clock signal and the strobe signal. And the clock signal in each of the third and fourth device regions corresponding to other types of devices under test and arranged adjacent to each other in a second direction orthogonal to the first direction. Or adjusting the other phase with reference to one of the strobe signals;
Obtaining a relative phase difference between the clock signals corresponding to each of the plurality of drivers or a relative phase difference between the strobe signals corresponding to each of the plurality of comparators. Method. Based on the form of the device under test,
Step A: adjusting the phase of each of the clock signal and the strobe signal in the first and second device regions based on the relative phase difference;
Step B: adjusting the phase of each of the clock signal and the strobe signal in the third and fourth device regions based on the relative phase difference;
The calibration method according to claim 6, further comprising a step of selectively executing either step A or step B.   The calibration method according to claim 6, wherein the phase of the other is simultaneously adjusted based on one of the plurality of clock signals or the plurality of strobe signals.   A relative phase difference between the clock signals corresponding to each of the plurality of drivers or a relative phase difference between the strobe signals corresponding to each of the plurality of comparators is simultaneously acquired. The calibration method according to any one of claims 6 to 8.

Images