JP2008004749A - Semiconductor device - Google Patents

Abstract

A semiconductor device having a high-performance field-effect transistor with a high ON / OFF ratio in which a channel region is formed of carbon nanotubes is provided.
A semiconductor device having a field effect transistor in which a channel region is formed of a carbon nanotube 1, wherein the chirality (n, m) of the carbon nanotube 1 is n−m = 3p + 1 where p is an integer, or n A semiconductor device represented by −m = 3p−1, wherein a tensile force or a compressive strain is applied in a direction parallel to the axis of the carbon nanotube.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a field effect transistor in which a channel region is formed of carbon nanotubes.

  Silicon super integrated circuits (LSIs) are one of the fundamental technologies that will support the advanced information society in the future. In order to increase the functionality of an integrated circuit, it is necessary to improve the performance of the MIS field effect transistor that is a component of the integrated circuit. The enhancement of device performance has been basically done by the proportional reduction law (scaling), but in recent years, due to various physical limitations, not only the enhancement of device performance by ultra-miniaturization of the device but also the operation of the device itself is difficult. It is in the situation. In order to overcome this situation, attempts have been made all over the world to realize a high-performance transistor by forming a channel region using a material that changes to silicon.

For example, an attempt to form a channel region of a p-type field effect transistor with germanium, an attempt to form a channel region of an n-type field effect transistor with a compound semiconductor such as gallium arsenide or indium arsenide, and a channel region with a carbon nanotube There are attempts to form it. In particular, the method of forming a channel region with carbon nanotubes facilitates the realization of a field effect transistor with a fine gate length, and the channel region of both n-type and p-type field effect transistors with a single material. It is very promising because it can be formed.
Therefore, a Schottky transistor in which the channel region is formed of carbon nanotubes and the metal / carbon nanotube (semiconductor) junction is the source / drain junction, or an n-type layer is formed by doping potassium, and the pn junction is the source -Transistors having drain junctions have been energetically studied (for example, Non-Patent Document 1).

  However, in the future, in order to use a field effect transistor in which a channel region is formed of carbon nanotubes, a so-called carbon nanotube transistor, in an actual LSI device, a technique for continuously improving the performance of the carbon nanotube transistor is necessary. It is. In the case of a conventional silicon transistor, by shortening the gate length and optimizing the impurity profile, it is possible to realize a transistor with a large ON current and a high ON / OFF ratio while suppressing the OFF current. It was. However, in the carbon nanotube transistor, ballistic transport is realized in which charge carriers are hardly scattered in the channel. Therefore, even if the channel length is shortened, it is not possible to expect an increase in charge carrier mobility due to reduction of scattering in the channel, and there is a problem that the ON current hardly increases.

Regarding this problem, it has been reported that the ON current increases by increasing the diameter of the carbon nanotube (Non-Patent Document 2). However, it has been found that increasing the diameter of the carbon nanotubes increases the OFF current as well as the ON current. Therefore, a truly high-performance carbon nanotube transistor having a large ON current and a small OFF current has not been realized.
As described above, the carbon nanotube transistor requires a guideline for making a high-performance transistor with a higher ON / OFF ratio, that is, a guideline for improving performance instead of miniaturization in the case of a silicon transistor. .
A. Javey et al. , Nano Letters, vol. 5, no. 2, pp 345-348, 2005. J. et al. Guo et al, IEEE Transactions on Electron Devices, Vol. 51, no. 2, pp 172-177, 2004.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having a high-performance field effect transistor with a high ON / OFF ratio in which a channel region is formed of carbon nanotubes. There is.

A semiconductor device of one embodiment of the present invention includes:
A semiconductor device having a field effect transistor having a channel region formed of carbon nanotubes,
The chirality (n, m) of the carbon nanotube is represented by nm = 3p + 1, where p is an integer,
A tensile strain is applied in a direction parallel to the axis of the carbon nanotube.

In addition, a semiconductor device of one embodiment of the present invention includes
A semiconductor device having a field effect transistor having a channel region formed of carbon nanotubes,
The chirality (n, m) of the carbon nanotube is represented by nm = 3p-1 where p is an integer,
A compressive strain is applied in a direction parallel to the axis of the carbon nanotube.

Here, the diameter of the carbon nanotube is 1 nm to 3 nm, more preferably 1.5 nm to 3 nm,
It is desirable that the equivalent gate oxide film thickness of the gate insulating film of the field effect transistor is more than 0 and 0.5 nm or less.

The field effect transistor is formed on an insulating film,
It is desirable that the insulating film has a silicon oxide equivalent film thickness of 160 nm or more.

In addition, a semiconductor device of one embodiment of the present invention includes
A semiconductor device having an n-type field effect transistor having a channel region formed of carbon nanotubes and a p-type field effect transistor having a channel region formed of carbon nanotubes,
The chirality (n, m) of the carbon nanotube of the n-type field effect transistor is represented by nm = 3p + 1, where p is an integer,
The chirality (j, k) of the carbon nanotube of the p-type field effect transistor is represented by j−k = 3q + 1, where q is an integer,
The carbon nanotubes of the n-type field effect transistor and the carbon nanotubes of the p-type field effect transistor are arranged in parallel,
A tensile strain is applied in a direction parallel to the axis of the carbon nanotube of the n-type field effect transistor and the axis of the carbon nanotube of the p-type field effect transistor.

In addition, a semiconductor device of one embodiment of the present invention includes
A semiconductor device having an n-type field effect transistor having a channel region formed of carbon nanotubes and a p-type field effect transistor having a channel region formed of carbon nanotubes,
The chirality (n, m) of the carbon nanotube of the n-type field effect transistor is represented by nm = 3p-1 where p is an integer,
The carbon nanotube chirality (j, k) of the p-type field effect transistor is represented by jk = 3q-1 where q is an integer,
The carbon nanotubes of the n-type field effect transistor and the carbon nanotubes of the p-type field effect transistor are arranged in parallel,
Compressive strain is applied in a direction parallel to the axis of the carbon nanotube of the n-type field effect transistor and the axis of the carbon nanotube of the p-type field effect transistor.

  According to the present invention, it is possible to provide a semiconductor device having a high-performance field effect transistor with a high ON / OFF ratio in which a channel region is formed of carbon nanotubes.

The inventor of the present invention, in a field effect transistor having a channel region formed of carbon nanotubes (hereinafter referred to as a carbon nanotube transistor), in parallel to the axial direction of the carbon nanotubes forming the channel, according to the chirality of the carbon nanotubes, It has been found that applying tensile or compressive strain is effective in improving the performance of a carbon nanotube transistor.
Here, the chirality is a parameter that characterizes the structure of the carbon nanotube. Carbon nanotubes have a structure in which a graphite sheet is wound, and the structural parameter for specifying the winding method is chirality.
Hereinafter, the characteristics of the carbon nanotube transistor found by the inventors and the principle thereof will be described in detail while explaining embodiments of the present invention.

(First embodiment)
FIG. 1 is a schematic view showing an element structure of a semiconductor device having a carbon nanotube transistor according to the first embodiment of the present invention. The carbon nanotube transistor of the present embodiment is an n-type carbon nanotube transistor using electrons as carriers.

  The carbon nanotube transistor of FIG. 1 includes a carbon nanotube 1 that forms a channel region, and a gate electrode 7 on the channel region (or the surface of the channel region) via a gate insulating film 6. Further, source / drain regions 5 are provided on both sides of the channel region. A contact electrode 4 is formed in contact with the source / drain region 5. A tensile strain is applied to the carbon nanotube forming the channel region in a direction parallel to the axis (the arrow direction in FIG. 1). Details of the configuration will be described below.

A carbon nanotube transistor is formed using a silicon substrate 3 on which a buried insulating film 2 made of a silicon oxide film having a thickness of 500 nm is formed as a supporting substrate. The diameter of the carbon nanotube 1 forming the channel region is about 1.5 nm. In addition, carbon nanotubes with chirality (19,0) satisfying the relationship represented by nm = 3p + 1, where p is an integer, are used.
On the carbon nanotube, a gate electrode 7 is formed via a gate insulating film 6 made of HfO ₂ having a physical thickness of 8 nm (equivalent thickness of silicon oxide film is about 2 nm). The gate length is about 75 nm. The source / drain regions 5 are made n-type by doping potassium (K), for example, in the range of about 87.5 nm in the horizontal direction, and electrons of about 1.2 × 10 ⁷ / cm are induced. . Further, for example, a contact electrode 4 made of palladium (Pd) is formed in contact with the source / drain regions.
A tensile strain is applied to the carbon nanotube forming the channel region in a direction parallel to the axis (the arrow direction in FIG. 1).

FIG. 2 shows a simulation result of the tensile strain dependence of the drain current of the carbon nanotube transistor of this embodiment. The horizontal axis is the gate voltage, and the vertical axis is the drain current shown in linear and log scale. The drain voltage (Vd) was 0.5 V, and the tensile strain was calculated based on the stretch rate of the carbon nanotubes under the conditions of 0% (no strain), 1% tensile strain, and 3% tensile strain.
As is apparent from this figure, as the tensile strain is applied, the OFF current (the drain current when the gate voltage is 0 V or less) decreases dramatically. On the other hand, when a tensile strain is applied, the ON current also decreases slightly, but the effect of reducing the OFF current is dramatic. Therefore, as shown in Table 1, the ON / OFF ratio increases dramatically by applying tensile strain. Therefore, according to this embodiment, a high-performance carbon nanotube transistor having a large ON / OFF ratio, that is, excellent switching characteristics can be realized.

  Here, the reason why the OFF current is reduced by applying tensile strain can be understood from the fact that the band gap of the carbon nanotube is increased. When the tensile strain is applied when the chirality (n, m) of the carbon nanotube is n−m = 3p + 1 where p is an integer, the chirality (n, m) of the carbon nanotube is nm = 3p−1 where p is an integer. It has been reported that the band cap of carbon nanotubes increases when compressive strain is applied at the time (L. Yang et al., Physical Review Lett, Vol. 85, No. 1, pp154-157, 2000. ). Therefore, in the present embodiment where the chirality (n, m) satisfies the condition of n−m = 3p + 1 where p is an integer, it is considered that the band gap of the carbon nanotube is increased by applying tensile strain. Therefore, it can be understood that the interband tunnel current, which is the main component of the leakage current (OFF current) between the source and drain of the carbon nanotube transistor, is suppressed, and the OFF current is reduced.

On the other hand, as described above, the ON current is slightly reduced by applying tensile strain. However, this decrease in ON current cannot always be explained by an increase in band gap.
Therefore, in order to clarify the physical origin of the ON current decrease, the inventor calculated the dependence of the state density of the carbon nanotube on the tensile strain. The result is shown in FIG. The horizontal axis indicates the electron energy in units of electron volts, and the vertical axis indicates the density of states. As is apparent from the figure, the density of states increases as the tensile strain is applied.
Here, in general, the higher the density of states, the lower the Fermi level when a constant gate voltage is applied. In ballistic conduction realized in carbon nanotubes, the lower the Fermi level, the smaller the drain current (ON current) that flows. Therefore, in the carbon nanotube transistor, it can be said that the drain current (ON current) is reduced by increasing the tensile strain. In other words, the ON current of the carbon nanotube transistor having a relationship of chirality (n, m) of carbon nanotubes where n is m = 3p + 1, where p is an integer, decreases with increasing tensile strain (1) due to tensile strain It has become clear that this occurs in the process of increasing the density of states, (2) decreasing the Fermi level, and (3) decreasing the drain current (ON current).

  In the carbon nanotube transistor, the diameter of the carbon nanotube is 1.5 nm. The diameter of the carbon nanotube is preferably 1 nm to 3 nm, more preferably 1.5 nm to 3 nm. This is because when the diameter is less than 1.5 nm, the band gap is widened and the ON current is significantly reduced. When the diameter is less than 1 nm, the reduction is further noticeable, and the reduction of the driving capability of the transistor becomes a problem in practical use. It is. On the other hand, if it exceeds 3 nm, the band gap of the carbon nanotube becomes too small, and it becomes difficult to function as a semiconductor at room temperature.

In the carbon nanotube transistor, the thickness of the buried insulating film 2 (FIG. 1) made of the silicon oxide film of the support substrate is 500 nm. The thickness of the buried insulating film 2 is equivalent to the thickness of the silicon oxide film. It is desirable that it is 160 nm or more. This is because as the buried insulating film becomes thinner, the leakage current increases, and when the equivalent silicon oxide film thickness is less than 160 nm, there is a high possibility that the standby current specification of the high-performance logic LSI cannot be satisfied.
FIG. 4 shows a simulation result of the dependency of the drain current of the carbon nanotube transistor of this embodiment on the buried insulating film thickness. The horizontal axis represents the gate voltage, the vertical axis represents the drain current in the log scale display, and the drain voltage (Vd) is 0.5V. The calculation was performed while changing the equivalent oxide thickness of the buried insulating film from 5 nm to 500 nm. As can be seen from the figure, the leakage current (the minimum value of the drain current) increases as the buried insulating film becomes thinner. Here, in order to satisfy the standby current specification of the logic LSI, it is desirable that the total leakage current amount of 100 carbon nanotubes is 100 nA or less. That is, the leakage current amount of one carbon nanotube is desirably 1 nA or less. Therefore, from FIG. 4, in order to satisfy this condition, it is desirable that the equivalent oxide thickness of the buried insulating film is 160 nm or more.

The reason why the leakage current decreases when the buried insulating film is thick and increases when the buried insulating film is thin will be described with reference to the band diagrams of the source / drain and channel regions in FIG.
FIG. 5A is a band diagram when the equivalent oxide thickness of the buried insulating film is 500 nm, and FIG. 5B is a band diagram when the equivalent oxide thickness of the buried insulating film is 10 nm. A band-to-band tunnel of carriers (electrons and holes) that causes a leak current occurs in the vicinity of the Fermi level indicated by a broken line. The distance (tunnel distance) between the conduction band edge profile (Ec) and the valence band edge profile (Ev) in the vicinity of the broken line is longer in FIG. 5A and shorter in FIG. 5B. I understand that. Thus, if the buried insulating film is thin, it is easily affected by the potential of the support substrate, and the profile in the source / drain region becomes constant (approximately the same as the potential of the support substrate). The potential at the transition from to the channel region becomes steep. Therefore, the tunnel distance is shortened and the leakage current is increased.

  As described above, the semiconductor device having an n-type carbon nanotube transistor using electrons as a carrier has been described. However, since the band structure of the carbon nanotube is completely symmetrical between the valence band side and the conduction band side, The p-type carbon nanotube transistor used as a carrier can obtain the same operation and effect.

  Next, a method for manufacturing a semiconductor device having a carbon nanotube transistor of this embodiment will be described.

First, a silicon substrate serving as a support substrate is oxidized in an oxygen atmosphere at 1000 ° C. to form a 500 nm silicon oxide film.
Next, single-walled carbon nanotubes separately prepared by the CVD method are put into water to which a surfactant (for example, Triton X-100) is added, and ultrasonic waves are applied to form single-walled carbon nanotubes one by one. Make a separate solution.
By spin-coating this solution onto a silicon substrate as a support substrate, single-walled carbon nanotubes are randomly distributed on the silicon oxide film.
Since the chirality of each single-walled carbon nanotube can be examined by using a scanning tunneling microscope, the single-walled carbon satisfying the condition that the chirality (n, m) satisfies nm = 3p + 1 where p is an integer. Only nanotubes are sorted on the silicon oxide film.
The selected single-walled carbon nanotubes are arranged in a region that becomes a channel of a transistor using an atomic force microscope or the like, and single-walled carbon nanotubes that do not satisfy other chirality conditions are excluded from the region that becomes an integrated circuit.

Next, a gate insulating film made of 8 nm of HfO ₂ and a gate electrode are formed on the channel region, and then an electrode made of palladium (Pd) or the like is formed by a lift-off method.
Then, by depositing potassium (K) in a region between the gate electrode and the source / drain electrodes to form an n-type layer, an n-type carbon nanotube transistor is formed.
In addition, when forming a p-type carbon nanotube transistor, special doping is unnecessary.
Then, an upper layer film having a tensile stress, for example, a silicon nitride film is deposited on the n-type carbon nanotube transistor to apply a tensile strain parallel to the axial direction of the carbon nanotube. In this embodiment, in order to realize high performance of the transistor, it is necessary to apply tensile strain. However, in the case where it is necessary to apply compressive strain as in the following embodiment, This can be realized by changing the film formation conditions and film type of the silicon nitride film to be deposited. Also, when packaging a semiconductor device, it is possible to mount an element (semiconductor device) on which a carbon nanotube transistor is mounted on a bed curved in a concave shape or a convex shape by adhering along the bed shape. It is possible to apply tensile / compressive strain.

(Second Embodiment)
Next, a semiconductor device having a carbon nanotube transistor according to the second embodiment of the present invention will be described. The semiconductor device according to the present embodiment is the same as the semiconductor device according to the first embodiment except that the gate insulating film has a thickness equivalent to a silicon oxide film thickness of 0.5 nm or less. The description is omitted.
Here, the equivalent silicon oxide film thickness is obtained by multiplying the thickness of the gate insulating film by the ratio of the dielectric constant of the gate insulating film to that of the silicon oxide film.
In this embodiment, for example, HfO ₂ having a physical film thickness of 0.8 nm can be applied to the gate insulating film. In this case, the equivalent silicon oxide film thickness is about 0.2 nm.

FIG. 6 shows a simulation of the dependence of the drain current on the tensile strain of the n-type carbon nanotube transistor of the present embodiment in which HfO ₂ having a physical thickness of 0.8 nm is applied to the gate insulating film in the structure of the first embodiment. Results are shown. The horizontal axis is the gate voltage, and the vertical axis is the drain current shown in linear and log scale. The drain voltage (Vd) was set to 0.5 V, and the tensile strain was calculated based on the stretching rate of the carbon nanotubes under the conditions of 0% (no strain) and 3% tensile strain.

  As is apparent from this figure, by applying a tensile strain of 3%, the OFF current is dramatically reduced as in the first embodiment. It should also be noted that the ON current is increased by applying tensile strain.

Here, it can be understood using the gate insulating film capacitance Cox and the channel quantum capacitance Cq that the ON current increases due to the tensile strain when the thickness of the gate insulating film is reduced as in the present embodiment. can do.
The total capacity (total capacity) Ctot is obtained as 1 / Ctot = 1 / Cq + 1 / Cox as the combined capacity of these two. The number of carriers that flow in the channel is determined by Ctot × Vg, where the gate voltage is Vg.

When the gate insulating film is thick and Cox is smaller than Cq, the total capacitance Ctot is dominated by Cox. At this time, the number of carriers induced when a gate voltage is applied is substantially constant regardless of the density of states. On the other hand, as described above, the Fermi level decreases as the state density increases (as the strain increases), and the drain current (ON current) decreases.
On the other hand, since the Cox increases as the gate insulating film becomes thinner, the total capacitance Ctot is dominated by Cq. Therefore, when tensile strain is applied and the density of states increases, the quantum capacity Cq increases, and as a result, Ctot also increases. Therefore, it can be understood that the number of carriers that can be induced with the same gate voltage increases and the drain current (ON current) also increases.
Thus, when the gate insulating film is made 0.5 nm or less in terms of a silicon oxide film, Cox becomes sufficiently larger than Cq. Therefore, an increase in quantum capacitance Cq due to tensile strain contributes to an increase in ON current.

  Therefore, by setting the gate insulating film to 0.5 nm or less in terms of silicon oxide film as in this embodiment, the ON current is increased in addition to the improvement of the ON / OFF ratio, and the switching characteristics are excellent and high. A semiconductor device having a high-performance carbon nanotube transistor having driving force can be realized.

(Third embodiment)
Next, a semiconductor device having a carbon nanotube transistor according to the third embodiment of the present invention will be described. In the semiconductor device of this embodiment, the chirality (n, m) of the carbon nanotube satisfies the relationship represented by nm = 3p−1 where p is an integer, and the channel region is formed by the chirality (20, 0) carbon nanotube. And the carbon nanotube forming the channel region is the same as the semiconductor device of the first embodiment except that a compressive strain is applied in a direction parallel to the axis. Is omitted.

FIG. 7 shows a simulation result of the dependence of the drain current of the carbon nanotube transistor of this embodiment on the amount of compressive strain. The horizontal axis is the gate voltage, and the vertical axis is the drain current shown in linear and log scale. The drain voltage (Vd) was 0.5 V, and the amount of compressive strain was calculated based on the expansion / contraction ratio of the carbon nanotubes under the following conditions: 0% (no strain), 1% compressive strain, and 3% compressive strain.
As is apparent from this figure, as compressive strain is applied, the OFF current (drain current when the gate voltage is 0 V or less) decreases dramatically. On the other hand, when compressive strain is applied, the ON current also decreases slightly, but the effect of reducing the OFF current is dramatic. Therefore, according to this embodiment, a high-performance carbon nanotube transistor having a large ON / OFF ratio, that is, excellent switching characteristics can be realized.

Although the present embodiment differs from the first embodiment in the chirality of carbon nanotubes and the direction in which strain is applied, the functions and effects are exactly the same.
As for the action and effect, the decrease in the OFF current is caused by the increase in the band gap due to the compressive strain, and the decrease in the ON current is caused by the increase in the state density due to the compressive strain shown in the state density diagram of FIG. This is also the same as in the first embodiment.

(Fourth embodiment)
Next, a semiconductor device having a carbon nanotube transistor according to the fourth embodiment of the present invention will be described. In the semiconductor device of this embodiment, the chirality (n, m) of the carbon nanotube satisfies the relationship represented by nm = 3p−1 where p is an integer, and the channel region is formed by the chirality (20, 0) carbon nanotube. And the carbon nanotube forming the channel region is the same as the semiconductor device of the second embodiment except that a compressive strain is applied in a direction parallel to the axis thereof. Is omitted.

  FIG. 9 shows a simulation result of the compressive strain dependence of the drain current of the n-type carbon nanotube transistor of this embodiment. The horizontal axis is the gate voltage, and the vertical axis is the drain current shown in linear and log scale. The drain voltage (Vd) was 0.5 V, and the amount of compressive strain was calculated based on the expansion / contraction ratio of the carbon nanotubes under the following conditions: 0% (no strain), 1% compressive strain, and 3% compressive strain.

  As is apparent from this figure, it can be seen that, by applying compressive strain, the OFF current is dramatically reduced as in the second embodiment, and the ON current is also increased by applying compressive strain. .

Although the present embodiment is different from the second embodiment in the chirality of carbon nanotubes and the direction in which strain is applied, the operation and effect are exactly the same.
As for the action and effect, the decrease in the OFF current is caused by the increase in the band gap due to the compressive strain, and the increase in the ON current is caused by the thinning of the gate insulating film and the compressive strain shown in the state density diagram of FIG. This is the same as in the second embodiment in that it is caused by an increase in the state density due to.

(Fifth embodiment)
FIG. 10 shows a semiconductor device having a carbon nanotube transistor according to the fifth embodiment of the present invention.
The semiconductor device according to the present embodiment is characterized in that a CMOS circuit including an n-type carbon nanotube transistor 105 and a p-type carbon nanotube transistor 106 is formed. In FIG. 10, a CMOS inverter is described as an example of a CMOS circuit. That is, the n-type carbon nanotube transistor 105 and the p-type carbon nanotube transistor 106, the power supply terminal 104 connected to the source of the p-type carbon nanotube transistor 106, the ground terminal 103 connected to the source of the n-type carbon nanotube transistor 105, n An input terminal 101 connected to the gate electrodes of both the p-type carbon nanotube transistor 105 and the p-type carbon nanotube transistor 106 and an output terminal 102 connected to the drains of both are formed.
The chirality (n, m) of the carbon nanotube forming the channel region of the n-type carbon nanotube transistor 105 is represented by nm = 3p + 1, where p is an integer, and the channel region of the p-type carbon nanotube transistor 106 is formed. The chirality (j, k) of the carbon nanotube to be expressed is represented by nm = 3q + 1 where q is an integer.

  Also, the carbon nanotubes of the n-type carbon nanotube transistor 105 and the carbon nanotubes of the p-type carbon nanotube transistor 106 are arranged in parallel as shown in FIG. Tensile strain is applied in a direction parallel to the axis of the carbon nanotube of the n-type carbon nanotube transistor 105 and the axis of the carbon nanotube of the p-type carbon nanotube transistor 106 (in the direction of the arrow in FIG. 10).

Carbon nanotubes / transistors improve their properties by applying tensile / compressive strain according to their chirality, and whether the tensile / compressive strain improves the properties is determined solely by chirality, and the carrier type (electron or hole) Do not depend on.
Therefore, as in the present embodiment, an n-type carbon nanotube transistor having a chirality (n, m) of nm = 3p + 1 and a p-type carbon nanotube transistor having a chirality (j, k) of nm = 3q + 1 Are arranged in parallel, and tensile strain is applied to the whole to improve the characteristics of both the n-type and p-type carbon nanotube transistors. Therefore, a semiconductor device having excellent switching characteristics, a low power consumption, and a high-speed CMOS circuit can be realized.

(Sixth embodiment)
In the semiconductor device having the carbon nanotube transistor according to the sixth embodiment of the present invention, the chirality (n, m) of the carbon nanotube of the n-type field effect transistor is represented by nm = 3p−1 where p is an integer. , The chirality (j, k) of the carbon nanotube of the p-type field effect transistor is represented by jk = 3q-1 where q is an integer, and the carbon nanotube axis of the n-type field effect transistor and the carbon of the p-type field effect transistor The description is omitted because it is the same as that of the fifth embodiment except that compressive strain is applied in the direction parallel to the axis of the nanotube.

  Also in this embodiment, the direction of applying strain is different from that of the fifth embodiment, but by applying strain, the characteristics of both the n-type and p-type carbon nanotube transistors are improved. Therefore, as in the fifth embodiment, a semiconductor device having excellent switching characteristics, low power consumption, and a high-speed CMOS circuit can be realized.

  In addition, this invention is not limited to each embodiment mentioned above. For example, for single-walled carbon nanotubes, not only single-walled nanotubes but also multi-walled carbon nanotubes can be applied. Various modifications can be made without departing from the scope of the present invention.

1 is a schematic diagram showing an element structure of a semiconductor device according to a first embodiment. The figure which shows the tensile strain amount dependence of the drain current of the semiconductor device of 1st Embodiment. The figure which shows the tensile strain amount dependence of the state density of 1st Embodiment. FIG. 6 is a diagram showing the dependency of drain current on the buried insulating film thickness of the semiconductor device of the first embodiment. FIG. 3 is a band diagram of source / drain and channel regions of the semiconductor device of the first embodiment. The figure which shows the tensile strain amount dependence of the drain current of the semiconductor device of 2nd Embodiment. The figure which shows the amount of compressive strain dependence of the drain current of the semiconductor device of 3rd Embodiment. The figure which shows the compressive strain amount dependence of the state density of 3rd Embodiment. The figure which shows the compressive strain amount dependence of the drain current of the semiconductor device of 4th Embodiment. Schematic which shows the element structure of the semiconductor device of 5th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Carbon nanotube 2 Embedded insulating film 3 Silicon substrate 4 Contact electrode 5 Source / drain region 6 Gate insulating film 7 Gate electrode 101 Input terminal 102 Output terminal 103 Ground terminal 104 Power supply terminal 105 n-type carbon nanotube transistor 106 p-type carbon nanotube Transistor

Claims (6)

A semiconductor device having a field effect transistor having a channel region formed of carbon nanotubes,
The chirality (n, m) of the carbon nanotube is represented by nm = 3p + 1, where p is an integer,
A semiconductor device, wherein a tensile strain is applied in a direction parallel to the axis of the carbon nanotube. A semiconductor device having a field effect transistor having a channel region formed of carbon nanotubes,
The chirality (n, m) of the carbon nanotube is represented by nm = 3p-1 where p is an integer,
A semiconductor device, wherein a compressive strain is applied in a direction parallel to the axis of the carbon nanotube. The diameter of the carbon nanotube is 1 nm to 3 nm, more preferably 1.5 nm to 3 nm,
3. The semiconductor device according to claim 1, wherein the gate oxide film of the field effect transistor has a silicon oxide equivalent film thickness of more than 0 and 0.5 nm or less. The field effect transistor is formed on an insulating film;
4. The semiconductor device according to claim 1, wherein the insulating film has a silicon oxide equivalent film thickness of 160 nm or more. A semiconductor device having an n-type field effect transistor having a channel region formed of carbon nanotubes and a p-type field effect transistor having a channel region formed of carbon nanotubes,
The chirality (n, m) of the carbon nanotube of the n-type field effect transistor is represented by nm = 3p + 1, where p is an integer,
The chirality (j, k) of the carbon nanotube of the p-type field effect transistor is represented by j−k = 3q + 1, where q is an integer,
The carbon nanotubes of the n-type field effect transistor and the carbon nanotubes of the p-type field effect transistor are arranged in parallel,
A semiconductor device, wherein a tensile strain is applied in a direction parallel to an axis of the carbon nanotube of the n-type field effect transistor and an axis of the carbon nanotube of the p-type field effect transistor. A semiconductor device having an n-type field effect transistor having a channel region formed of carbon nanotubes and a p-type field effect transistor having a channel region formed of carbon nanotubes,
The chirality (n, m) of the carbon nanotube of the n-type field effect transistor is represented by nm = 3p-1 where p is an integer,
The carbon nanotube chirality (j, k) of the p-type field effect transistor is represented by jk = 3q-1 where q is an integer,
The carbon nanotubes of the n-type field effect transistor and the carbon nanotubes of the p-type field effect transistor are arranged in parallel,
A semiconductor device, wherein a compressive strain is applied in a direction parallel to an axis of the carbon nanotube of the n-type field effect transistor and an axis of the carbon nanotube of the p-type field effect transistor.

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