JP2008004692A - Solid-state imaging device - Google Patents

Abstract

In a solid-state imaging device capable of performing an electronic shutter operation simultaneously for all pixels, it is possible to reduce noise by reducing a charge generated in a deep portion of a semiconductor region from entering a charge storage portion.
A P-type well is disposed on an N-type substrate. The pixel includes an N-type charge storage unit 3 that accumulates charges transferred from the photodiode 1, an amplification transistor that outputs a signal corresponding to the charge amount of the floating diffusion 4, and a charge from the photodiode 1 to the charge storage unit 3. The first transfer gate unit 11 for transferring the charge and the second transfer unit 5 for transferring the charge from the charge storage unit 3 to the floating diffusion 4 are provided. A P-type layer 30 having an impurity concentration higher than that of the P-type well 22 is provided below at least a part of the charge storage unit 3 via a part of the P-type well 22.
[Selection] Figure 3

Description

  The present invention relates to a solid-state imaging device that captures a subject image.

  In recent years, video cameras, electronic still cameras, and the like have been widely used. For these cameras, CCD type or amplification type solid-state imaging devices are used. In an amplification type solid-state imaging device, signal charges generated and accumulated in a photoelectric conversion unit of a light receiving pixel are guided to an amplification unit provided in the pixel, and a signal amplified by the amplification unit is output from the pixel. In an amplification type solid-state imaging device, a plurality of such pixels are arranged in a matrix. The amplification type solid-state imaging device includes, for example, a solid-state imaging device using a junction field effect transistor (JFET) in an amplification unit (Patent Documents 1 and 2 below), and a solid-state imaging device using a MOS transistor in an amplification unit ( There is the following Patent Document 3).

  Conventionally, in an amplification type solid-state imaging device, in order to prevent image distortion caused by the exposure accumulation time of each pixel being shifted for each row when performing an electronic shutter operation (so-called rolling shutter), There has been proposed a configuration that realizes an electronic shutter operation simultaneously for all pixels in which the exposure time of pixels is constant (Patent Documents 1 to 3 below).

In the conventional solid-state imaging device disclosed in Patent Documents 1 to 3, each pixel has a photoelectric conversion unit and an amplification unit, and a charge storage unit (storage unit) that temporarily stores charges between them. is doing. In such a conventional solid-state imaging device, after all the pixels are exposed simultaneously, the signal charges generated in each photoelectric conversion unit are transferred to each charge storage unit at the same time, and accumulated once. The signal charges are sequentially converted into pixel signals at a predetermined readout timing.
JP-A-11-177076 JP 2004-335882 A JP 2004-111590 A

  However, in the above-described conventional technology, some of the charges generated in a relatively deep part of the semiconductor region and relatively close to the charge storage part do not enter the charge storage layer of the photoelectric conversion part, There has been a problem that the signal charge enters the charge storage section that temporarily accumulates the signal charge, resulting in noise charge. The ratio of the generated charges that enter the charge storage section and become noise charges is extremely low, but this is a serious problem when performing electronic shutter operation simultaneously for all pixels. In other words, the noise charge becomes a big problem because the time for storing the signal charge in the charge storage unit is overwhelmingly long with respect to the electronic shutter speed.

  For example, consider a case where the frame rate is 1/60 sec. In this case, charges are accumulated in the charge storage portion for a maximum of 1/60 sec. On the other hand, when the shutter speed is 1/1000 sec, the charge storage unit has a maximum of about 17 times as long as the signal charge is stored in the charge storage layer of the photoelectric conversion unit. The signal charge transferred from the must be retained. Even if the ratio of the generated noise charge to the noise charge is extremely low, the amount of the noise charge is considerably increased after about 17 times, and the ratio of the noise charge to the signal charge is considerably increased. . Therefore, the noise charge becomes a big problem.

  In addition, since the time during which the signal charge is stored in the charge storage unit differs depending on the readout line, the output voltage is caused by the difference in the amount of noise charge between the first read line and the last read line. There is also a problem that a difference occurs.

  The present invention has been made in view of such circumstances, and is generated in a deep portion of a semiconductor region in a solid-state imaging device capable of performing an electronic shutter operation simultaneously for all pixels by having a charge storage portion. It is an object of the present invention to provide a solid-state imaging device that can reduce noise by reducing the amount of charged charges entering the charge storage portion.

  In order to solve the above problems, a solid-state imaging device according to a first aspect of the present invention includes a first semiconductor layer of a first conductivity type and a second conductivity type of a second semiconductor layer disposed on the first semiconductor layer. Two semiconductor layers and a plurality of pixels, wherein each pixel is disposed in the second semiconductor layer and has the first conductivity type charge accumulation unit for accumulating photoelectrically converted charges, A charge storage unit that accumulates charges transferred from the photoelectric conversion unit, an amplification unit that outputs a signal corresponding to a charge amount of a predetermined portion, and a first transfer gate that transfers charges from the photoelectric conversion unit to the charge storage unit And a plurality of pixels having a second transfer gate unit that transfers charges from the charge storage unit to the predetermined part, wherein at least one of the plurality of pixels In the pixel, at least a part of the charge storage portion Those having a layer of said second conductivity type impurity concentration is higher concentration than said second semiconductor layer is provided through a portion of the under second semiconductor layer.

  The solid-state imaging device according to the second aspect of the present invention includes a first semiconductor layer of a first conductivity type and a plurality of pixels, each pixel being disposed in the first semiconductor layer and subjected to photoelectric conversion. A photoelectric conversion unit having a charge accumulation unit of a second conductivity type for accumulating charges, a charge storage unit for accumulating charges transferred from the photoelectric conversion unit, an amplification unit for outputting a signal corresponding to the charge amount of a predetermined part, A plurality of pixels having a first transfer gate portion that transfers charges from the photoelectric conversion portion to the charge storage portion, and a second transfer gate portion that transfers charges from the charge storage portion to the predetermined portion. A solid-state imaging device, wherein at least one of the plurality of pixels includes a charge discharging unit provided via at least a part of the first semiconductor layer under at least a part of the charge storage unit. Either electrically or electrically Those having a layer of connection to said second conductivity type.

  A solid-state imaging device according to a third aspect of the present invention includes a first conductive type first semiconductor layer and a plurality of pixels, each pixel being disposed in the first semiconductor layer and subjected to photoelectric conversion. A photoelectric conversion unit having a charge accumulation unit of a second conductivity type for accumulating charges, a charge storage unit for accumulating charges transferred from the photoelectric conversion unit, an amplification unit for outputting a signal corresponding to the charge amount of a predetermined part, A plurality of pixels having a first transfer gate portion that transfers charges from the photoelectric conversion portion to the charge storage portion, and a second transfer gate portion that transfers charges from the charge storage portion to the predetermined portion. In the solid-state imaging device, in at least one of the plurality of pixels, the charge storage unit is provided via at least a part of the first semiconductor layer below at least a part of the charge storage unit. The second conductivity electrically connected to Those having a layer.

  According to the present invention, in a solid-state imaging device capable of performing an electronic shutter operation simultaneously for all pixels by having a charge storage unit in a pixel, the charge generated in a deep region of the semiconductor region enters the charge storage unit. It is possible to provide a solid-state imaging device that can reduce noise by reducing the noise.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is an electric circuit diagram showing a schematic configuration of the solid-state imaging device according to the first embodiment of the present invention.

  In FIG. 1, the solid-state imaging device according to the present embodiment is illustrated as having 2 columns × 2 rows = 4 pixels 10 arranged in a two-dimensional matrix. The number of pixels is not particularly limited, but actually, for example, tens to thousands of pixels are arranged in each row and each column, and the resolution is increased by increasing the number of pixels. The present invention can be applied not only to a two-dimensional image sensor but also to a one-dimensional image sensor.

  As shown in FIG. 1, each pixel 10 includes a photodiode 1 as a photoelectric conversion unit that generates and accumulates charges according to incident light, and a charge storage unit 3 that accumulates charges transferred from the photodiode 1. Floating diffusion (FD) 4 as a predetermined part, MOS transistor (amplifying transistor) 7 as an amplifying part for outputting a signal corresponding to the charge amount of the predetermined part (in this embodiment, FD4), Reset gate section 6 for discharging charge, first transfer gate section 11 for transferring charge from photodiode 1 to charge storage section 3, gate electrode constituting first transfer gate section 11 and charge storage section 3 An electrode 2 that functions as both gate electrodes of the first gate electrode, a second transfer gate portion 5 that transfers charges from the charge storage portion 3 to the FD 4, and a photodiode 1 A MOS transistor (unnecessary charge discharging transistor) 8 as an unnecessary charge discharging gate portion for discharging unnecessary charges that do not contribute to image formation generated from the photodiode 1, and a vertical selection switch 9 made of a MOS transistor; It has.

  Further, as shown in FIG. 1, the solid-state imaging device according to the present embodiment has a drive control unit provided outside the imaging unit, a CDS (Correlated Double Sampling; (Correlated double sampling) circuit 51. The drive control unit includes a horizontal scanning circuit 52, a vertical scanning circuit 53, a horizontal selection switch 54 composed of MOS transistors, an output buffer amplifier 55, and the like.

  As shown in FIG. 1, the gate electrodes of the unnecessary charge discharging transistors 8 of all the pixels 10 are connected in common and receive a driving pulse φPDRST from the vertical scanning circuit 53. The electrodes 2 of all the pixels 10 (the electrode serving as the gate electrode of the first transfer gate unit 11 and the gate electrode for the charge storage unit 3) are connected in common and receive the drive pulse φSTG from the vertical scanning circuit 53.

  As shown in FIG. 1, one end of the vertical selection switch 9 is connected to a vertical signal line 50 for each column, and further connected to a CDS circuit 51 provided for each column. The signal processed by the CDS circuit 51 is input to the output buffer 55 via the horizontal selection switch 54, and is supplied from an output terminal Vout to an external circuit (not shown) as an imaging signal. The horizontal selection switch 54 is controlled by the horizontal scanning circuit 52.

  As shown in FIG. 1, the gate electrode of the second transfer gate unit 5 is connected for each row, and receives drive pulses φTX (1) and φTX (2) from the vertical scanning circuit 53 for each row. The gate electrode of the vertical selection switch 9 is connected to each row, and receives drive pulses φSEL (1) and φSEL (2) from the vertical scanning circuit 53 for each row. The gate electrode of the reset gate unit 6 is connected to each row and receives drive pulses φRST (1) and φRST (2) from the vertical scanning circuit 53 for each row.

  Next, the operation of the solid-state imaging device according to the present embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing the operation of the solid-state imaging device according to this embodiment. In FIG. 2, it is assumed that the corresponding transistor is turned on when each drive pulse is high.

  First, φPDRST is set to high to turn on the unnecessary charge discharging transistors 8 of all the pixels 10 at the same time, and the charges stored in the photodiodes 1 of all the pixels 10 are discarded to the power supply VDD.

  Next, φPDRST is set to low to turn off unnecessary charge discharging transistors 8 of all the pixels 10 at the same time, and charge accumulation in the photodiodes 1 of all the pixels 10 is started. At this time, the charges stored in the charge storage unit 3 are sequentially read at the time of the previous reading and the charge storage unit 3 is empty. However, a separate timing for resetting the charge storage unit 3 may be provided. .

  Next, before the predetermined accumulation time has elapsed since φPDRST was set to low, φSTG was set to high to turn on the first transfer gates 11 of all the pixels 10 at the same time, and the charge stored in the photodiodes 1 was stored as a charge. The data is transferred to the unit 3, and φSTG is set to low to turn off the first transfer gate unit 11 of all the pixels 10. As shown in FIG. 2, the time from when φPDRST is made low to when φSTG is made low again is the accumulated exposure time (electronic shutter time). When the charge is transferred from the photodiode 1 to the first transfer gate section 2 with φSTG being high, the potential of φSTG is set to a potential at which the charge from the photodiode 1 can be completely transferred.

  Next, φPDRST is set to high to turn on the unnecessary charge discharging transistors 8 of all the pixels 10 to reset the photodiodes 1. This prevents the charge from being overflowed into the charge storage unit 3 when it is stored in the photodiode 1 and exceeds the maximum accumulated charge of the photodiode 1 while reading out the charge stored in the charge storage unit 3. Alternatively, the photodiode 1 is reset to the power supply VDD in preparation for the next charge accumulation. While the charge is stored in the charge storage unit 3, a potential that forms an inversion layer on the surface of the charge storage unit 3 may be applied as the potential of φSTG, thereby generating dark current during storage. You can prevent it.

  Thereafter, φSEL (1) is set high to turn on the vertical selection switch 9 in the first row, and the pixel 10 in the first row is selected. In this selected state, φRST (1) is set to high to turn on the reset gate unit 6, thereby resetting the FD 4 connected to the gate electrode of the amplifying transistor 7. The reset output from the amplifying transistor 7 at this time is stored in the CDS circuit 51 via the vertical signal line 50. Next, φRST (1) is set to low, and the reset gate unit 6 is turned off. Next, φTX (1) is set high to turn on the second transfer gate portion 5 of the pixel 10 in the first row, and charges in the charge storage portion 3 of the pixel 10 in the first row are transferred to the FD 4. At this time, the potential of φTX (1) is set to a potential at which charges can be completely transferred from the charge storage unit 3 to the FD 4. An amplified potential corresponding to the charge amount of the FD 4 is sent to the CDS circuit 51 through the vertical output line 50. In the CDS circuit 51, the difference from the reset output stored earlier is output as a pixel signal of the pixels 10 in the first row. The pixel signals of the pixels 10 in the first row are serially output from the output terminal Vout via the output buffer amplifier 55 by sequentially turning on the horizontal selection switch 54 by the horizontal scanning circuit 52.

  Thereafter, φSEL (1) is set to low, then φSEL (2) is set to high, and the vertical selection switch 9 in the second row is turned on to select the pixel 10 in the second row. In this selected state, as shown in FIG. 2, the states of the drive pulses φTX (2) and φRST (2) are the same as the states of the drive pulses φTX (1) and φRST (1) when φSEL (1) is high. And the same state. Thereby, the same readout operation as the pixel 10 in the first row described above is performed on the pixels 10 in the second row.

  As can be seen from the above description, an electronic shutter operation simultaneously for all pixels is realized.

  Here, a cross-sectional structure of a pixel of the solid-state imaging device according to the present embodiment will be described with reference to FIG. FIG. 3 is a schematic cross-sectional view schematically showing a pixel. FIG. 3 also schematically shows the state of the charge q generated at a location deep in the P-type well 22 and relatively close to the charge storage portion 3.

  As shown in FIG. 3, a P-type well 22 as a semiconductor layer is formed by injecting, for example, boron into a surface side region of an N-type silicon substrate 21 constituting one semiconductor layer and thermally diffusing it. ing. Thus, instead of using the surface side region itself of the silicon substrate 21 as the P-type well 22, for example, the P-type layer 22 may be constituted by an epitaxial layer grown on the silicon substrate 21.

  As shown in FIG. 3, the photodiode 1 includes an N-type layer 23 as a charge storage unit (charge storage unit that stores photoelectrically converted charges) formed in a P-type well 22, and the surface of the N-type layer 23. And a P-type depletion prevention layer 24 formed on the side, and is configured as a buried photodiode. Although a buried photodiode is shown here, a photodiode that does not have the depletion prevention layer 24 may be used.

As shown in FIG. 3, the charge storage unit 3 includes an N-type layer (N ⁺ ) formed in the P-type well 22. A portion 2a corresponding to a gate electrode for the charge storage portion 3 of the electrode 2 made of polysilicon is formed on the charge storage portion 3, and the charge storage portion 3 is effectively a MOS diode having a gate. It is configured.

  As shown in FIG. 3, the electrode 2 has a portion 2b formed between the charge storage portion 3 and the photodiode 1 in addition to the portion 2a. The first transfer gate portion 11 is configured as a MOS transistor having the portion 2b of the electrode 2 as a gate and the charge storage portion 3 and the N-type layer 23 of the photodiode 1 as a source or a drain.

Further, as shown in FIG. 3, the P-type well 22 is formed with an FD 4 made of an N-type layer (N ⁺ ). A gate electrode 5a made of polysilicon is formed between the charge storage unit 3 and the FD 4, and the second transfer gate unit 5 uses the gate electrode 5a as a gate and the charge storage unit 3 and FD 4 as a source or a drain. Is configured as a MOS transistor.

Further, as shown in FIG. 3, an N-type layer (N ⁺ ) 25 is formed in the P-type well 22. Although not shown in the drawing, the N-type layer 25 is connected to the power supply VDD and serves as a charge discharge region. A gate electrode 6a made of polysilicon is formed between the FD 4 and the N-type layer 25, and the reset gate portion 6 is a MOS having the gate electrode 6a as a gate and the FD 4 and the N-type layer 25 as a source or drain. It is configured as a transistor.

Further, as shown in FIG. 3, an N-type layer (N ⁺ ) 26 is formed in the P-type well 22. Although not shown in the drawing, the N-type layer 26 is connected to the power supply VDD and serves as a charge discharge region. A gate electrode 8 a made of polysilicon is formed between the N-type layer 23 and the N-type layer 26 of the photodiode 1, and the unnecessary charge discharging transistor 8 uses the gate electrode 8 a as a gate and the photodiode 1. This is configured as a MOS transistor having the N-type layer 23 and the N-type layer 26 as sources or drains.

  Although not appearing in FIG. 3, the amplification transistor 7 and the vertical selection switch 9 are also configured as MOS transistors, like the second transfer gate unit 5, the reset gate unit 6, and the unnecessary charge discharging transistor 8. .

  In FIG. 3, reference numeral 27 denotes a thin insulating film, 28 denotes an interlayer insulating film, and 29 denotes a light shielding layer that also serves as a wiring. A wiring layer is also disposed in the interlayer insulating film 28, but the illustration thereof is omitted in FIG. Further, in FIG. 3, well-known microlenses and color filters are not shown.

In the present embodiment, as shown in FIG. 3, in each pixel, the P-type well 22 has a P-type via a part of the P-type well 22 below the N-type charge storage portion 3. A layer 30 of the same conductivity type as the well 22 is disposed. The depth of the P-type layer 30 (the distance from the upper surface of the P-type well 22 to the place where the impurity concentration of the P-type layer 30 is maximized) is, for example, 0.5 μm to 2 μm. In this embodiment, the P-type layer 30 is formed under the entire N-type charge storage unit 3. However, the P-type layer 30 is formed under only a part of the N-type charge storage unit 3. May be. The P-type layer 30 is not formed under the N-type layer 23 as a charge storage portion of the photodiode 1. In the present embodiment, the P-type layer 30 is formed in most of the region except under the N-type layer 23 as a charge storage portion, such as under the FD 4 and the N-type layer 25, but is not limited thereto. It is not something. The impurity concentration of the P-type layer 30 is set higher than the impurity concentration of the P-type well 22, and is set to 1 × 10 ¹⁸ / cm ³ , for example. The impurity concentration of the P-type layer 30 is preferably higher by one digit or more than the impurity concentration of the P-type well 22, but is not limited to this and may be higher than the impurity concentration of the P-type well 22.

  Next, how the charge Q is transferred during the operation described with reference to FIG. 2 will be described with reference to FIG. FIG. 4 is a potential diagram along the line A-A ′ in FIG. 3 in each state.

  FIG. 4A shows a state before φSTG goes high in the accumulated exposure period in FIG. In this state, charge Q is accumulated in the N-type layer 23 as the charge accumulation portion of the photodiode 1.

  FIG. 4B shows a state immediately before the end of the accumulation exposure period in FIG. 2 (just before φSTG changes from high to low and immediately before φPDRST changes from low to high). In this state, the first transfer gate unit 11 is turned on, and the charge Q stored in the N-type layer 23 as the charge storage unit of the photodiode 1 is transferred to the charge storage unit 3. ing.

  FIG. 4C shows a state before φTX of the pixel row (for example, φTX (1) in the case of the first pixel row) becomes high after the accumulation exposure period in FIG. 2 ends. In this state, φSTG is set to low and the first transfer gate unit 11 is turned off, so that the charge Q continues to be held in the charge storage unit 3, while φPDRST is set to high and the unnecessary charge discharging transistor 8. Is turned on, and unnecessary charges (not shown) entering the N-type layer 23 as the charge storage portion of the photodiode 1 are discharged to the charge discharge region 26 after the end of the accumulation exposure period. Thus, unnecessary charges do not overflow from the N-type layer 23 serving as the charge storage unit to the charge storage unit 3.

  FIG. 4D shows a state in which φTX of the pixel row (for example, φTX (1) in the case of the first pixel row) is set to high. In this state, the second transfer gate unit 5 is turned on, and the charge Q accumulated in the charge storage unit 3 is transferred to the FD 4.

  Next, the operation of the high concentration P-type layer 30 will be described with reference to FIGS. FIG. 5 is a potential diagram along the line B-B ′ in FIG. 3 in the same state as FIG. 4C (a state in which the signal charge Q is held in the charge storage unit 3).

  Charges are generated by the incident light even at a relatively deep location in the P-type well 22. Of these charges, a charge q generated relatively close to the charge storage unit 3 is schematically shown in FIG.

  A part of such charge q enters the N-type layer 23 as a charge storage portion of the photodiode 1. As shown in FIG. 4C, in the state where the signal charge Q is accumulated in the charge storage unit 3, the charge that has entered the N-type layer 23 as the charge accumulation unit out of the charge q is discharged to the charge discharge region 26. Therefore, the signal charge Q does not enter the charge storage unit 3 in which the signal charge Q is accumulated, and no noise charge is generated.

  In the present embodiment, as shown in FIG. 5, a high-concentration P-type layer 30 makes a potential gradient in the P-type well 22. Due to this gradient, the charge q that does not enter the N-type layer 23 as the charge storage unit and is generated deeper than the P-type layer 30 is transferred to the charge storage unit 3 as shown in FIGS. Without entering, it drifts to the N-type silicon substrate 21 and is absorbed by the N-type silicon substrate 21 and does not become noise charges.

  Therefore, according to the present embodiment, it is possible to reduce the charge q generated deep in the P-type well 22 from entering the charge storage unit 3 in which the signal charge Q is temporarily accumulated, Thereby, noise can be reduced.

  Here, a solid-state imaging device according to a comparative example compared with the present embodiment will be described with reference to FIGS.

  FIG. 6 is a schematic cross-sectional view schematically showing a pixel of the solid-state imaging device according to this comparative example, and corresponds to FIG. FIG. 7 is a potential diagram along C-C ′ in FIG. 6 in a state where the signal charge Q is held in the charge storage unit 3, and corresponds to FIG. 5. 6 and 7, elements that are the same as or correspond to those in FIGS. 3 and 5 are given the same reference numerals, and redundant descriptions thereof are omitted.

  This comparative example is different from the present embodiment only in that the P-type well 22 is not provided with the high-concentration P-type layer 30. This comparative example corresponds to the above-described prior art.

  In this comparative example, unlike the present embodiment, the high-concentration P-type layer 30 is not formed, so that the charge q generated at a relatively deep place of the P-type well 22 and relatively close to the charge storage portion 3. Among them, the charge that does not enter the N-type layer 23 as the charge storage section of the photodiode 1 enters the charge storage section 3 in which the signal charge Q is stored, and becomes a noise charge.

  On the other hand, in the present embodiment, since the high-concentration P-type layer 30 is formed, such charge does not enter the charge storage unit 3 as shown in FIGS. It drifts to the type silicon substrate 21 and is absorbed by the N type silicon substrate 21 and does not become noise charges.

  [Second Embodiment]

  FIG. 8 is a schematic cross-sectional view schematically showing a pixel of the solid-state imaging device according to the second embodiment of the present invention, and corresponds to FIG. FIG. 9 is a potential diagram along D-D ′ in FIG. 8 in a state where the signal charge Q is held in the charge storage unit 3, and corresponds to FIG. 5. 8 and 9, the same or corresponding elements as those in FIGS. 3 and 5 are denoted by the same reference numerals, and redundant description thereof is omitted.

  The solid-state imaging device according to the present embodiment differs from the solid-state imaging device according to the first embodiment in that an N-type layer 40 (opposite conductivity type to the well 22) is used instead of the high-concentration P-type layer 30. Are only arranged in the P-type well 22. The N-type layer 40 is disposed under the N-type charge storage unit 3 via a part of the P-type well 22. The N-type layer 40 is connected to the N-type charge discharge region 25 that constitutes the drain of the reset gate unit 6. Instead of being connected to the charge discharging region 25, the N-type layer 40 may be connected to the charge discharging region 26 constituting the drain of the unnecessary charge discharging transistor 8. Further, the N-type layer 40 may be directly connected to the power supply VDD without passing through other charge discharging regions such as the charge discharging regions 25 and 26, and the N-type layer 40 itself may be used as the charge discharging region.

The depth of the N-type layer 40 (the distance from the upper surface of the P-type well 22 to the place where the impurity concentration of the N-type layer 40 is maximized) is, for example, 0.5 μm to 2 μm. In the present embodiment, the N-type layer 40 is formed under the entire N-type charge storage unit 3, but the N-type layer 40 is formed under only a part of the N-type charge storage unit 3. May be. The N-type layer 40 is not formed under the N-type layer 23 as a charge storage portion of the photodiode 1. In the present embodiment, the N-type layer 40 is formed in most of the region except under the N-type layer 23 as a charge storage portion, such as under the FD 4 and the N-type layer 25, but is not limited thereto. It is not something. The impurity concentration of the N-type layer 40 is N-type, for example, 1 × 10 ¹⁷ / cm ³ , but any concentration may be used as long as the P-type well 22 is inverted to the N-type in the region of the N-type layer 40. .

  Next, the operation of the N-type layer 40 will be described with reference to FIGS.

  Note that the description of the operation described with reference to FIGS. 2 and 4 with respect to the first embodiment also applies to this embodiment as it is, and FIG. 9 shows the same state as FIG.

  In the present embodiment, since the N-type layer 40 is formed, the charge of the photodiode 1 out of the charge q generated relatively deep in the P-type well 22 and relatively close to the charge storage portion 3. Charges that do not enter the N-type layer 23 as the storage unit and are generated deeper than the N-type layer 40 are sucked into the N-type layer 40 without entering the charge storage unit 3 as shown in FIGS. And actively collected by the N-type layer 40. The charge sucked into the N-type layer 40 is discarded to the power supply VDD through the charge discharging region 25.

  Therefore, also in the present embodiment, as in the first embodiment, the charge q generated in the deep portion of the P-type well 22 is stored in the charge storage unit 3 in which the signal charge Q is temporarily accumulated. Entry can be reduced, which can reduce noise.

  [Third Embodiment]

  FIG. 10 is a schematic cross-sectional view schematically showing a pixel of the solid-state imaging device according to the third embodiment of the present invention, and corresponds to FIG. 10, elements that are the same as or correspond to those in FIG. 3 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The solid-state imaging device according to the present embodiment is different from the solid-state imaging device according to the first embodiment only in the points described below.

  In this embodiment, instead of the high-concentration P-type layer 30, an N-type (converse conductivity type to the well 22) layer 50 is disposed in the P-type well 22. The N-type layer 50 is disposed below the N-type charge storage unit 3 via a part of the P-type well 22. Unlike the N-type layer 40 in FIG. 8 showing the second embodiment, the N-type layer 50 is not connected to the charge discharge region 25 but is used as a charge storage portion of the photodiode 1. 23.

The depth of the N-type layer 50 (the distance from the upper surface of the P-type well 22 to the place where the impurity concentration of the N-type layer 50 is maximum) is, for example, 0.5 μm to 2 μm. In the present embodiment, the N-type layer 50 is formed under the entire N-type charge storage unit 3. However, the N-type layer 50 is formed under only a part of the N-type charge storage unit 3. May be. In the present embodiment, the N-type layer 50 is also formed under the entire N-type layer 23 as the charge storage portion of the photodiode 1, but is not limited thereto. In the present embodiment, the N-type layer 50 is formed in most of the region including under the FD 4 and the N-type layer 25 and under the N-type layer 23 as a charge storage portion, but is not limited thereto. It is not something. The impurity concentration of the N-type layer 50 is N-type, for example, 1 × 10 ¹⁷ / cm ³ , but any concentration may be used as long as the P-type well 22 is inverted to the N-type in the region of the N-type layer 50. .

  Next, the operation of the N-type layer 50 will be described with reference to FIG.

  In the present embodiment, since the N-type layer 50 is formed, the charge generated at a relatively deep location in the P-type well 22 and deeper than the N-type layer 50 is relatively close to the charge storage portion 3. As shown in FIG. 10, the charge q generated at this location is sucked into the N-type layer 50 and actively collected by the N-type layer 50 without entering the charge storage portion 3. In a state where the signal charge Q is temporarily stored in the charge storage unit 3 (see FIG. 11C described later), the unnecessary charge discharging transistor 8 is turned on, and therefore is collected by the N-type layer 50. The generated charge q is discarded to the power supply VDD via the charge discharge region 26.

  Therefore, also in the present embodiment, as in the first and second embodiments, the charge q generated in the deep portion of the P-type well 22 stores the signal charge Q temporarily. Entering the unit 3 can be reduced, and noise can be reduced.

  Further, in the present embodiment, during the exposure accumulation period in FIG. 2, the N-type layer 23 as a charge accumulation portion of the photodiode 1 using more charges as signal charges than in the second embodiment. The advantage that light utilization efficiency can be improved can also be obtained. That is, in the second embodiment, as can be understood from FIG. 8, even during the exposure accumulation period, the charges generated in a relatively deep place of the P-type well 22 and in a place relatively close to the charge storage portion 3. A part of q is sucked into the N-type layer 40 connected to the charge discharge region 25 and is discarded to the power supply VDD through the charge discharge region 25. On the other hand, in the present embodiment, such charges are also sucked into the N-type layer 50 connected to the N-type layer 23 as the charge storage portion of the photodiode 1, and the N-type layer 23 as the charge storage portion. It can be used as a signal charge.

  Note that the description of the operation described with reference to FIG. 2 regarding the first embodiment also applies to this embodiment as it is.

  Furthermore, in this embodiment, as can be understood from FIG. 10, in the exposure accumulation period in FIG. 2, the signal charge is applied not only to the N-type layer 23 as the charge accumulation portion of the photodiode 1 but also to the N-type layer 50. Can be accumulated. That is, the amount of charge handled by the photodiode 1 can be increased. In other words, even if the handling charge amount of the N-type layer 23 as the charge storage portion is lowered, the handling charge amount as a whole can be maintained. If the amount of charge handled by the N-type layer 23 serving as a charge storage unit is reduced, it is difficult for unread reading to occur. Therefore, according to the present embodiment, there is an advantage that it is possible to make it difficult for unread reading to occur while maintaining a sufficient amount of charge to be handled.

  This point will be described below with reference to FIG. FIG. 11 is a potential diagram along line E-E ′ in FIG. 10 in each state, and corresponds to FIG. 4. FIGS. 11A to 11D show the same state as FIGS. 4A to 4D, respectively, and therefore redundant description thereof is omitted.

  The amount of charge handled is determined by the depth and area of the potential well. In the present embodiment, since signal charges can be stored not only in the N-type layer 23 as the charge storage portion but also in the N-type layer 50, as shown in FIG. 11A, as compared with FIG. Even if the depth of the potential well of the N-type layer 23 serving as the charge storage portion is reduced, the same amount of charge as in the case of the first embodiment can be maintained as a whole.

  In the present embodiment, as shown in FIG. 11A, the potential well of the N-type layer 23 as the charge storage unit is set shallow, so that the charge storage unit 3 is transferred to as shown in FIG. The potential step Δ under the portion 2b of the electrode 2 when transferring the signal charge is larger than that in the case of FIG. Therefore, according to the present embodiment, the transfer of the signal charge Q to the charge storage unit 3 is easier than in the first embodiment. As a result, according to the present embodiment, it is difficult for unread reading of charges to occur.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

  For example, in each of the embodiments, the conductivity type of each part described above may be a reverse conductivity type.

  The present invention can also be applied to a solid-state imaging device using a junction field effect transistor in an amplifying unit as disclosed in Patent Documents 1 and 2.

1 is an electric circuit diagram showing a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention. 3 is a timing chart illustrating an operation of the solid-state imaging device according to the first embodiment of the present invention. It is a schematic sectional drawing which shows typically the pixel of the solid-state imaging device by the 1st Embodiment of this invention. FIG. 4 is a potential diagram along line A-A ′ in FIG. 3 in each state. FIG. 4 is a potential diagram along line B-B ′ in FIG. 3. It is a schematic sectional drawing which shows typically the pixel of the solid-state imaging device by a comparative example. FIG. 7 is a potential diagram along C-C ′ in FIG. 6. It is a schematic sectional drawing which shows typically the pixel of the solid-state imaging device by the 2nd Embodiment of this invention. FIG. 9 is a potential diagram along D-D ′ in FIG. 8. It is a schematic sectional drawing which shows typically the pixel of the solid-state imaging device by the 3rd Embodiment of this invention. FIG. 11 is a potential diagram along line E-E ′ in FIG. 10 in each state.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photodiode 3 Charge storage part 4 Floating diffusion 5 2nd transfer gate part 7 Amplifying transistor 11 1st transfer gate part 21 N type silicon substrate 22 P type well 23 N type layer as a charge storage part 30 P type layer 40, 50 N-type layer

Claims (3)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type disposed on the first semiconductor layer;
A plurality of pixels, each of which is arranged in the second semiconductor layer and has a charge storage unit of the first conductivity type that stores the photoelectrically converted charge, and is transferred from the photoelectric conversion unit A charge storage unit for storing the generated charge, an amplifying unit for outputting a signal corresponding to a charge amount of a predetermined part, a first transfer gate unit for transferring the charge from the photoelectric conversion unit to the charge storage unit, and the charge A plurality of pixels having a second transfer gate portion for transferring charge from the storage portion to the predetermined portion;
A solid-state imaging device comprising:
In at least one of the plurality of pixels, the impurity concentration is higher than that of the second semiconductor layer, which is provided below at least a portion of the charge storage portion via a portion of the second semiconductor layer. A solid-state imaging device comprising the second conductivity type layer having a concentration. A first semiconductor layer of a first conductivity type;
A plurality of pixels, each of which is transferred from the photoelectric conversion unit, the photoelectric conversion unit having a second conductivity type charge storage unit that is arranged in the first semiconductor layer and stores the photoelectrically converted charge; A charge storage unit that accumulates charges, an amplification unit that outputs a signal corresponding to the amount of charge at a predetermined site, a first transfer gate unit that transfers charges from the photoelectric conversion unit to the charge storage unit, and the charge storage A plurality of pixels having a second transfer gate portion for transferring charges from the portion to the predetermined portion;
A solid-state imaging device comprising:
In at least one pixel of the plurality of pixels, the charge discharging unit is provided below at least a part of the charge storage unit via a part of the first semiconductor layer, or is electrically connected to the charge discharging unit. A solid-state imaging device comprising: the second conductivity type layers connected in an electrically connected manner. A first semiconductor layer of a first conductivity type;
A plurality of pixels, each of which is transferred from the photoelectric conversion unit, the photoelectric conversion unit having a second conductivity type charge storage unit that is arranged in the first semiconductor layer and stores the photoelectrically converted charge; A charge storage unit that accumulates charges, an amplification unit that outputs a signal corresponding to the amount of charge at a predetermined site, a first transfer gate unit that transfers charges from the photoelectric conversion unit to the charge storage unit, and the charge storage A plurality of pixels having a second transfer gate portion for transferring charges from the portion to the predetermined portion;
A solid-state imaging device comprising:
In at least one of the plurality of pixels, the charge storage unit is provided below at least a part of the charge storage unit via a part of the first semiconductor layer and is electrically connected to the charge storage unit. A solid-state imaging device comprising a second conductivity type layer.

Images