JP2008004011A - Computer apparatus provided with data recovery method for nonvolatile memory - Google Patents

Abstract

[Problem] There is a problem that data is damaged and a failure (error code output) occurs when the power is turned off while writing to a readable / writable nonvolatile memory device (HDD, SRAM, FRAM, FLASH, etc.). However, simply discarding data that was in the middle of writing may cause inconsistencies among multiple data, and recovery may not be possible.
[Solution] (1) Subdivide the nonvolatile memory area and reduce the parity calculation time. (2) Save the write area before writing the actual data to prepare for power failure. (3) Use a mechanism that backs up two or more areas at the same time when data writing across multiple areas occurs to prevent data inconsistencies.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile memory write guarantee method, and more particularly to a recovery method in the case where power is cut off during writing to a nonvolatile memory.

  There is a problem that data is damaged and a failure (error code output) occurs when the power is turned off while writing to a readable / writable nonvolatile memory device (HDD, SRAM, FRAM, FLASH, etc.). The parts that fail due to a power failure are divided into the hardware, device driver, file system, and application in order from the lower layer. The layer above the device driver is generally created by software, the device driver is read / write in the management area and bit unit, the file system is in data read / write in the management area and file unit, and the application is in data read / write in multiple file units The Of course, device drivers have different management methods for each non-volatile device, and some devices do not involve a file system. The above hardware failures are physical and difficult to handle, but software failures can be avoided by methods. However, when the power is cut off, simply discarding the failed data will cause inconsistency between the data in the multi-bit data or multi-file data and cannot be recovered.

  The following describes the prior art on how to recover from a power failure while writing to a readable / writable nonvolatile memory device (HDD, SRAM, FRAM, FLASH, etc.).

  Japanese Patent Laid-Open No. 06-180664 (Brother Industries) copies a control program on a nonvolatile memory to a volatile memory, updates the control program on the volatile memory, and writes the control program on the volatile memory back to the nonvolatile memory. It is an invention related to a method for enabling batch erasure and update of memory. The prior patent states that if the power is cut off during write-back, the address is converted and restored, but the data integrity cannot be guaranteed after all. In contrast, this proposal does not perform address translation and can be recovered even if the power is turned off during write-back.

  JP 09-128156 (Hitachi, Ltd.) has a backup area on each disk in a disk recording control system that performs variable length and fixed length data conversion between disks using cache memory, and recovers when power is cut off It is an invention related to the method to do. In the present invention, fixed variable length conversion is not an issue.

  Japanese Patent Application Laid-Open No. 09-305491 (Toshiba) is an invention relating to a method of simultaneously storing a check code in an SRAM when writing to an HDD. Prior patents may be restored each time depending on the writing timing of HDD and SRAM. Also, the issue and the recovery method are different from this proposal.

  Japanese Patent Application Laid-Open No. 10-161938 (Toshiba) is an invention relating to a method of attaching not only a volatile cache area but also a nonvolatile cache area to an HDD, storing write-back data in the nonvolatile cache area, and restoring it when the power is turned off. This proposal does not use the method of the prior patent because it is not practical in terms of cost and communication speed. Also, the issue and the recovery method are different from this proposal.

  Japanese Patent Laid-Open No. 11-085629 (Fujitsu) is a method of extending the life by reducing the number of times of flash memory rewriting and erasing, and subdividing the minimum writing unit of the flash memory into a management area and a data area, and averaging the number of times of rewriting by replacement, etc. How to do. Prior patents may not be able to be restored if data is rewritten on the volatile memory used together.

  Japanese Patent Application Laid-Open No. 11-154058 (Toshiba) is an invention relating to a method of restoring data when a power is cut off during data writing using a plurality of disk devices. In contrast to prior patents, the present invention does not use multiple storage devices.

  Japanese Patent Laid-Open No. 2000-132464 (Canon) is an invention relating to a method for facilitating recovery when power is cut off by using a marker bit and a checksum indicating how much data has been written when recording data in a nonvolatile storage device. The prior invention has problems such as the amount of checksum calculation increases as the data becomes large, data restoration during writing cannot be performed, and inconsistency eventually occurs when the data being written crosses areas .

  Japanese Patent Laid-Open No. 2000-305862 (Mitsubishi Electric) is an invention relating to a method of erasing data by backing up the erase area to another nonvolatile memory when rewriting the flash memory. The prior invention can be recovered when the power is turned off. However, it is necessary to have an area larger than the erase unit of the flash memory in another nonvolatile device, and the number of times the flash memory is erased is reduced. This will increase the number of rewrites of volatile memory.

  Japanese Patent Laid-Open No. 2001-154926 (Shizuoka NEC) relates to a method for restoring a flash memory. In a flash memory capable of reading a second nonvolatile surface while writing and erasing the first nonvolatile surface, the power supply is cut off using the backup surface. It is an invention related to a method of recovering in case of failure. Prior patents have different issues from this proposal, and there is a problem that inconsistencies occur in the case of cross-domain data.

  Japanese Patent Application Laid-Open No. 2002-312147 (Konica) relates to a method for increasing the number of times of writing to a nonvolatile memory area, creates a volatile storage area N and a nonvolatile storage area M that is n times N, and divides M by N and circulates it. This is an invention related to a method for eliminating local writing. Although it is possible to cope with the power failure while erasing the data record of the non-volatile storage device, the data area being written cannot be guaranteed.

  Japanese Patent Application Laid-Open No. 2002-358248 (Pioneer) relates to a recovery method in the event of power interruption while data is being recorded on the HDD, and is an invention related to a method of recovering by double holding the FAT file system management area. In contrast to the prior patent, the present invention relates to recovery from power failure, but it is not a method using the management area of the file system.

  Japanese Unexamined Patent Application Publication No. 2003-122647 (Mitsubishi Electric Corp.) relates to a power-off response of a volatile memory, and in an information processing apparatus including a power supply system that supplies power to the main storage device for a predetermined time, It is an invention related to a method for storing data in a binary storage device. The method of the prior patent requires a small capacity battery to move the main storage device and the secondary storage device after the power is cut off, which is not practical in terms of cost and differs from the point of the proposal.

  JP 2004-021811 (Hitachi, Ltd.) relates to a method for improving fault tolerance by using nonvolatile memory devices such as flash memory in parallel and enabling restoration from parity data and a protection code when a failure occurs. It is an invention. Prior patents have multiple memory devices, except that the present invention is completed with a single device.

  Japanese Patent Laid-Open No. 2005-025401 (Sharp) is an invention related to a method for managing the progress of data area writing in the IC card in the management area in the IC card, in response to power-off of the flash memory in the IC card. Progress management in the management area is the same method as in JP 2000-132464 (Canon). In contrast, the present invention does not cover progress management.

  Japanese Patent Application Laid-Open No. 2005-056144 (NEC View Technology) is an invention relating to a method for managing the progress of data writing in a management area in relation to power-off of a flash memory. Progress management in the management area is the same method as disclosed in JP 2000-132464 (Canon) and JP 2005-025401 (Sharp). In contrast, the present invention does not cover progress management.

  JP 2005-149291 (Hitachi High-Technologies Corporation) has a management area and two data areas A and B in response to the power failure of the file system. When updating data, merge the data to be written into the original data A This invention relates to a method of writing to area B and changing the data area indicated by the management area from A to B. Prior patents cannot be recovered if the power is cut off while the management area is changed, and the point of argument differs from this proposal.

This proposal is an invention related to the restoration of non-volatile memory of a computer device implemented in view of such a situation.
Japanese Patent Laid-Open No. 06-180664 Japanese Patent Laid-Open No. 09-128156 JP 09-305491 A Japanese Patent Laid-Open No. 10-161938 Japanese Patent Laid-Open No. 11-085629 Japanese Patent Laid-Open No. 11-154058 JP 2000-132464 A JP 2000-305862 A JP 2001-154926 A Japanese Patent Laid-Open No. 2002-312147 JP 2002-358248 A JP 2003-122647 A JP 2004-021811 A JP 2005-025401 A JP 2005-056144 A JP 2005-149291 A

  From the above, the problem is that the power is cut while writing to a readable / writable non-volatile memory device (HDD, SRAM, FRAM, FLASH, etc.), causing data corruption and failure (error code output). However, simply discarding data that was in the middle of writing may cause inconsistencies among multiple data, and recovery may not be possible. Also, when error detection and correction is performed by applying the existing memory recovery method to the entire nonvolatile memory as one area, it takes time to calculate the parity of large-capacity data, and the actual data writing timing and parity bit There is a possibility that the data written and the parity bit will be inconsistent when the power is turned off, and the data cannot be recovered.

  (1) Subdivide the nonvolatile memory area and reduce the parity calculation time. (2) Save the write area before writing the actual data to prepare for power failure. (3) Use a mechanism that backs up two or more areas at the same time when data writing across multiple areas occurs to prevent data inconsistencies.

  By the above method, you can solve the problem of software inconsistency by turning off the power while writing to the nonvolatile storage device.

  The present invention and other features will be described below with reference to the drawings as appropriate.

(1) Hardware Configuration The overall hardware configuration of the image input / output system according to the embodiment of the present invention will be described with reference to FIG.

  A reader unit (image input device) 200 optically reads a document image and converts it into image data. The reader unit 200 includes a scanner unit 210 having a function for reading a document, and a document feeding unit 250 (hereinafter referred to as a feeder) having a function for conveying a document sheet.

  A printer unit (image output device) 300 conveys recording paper, prints image data as a visible image thereon, and discharges the recording paper out of the device. The printer unit 300 includes a paper feed unit 310 having a plurality of types of recording paper cassettes, a marking unit 320 having a function of transferring and fixing image data onto the recording paper, and sorting and stapling the printed recording papers. And a paper discharge unit 330 having a function of outputting to

  The control device 110 is electrically connected to the reader unit 200, the printer unit 300, the FAX modem 510, and the HDD (hard disk drive) 520, and further via the network 400, the host computers 401 and 402, the image input / output system 101, and the FAX It is connected to FAX 501,502 via a modem 510 and a telephone line 500.

  The control device 110 controls the reader unit 200 to read image data of a document, and controls the printer unit 300 to output the image data to a recording sheet to provide a copy function. In addition, the image data read from the reader unit 200 is converted into code data and transmitted to the host computer via the network 400, the code data received from the host computer via the network 400 is converted into image data, A printer function for outputting to the printer unit 300, a FAX function for transmitting and receiving input image data via the FAX modem 510 and the telephone line 500, and a box function for storing the transmitted and received image data in the HDD 520 are provided.

  Next, the operation unit 150 will be described with reference to FIG.

  The operation unit 150 is connected to the control device 110, is configured with a liquid crystal touch panel, and provides a user I / F for operating the image input / output system.

  600 is an LCD touch panel, and the main mode setting and status display are performed here. Reference numeral 601 denotes a numeric keypad for inputting numerical values from 0 to 9. Reference numeral 602 denotes an ID key, which is used when a department number and a reef mode are input when the apparatus is under department management.

  603 is a reset key for resetting the set mode, 604 is a guide key for displaying an explanation screen for each mode, 605 is a user mode key for entering the user mode screen, and 606 is for performing interrupt copying It is an interrupt key.

  Reference numeral 607 denotes a start key for starting a copy operation, and reference numeral 608 denotes a stop key for stopping a copy job being executed.

  609 is a soft power switch, and when pressed, the backlight of the LCD 600 is extinguished and the device falls into a low power state. Reference numeral 610 denotes a power saving key, which is pressed to enter a power saving state and is pressed again to return from the power saving state.

  Reference numerals 611, 612, 613, and 614 denote function keys for shifting to copy, transmission, box, and expansion. In FIG. 2, the standard screen for copying is displayed, and by pressing the other function keys 612, 613, 614, the standard screen for each function is displayed.

  Reference numeral 615 denotes an adjustment key for adjusting the contrast of the LCD touch panel.

  Reference numeral 616 denotes a counter confirmation key. When this key is pressed, a count screen for displaying the total number of copies specified so far is displayed on the LCD.

  617 is an LED indicating that the job is being executed and the image is being stored in the image memory, 618 is an error LED indicating that the device is in an error state such as a jam or door open, and 619 is that the main switch of the device is ON. The power LED indicates.

  FIG. 3 is a cross-sectional view of the reader unit 200 and the printer unit 300. The document feeding unit 250 of the reader unit feeds the documents one by one onto the platen glass 211 in order from the top, and discharges the documents on the platen glass 211 to the discharge tray 219 after the document reading operation is completed. When the document is conveyed onto the platen glass 211, the lamp 212 is turned on, and the movement of the optical unit 213 is started to expose and scan the document. Reflected light from the original at this time is guided to a CCD image sensor (hereinafter referred to as CCD) 218 by mirrors 214, 215, 216 and lens 217. In this way, the scanned image of the document is read by the CCD 218. Image data output from the CCD 218 is transferred to the control device 110 after being subjected to predetermined processing.

  The laser driver 321 of the printer unit 300 drives the laser light emitting unit 322, and causes the laser light emitting unit 322 to emit laser light corresponding to the image data output from the control device 110. The laser beam is irradiated on the photosensitive drum 323, and a latent image corresponding to the laser beam is formed on the photosensitive drum 323. A developer is attached to the latent image portion of the photosensitive drum 323 by a developing device 324.

  The recording paper is fed from one of the cassette 311, the cassette 312, the cassette 313, the cassette 314, and the manual paper feed stage 315 at the timing synchronized with the start of laser light irradiation, and guided to the transfer unit 325 by the transport path 331. Then, the developer attached to the photosensitive drum 323 is transferred to the recording paper. The recording paper on which the developer is placed is conveyed to the fixing unit 327 by the conveyance belt 326, and the developer is fixed to the recording paper by the heat and pressure of the fixing unit 327. Thereafter, the recording paper that has passed through the fixing unit 327 passes through the transport path 325 and the transport path 324 and is discharged to the paper discharge bin 328. Alternatively, when the printing surface is reversed and discharged to the paper discharge bin 328, the recording paper is guided to the transport path 336 and the transport path 338, and then the recording paper is transported in the reverse direction and passes through the transport path 337 and the transport path 324. .

  If double-sided recording is set, after passing through the fixing unit 327, the recording paper is guided from the conveyance path 336 to the conveyance path 333 by the flapper 329, and then the recording paper is conveyed in the reverse direction. Thus, the sheet is guided to the conveyance path 338 and the refeed conveyance path 332. The recording sheet guided to the refeed conveyance path 332 passes through the conveyance path 331 at the timing described above and is fed to the transfer unit 325.

  Details of the control device will be described below.

(1-1) Description of Control Device The function of the control device 110 will be described based on the block diagram shown in FIG.

  The main controller 111 mainly includes a CPU 112, a bus controller 113, and various I / F controller circuits.

  The CPU 112 and the bus controller 113 control the overall operation of the control device 110, and the CPU 112 operates based on a program read from the ROM 114 via the ROM I / F 115. The operation of interpreting PDL (page description language) code data received from the host computer and decompressing it into raster image data is also described in this program and processed by software. The bus controller 113 controls data transfer input / output from each I / F, and performs arbitration at the time of bus contention and control of DMA data transfer.

  The DRAM 116 is connected to the main controller 111 by a DRAM I / F 117, and is used as a work area for operating the CPU 112 and an area for storing image data.

  The network controller 121 is connected to the main controller 111 by an I / F 123 and is connected to an external network by a connector 122. A network generally includes a telephone line 500 via a LAN and a FAX modem 510.

  An expansion connector 124 for connecting an expansion board and an I / O control unit 126 are connected to the general-purpose high-speed bus 125. A general-purpose high-speed bus is a PCI bus.

  The I / O control unit 126 is equipped with two channels of an asynchronous serial communication controller 127 for transmitting and receiving control commands to and from the CPUs of the reader unit 200 and the printer unit 300. F circuits 140 and 145 are connected.

  The panel I / F 132 is connected to the LCD controller 131 and includes an I / F for displaying on the liquid crystal screen 600 on the operation unit 150 and a key input I / F 130 for inputting hard keys and touch panel keys. Composed.

  The operation unit 150 includes a liquid crystal display unit, a touch panel input device attached on the liquid crystal display unit, and a plurality of hard keys. A signal input from the touch panel or hard key is transmitted to the CPU 112 via the panel I / F 132 described above, and the liquid crystal display unit displays image data sent from the panel I / F 132. The liquid crystal display unit displays function display, image data, and the like in the operation of the image display apparatus.

  The real-time clock module 133 is for updating / saving the date and time managed in the device, and is backed up by a backup battery 134.

  The E-IDE interface 161 is for connecting an external storage device. A hard disk or CD-ROM drive can be connected via this I / F, and programs and image data can be written and read.

  The connectors 142 and 147 are connected to the reader unit 200 and the printer unit 300, respectively, and are composed of a synchronized step serial I / F (143, 148) and a video I / F (144, 149).

  The scanner I / F 140 is connected to the reader unit 200 via the connector 142, and is also connected to the main controller 111 via the scanner bus 141, and the image received from the reader unit 200 is processed according to the contents of processing in the subsequent process. , Have the function of performing the optimal binarization, scaling processing of the main scanning and sub scanning, and further, the control signal generated based on the video control signal sent from the reader unit 200, It also has a function of outputting to the scanner bus 141.

  Data transfer from the scanner bus 141 to the DRAM 116 is controlled by the bus controller 113.

  The printer I / F 145 is connected to the printer unit 300 via the connector 147, and is also connected to the main controller 111 via the printer bus 146. The printer I / F 145 performs smoothing processing on the image data output from the main controller 111, and And a function of outputting a control signal generated based on the video control signal sent from the printer unit 300 to the printer bus 146.

  Transfer of raster image data expanded on the DRAM 116 to the printer unit is controlled by the bus controller 113 and DMA-transferred to the printer unit 300 via the printer bus 146 and the video I / F 149.

(1-2) Description of Main Controller FIG. 5 shows a block diagram of the main controller.

  The processor core 401 is connected to a system bus bridge (SBB) 402 via a 64-bit processor bus (SC bus). The SBB402 is a 4 × 4 64-bit crossbar switch, connected to the processor core 401, the memory controller 403 that controls the SDRAM and ROM with cache memory, and a dedicated local bus (MC bus). The G bus 404, which is a graphic bus, and the B bus 405, which is an IO bus, are connected to a total of four buses. The SBB402 is designed to ensure simultaneous parallel connection between these four modules as much as possible.

  The data compression / decompression unit (codec) 418 is also connected via a codec I / F.

  The G bus 404 is cooperatively controlled by a G bus arbiter (GBA) 406, and is connected to a scanner / printer controller (SPC) 408 for connecting to a scanner or a printer. The B bus 405 is cooperatively controlled by a B bus arbiter (BBA) 407. In addition to the SPC 408, a power management unit (PMU) 409, an interrupt controller (IC) 410, and a serial interface controller (SIC) 411 using a UART , USB controller 412, parallel interface controller (PIC) 413 using IEEE1284, LAN controller (LANC) 414, LCD panel, key, general purpose input / output controller (PC) 415, PCI bus interface (PCIC) 416 Yes.

  An operation panel 417 having a display panel and a keyboard is connected to the PC 415.

(1-2-1) Description of Interrupt Controller The interrupt controller 410 is connected to the B bus 405, integrates each functional block in the main controller chip and interrupts from outside the chip, and is supported by the CPU core 401. Redistribute level external interrupts and non-maskable interrupts (NMI). Each functional block includes a power management unit 409, a serial interface controller 411, a USB controller 412, a parallel interface controller 413, a LAN controller 414, a general-purpose IO controller 415, a PCI interface controller 416, a scanner / printer controller 408, and the like.

(1-2-2) Description of Memory Controller The memory controller 403 is connected to the MC bus, which is a local bus dedicated to the memory controller, and controls synchronous DRAM (SDRAM), flash ROM, and ROM.

(1-3) Description of System Bus Bridge FIG. 6 is a block diagram of the system bus.

  The SBB 402 is a multi-channel bidirectional bus bridge that provides interconnections between the B bus (input / output bus), the G bus (graphic bus), the SC bus (processor local bus), and the MC bus using a crossbar switch. With the cross bus switch, two systems can be established at the same time, and high-speed data transfer with high parallelism can be realized.

  The SBB 402 includes a B bus interface 2009 for connecting to the B bus 405, a G bus interface 2006 for connecting to the G bus 404, a CPU interface slave port 2002 for connecting to the processor core 401, a memory controller 403, In addition to a memory interface master port 2001 for connection and a CODEC bus interface 2014 for connection to the compression / decompression unit 418, an address switch 2003 for connecting an address bus and a data switch 2004 for connecting a data bus are included. Further, a cache invalidation unit 2005 that invalidates the cache memory of the processor core is provided.

(1-3-1) Description of PCI bus interface
The PCI bus interface 416 is a block that interfaces between the B bus, which is a general-purpose IO bus inside the main controller, and the PCI bus, which is an external IO bus on the chip.

(1-3-2) Explanation of G bus arbiter and B bus arbiter
The arbitration of the G bus is a central arbitration method, and each bus master has a dedicated request signal and grant signal. This arbiter can program the control method. Also, as a method of giving priority to the bus master, all bus masters have the same priority, the fair arbitration mode in which the bus right is given fairly, and the priority of any one bus master is raised, and the bus is used preferentially. You can specify either the priority arbitration mode.

  The B bus arbiter 407 receives a bus use request for the B bus 405, which is an IO general-purpose bus, and after arbitration, gives a use permission to one selected master, and two or more masters simultaneously access the bus. Is prohibited. The arbitration method has three levels of priority, and a plurality of masters can be assigned to each priority in a programmable manner.

(1-4) Scanner Controller / Printer Controller FIG. 7 is a block diagram of the scanner controller and printer controller.

  The scanner / printer controller 408 is a block that is connected to the scanner and printer by Video I / F and interfaces with the internal bus G bus and B bus. Broadly divided into the following three blocks.

(1-4-1) Scanner controller The scanner controller is connected to the scanner through a video I / F, and performs operation control and data transfer control. The G bus / B bus I / F unit (GBI) 4301A is connected by an IF bus to perform data transfer and register read / write.

(1-4-2) Printer controller The printer controller is connected to the printer through a video I / F, and performs operation control and data transfer control. The GBI 4301B is connected by an IF bus to perform data transfer and register read / write.

  The CP bus is a bus for directly connecting the image data of the scanner and the printer and a synchronization signal for horizontal and vertical synchronization.

(1-4-3) G bus / B bus I / F unit (GBI)
This is a unit for connecting the scanner controller 4302 and the printer controller 4303 to the G bus or B bus. The scanner controller 4302 and the printer controller 4303 are independently connected to each other, and are connected to both the G bus and the B bus.

(1-5) Description of Power Management Unit The main controller 111 is a large-scale ASIC with a built-in CPU. For this reason, if all the internal logics operate simultaneously, a large amount of heat is generated and the chip itself may be destroyed. In order to prevent this, the main controller performs power management for each block, that is, power management, and further monitors the power consumption of the entire chip.

  Each block performs power management individually. Information on the power consumption of each block is collected in a power management unit (PMU) 409 as a power management level. In the PMU 409, the power consumption of each block is totaled, and the power consumption of each block of the main controller is collectively monitored so that the value does not exceed the limit power consumption.

  The following explains how to restore non-volatile memory using the above hardware using examples.

  The basic pattern of data writing in the nonvolatile memory device will be described using the flowchart in FIG.

  When the working bit is scanned and the working bit remains standing (F11), it is determined that the previous work was interrupted due to a power failure or the like, and the data is transferred from the backup area to the area where the working bit is kept. Return (F12), drop the working bit (F13). Next, the data is saved from the rewrite area to the backup area (F14), and it is determined whether the data end of the rewrite area straddles the areas (F15). Complete Next, the working bit in the rewriting area is set (F16), the data is rewritten (F17), the parity is calculated and rewritten (F18), and the working bit is dropped (F19).

  8, 9, 10, and 11 are non-volatile storage area management charts. When explaining the figure, a data area (A01, Z01, X01), a parity area (A11, Z02, X02), a rewriting work bit (A02, A04, Z03, X03), a backup area (A03, A13, Z04, X04), cross-region data example (A05, Z21, X21), cross-region parity example (A15), cross-region parity calculation example (Z22, X22). FIG. 8 is a general area management diagram having a data, parity, and backup area, FIG. 9 is an area management chart in which the backup area is changed when the rewrite area size becomes large, and FIG. 10 is all area data without parity. Fig. 11 is an area management chart in which data is calculated separately for all area parity data.

  The case where the data straddles the area will be explained using the area management chart of the non-volatile storage area in FIGS. If the data arrangement is across the areas (Z21, X21), combine the multiple areas and recalculate the parity to invalidate the parity between the areas. In addition, the rewriting work bit is used as a flag to indicate that a data area crossing has occurred. By performing parity calculation across areas, even if data is saved for each area, data consistency between the two areas can be guaranteed.

  Writing data only and parity only will be explained using the non-volatile storage area management charts shown in Figs. Execute the flow excluding the parity calculation and rewriting (F18) from the flowchart in Fig.12. This makes it possible to guarantee writing in the case of no parity calculation.

  The following is not explained, but is explicit.

  (1) The rewriting flag can be managed not only in the last bit of each small area of the nonvolatile storage device but also in the device management area on the same device or on another device. In addition, the rewriting flag can be replaced with a binary semaphore in the nonvolatile storage area.

  (2) If only parity is managed on a non-volatile storage device and the data area is calculated and generated by another device, the parity can be considered as data.

  (3) Since it takes time to check each time data is written to the non-volatile device, and this method is mainly for recovery from power failure, the rewriting work flag should be checked only at startup. Is also possible.

  (4) If the data managed in each small area of the non-volatile seat storage device is data without parity, it is possible not to calculate the parity.

  (5) When writing data across each small area of the non-volatile seat storage device, it is possible to combine the areas and calculate the parity, or to calculate the parity of each area.

  (6) Although fixed area rewriting of non-volatile memory has been explained, variable length is also possible.

  (7) The backup area can be fixed or changed in size. It is also possible to reserve the area in other nonvolatile storage devices.

  (8) By determining the data string of the nonvolatile memory device as just a bit sequence, it is possible to determine that the rewrite area of the nonvolatile memory device does not always straddle the end (F15).

Explanatory drawing of the whole structure of the image input / output system concerning a present Example User I / F to be the operation unit 150 Cross section of leader and printer Block diagram of control device Main controller block diagram System bus bridge block diagram Block diagram of scanner controller and printer controller Data structure diagram of nonvolatile memory area Data structure diagram of nonvolatile memory area Data structure diagram of nonvolatile memory area Data structure diagram of nonvolatile memory area Flowchart diagram of the first embodiment

Explanation of symbols

331 Conveying path 335 Conveying path 336 Conveying path 338 Conveying path 333 Conveying path 332 Refeeding conveying path 325 Fixing unit 323 Photosensitive drum

Claims (3)

A function of subdividing and managing data in a nonvolatile storage device into one or more areas of fixed length or variable length;
In a computer device having
A function of rewriting data after saving data in the subdivision area when rewriting data in one or more subdivision areas in the nonvolatile memory device;
A computer apparatus comprising: If the data to be written in the nonvolatile storage device is continuous data between the subdivision areas, a function of rewriting data after saving two or more subdivision areas;
The computer apparatus according to claim 1, further comprising: 2. The computer apparatus according to claim 1, further comprising a function of overwriting the saved data by overwriting the data being rewritten when the writing operation into the nonvolatile storage device is not completed. .

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