JP2008099093A - Oscillation circuit and semiconductor device - Google Patents

Abstract

The present invention provides an oscillation circuit capable of easily controlling an oscillation frequency with a simple configuration.
By connecting an input terminal of an inverter INV1 located at one end and an output terminal of an inverter INV7 located at the other end among a plurality of inverters INV1 to INV7 connected in series, a plurality of inverters are connected to each other. Ring oscillator 10R connected in a line, at least one capacitor C1-C3 selectively connected to the output terminals of at least one desired inverter INV1, INV3, and INV5 among the plurality of inverters, and a plurality of inverters Among them, at least one current adjusting transistor M2, M4, M6, M10, M12, and M14, which is selectively connected to the power supply terminal of the inverter connected to the output terminal and adjusts the operating current for operating the inverter, Prepare.
[Selection] Figure 1

Description

  The present invention relates to an oscillation circuit.

  Conventionally, as an oscillation circuit, there is a ring oscillator formed by connecting a plurality of CMOS inverters (hereinafter referred to as inverters) in a ring shape. Such a ring oscillator changes the delay time of each inverter by adjusting the operating current for operating each inverter, thereby controlling the oscillation frequency of the clock signal output from the ring oscillator.

However, such a ring oscillator cannot ensure linearity between the operating current of each inverter and the oscillation frequency of the generated clock signal. Therefore, this ring oscillator has a problem that it is necessary to make a complicated adjustment to the operating current of each inverter in order to control the oscillation frequency.
Japanese Patent Laid-Open No. 11-8532

  The present invention provides an oscillation circuit capable of easily controlling the oscillation frequency with a simple configuration.

An oscillation circuit according to one embodiment of the present invention includes:
A ring in which the plurality of inverters are connected in a ring shape by connecting an input terminal of the inverter located at one end and an output terminal of the inverter located at the other end among the plurality of inverters connected in series An oscillator,
At least one capacitor selectively connected to an output terminal of at least one desired inverter among the plurality of inverters;
Among the plurality of inverters, the capacitor is selectively connected to a power supply terminal of the inverter connected to an output terminal, and includes at least one current adjusting transistor that adjusts an operating current for operating the inverter.

A semiconductor device according to one embodiment of the present invention includes:
A ring in which the plurality of inverters are connected in a ring shape by connecting an input terminal of the inverter located at one end and an output terminal of the inverter located at the other end among the plurality of inverters connected in series An oscillator,
At least one capacitor selectively connected to an output terminal of at least one desired inverter among the plurality of inverters;
An oscillation circuit comprising: at least one current adjustment transistor for adjusting an operating current for operating the inverter, wherein the capacitor is selectively connected to a power supply terminal of the inverter connected to an output terminal among the plurality of inverters. When,
A semiconductor integrated circuit that operates based on a clock signal generated by the oscillation circuit.

  According to the oscillation circuit of the present invention, the oscillation frequency can be easily controlled with a simple configuration.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration of an oscillation circuit 10 according to the embodiment of the present invention. The oscillation circuit 10 includes a ring oscillator 10R, and the ring oscillator 10R is formed by connecting inverters INV1 to INV7 in series and connecting an input terminal of the inverter INV1 and an output terminal of the inverter INV7. .

  A capacitor C1 for delaying transmission of an output signal output from the inverter INV1 is connected between the output terminal of the inverter INV1 and the low potential side power source VSS. Similarly, capacitors C2 and C3 are connected between the output terminals of the inverters INV3 and INV5 and the low potential side power source VSS, respectively.

  In the case of the present embodiment, the capacitances of these capacitors C1 to C3 are much larger than the parasitic capacitances of the PMOS transistors and NMOS transistors forming the inverters INV1 to INV7 so that the parasitic capacitances can be ignored. Selected.

  Between the high potential side power supply terminal (first power supply terminal) of the inverter INV1 and the high potential side power supply VDD (first potential side power supply), the current supplied to the inverter INV1 (that is, the operation for operating the inverter INV1) A PMOS transistor M2 is connected as a current adjusting transistor for limiting and adjusting (current). Specifically, the drain of the PMOS transistor M2 is connected to the high potential side power supply terminal of the inverter INV1, and the high potential side power supply VDD is connected to the source of the PMOS transistor M2.

  Further, an NMOS transistor M10 is connected as a current adjusting transistor between the low potential side power supply terminal (second power supply terminal) and the low potential side power supply VSS (second potential side power supply) of the inverter INV1. ing. Specifically, the drain of the NMOS transistor M10 is connected to the low potential side power supply terminal of the inverter INV1, and the low potential side power supply VSS is connected to the source of the NMOS transistor M10.

  Similarly, a PMOS transistor M4 is connected as a current adjusting transistor between the high potential side power supply terminal of the inverter INV3 and the high potential side power supply VDD, and the low potential side power supply terminal of the inverter INV3 and the low potential side power supply are connected. An NMOS transistor M12 is connected between the power supply VSS as a current adjusting transistor.

  Similarly, a PMOS transistor M6 is connected as a current adjusting transistor between the high potential side power supply terminal of the inverter INV5 and the high potential side power supply VDD, and the low potential side power supply terminal of the inverter INV5 and the low potential side power supply are connected. Between the power supply VSS, an NMOS transistor M14 is connected as a current adjusting transistor.

  The PMOS transistors M2, M4, and M6 and the NMOS transistors M10, M12, and M14 are formed to have the same element size.

  On the other hand, the high potential side power supply terminal of the inverter INV2 is connected to the high potential side power supply VDD, and the low potential side power supply terminal of the inverter INV2 is connected to the low potential side power supply VSS. Similarly, the high potential side power supply terminals of the inverters INV4, INV6, and INV7 are connected to the high potential side power supply VDD, and the low potential side power supply terminals of the inverters INV4, INV6, and INV7 are connected to the low potential side power supply VSS. .

  Incidentally, a PMOS transistor M1 is connected between one end of the variable current source I2 and the high potential side power source VDD. One end of the variable current source I2 is connected to the gates of the PMOS transistors M1, M2, M4, and M6, and the other end of the variable current source I2 is connected to the low potential side power source VSS.

  Thereby, the PMOS transistors M1, M2, M4, and M6 form a current mirror circuit having the PMOS transistor M1 as a reference current generating transistor as a master. Therefore, the same current as the current flowing through the PMOS transistor M1 flows through the PMOS transistors M2, M4, and M6.

  On the other hand, an NMOS transistor M9 is connected between one end of the variable current source I1 and the low potential side power source VSS. One end of the variable current source I1 is connected to the gates of the NMOS transistors M9, M10, M12, and M14, and the other end of the variable current source I1 is connected to the high potential side power supply VDD.

  As a result, the NMOS transistors M9, M10, M12, and M14 form a current mirror circuit having the NMOS transistor M9 as a reference current generating transistor as a master. Accordingly, the same current as the current flowing through the NMOS transistor M9 flows through the NMOS transistors M10, M12, and M14.

  The oscillation circuit 10 controls the oscillation frequency of the clock signal output from the oscillation circuit 10 by adjusting the current generated in the variable current sources I1 and I2.

  In the present embodiment, no current adjusting transistor is connected to the inverters INV2, INV4, INV6, and INV7. Therefore, an operating current larger than that of the inverters INV1, INV3, and INV5 flows.

  Further, the capacitances of the capacitors C1 to C3 are selected so as to be much larger than the parasitic capacitances of the PMOS transistors and NMOS transistors forming the inverters INV1 to INV7 and to have a value that can ignore the parasitic capacitances.

  Thereby, the inverters INV2, INV4, INV6, and INV7 operate at high speed, and the delay time in the inverters INV2, INV4, INV6, and INV7 can be shortened.

  Incidentally, the delay time means the time required from the timing when the input signal of the inverter INV changes from “H” level to “L” level to the timing when the output signal changes from “L” level to “H” level. To do.

  On the other hand, the operating current for operating the inverters INV1, INV3, and INV5 is adjusted by the current adjusting transistors (M2, M4, M6, M10, M12, and M14).

  That is, by adjusting the operating current of the inverters INV1, INV3, and INV5, the charge / discharge current for charging / discharging the capacitors C1 to C3 is changed, and the charge / discharge time required for the charge / discharge is changed. Thereby, the delay time when transmitting the output signals output from the inverters INV1, INV3, and INV5 is changed, and the oscillation frequency of the clock signal is controlled.

  Thus, the ratio of the delay time of the inverters INV1 to INV7 in the delay time of the entire oscillation circuit 10 is reduced, and the ratio of the delay time due to the capacitors C1 to C3 is increased.

  Therefore, the oscillation frequency of the clock signal is substantially determined by the delay time caused by the capacitors C1 to C3. That is, the oscillation frequency of the clock signal can be easily determined by the current generated in the variable current sources I1 and I2 and the capacitances of the capacitors C1 to C3.

  As a result, linearity between the operating current and the oscillation frequency can be ensured, and therefore, simple adjustment that simply increases or decreases the operating current without making a complicated adjustment to the operating current. The oscillation frequency can be easily controlled.

  Here, FIG. 2 shows a configuration of an oscillation circuit 20 in which current adjusting transistors (PMOS transistors M2 to M8, NMOS transistors M10 to M16) are connected to all inverters INV1 to INV7 as a comparative example.

  In the case of this comparative example, the proportion of the delay time of the inverters INV1 to INV7 in the delay time of the entire oscillation circuit 20 is large, and the delay time of the inverters INV1 to INV7 cannot be ignored. Therefore, the oscillation frequency of the clock signal output from the oscillation circuit 20 is determined by the delay time of the inverters INV1 to INV7 and the delay time caused by the capacitors C1 to C3, and linearity between the operating current and the oscillation frequency. Can not be secured.

  Here, FIG. 3 shows a simulation result of the oscillation frequency vs. operating current characteristics. As shown in FIG. 3, in the oscillation circuit 20 of the comparative example, the linearity cannot be secured as the oscillation frequency is lowered. However, in the oscillation circuit 10 of the present embodiment, the oscillation frequency is lowered. Even so, linearity is ensured.

  Further, FIG. 4 shows an example of the error rate with respect to the oscillation frequency. In this case, when the oscillation frequency is set to 5 MHz, the oscillation circuits 10 and 20 are formed so that the oscillation frequency of the actually generated clock signal is 5 MHz. In the oscillation circuits 10 and 20, the error rate obtained by changing the oscillation frequency is shown.

  As shown in FIG. 4, in the oscillation circuit 20 of the comparative example, an error of about 13% occurs when the oscillation frequency is 2 MHz, whereas in the oscillation circuit 10 of the present embodiment, about 3%. It is only necessary to generate the error.

  FIG. 5 shows an example of the semiconductor memory 30 as a semiconductor device using the oscillation circuit 10 according to the present embodiment. In this case, the timing generator 50 (semiconductor integrated circuit) generates a timing signal based on the clock signal generated in the oscillation circuit 10 and supplies the timing signal to the SRAM 60. The SRAM 60 executes writing and reading of data with respect to the memory cell based on this timing signal, and outputs the read data to the outside via the output circuit 70.

  The above-described embodiment is an example and does not limit the present invention. For example, an example of an IC card 80 is shown as a semiconductor device using the oscillation circuit 10 according to the present embodiment. The IC card 80 includes an EEPROM 110, a microcontroller 100 that controls the operation of the EEPROM 110, and an oscillation circuit 10 that generates a clock signal that is used when data is written to and read from the EEPROM 110.

  In the above-described embodiment, among the inverters INV1 to INV7, the capacitors and current adjusting transistors are selectively connected to the inverters INV1, INV3, and INV5, but the capacitors and currents are selectively connected to the inverters INV2, INV4, and INV6. An adjustment transistor may be connected, and various other changes can be made. Further, it is not necessary to connect both the capacitor and the current adjustment transistor to the inverter INV. For example, only the current adjustment transistor may be connected and the capacitor may not be connected.

It is a circuit diagram which shows the structure of the oscillation circuit by embodiment of this invention. It is a circuit diagram which shows the structure of the oscillation circuit by a comparative example. It is explanatory drawing which shows an oscillation frequency versus operating current characteristic. It is explanatory drawing which shows the relationship of the error rate with respect to an oscillation frequency. It is a block diagram which shows the structure of the semiconductor device by embodiment of this invention. It is a block diagram which shows the structure of the semiconductor device by other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Oscillator 10R Ring oscillator INV1-INV7 Inverter C1-C3 Capacitor M1-M8 PMOS transistor M10-M16 NMOS transistor I1, I2 Variable current source

Claims (5)

A ring in which the plurality of inverters are connected in a ring shape by connecting an input terminal of the inverter located at one end and an output terminal of the inverter located at the other end among the plurality of inverters connected in series An oscillator,
At least one capacitor selectively connected to an output terminal of at least one desired inverter among the plurality of inverters;
The capacitor is selectively connected to a power supply terminal of the inverter connected to an output terminal of the plurality of inverters, and includes at least one current adjustment transistor that adjusts an operating current for operating the inverter. Features an oscillation circuit. The capacitor is
The oscillation circuit according to claim 1, wherein the oscillation circuit has a capacitance larger than a parasitic capacitance of a transistor forming the inverter. The current adjusting transistor is:
Between the first power supply terminal of the inverter and the first potential side power supply, and between the second power supply terminal of the inverter and the second potential side power supply lower than the first potential, respectively. The oscillation circuit according to claim 1, wherein the oscillation circuit is connected. 2. The oscillation circuit according to claim 1, further comprising a reference current generation transistor that forms a current mirror circuit together with the current adjustment transistor and generates a reference current of a current flowing through the current adjustment transistor. A ring in which the plurality of inverters are connected in a ring shape by connecting an input terminal of the inverter located at one end and an output terminal of the inverter located at the other end among the plurality of inverters connected in series An oscillator,
At least one capacitor selectively connected to an output terminal of at least one desired inverter among the plurality of inverters;
An oscillation circuit comprising: at least one current adjustment transistor for adjusting an operating current for operating the inverter, wherein the capacitor is selectively connected to a power supply terminal of the inverter connected to an output terminal among the plurality of inverters. When,
A semiconductor integrated circuit that operates based on a clock signal generated by the oscillation circuit.

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