JP2008098923A - Receiver - Google Patents

Abstract

In a diversity receiving system, a receiving apparatus capable of reducing the size and selecting or synthesizing digital signals generated by each demodulator in a timely manner is realized.
A receiver 1 according to the present invention includes tuner sections 10 and 20 on one surface of a multilayer substrate 60, and includes the demodulation sections 30 and 40 on the other surface of the multilayer substrate 60. A crystal oscillation circuit 50 that generates a reference clock and outputs the reference clock to the tuner units 10 and 20 is provided on the surface of the multilayer substrate 60 including the tuner units 10 and 20.
[Selection] Figure 1

Description

  The present invention relates to a receiving apparatus including a tuner unit that receives an RF signal and a demodulation unit that demodulates a signal received by the tuner unit and outputs the demodulated signal as a data signal.

  Conventionally, information to be transmitted is converted into a digital signal, and a high-frequency digital modulation signal is generated by modulating a high-frequency carrier wave with this digital signal, and this high-frequency digital modulation signal is transmitted to a receiving device via space or a transmission line. Technology is used.

  Further, the receiving device includes a tuner unit and a demodulating unit. The tuner unit extracts a specific high-frequency digital modulation signal. The high-frequency digital modulation signal is converted into a digital signal by the demodulation unit, and then demodulated into a digital signal before modulation.

  Here, since the specific high frequency digital modulation signal extracted in the tuner section is extracted from a plurality of high frequency digital modulation signals existing in a certain frequency band, the input level is not constant. For this reason, the tuner unit is required to be able to receive normally even in the case of a signal with a particularly low input level. Therefore, in the receiving device, the influence of noise radiation from outside or inside the receiving device is reduced. There is a need. Further, the receiving device is required to be miniaturized so that it can be provided in a mobile communication terminal such as a mobile phone.

  Therefore, in order to reduce the size of the receiving device and reduce the influence of noise, for example, there are devices disclosed in Patent Documents 1 and 2 as described below.

  In Patent Document 1, a shield layer with a GND pattern is set inside the multilayer substrate, a high-frequency circuit is mounted on the multilayer substrate on the surface side of the GND pattern, and a shield cap is placed thereon to cover the GND pattern. A high-frequency SMD module in which a high-frequency circuit is shielded by connecting is disclosed. Further, in Patent Document 1, the size of the apparatus is reduced by setting a resistor constituting the high-frequency circuit as a printing resistor on the bottom surface side of the multilayer substrate.

  In Patent Document 2, a receiving antenna unit and a receiving circuit digital circuit unit are arranged in parallel on one surface of a circuit wiring board, and a receiving circuit analog circuit unit is arranged on the other surface of the circuit wiring board. There is disclosed a receiving device which is provided and is reduced in size by interposing an electromagnetic shield layer on the circuit wiring board.

  Furthermore, in order to suppress electromagnetic noise generated from the substrate, for example, Patent Document 3 discloses a digital GND layer for digital circuits disposed on the entire surface of the inner layer of the substrate, an analog adjacent to the digital GND layer, A printed wiring board having an analog GND layer for an analog circuit disposed in an inner layer of a signal processing area is disclosed.

  However, in Patent Document 1, it is possible to reduce the size of the device in the width direction by setting the resistance constituting the high-frequency circuit on the bottom surface side of the multilayer substrate, but there is a limit to the size reduction of the device by this method.

  Further, in Patent Document 2, since sufficient isolation between the receiving circuit analog circuit unit and the receiving circuit digital circuit unit cannot be ensured, the harmonic signal generated by ON / OFF of the output signal of the receiving circuit digital circuit unit is received by the receiving circuit. There is a risk of affecting the analog circuit section.

  Specifically, the amplitude of the output signal from the receiver circuit digital circuit section is very large with respect to the voltage of the signal input to the receiver circuit analog section. Occurs. In Patent Document 2, although an electromagnetic shield layer is interposed in a circuit wiring board, when a harmonic signal current flows through a parasitic inductance generated in the electromagnetic shield layer, a voltage of a harmonic signal component is generated, and the potential of the electromagnetic shield layer is It is not 0 V, and becomes a value obtained by adding this voltage. This potential variation of the electromagnetic shield layer affects the tuner portion.

  Therefore, in order to solve such a problem, for example, the electromagnetic shield layer in Patent Document 2 is made to have a multilayer structure including an analog GND layer and a digital GND layer as disclosed in Patent Document 3. Conceivable.

However, in this case, the analog GND layer and the digital GND layer are coupled by the parasitic capacitance generated between both GND layers, and the potential of the analog GND may fluctuate and affect the receiving circuit analog circuit unit. . For this reason, when the tuner unit and the demodulating unit are brought close to each other in order to reduce the size of the receiving apparatus, there is a problem that the influence of the harmonic signal generated from the demodulating unit that handles a large amplitude signal has a large effect Arise. In addition, in order to receive a weak signal, it is necessary to increase the parasitic capacitance generated between the analog GND layer and the digital GND layer as much as possible.
JP 5-14015 A (published on January 22, 1993) JP 10-197662 A (published July 31, 1998) JP 2000-353895 A (released on December 19, 2000)

  Therefore, the present applicant intends to reduce the size of the receiving device by providing the tuner unit and the demodulation unit on different surfaces of the substrate, and the current of the harmonic signal generated in the demodulation unit affects the tuner unit. (Japanese Patent Application No. 2005-277682 (filing date: September 26, 2005); unpublished at the time of confirmation prior to the filing of the present application). FIG. 14 shows the configuration of receiving apparatus 200 in the above application.

  As shown in FIG. 14, the receiving apparatus 200 includes a tuner unit 210 on one surface of the multilayer substrate 230 and a demodulation unit 220 on the other surface. Further, the surface of the multilayer substrate 230 on the demodulator 220 side is sealed with a sealing material 240. Furthermore, a shield GND layer is interposed between the analog GND layer and the digital GND layer in the multilayer substrate 230 via an insulating layer. Thereby, in the receiving apparatus 200, the apparatus is reduced in size and the current of the harmonic signal generated in the demodulator 220 is prevented from affecting the tuner section 210.

  As shown in FIG. 15, the tuner unit 210 includes an input terminal 212, an RF amplifier 213, a mixer 214, a voltage control circuit 215, a PLL circuit 216, a filter unit 217, and an IF amplifier 218. I have.

  The RF signal input from the antenna 211 is amplified by the RF amplifier 213 and then converted into an IF signal by the mixer 214, the voltage control circuit 215, and the PLL circuit 216. The IF signal is band-limited by the filter unit 217, amplified by the IF amplifier 218, and output to the demodulation unit 220.

  Further, the demodulator 220 includes an AD converter 221 and a digital signal processor 222 as shown in FIG. The IF signal input to the demodulation unit 220 is converted into a digital signal by the AD conversion unit 221 and then demodulated into a digital signal before being modulated by the digital signal processing unit 222.

  Further, the crystal oscillator 251 provided outside the tuner unit 210 is connected to the PLL circuit 216. The tuner unit 210 operates based on a reference clock output from the crystal oscillator 251.

  However, since the receiving device 200 is a closed module in which one tuner unit 210 and one demodulating unit 220 are mounted, it is difficult to apply the diversity receiving method to receive a high frequency signal from two or more antennas. . In addition, in the case of the diversity reception method, when the reference clock is output from the crystal oscillator 251 to each PLL circuit, it is affected by an external radio wave or the like, so that there is a possibility that the PLL circuit cannot be accurately synchronized. is there. For this reason, there arises a problem that a plurality of received signals cannot be selected or synthesized in a timely manner.

  Further, the receiving apparatus 300 shown in FIG. 16 is configured to mount the tuners 310 and 320 and the demodulating units 330 and 340 on one surface of the multilayer substrate, but the receiving apparatus 300 is further downsized. In some cases, it is disadvantageous in terms of area.

  The present invention has been made in view of the above problems, and an object of the present invention is to realize a receiving apparatus that can select or synthesize received signals in a timely manner and can be downsized in a diversity reception system. There is.

  In order to solve the above problems, a receiving apparatus according to the present invention extracts a specific high-frequency signal from a plurality of digitally modulated high-frequency signals and converts it to a low-frequency signal, and outputs from the tuner section A diversity reception type receiving device including at least two or more demodulating units that convert a low-frequency signal into a digital signal and perform demodulation processing, and includes the tuner unit on one surface of the multilayer substrate, The other surface of the multilayer board is provided with the demodulator, and the surface of the multilayer board provided with the tuner is provided with an oscillation circuit that generates a reference clock and outputs the reference clock to the tuner. .

  According to the above configuration, even in a receiving apparatus applied to the diversity receiving method, the oscillation circuit generates a reference clock and outputs it to each tuner unit, so that each tuner unit can be synchronized. This makes it possible to select or synthesize digital signals generated by the respective demodulation units with good timing.

  The receiving apparatus includes a tuner unit and an oscillation circuit on one surface of the multilayer substrate, and a demodulation unit on the other surface. Therefore, when the tuner unit, the demodulation unit, and the oscillation circuit are combined into one package, the size of the receiving device can be reduced.

  The oscillation circuit preferably includes a crystal oscillator that outputs a reference clock, and impedance conversion means that performs impedance conversion on a reference clock signal output from the crystal oscillator.

  According to the above configuration, it is possible to keep the waveform of the reference clock constant by impedance-converting the reference clock output from the crystal oscillator. As a result, even when the reference clock passes through the outside of the shield and is affected by external radio waves, the reference clock can be prevented from being lost.

  The oscillation circuit preferably further includes a buffer circuit that amplifies the reference clock. According to the above configuration, the reference clock is amplified by the buffer circuit. For this reason, it is possible to suppress the rounding of the reference clock due to the influence from the outside even when each tuner unit approaches as the receiving device is downsized. Thereby, it is possible to further reduce the size of the receiving apparatus.

  The oscillation circuit preferably further includes a multiplier that multiplies the reference clock frequency or a frequency divider that divides the reference clock frequency. According to the above configuration, the frequency of the reference clock can be converted to a desired frequency by including the multiplier or the frequency divider. As a result, even if the clock frequency used in each tuner unit is different, the reference clock can be distributed in accordance with the clock frequency used in each tuner unit.

  The oscillation circuit is preferably provided in at least one tuner unit. According to the above configuration, the oscillation circuit is provided in the tuner unit. Therefore, it is possible to further reduce the size of the receiving device as compared with the configuration in which the oscillation circuit is provided on the multilayer substrate.

  The tuner section on the side where the oscillation circuit is not provided preferably includes a buffer circuit that amplifies the reference clock. According to the above configuration, the reference clock is amplified by the buffer circuit. For this reason, even when each tuner unit approaches as the receiving device is downsized, it is possible to suppress the rounding of the reference clock due to an external influence. Therefore, the influence of the reference clocks input to the tuner units can be suppressed, and the receiving device can be further downsized.

  It is preferable that the tuner portion on which the oscillation circuit is not provided further includes a multiplier that multiplies the reference clock frequency or a frequency divider that divides the reference clock frequency.

  According to the above configuration, the multiplier or the frequency divider is provided in the tuner portion on which the oscillation circuit is not provided. As a result, even if the clock used in the tuner unit on which the oscillation circuit is not provided is different from the clock used in the tuner unit provided with the oscillation circuit, each tuner unit can have a desired It is possible to supply the frequency of the clock.

  An analog GND layer connected to the tuner unit, a digital GND layer connected to the demodulator unit, and the analog GND layer and the digital GND layer are provided on the multilayer substrate, and insulated from both GND layers. It is preferable to provide a shield GND layer separated by layers.

  According to the above configuration, since the shield GND layer is provided between the digital GND layer and the analog GND layer, it is possible to prevent a harmonic signal current flowing in the digital GND layer from flowing into the analog GND layer. Thereby, it is possible to prevent the influence of the harmonic signal from the demodulation unit from reaching the tuner unit and to prevent the reception performance from deteriorating.

  The tuner unit or the demodulating unit is preferably formed of a semiconductor integrated circuit. According to the above configuration, since the tuner unit or the demodulating unit is made of a semiconductor integrated circuit formed as an IC chip, it is possible to reduce the size of the tuner unit and the demodulating unit. Along with this, it is possible to further reduce the size of the receiving apparatus.

  In order to solve the above problems, a receiving apparatus according to the present invention extracts a specific high-frequency signal from a plurality of digitally modulated high-frequency signals and converts it to a low-frequency signal, and outputs from the tuner section A diversity reception type receiving device including at least two or more demodulating units that convert a low-frequency signal into a digital signal and perform demodulation processing, and includes the tuner unit on one surface of the multilayer substrate, The other surface of the multilayer board is provided with the demodulator, and the surface of the multilayer board provided with the tuner is provided with an oscillation circuit that generates a reference clock and outputs the reference clock to the tuner. As a result, it is possible to reduce the size of the receiving apparatus and to select or synthesize digital signals generated by the respective demodulation units with good timing.

Embodiment 1
An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a cross-sectional view illustrating a schematic configuration of a receiving device 1 according to the present embodiment.

  The receiving apparatus 1 employs a diversity reception method in which high-frequency signals received from two or more antennas are converted into digital signals, and selection or synthesis processing is performed on the digital signals. Thereby, even when the receiving apparatus 1 is in a moving state or in a region where reception is difficult, stable reception is performed and an audio signal and / or video signal is output.

  As shown in FIG. 1, the receiving device 1 includes tuner units 10 and 20 and a crystal oscillation circuit 50 on one surface of a multilayer substrate 60. On the other surface, demodulation units 30 and 40 are provided. In the receiving device 1, the demodulation units 30 and 40 are sealed with a sealing material 70.

  The tuner units 10 and 20 and the demodulation units 30 and 40 are made of semiconductor integrated circuits formed as IC chips. The external connection electrodes of these IC chips and the electrodes of the multilayer substrate 60 are made of gold or the like. Bonding with a conductor. In the receiving apparatus 1, the tuner unit 10 and the demodulation unit 30 operate as a pair, and the tuner unit 20 and the demodulation unit 40 operate as a pair.

  The sealing material 70 is applied to the demodulating units 30 and 40 in order to prevent the demodulating units 30 and 40 from being affected by moisture, dust, and the like, but is not limited to the demodulating units 30 and 40. And 20 may be applied. Moreover, you may apply | coat to the receiver 1 whole.

  As shown in FIG. 2, the multilayer substrate 60 has a plurality of wiring layers and insulating layers alternately stacked. An analog GND layer (AGND) 62 that is electrically connected to the tuner units 10 and 20 is provided in the first wiring layer 61a and the second wiring layer 61b that are the layers on the tuner units 10 and 20 side. A shield GND layer 63 is provided on the third wiring layer 61c. The fourth wiring layer 61d, the fifth wiring layer 61e, and the sixth wiring layer 61f are provided with a digital GND layer (DGND) 64 that is electrically connected to the demodulation units 30 and 40. The seventh wiring layer 61g and the eighth wiring layer 61h have a function as a frame for realizing a space in which the demodulation units 30 and 40 are disposed. Further, each of the wiring layers 61a to 61h includes an antenna terminal (not shown) provided on a substrate on which the receiving device 1 is mounted and the tuner units 10 and 20, and the tuner units 10 and 20 and the demodulation units 30 and 40. And vias for electrically connecting the demodulating units 30 and 40 and a demodulated data signal input terminal (not shown) provided on a substrate on which the receiving device 1 is mounted, respectively. Yes. In the present embodiment, eight wiring layers are provided, but the number of wiring layers is not limited to this.

  The shield GND layer 63 is provided so as to face the analog GND layer 62 and the digital GND layer 64 with an insulating layer interposed therebetween, and the analog GND layer 62 and the digital GND layer 64 are electrically separated (shielded). is doing.

  In addition, the analog GND layer 62, the shield GND layer 63, and the digital GND layer 64 are not connected to each other in the receiving device 1, and are connected to the GND of the substrate on which the receiving device 1 is mounted via separate GND connection terminals. Connected to the layer. Note that the shield GND layer 63 is not connected to any signal line in the receiving apparatus 1 and is connected only to the GND layer of the substrate on which the receiving apparatus 1 is mounted.

  With the above-described configuration of the multilayer substrate 60, the harmonic signal from the digital GND layer 64 flows to the GND layer of the substrate on which the receiving device 1 is mounted via the shield GND layer 63, and thus the analog GND layer from the digital GND layer 64. It is possible to prevent or reduce the flow of the harmonic signal current to 62.

  Accordingly, even when the tuner unit 10 and 20 is provided on one surface of the multilayer substrate 60 and the demodulating units 30 and 40 are provided on the other surface, the reception apparatus 1 can be handled in a small size, so that a weak signal is handled. The tuner units 10 and 20 can be prevented from being affected by the harmonic signal components from the demodulating units 30 and 40 handling a large amplitude, and the reception performance can be prevented from deteriorating.

  FIG. 3 is a block diagram illustrating a schematic circuit configuration of the receiving device 1. As shown in FIG. 3, the receiving device 1 according to the present embodiment includes tuner units 10 and 20 and demodulation units 30 and 40. The receiving device 1 is connected to the antennas 11 and 21.

  The tuner unit 10 includes an input terminal 12, an RF amplifier 13, a mixer 14, a voltage control circuit 15, a PLL circuit 16, a filter unit 17, and an IF amplifier 18. Similarly, the tuner unit 20 includes an input terminal 22, an RF amplifier 23, a mixer 24, a voltage control circuit 25, a PLL circuit 26, a filter unit 27, and an IF amplifier 28.

  The antenna 11 is connected to the tuner unit 10 via the input terminal 12. Similarly, the antenna 21 is connected to the tuner unit 20 via the input terminal 22. Thereby, tuner units 10 and 20 can receive RF signals from antennas 11 and 21.

  RF signals received by tuner units 10 and 20 are amplified by RF amplifiers 13 and 23 and input to mixers 14 and 24.

  Mixers 14 and 24 are connected to PLL circuits 16 and 26 via voltage control circuits 15 and 25. Voltage control circuits 15 and 25 and PLL circuits 16 and 26 generate local signals input to mixers 14 and 24. The mixers 14 and 24 convert the RF signal into an IF signal by mixing the RF signal and the local signal, and output the IF signal to the subsequent filter units 17 and 27.

  The IF signal is band-limited to a specific frequency band by the filter units 17 and 27, amplified by the IF amplifiers 18 and 28, and then output to the demodulation units 30 and 40.

  The demodulator 30 includes an AD converter 31, a selector / synthesizer 32, and a digital signal processor 33. The demodulator 40 includes an AD converter 41 and is connected to the selector / synthesizer 32.

  The AD converters 31 and 41 convert the IF signal, which is an analog signal, into a digital signal and output the digital signal to the selector / synthesizer 32. The selector / synthesizer 32 selects or synthesizes the two digital signals output from the AD converters 31 and 41, for example, by performing arithmetic processing. That is, the selector / synthesizer 32 selects a strong digital signal from the two digital signals or generates a strong digital signal by synthesizing the two signals.

  The selected or synthesized digital signal is demodulated by the digital signal processing unit 33 into a digital signal before being modulated (demodulated data signal) and output to a subsequent circuit.

  The selector / synthesizer 32 and the digital signal processing unit 33 are provided in the demodulator 30, but the configuration is not limited thereto, and may be provided in the demodulator 40.

  The receiving device 1 further includes a crystal oscillation circuit 50. The crystal oscillation circuit 50 includes a crystal oscillator 51 and an impedance converter 52.

  The crystal oscillator 51 generates a reference clock to synchronize the PLL circuits 16 and 26. As a result, the IF signals are output from the tuner units 10 and 20 with good timing, and the two digital signals output from the AD conversion units 31 and 41 can be synchronized. Therefore, the selector / synthesizer 32 can accurately select or synthesize the two digital signals.

  The impedance converter 52 is connected between the crystal oscillator 51 and the PLL circuits 16 and 26, and operates as a matching circuit between the crystal oscillator 51 and the PLL circuits 16 and 26.

  Specifically, the impedance converter 52 includes resistors R1 and R2 and capacitors C1 and C2. The crystal oscillator 51 is connected to the PLL circuit 16 via a resistor R1 and a capacitor C1, and is connected to the PLL circuit 26 via a resistor R2 and a capacitor C2. In addition, the impedance conversion part 52 is not restricted to the said structure, You may be comprised from resistance R1 and R2.

  The capacitors C1 and C2 are connected between the crystal oscillator 51 and the PLL circuits 16 and 26, and cut the DC component.

  The resistors R1 and R2 correct the amount by which the reference clock generated by the crystal oscillator 51 is supplied to the PLL circuits 16 and 26. Further, since the resistors R1 and R2 are provided in the coupling line of the PLL circuits 16 and 26, the receiving device 1 can ensure isolation of the PLL circuits 16 and 26.

  Therefore, the impedance converter 52 can adjust the degree to which one PLL circuit (for example, the PLL circuit 16) becomes a load of the other PLL circuit (for example, the PLL circuit 26). As a result, it is possible to keep the waveform of the reference clock constant and control so that the reference clock does not become dull.

  Here, the tuner units 10 and 20 and the crystal oscillation circuit 50 are provided on the same surface of the multilayer substrate 60. For this reason, the reference clock is output from the crystal oscillation circuit 50 to the tuner units 10 and 20 without passing through the shield GND layer 63 provided in the multilayer substrate 60. Therefore, the reference clock is affected by external radio waves. End up.

  However, since the impedance converter 52 includes resistors R1 and R2 in the coupled line between the crystal oscillator 51 and the PLL circuits 16 and 26, the receiving device 1 reduces the influence of the external radio wave received by the reference clock. It becomes possible.

  As described above, since the receiving apparatus 1 includes the crystal oscillation circuit 50, when the RF signal input from the antennas 11 and 21 is converted into an IF signal, the demodulation unit 30 is synchronized with the IF signal. And 40 can be input. As a result, in the receiving apparatus 1 that adopts the diversity reception method, it is possible to perform selection or synthesis processing with good timing on the digital signal obtained by converting the IF signal.

  In addition, the receiving apparatus 1 includes the tuner units 10 and 20 on one surface of the multilayer substrate 60 and the demodulation units 30 and 40 on the other surface. This makes it possible to reduce the size of the receiving device 1.

  FIG. 4 is a cross-sectional view showing a schematic configuration of the receiving device 2, and FIG. 5 is a block diagram showing a schematic circuit configuration of the receiving device 2. Here, the receiving device 2 is different from the receiving device 1 in that it includes a crystal oscillation circuit 50a instead of the crystal oscillation circuit 50 of FIG.

  The crystal oscillation circuit 50 a includes a crystal oscillator 51, an impedance conversion unit 52, and buffer circuits 53 and 54. Buffer circuits 53 and 54 amplify the reference clock distributed by impedance converter 52, respectively.

  The impedance conversion unit 52 is connected to the PLL circuit 16 via the buffer circuit 53, and is connected to the PLL circuit 26 via the buffer circuit 54. The reference clock output from the crystal oscillator 51 is distributed by the impedance converter 52.

  Here, since the tuner units 10 and 20 included in the receiving device 2 are mounted on the same surface of the multilayer substrate 60, the tuner units 10 and 20 approach when the size of the receiving device 2 is reduced. At this time, there is a possibility that the reference clock input to the PLL circuits 16 and 26 may be lost due to an external influence.

  Therefore, the buffer clocks 53 and 54 amplify the reference clock, so that even if the tuner units 10 and 20 approach as the receiver 2 is downsized, the reference clock is rounded due to external influences. Can be suppressed. As a result, the receiving device 2 can be further reduced in size.

  Further, FIG. 6 is a cross-sectional view showing a schematic configuration of the receiving device 3, and FIG. 7 is a block diagram showing a schematic circuit configuration of the receiving device 3. Here, the receiving device 3 is different from the receiving devices 1 and 2 in that it includes a crystal oscillation circuit 50b instead of the crystal oscillation circuit 50 or the crystal oscillation circuit 50a.

  The crystal oscillation circuit 50b includes a crystal oscillator 51, an impedance conversion unit 52, buffer circuits 53 and 54, and multipliers 55 and 56.

  The reference clock generated by the crystal oscillator 51 and controlled to keep the waveform constant by the impedance converter 52 is distributed to the multipliers 55 and 56. The multiplier 55 is connected to the PLL circuit 16 via the buffer circuit 53, and the multiplier 56 is connected to the PLL circuit 26 via the buffer circuit 54. The multipliers 55 and 56 convert the frequency of the reference clock by multiplying the frequency of the input reference clock.

  For example, the reference clock is 2 MHz, the clock used in the tuner unit 10 is 4 MHz, and the clock used in the tuner unit 20 is 6 MHz. That is, in this case, the clocks used in the tuner units 10 and 20 are different.

  At this time, a double multiplier is used for the multiplier 55 connected to the tuner unit 10 side, and a triple multiplier is used for the multiplier 56 connected to the tuner unit 20 side. This makes it possible to output a reference clock having a desired frequency to the tuner units 10 and 20.

  Therefore, even when the clocks used in the tuner units 10 and 20 are different, the reference clock can be distributed in accordance with the clock frequency used in the tuner units 10 and 20.

  In the receiving apparatus 3, the multipliers 55 and 56 are used in order to match the reference clock to the clock frequency used in the tuner units 10 and 20. However, the present invention is not limited to this. For example, only one of the multipliers 55 and 56 may be provided, and a frequency divider may be used instead of the multiplier.

[Embodiment 2]
Another embodiment of the present invention will be described as follows. In addition, about the member which has the same function as Embodiment 1, the same code | symbol is attached and the description is abbreviate | omitted.

  FIG. 8 is a cross-sectional view illustrating a schematic configuration of the receiving device 4. As shown in FIG. 8, the receiving device 4 includes tuner units 10 a and 20 on one surface of the multilayer substrate 60, and includes demodulation units 30 and 40 on the other surface. A sealing material 70 is applied to the demodulation units 30 and 40. The sealing material 70 is applied to the demodulation units 30 and 40, but may be applied to the tuner units 10 and 20 without being limited to the demodulation units 30 and 40. Moreover, you may apply | coat to the receiver 4 whole.

  FIG. 9 is a block diagram illustrating a schematic circuit configuration of the receiving device 4. The tuner unit 10 a includes a crystal oscillation circuit 100, and the crystal oscillation circuit 100 is connected to the PLL circuits 16 and 26. The crystal oscillation circuit 100 includes a crystal oscillator 101 and an impedance conversion unit 102.

  The crystal oscillator 101 is connected to the PLL circuit 16 and the PLL circuit 26 via the impedance converter 102. The crystal oscillator 101 generates a reference clock to synchronize the PLL circuits 16 and 26.

  Similar to the impedance converter 52, the impedance converter 102 operates as a matching circuit between the crystal oscillator 101 and the PLL circuits 16 and 26, and includes a resistor R3 and a capacitor C1.

  The capacitor C3 is connected between the crystal oscillator 101 and the PLL circuit 26, and cuts a DC component.

  The resistor R3 corrects the amount by which the reference clock generated by the crystal oscillator 101 is supplied to the PLL circuit 26. In addition, since the resistor R3 is provided in the coupling line of the PLL circuits 16 and 26, the isolation of the PLL circuits 16 and 26 can be ensured in the receiving device 4.

  Therefore, the impedance converter 102 can adjust the degree to which one PLL circuit (for example, the PLL circuit 16) becomes a load of the other PLL circuit (for example, the PLL circuit 26). As a result, it is possible to keep the waveform of the reference clock constant and control so that the reference clock does not become dull.

  Here, since the crystal oscillation circuit 100 is provided in the tuner unit 10a, it is not affected by external radio waves. Therefore, the reference clock output from the crystal oscillator 101 is input to the PLL circuit 16 as a clock used in the tuner unit 10a.

  On the other hand, when the reference clock is input to the PLL circuit 26, the tuner units 10 a and 20 are provided on the same surface of the multilayer substrate 60, and therefore the reference clock passes through the shield GND layer 63 provided in the multilayer substrate 60. The signal is output to the tuner unit 20 without passing through. For this reason, the waveform of the reference clock is distorted due to the influence of external radio waves.

  However, since the impedance converter 102 includes the resistor R3 in the coupling line between the crystal oscillator 101 and the PLL circuit 26, the receiving device 1 can reduce the influence of the external radio wave received by the reference clock. Become.

  As described above, in the diversity reception method, when an RF signal input from each antenna is converted into an IF signal, the IF signal can be synchronized and input to the demodulator 30. For this reason, it becomes possible to select or synthesize the digital signal converted from the IF signal with good timing.

  In addition, since the receiving device 4 has a configuration in which the crystal oscillation circuit 100 is provided in the tuner unit 10a, as shown in the receiving devices 1 to 3, the crystal oscillation circuits 50, 50a and 50b are formed on the multilayer substrate 60. Compared to the configuration provided with the above, further miniaturization can be achieved.

  FIG. 10 is a cross-sectional view illustrating a schematic configuration of the receiving device 5, and FIG. 11 is a block diagram illustrating a schematic circuit configuration of the receiving device 5. Here, the receiving device 5 differs from the receiving device 4 in that the tuner unit 20a includes the buffer circuit 103.

  The buffer circuit 103 is provided in the tuner unit 20 a and is connected between the impedance conversion unit 102 and the PLL circuit 26.

  The reference clock generated by the crystal oscillator 101 is input to the tuner unit 20a via the impedance conversion unit 102. However, when the tuner units 10a and 20a are approaching, the reference clock input to the PLL circuit 26 via the impedance conversion unit 102 may be lost due to an external influence.

  Accordingly, by amplifying the reference clock input to the PLL circuit 26 via the buffer circuit 103, even if the tuner units 10a and 20a approach each other as the receiving device 5 is reduced in size, It becomes possible to suppress the rounding of the reference clock due to the influence. As a result, the receiving device 5 can be further downsized.

  Further, FIG. 12 is a cross-sectional view showing a schematic configuration of the receiving device 6, and FIG. 13 is a block diagram showing a schematic circuit configuration of the receiving device 6. Here, the receiving device 6 is different from the receiving device 5 in that the tuner unit 20b includes a multiplier 104.

  The tuner unit 20 b includes a multiplier 104. The multiplier 104 is connected between the impedance converter 102 and the buffer circuit 103, and multiplies the frequency of the input reference clock.

  The reference clock generated by the crystal oscillator 101 is input to the PLL circuit 16 as a clock used by the tuner unit 10a. Therefore, when the frequency of the clock used by the tuner unit 10a and the tuner unit 20b is different, the reference clock input to the tuner unit 20b is multiplied by the multiplier 104 and used by the tuner unit 20b. The frequency is converted to a clock.

  Thereby, even when the clocks used in the tuner units 10a and 20b are different, the reference clock can be distributed in accordance with the clock frequency used in the tuner units 10a and 20b.

  Note that the receiving device 6 uses the multiplier 104, but is not limited to this. For example, a frequency divider may be used instead of the multiplier 104.

  Further, the crystal oscillation circuit 100 is provided in the tuner unit 10a, but is not limited to this, and may be provided in the tuner units 20, 20a, and 20b. However, when the crystal oscillation circuit 100 is provided in the tuner units 20a and 20b, the buffer circuit 103 and / or the multiplier 104 are preferably provided in the tuner unit 10a.

  The receiving apparatuses 1 to 6 have been described as including the two tuner units 10 and 20 and the two demodulating units 30 and 40. However, the present invention is not limited to this, and three or more tuner units and demodulating units are provided. May be provided. In this case, a plurality of tuner units are provided on one surface of the multilayer substrate 60, and a plurality of demodulation units are provided on the other surface.

  Further, in the case where the receivers 1 to 6 are provided with three or more tuner units and a crystal oscillation circuit is provided in the tuner unit, at least one tuner unit may be provided with a crystal oscillation circuit. That's fine.

  The demodulating units 30 and 40 provided in the receiving devices 1 to 6 are each built in independent chips. However, the present invention is not limited to this, and the demodulating units 30 and 40 are integrated into one chip. You can make it.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The receiving apparatus according to the present invention is effective for a movable communication device such as a portable terminal that employs a diversity receiving method.

BRIEF DESCRIPTION OF THE DRAWINGS It is Embodiment 1 of this invention, and is sectional drawing which shows schematic structure of a receiver. It is sectional drawing which shows schematic structure of the multilayer substrate of the receiver shown by FIG. It is a block diagram which shows the schematic circuit structure of the receiver shown by FIG. FIG. 6 is a cross-sectional view illustrating a schematic configuration of the receiving device when the crystal oscillation circuit includes a buffer circuit, which is a modification of the receiving device illustrated in FIG. 1. FIG. 5 is a block diagram showing a schematic circuit configuration of the receiving apparatus shown in FIG. 4. FIG. 5 is a cross-sectional view illustrating a schematic configuration of the receiving device when the crystal oscillation circuit includes a multiplier, which is a modification of the receiving device illustrated in FIG. 4. FIG. 7 is a block diagram illustrating a schematic circuit configuration of the receiving device illustrated in FIG. 6. FIG. 9 is a cross-sectional view illustrating a schematic configuration of a receiving apparatus according to a second embodiment of the present invention. It is a block diagram which shows the schematic circuit structure of the receiver shown by FIG. FIG. 10 is a cross-sectional view illustrating a schematic configuration of the receiving device when the crystal oscillation circuit includes a buffer circuit, which is a modification of the receiving device illustrated in FIG. 8. It is a block diagram which shows the schematic circuit structure of the receiver shown by FIG. FIG. 11 is a cross-sectional view illustrating a schematic configuration of the receiving device when the crystal oscillation circuit includes a multiplier, which is a modification of the receiving device illustrated in FIG. 10. It is a block diagram which shows the schematic circuit structure of the receiver shown by FIG. It is sectional drawing which shows schematic structure of the receiver with which one tuner part and one demodulation part are provided. FIG. 15 is a block diagram illustrating a schematic circuit configuration of the receiving device illustrated in FIG. 14. It is sectional drawing which shows schematic structure of the receiver with which two tuner parts and two demodulation parts are provided in one surface of the multilayer substrate.

Explanation of symbols

1, 2, 3, 4, 5, 6 Receiving device 10, 10a, 20 Tuner unit 30, 40 Demodulator unit 50, 50a, 50b, 100 Crystal oscillation circuit (oscillation circuit)
51, 101 Crystal oscillator 52, 102 Impedance converter (impedance converter)
53, 54, 103 Buffer circuit 55, 56, 104 Multiplier 62 Analog GND layer 63 Shield GND layer 64 Digital GND layer 20a, 20b Tuner section

Claims (9)

A tuner unit that extracts a specific high-frequency signal from a plurality of digitally modulated high-frequency signals and converts it into a low-frequency signal, and a low-frequency signal output from the tuner unit is converted into a digital signal to perform demodulation processing A diversity reception system receiving device including at least two sets of demodulation units,
The one side of the multilayer board is provided with the tuner section, the other side of the multilayer board is provided with the demodulation section,
A receiving apparatus comprising: an oscillation circuit configured to generate a reference clock and output the reference clock to a surface of the multilayer substrate including the tuner unit. The oscillation circuit is
A crystal oscillator that outputs a reference clock; and
The receiving apparatus according to claim 1, further comprising impedance conversion means for performing impedance conversion on a reference clock signal output from the crystal oscillator.   The receiving apparatus according to claim 2, wherein the oscillation circuit further includes a buffer circuit for amplifying a reference clock.   4. The receiving apparatus according to claim 2, wherein the oscillation circuit further includes a multiplier that multiplies the reference clock frequency or a frequency divider that divides the reference clock frequency.   The receiving apparatus according to claim 2, wherein the oscillation circuit is provided in at least one tuner unit.   6. The receiving apparatus according to claim 5, wherein the tuner unit on which the oscillation circuit is not provided includes a buffer circuit that amplifies a reference clock.   6. The tuner section on which the oscillation circuit is not provided further comprises a multiplier that multiplies a reference clock frequency or a frequency divider that divides the reference clock frequency. 6. The receiving device according to 6. In the multilayer substrate,
An analog GND layer connected to the tuner section;
A digital GND layer connected to the demodulator;
8. The semiconductor device according to claim 1, further comprising a shield GND layer provided between the analog GND layer and the digital GND layer and separated by both the GND layers and the insulating layer. The receiving device described.   The receiving apparatus according to claim 1, wherein the tuner unit or the demodulating unit includes a semiconductor integrated circuit.

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