JP2008098587A - ESD protection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ESD protection circuit which can effectively protect an internal circuit from breakage due to ESD. <P>SOLUTION: The ESD protection circuit comprising a first NMOS transistor 16 for a clamp, a second NMOS transistor 17 for a trigger, and a load element 18 is disclosed. The first NMOS transistor connects one end of the current passage to a first terminal 11 and connects the other end to a second terminal 12 and has a gate oxide film having the same thickness as an NMOS transistor 15 which constitutes the internal circuit 13. The second NMOS transistor 17 connects one end of the current passage to the first terminal and connects the other end and a gate to the gate of the first NMOS transistor and has a gate oxide film having a thickness thinner than the first NMOS transistor. One end of the load element is connected to the gate of the first NMOS transistor and the other end is connected to the second terminal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an ESD protection circuit for protecting an internal circuit of a CMOS integrated circuit device from destruction caused by ESD (Electro Static Discharge).

  In general, a CMOS integrated circuit device incorporates an ESD protection circuit in order to protect an internal circuit from destruction due to ESD. Various structures have been proposed for the ESD protection circuit, and a GGNMOS transistor (Grounded Gate N-channel MOS transistor) is known as a MOS type protection element. The GGNMOS transistor has a drain connected to a power supply terminal (power supply pad), a source connected to a ground terminal (ground pad), and a gate connected to the ground terminal (source).

  Therefore, the GGNMOS transistor is normally in an off state as the operation of the transistor. When ESD is applied, the PN junction between the drain and the substrate (back gate) breaks down to protect the internal circuit.

The voltage (snapback voltage) Vt1 at which the GGNMOS transistor as the protection element operates is determined by the junction breakdown voltage of the NP junction between the drain and the back gate. When a MOS transistor is used as a protection element, the relationship between the snapback voltage Vt1 and the gate breakdown voltage Vox of the MOS transistor constituting the internal circuit is:
Vox> Vt1
If the above is not established, the gate breakdown of the MOS transistor constituting the internal circuit occurs before the protection element operates.

  Normally, when the GGNMOS transistor and the MOS transistor in the input stage of the internal circuit are formed in the same size and in the same process, the gate breakdown voltage Vox becomes higher than the snapback voltage Vt1. However, when the channel width of a recent submicron process, for example, a MOS transistor is 130 nm or less (the gate oxide film thickness is 60 nm) or less, a reverse phenomenon occurs in the relationship between the gate breakdown voltage Vox and the snapback voltage Vt1, and the snapback voltage Vt1 Becomes higher than the gate breakdown voltage Vox (see, for example, Patent Document 1). For this reason, the MOS type protection element cannot effectively protect the internal circuit.

  Further, it is known that when the MOS type protection element is applied to a terminal with an output buffer, for example, an output terminal (output pad) or an input / output terminal (input / output pad), a sufficient protection effect cannot be obtained. That is, since the snapback voltage Vt1 of the NMOS transistor that constitutes the output buffer and the NMOS transistor that constitutes the protection element is the same, current flows not only in the protection element but also in the output buffer during the protection operation. At this time, if the drive capability of the output buffer is small, a large current due to ESD flows and the NMOS transistor is destroyed.

Furthermore, in order to effectively protect the internal circuit, a configuration has been proposed in which MOS type protection elements are connected in parallel to allow a large current to flow. However, in the parallel structure, the voltage at the anode terminal of the protection element drops at the moment when any of the protection elements operates, and thus there is a possibility that other protection elements may not operate. That is, even if the size of the protection element is increased, if the current concentrates on a specific protection element, the expected protection breakdown voltage is not satisfied.
EOS / ESD SYMPOSIUM PROCEEDINGS 1994 pp.6.1.1-6.1.9 "The Impact of Technology Scaling on ESD Robustness and Protection Circuit Design" Ajith Amerasekera et.al.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an ESD protection circuit capable of effectively protecting an internal circuit from destruction by ESD.

  According to one embodiment of the present invention, the gate oxide film having the same thickness as the NMOS transistor constituting the internal circuit is provided, one end of the current path is connected to the first terminal, and the other end of the current path is the second terminal. A first NMOS transistor for clamping connected to the first NMOS transistor, a gate oxide film thinner than the first NMOS transistor, one end of the current path connected to the first terminal, and the other end of the current path and the gate connected to the first NMOS transistor An ESD protection circuit comprising: a trigger second NMOS transistor connected to the gate of one NMOS transistor; and a load element having one end connected to the gate of the first NMOS transistor and the other end connected to the second terminal. Provided.

  According to another aspect of the present invention, the gate oxide film having the same thickness as the NMOS transistor constituting the internal circuit is provided, and one end of each current path is commonly connected to the first terminal, A plurality of first NMOS transistors for clamping, the other end of which is commonly connected to the second terminal, and a gate oxide film thinner than the plurality of first NMOS transistors, and one end of the current path is the first terminal The other end and gate of the current path are commonly connected to the gates of the plurality of first NMOS transistors, and one end is commonly connected to the gates of the plurality of first NMOS transistors. An ESD protection circuit comprising a load element connected to the second terminal.

  According to the present invention, an ESD protection circuit capable of effectively protecting an internal circuit from destruction due to ESD can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 shows an ESD protection circuit according to a first embodiment of the present invention. The ESD protection circuit 10 is provided between a power supply terminal (VDD pad) 11 and a reference potential terminal (VSS pad) 12 in the CMOS integrated circuit device, and an internal circuit 13 is formed from the ESD applied to these terminals 11 and 12. Protect. The internal circuit 13 is a CMOS inverter composed of a PMOS transistor 14 and an NMOS transistor 15 in this example, and operates with the voltage between the terminals 11 and 12.

  The ESD protection circuit 10 includes a clamp NMOS transistor 16, a trigger NMOS transistor 17, and a resistance element 18 as a load element. The drain of the NMOS transistor 17 is connected to the power supply terminal 11, and the gate and source are connected to one end of the resistance element 18. The other end of the resistance element 18 is connected to the reference potential terminal 12. The drain of the NMOS transistor 16 is connected to the power supply terminal 11, the gate is connected to a connection node between the NMOS transistor 17 and the resistance element 18, and the source is connected to the reference potential terminal 12.

  As shown in FIG. 2, the gate oxide film thickness Tox16 of the NMOS transistor 16 is the same as the gate oxide film thickness Tox15 of the NMOS transistor 15 constituting the internal circuit 13, and the gate oxide film thickness Tox17 of the NMOS transistor 17 is It is thinner than the NMOS transistors 15 and 16. The gate insulating film thickness Tox15 of the NMOS transistor 15 is a film thickness at which the snapback voltage Vt1 is higher than the gate breakdown voltage Vox. Further, the snapback voltage Vt1 of the trigger NMOS transistor 17 is lower than the gate breakdown voltage Vox of the NMOS transistor 15 constituting the internal circuit 13 by ΔV1. The gate insulating film thickness Tox15 of the NMOS transistor 15 is a film thickness at which the snapback voltage Vt1 is higher than the gate breakdown voltage Vox. That is, for example, the MOS transistor is formed by a submicron process with a channel width of 130 nm or less.

  The snapback voltage Vt1 is controlled by adjusting the gate oxide film thickness of the trigger NMOS transistor 17. Further, the NMOS transistor 17 can be designed so that the NMOS transistor 17 itself is not destroyed by adjusting each capacitance relationship with the clamping NMOS transistor 16 through which the ESD current flows. Further, the resistance element 18 has a resistance value that can turn on the NMOS transistor 16 after the NMOS transistor 17 snaps back and before the transistors 14 and 15 in the internal circuit 13 are destroyed. In addition, the leakage current of the NMOS transistor 17 is set to a resistance value that has a voltage value that does not allow the NMOS transistor 16 to turn on.

  In the configuration as described above, when a positive ESD is applied to the power supply terminal 11 with reference to the potential VSS applied to the reference potential terminal 12, the NMOS transistor 17 causes the internal circuit 13 as shown in FIG. In order to perform snapback at a voltage V1 lower than the gate breakdown voltage Vox of the NMOS transistor 15 that constitutes, the MOS transistors 14 and 15 in the internal circuit 13 are turned on before the gate breakdown occurs. As a result, the gate potential of the clamping NMOS transistor 16 is raised and turned on, so that the ESD protection circuit 10 can be operated reliably and the internal circuit 13 can be effectively protected. In addition, since the snapback characteristic of the NMOS transistor 17 is used, almost no leakage current flows through the NMOS transistor 17 during normal operation of the internal circuit 13, and current consumption can be minimized.

  On the other hand, when negative polarity ESD is applied to the power supply terminal 11, the NMOS transistor 17 functions as a diode, and the gate of the clamping NMOS transistor 16 is biased by the diode and the resistance element 18 to be turned on. Can be protected.

  If the gate oxide film thickness of the NMOS transistor 17 is the same as that of the NMOS transistors 15 and 16, snapback is performed at a voltage V2 higher than the gate breakdown voltage Vox. Therefore, before the ESD protection circuit 10 operates, the internal circuit 13 is destroyed and cannot provide sufficient protection.

[Second Embodiment]
FIG. 4 shows an ESD protection circuit according to the second embodiment of the present invention. The ESD protection circuit 20 is provided between an output terminal (output pad) 21 and a reference potential terminal (VSS pad) 22 in the CMOS integrated circuit device, and protects the output buffer 23 from ESD applied to the output terminal 21. . The output buffer 23 is a CMOS inverter composed of a PMOS transistor 24 and an NMOS transistor 25 in this example, and operates with a voltage between the power supply terminal (VDD pad) 26 and the reference potential terminal 22. The output buffer 23 is supplied with a signal from an internal circuit and outputs a signal from the output terminal 21 to the outside of the chip.

  Similar to the ESD protection circuit 10 shown in FIG. 1, the ESD protection circuit 20 includes a clamp NMOS transistor 27, a trigger NMOS transistor 28, and a resistance element 29 as a load element. The drain of the NMOS transistor 28 is connected to the output terminal 21, and the gate and source are connected to one end of the resistance element 29. The other end of the resistance element 29 is connected to the reference potential terminal 22. The drain of the NMOS transistor 27 is connected to the output terminal 21, the gate is connected to a connection node between the NMOS transistor 28 and the resistance element 29, and the source is connected to the reference potential terminal 22.

  As shown in FIG. 5, the gate oxide film thickness Tox 28 of the trigger NMOS transistor 28 is thinner than the gate oxide film thickness Tox 25 of the NMOS transistor 25 constituting the output buffer 23. The snapback voltage of the triggering NMOS transistor 28 in the ESD protection circuit 20 is lower by ΔV2 than the snapback voltage of the NMOS transistor 25 constituting the output buffer 23. For this reason, when ESD is applied to the output terminal 21, the ESD protection circuit 20 operates before the output buffer 23.

  That is, when a positive ESD is applied to the output terminal 21, the trigger NMOS transistor 28 in the ESD protection circuit 20 always snaps before the NMOS transistor 25 constituting the output buffer 23 as shown in FIG. Back. For this reason, even when the size of the MOS transistors 24 and 25 as output drivers is small, it is possible to prevent the ESD current from flowing through the output buffer 23 and to suppress the breakdown due to ESD.

  On the other hand, when negative polarity ESD is applied to the output terminal 21, the NMOS transistor 28 functions as a diode, and the gate of the clamping NMOS transistor 27 is biased by this diode and the resistance element 29 so that the internal circuit 13 is turned on. Can protect.

  The snapback voltage Vt1 is controlled by adjusting the gate oxide film thickness of the trigger NMOS transistor 28. The NMOS transistor 28 can be designed so that the NMOS transistor 28 itself is not destroyed by adjusting the capacitance relationship with the clamping NMOS transistor 27 through which the ESD current flows. Further, the resistance element 29 has a resistance value that can turn on the NMOS transistor 27 after the NMOS transistor 28 snaps back and before the transistors 24 and 25 in the output buffer 23 are destroyed. In addition, the leakage current of the NMOS transistor 28 is set to a resistance value that has a voltage value that does not turn on the NMOS transistor 27.

  Furthermore, in the second embodiment, the case where the output buffer is protected from the ESD surge applied to the output terminal (output pad) has been described as an example. However, the input buffer from the ESD surge applied to the input terminal (input pad) has been described. It can be applied in the same way to protect Of course, the present invention can also be applied to the case where the input / output buffer is protected from an ESD surge applied to the input / output terminal (input / output pad).

[Third Embodiment]
FIG. 7 shows an ESD protection circuit according to the third embodiment of the present invention. This ESD protection circuit 30 is provided between a power supply terminal (VDD pad) 31 and a reference potential terminal (VSS pad) 32 in the CMOS integrated circuit device, and an internal circuit 33 is formed from the ESD applied to these terminals 31 and 32. Protect. The internal circuit 33 is a CMOS inverter composed of a PMOS transistor 34 and an NMOS transistor 35, for example, as in the first embodiment, and operates with the voltage between the terminals 31 and 32.

  The ESD protection circuit 30 includes a plurality of (four in this example) NMOS transistors 36-1 to 36-4 for clamping, an NMOS transistor 37 for triggering, and a resistance element 38 as a load element. The drain of the NMOS transistor 37 is connected to the power supply terminal 31, and the gate and source are connected to one end of the resistance element 38. The other end of the resistance element 38 is connected to the reference potential terminal 32. The drains of the NMOS transistors 36-1 to 36-4 are commonly connected to the power supply terminal 31, the gates are respectively connected to connection nodes between the NMOS transistor 37 and the resistance element 38, and the sources are respectively connected to the reference potential terminal 32. Connected to.

  The gate oxide film thickness of the NMOS transistors 36-1 to 36-4 is the same as the NMOS transistor 35 of the internal circuit 33, and the gate oxide film thickness of the NMOS transistor 37 is thinner than that of the NMOS transistor 35. The snapback voltage Vt1 of the NMOS transistor 37 is lower than the gate breakdown voltage Vox of the NMOS transistor 35 of the internal circuit 33. Further, the gate insulating film thickness of the NMOS transistor 35 is such that the snapback voltage Vt1 is higher than the gate breakdown voltage Vox. That is, for example, the MOS transistor is formed by a submicron process with a channel width of 130 nm or less.

  The snapback voltage Vt1 is controlled by adjusting the gate oxide film thickness of the trigger NMOS transistor 37. The NMOS transistor 37 is designed so that the NMOS transistor 37 itself is not destroyed by adjusting the capacitance relationship with the clamping NMOS transistors 36-1 to 36-4 through which ESD current flows. Further, the resistance element 29 can turn on the NMOS transistors 36-1 to 36-4 after the NMOS transistor 37 snaps back and before the transistors 34 and 35 in the internal circuit 33 are destroyed. Resistance value. In addition, the leakage current of the NMOS transistor 37 is set to a resistance value that has a voltage value that does not turn on the NMOS transistors 36-1 to 36-4.

  In the above configuration, when ESD is applied from the power supply terminal 31, the triggering NMOS transistor 37 first snaps back, and all the clamping NMOS transistors 36-1 to 36-4 operate simultaneously. Thus, the internal circuit 33 is protected. For this reason, as shown in FIG. 8, the current is concentrated on a specific protection element, the effective channel width of the protection operation is reduced and the breakdown voltage is lowered. However, the ESD breakdown voltage is kept in a linear relationship. High protection effect. In addition, the presence of the parasitic capacitances of the clamping NMOS transistors 36-1 to 36-4 makes the change in the ESD current value moderate, so that the internal circuit can be more effectively protected.

  On the other hand, when a negative ESD is applied to the power supply terminal 31, the NMOS transistor 37 functions as a diode, and the gate of the clamping NMOS transistors 36-1 to 36-4 is biased by this diode and the resistance element 38 to turn on. Therefore, the internal circuit 33 can be protected.

  In the third embodiment, the case where the internal circuit 33 is protected from the ESD surge applied to the power supply terminal 31 has been described as an example. However, the output buffer is protected from the surge applied to the output terminal (output pad). When protecting the input buffer from a surge applied to the input terminal (input pad), it can be applied to both protecting the input buffer from a surge applied to the input / output terminal (input / output pad). Of course.

  As described above, according to the embodiments of the present invention, the snapback voltage Vt1 of the transistor and the gate breakdown voltage Vox of the internal circuit have a relationship of Vox <Vt1, for example, the sub-micron of the MOS transistor having a channel width of 130 nm or less. Even in a CMOS integrated circuit device formed by the process, the internal circuit can be effectively protected if the relationship between the snapback voltage Vt1 of the trigger transistor and the gate breakdown voltage Vox of the internal circuit is Vox> Vt1. .

  In each of the above embodiments, the snapback voltage Vt1 can always be lower than that of an internal circuit such as an output buffer. Therefore, there is no competition with other transistors, and only the protection element can be operated efficiently.

  Furthermore, in each of the above embodiments, since the snapback characteristics of the trigger NMOS transistor and the bias voltage are directly applied to the gate of the clamp NMOS transistor using a resistance element to turn on, the protection element size and the ESD protection capability are linear. You can keep in a relationship. Therefore, it is easy to effectively use the size of the ESD protection circuit, which is suitable for size optimization.

  Although the present invention has been described using the first to third embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention in the implementation stage. It is possible. Each of the above embodiments includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in each embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When at least one of the effects is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

1 is a circuit diagram showing an ESD protection circuit according to a first embodiment of the present invention. FIG. 3 is a characteristic diagram illustrating a relationship among a gate oxide film thickness, a gate breakdown voltage, and a snapback voltage for explaining element characteristics of an NMOS transistor constituting the ESD protection circuit shown in FIG. FIG. 3 is a voltage-current characteristic diagram illustrating a relationship among a power supply voltage, a gate breakdown voltage, and a snapback voltage for explaining the operation of the ESD protection circuit illustrated in FIG. 1. The circuit diagram which shows the ESD protection circuit which concerns on the 2nd Embodiment of this invention. FIG. 5 is a characteristic diagram illustrating a relationship between a gate oxide film thickness and a snapback voltage for explaining element characteristics of an NMOS transistor constituting the ESD protection circuit shown in FIG. 4. FIG. 5 is a voltage-current characteristic diagram illustrating a snapback voltage of an NMOS transistor for explaining an operation of the ESD protection circuit illustrated in FIG. 4. The circuit diagram which shows the ESD protection circuit which concerns on the 3rd Embodiment of this invention. FIG. 8 is a channel width-withstand voltage characteristic diagram for explaining the channel width dependence of the withstand voltage in the clamping NMOS transistor in the ESD protection circuit shown in FIG.

Explanation of symbols

  10, 20, 30 ... ESD protection circuit, 11, 26, 31 ... power supply terminal (VDD pad), 12, 22, 32 ... reference potential terminal (VSS pad), 13, 33 ... internal circuit, 14, 24, 34 ... PMOS transistor, 15, 25, 35 ... NMOS transistor, 17, 28, 37 ... NMOS transistor for trigger, 16, 27, 36-1 to 36-4 ... NMOS transistor for clamping, 18, 29, 38 ... resistance element , 21 ... output terminal (output pad), 23 ... output buffer.

Claims (5)

A clamp oxide having a gate oxide film having the same thickness as the NMOS transistor constituting the internal circuit, one end of the current path connected to the first terminal and the other end of the current path connected to the second terminal. 1 NMOS transistor,
The trigger has a gate oxide film thinner than the first NMOS transistor, one end of the current path is connected to the first terminal, and the other end and gate of the current path are connected to the gate of the first NMOS transistor. 2 NMOS transistors,
An ESD protection circuit comprising: a load element having one end connected to the gate of the first NMOS transistor and the other end connected to the second terminal.   The snapback voltage of the second NMOS transistor is lower than the snapback voltages of the NMOS transistor and the first NMOS transistor constituting the internal circuit and higher than a power supply potential applied to the first terminal. The ESD protection circuit according to claim 1. The potential applied to the first terminal is a power supply potential, the potential applied to the second terminal is a ground potential,
The ESD protection circuit according to claim 1, wherein the internal circuit includes an inverter. A third terminal connected to the internal circuit;
The potential applied to the first terminal is a power supply potential, the potential applied to the second terminal is a ground potential,
The ESD protection circuit according to claim 1, wherein the internal circuit includes a buffer circuit, and inputs or outputs a signal from the third terminal. It has a gate oxide film of the same thickness as the NMOS transistor constituting the internal circuit, one end of each current path is commonly connected to the first terminal, and the other end of each current path is commonly connected to the second terminal A plurality of clamped first NMOS transistors;
The gate oxide film is thinner than the plurality of first NMOS transistors, one end of the current path is connected to the first terminal, and the other end and gate of the current path are commonly connected to the gates of the plurality of first NMOS transistors. A second NMOS transistor for triggering;
An ESD protection circuit comprising: a load element having one end commonly connected to the gates of the plurality of first NMOS transistors and the other end connected to the second terminal.

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