JP2008098541A - Solid-state image sensing device and manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image sensing device and its manufacturing method for restricting a decrease in the amount of saturation charges even when downscaling the element. <P>SOLUTION: An n-type charge storage region 14 is formed in a p-type well region 16, which was formed on an n-type semiconductor substrate 11. In addition a p-type gate region 15a on the charge storage region 14 and an n-type read out region 15b arranged on the inner side of the p-type gate region are provided. The charge accumulated in the charge storage region 14 is read by the read out region 15b, which was connected to the charge storage region 14, by applying voltage to the gate region 15a and thereby depleting the read out region 15b. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly to a solid-state imaging device and a manufacturing method thereof that can suppress a decrease in the amount of saturated charge even when the device is miniaturized.

  A solid-state imaging device using an amplifying MOS sensor amplifies a signal detected by a photodiode for each pixel by a transistor, and has a characteristic of high sensitivity.

  8A and 8B are diagrams showing a general configuration of a conventional solid-state imaging device, FIG. 8A is a plan view thereof, and FIG. 8B is along VIIIb-VIIIb. It is sectional drawing.

  As shown in FIGS. 8A and 8B, in the pixel region defined by the separation region 102 formed in the P-type silicon substrate 101, the charge storage region 103 made of an N-type diffusion layer and the charge storage region 103 are formed. A transfer gate 104 for transferring the stored charge and a floating diffusion (FD) 105 for storing the transferred charge are formed.

  In recent years, in order to highly integrate a large number of pixels, miniaturization of solid-state imaging elements has been promoted, but due to the reduction in the area of the charge storage region 103 with the miniaturization of the pixel size, There was a problem that the amount of saturation charge was reduced.

In order to suppress the decrease of the saturation charge amount, it is effective to increase the impurity concentration of the charge storage region 103 or to increase the diffusion depth of the charge storage region 103. There is a problem that the potential of the region becomes high and an afterimage is likely to occur, and in the latter case, a problem of color mixing occurs due to charge movement between adjacent pixels (see, for example, Patent Document 1).
JP 2003-142673 A

  As described above, various technical difficulties are involved in suppressing the decrease in the amount of saturated charge accompanying the reduction in pixel size. In addition, since the reduction of the saturation charge amount is essentially due to the volume reduction of the charge storage region, it is difficult to achieve a fundamental solution.

  The present invention has been made in view of the above problems, and a main object thereof is to provide a solid-state imaging device having a completely new configuration that can suppress a decrease in the amount of saturated charges even when the device is miniaturized. There is to do.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a gate region having a conductivity type opposite to the charge accumulation region on the charge accumulation region, and a readout having the same conductivity type as the charge accumulation region inside the gate region. A configuration is employed in which a region is provided and control is performed to read out the charges accumulated in the charge accumulation region to the reading region by a voltage applied to the gate region.

  That is, a solid-state imaging device according to the present invention includes a first conductivity type semiconductor substrate, a second conductivity type charge accumulation region formed in the semiconductor substrate, and a first conductivity type charge accumulation region formed on the charge accumulation region. A gate region and a second conductivity type readout region disposed inside the gate region and connected to the charge storage region, and the charge stored in the charge storage region by the voltage applied to the gate region, It is characterized by performing control to read to the reading area.

  According to such a configuration, in place of the transfer gate and the floating diffusion, which are conventionally provided adjacent to the charge storage region as a control means for reading the stored charge, the gate region and the read region above the charge storage region. By providing the readout control means consisting of the above, it is possible to form a charge accumulation region in the entire pixel region. Thereby, it is possible to suppress a decrease in the saturation charge amount even when the element is miniaturized.

  In the above structure, it is preferable that the charge accumulated in the charge accumulation region is read out to the readout region by applying a predetermined potential to the gate region to deplete the readout region. Further, it is preferable that the impurity concentration in the readout region is lower than the impurity concentration in the charge storage region. Thereby, the charge accumulated in the charge accumulation region can be reliably read out to the readout region.

  In the method of manufacturing a solid-state imaging device according to the present invention, a first conductivity type first impurity is ion-implanted into a first conductivity type semiconductor substrate to form a charge accumulation region having a peak impurity concentration distribution inside the substrate. A step of ion-implanting a second impurity of the second conductivity type into the surface of the charge storage region to form a read region having a predetermined impurity concentration above the charge storage region, and an upper part of the charge storage region And a step of selectively ion-implanting a third impurity of the first conductivity type to form a gate region surrounding the readout region on the charge storage region.

  According to the solid-state imaging device according to the present invention, since a charge accumulation region (photodiode) can be formed in the entire pixel region, it is possible to suppress a decrease in the saturation charge amount even if the device is miniaturized.

  Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of simplicity.

(First embodiment)
1A and 1B are diagrams schematically showing the configuration of the solid-state image sensor 10 according to the first embodiment of the present invention. FIG. 1A is a plan view of the solid-state image sensor 10. 1 (b) is a cross-sectional view taken along line Ib-Ib in FIG. 1 (a).

  As shown in FIGS. 1A and 1B, the basic configuration of the solid-state imaging device 10 in the present embodiment is an N-type in a P-type well region 16 formed in an N-type semiconductor substrate 11. The charge storage region 14 is formed, and a P-type gate region 15a and an N-type read region 15b arranged inside the P-type gate region 15a are further provided on the charge storage region 14. The charges accumulated in the charge accumulation region 14 are read out to the readout region 15b connected to the charge accumulation region 14 by the voltage applied to the gate region 15a.

  In order to surely read out the accumulated charge, it is preferable to completely deplete the readout region 15b by applying a predetermined potential to the gate region 15a, and the impurity concentration in the readout region 15b It is preferable that the impurity concentration is lower than that of the accumulation region 14.

  Here, the readout control of the accumulated charge is performed as follows. First, at the time of charge accumulation, the potential of the gate region 15a is set lower than the potential of the readout region 15b. For example, when the read region 15b is fixed to 0 V and a negative voltage is applied to the gate region 15a, the depletion layer does not reach the read region 15b, so that no current flows and charges are accumulated in the charge accumulation region 14. Next, at the time of charge reading, the potential of the gate region 15a is made higher than the potential of the reading region 15b. For example, when the read region 15b is fixed to 0 V and a positive voltage is applied to the gate region 15a, the depletion layer extends to the read region 15b, and the charge accumulated in the charge accumulation region 14 is read to the read region 15b.

  According to the configuration of the solid-state imaging device 10 shown in FIGS. 1A and 1B, in the conventional solid-state imaging device shown in FIGS. 8A and 8B, charge accumulation is performed as control means for reading the accumulated charge. Since the transfer gate 104 and the floating diffusion 105 provided adjacent to the region 103 can be omitted, the charge accumulation region 14 can be expanded over the entire pixel region. Thereby, it is possible to suppress a decrease in the saturation charge amount even when the element is miniaturized.

  Further, the configuration of the solid-state imaging device 10 in this embodiment will be described in detail with reference to FIGS. 1 (a) and 1 (b).

As shown in FIG. 1B, in the pixel region 12 of the semiconductor substrate 11 made of N-type silicon, a P-type well region 16 made of an impurity diffusion layer of boron (B) and an impurity diffusion of arsenic (As). An N-type charge accumulation region 14 having a peak concentration of about 1E17 to 1E18 / cm ³ and a depth of about 0.1 to 1 μm is formed. Furthermore, a P-type gate region 15a having a peak concentration of about 5E17 to 3E18 / cm ³ and a depth of about ³⁰ to 80 nm composed of an impurity diffusion layer of B and a gate region 15a are surrounded by the upper portion of the charge storage region 14, and An N-type readout region 15b having a peak concentration of about 1E15 to 1E16 / cm ³ and a depth of about ³⁰ to 80 nm made of a phosphorus (P) impurity diffusion layer formed continuously from the charge storage region 14 is formed. Yes.

  An interlayer insulating film 19 is formed on the surface of the semiconductor substrate 11, and a gate electrode 20 connected to the gate region 15a and a read electrode 21 connected to the read region 15b are formed. Note that the readout region 15b can be formed at an arbitrary position in the pixel region 12. However, in consideration of the routing of the wiring from the readout electrode 21, as shown in FIG. It is preferable that it is formed in a peripheral part. Further, the gate electrode 20 can also be formed at an arbitrary position in the pixel region 12, and may be provided, for example, at a peripheral corner of the pixel region 12 as shown in FIG.

  In addition, in the element isolation region 13, an insulating film 13 c is embedded in a groove portion formed in the semiconductor substrate 11 to a depth of about 0.2 to 1 μm via a base protective film 13 b. A P-type white defect suppressing region 17 is formed on the semiconductor substrate 11 in contact with the side surface, and an N-type isolation diffusion layer 18 is formed on the semiconductor substrate 11 in contact with the bottom of the element isolation region 13.

  Next, a method for manufacturing the solid-state imaging device 10 according to the present embodiment will be described with reference to FIGS. 2 (a) to 3 (c). Here, FIG. 2A to FIG. 3C show process cross-sectional views along Ib-Ib in FIG.

  First, as shown in FIG. 2A, a hard mask 23 made of an oxide film having an opening to be an element isolation region 13 is formed on a semiconductor substrate 11 made of an N-type silicon substrate. The groove 13a is formed in Thereafter, after forming a base protective film 13b on the surface of the groove 13a, ions of P-type impurities and boron are ion-implanted into the pixel region 12 in the semiconductor substrate 11 from the side surface of the groove 13a, and P is formed on the side surface of the groove 13a. The mold white scratch suppression region 17 is formed.

  Next, as shown in FIG. 2B, phosphorus (P) is ion-implanted into the bottom of the groove 13a at a substantially vertical angle, and an N-type for separating a P-type well region to be formed thereafter. An isolation diffusion layer 18 is formed.

  Next, as shown in FIG. 2C, after an insulating film is formed on the entire surface of the semiconductor substrate 11, the insulating film on the hard mask 23 is polished and removed by CMP, and then the hard mask 23 is removed. As a result, the element isolation region 13 in which the insulating film 13c is embedded in the trench 13a via the base protective film 13b is formed. Thereafter, boron (B) is ion-implanted into the pixel region 12 in the semiconductor substrate 11 to form a P well region 16.

Next, as shown in FIG. 3A, an N-type impurity, for example, arsenic (As) is ion-implanted into the pixel region 12 in the semiconductor substrate 11 using a resist mask (not shown), and the charge is charged. The accumulation region 14 is formed. At this time, the charge storage region 14 is formed at a depth of about 0.05 to 0.15 μm from the surface of the semiconductor substrate 11 so as to have a peak concentration of about 1E17 to 1E18 / cm ³ . As a result, the charge storage region 14 is surrounded by the P well region 16 provided on the bottom surface side and the white flaw suppression region 17 provided on the side surface side. Subsequently, an N-type impurity such as phosphorus (P) is ion-implanted into the surface of the charge storage region 14 to form a read region 15b. At this time, the read region 15b is adjusted to have an impurity concentration of about 1E15 to 1E16 / cm ³ .

Next, as shown in FIG. 3B, for example, B is ion-implanted into the pixel region 12 of the semiconductor substrate 11 using a resist mask (not shown), and an impurity of about 5E17 to 3E18 / cm ^3. A P-type gate region 15a having a concentration is formed. As a result, a desired readout region 15b surrounded by the gate region 15a and connected to the charge storage region 14 is formed.

  Thereafter, after the ion-implanted impurity is activated by heat treatment, an interlayer insulating film 19 is deposited on the semiconductor substrate 11 as shown in FIG. 3C, and then a gate region is formed in the interlayer insulating film 19. The gate electrode 20 connected to 15a and the readout electrode 21 connected to the readout region 15b are formed to complete the solid-state imaging device.

  In the step shown in FIG. 2B, when the element isolation region 13 becomes deep, phosphorus (P) is ion-implanted into the bottom of the groove 13a at a substantially vertical angle to form the N-type isolation diffusion layer 18. When forming, phosphorus may be ion-implanted also into the side surface of the groove 13a. In order to prevent this, for example, as shown in FIG. 4, by forming a side wall protective film 13d as an implantation mask on the side surface of the groove 13a, phosphorus can be ion-implanted only at the bottom of the groove 13a.

(Second Embodiment)
5A and 5B are diagrams schematically showing the configuration of the solid-state image sensor 10 according to the second embodiment of the present invention. FIG. 5A is a plan view of the solid-state image sensor 10. FIG. 5B is a cross-sectional view taken along Vb-Vb in FIG. FIGS. 5A and 5B have the same configuration as that of FIGS. 1A and 1B except that the configuration of the gate electrode 20 is different.

  As described above, since the gate region 15a is formed over almost the entire surface of the pixel region 12 excluding the readout region 15b, the gate electrode 20 can be formed at an arbitrary position in the pixel region 12. Since the gate electrode 20 is made of metal, in order not to block light incident on the pixel region 12 as much as possible, for example, as shown in FIG. Is preferred.

  On the other hand, if the charge accumulation region 14 becomes deep in order to increase the saturation charge amount, the charge accumulation region 14 becomes difficult to be completely depleted when reading the charge, and as a result, an afterimage is likely to occur. In such a case, as shown in FIG. 5A, the gate electrode 20 is formed on the periphery of the gate region 15a, in other words, in a ring shape so as to surround the pixel region 12, thereby accumulating charge. Full depletion of the region 14 can be facilitated.

FIGS. 6A and 6B are diagrams schematically showing a configuration of the solid-state image sensor 10 in a modification of the second embodiment of the present invention. FIG. 6A is a plan view of the solid-state image sensor 10. FIG. 6 and FIG. 6B are cross-sectional views along VIb-VIb in FIG. FIGS. 6A and 6B have the same configuration as that of FIGS. 1A and 1B except that the configurations of the gate electrode 20 and the interlayer insulating film 19 are different.
As the elements are miniaturized, the wiring layer is also multilayered, and incident light is diffusely reflected by the wiring layer, so that light is easily mixed into adjacent pixel regions. As a result, the problem of color mixing tends to occur. In such a case, as shown in FIGS. 6A and 6B, the ring-shaped gate electrode 20 is formed higher than the readout electrode 21 on the periphery of the gate region 15a, thereby adjacent pixel regions. It is possible to prevent light from being mixed in.

  Next, a method for manufacturing the solid-state imaging device shown in FIGS. 5A and 5B and FIGS. 6A and 6B will be described with reference to FIGS.

  FIG. 7A is a cross-sectional view showing a state in which the charge storage region 14, the gate region 15a, and the readout region 15b are formed on the semiconductor substrate 11, and FIGS. 2A to 2C in the first embodiment. It is formed by the same method as the process shown in 3 (b).

  Thereafter, as shown in FIG. 7B, after depositing an interlayer insulating film 19 on the semiconductor substrate 11, a gate electrode 20 and a readout electrode 21 are formed by selective etching and metal deposition. At this time, the gate electrode 20 is formed on the periphery of the pixel region 12 including the gate region 15a as shown in FIG.

  When the solid-state imaging device shown in FIGS. 6A and 6B is formed, a second interlayer insulating film 19a is further formed on the interlayer insulating film 19 as shown in FIG. 7C. Then, the gate electrode 20a stacked in connection with the gate electrode 20 is formed by selective etching and metal deposition. At this time, in order to easily lead out the wiring from the readout electrode 21 to the outside of the pixel region, the gate electrode 20 is not formed in a completely closed ring shape as shown in FIG. May be formed in the shape of a ring separated from each other.

  As mentioned above, although this invention was demonstrated by suitable embodiment, such description is not a limitation matter and of course various modifications are possible. For example, in the above embodiment, the charge accumulation region is formed in the well region, but the charge accumulation region may be formed in the semiconductor substrate. Moreover, the polarity of the impurity of each structure specifically shown in the said embodiment is not limited to it, Of course, the effect of this invention can be acquired even if the polarity of the impurity of each structure is reversed.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state image sensor which can suppress the reduction | decrease of the amount of saturation charges also with respect to refinement | miniaturization of an element, and its manufacturing method can be provided.

It is the figure which showed the structure of the solid-state image sensor in the 1st Embodiment of this invention, (a) is the top view, (b) is sectional drawing along Ib-Ib of Fig.1 (a). (A)-(c) is process sectional drawing which showed the manufacturing method of the solid-state image sensor in the 1st Embodiment of this invention. (A)-(c) is process sectional drawing which showed the manufacturing method of the solid-state image sensor in the 1st Embodiment of this invention. It is process sectional drawing which showed the manufacturing method of the solid-state image sensor in the modification of the 1st Embodiment of this invention. It is the figure which showed the structure of the solid-state image sensor in the 2nd Embodiment of this invention, (a) is the top view, (b) is sectional drawing along Vb-Vb of Fig.5 (a). It is the figure which showed the structure of the solid-state image sensor in the modification of the 2nd Embodiment of this invention, (a) is the top view, (b) is sectional drawing along VIb-VIb of Fig.6 (a). It is. (A)-(c) is process sectional drawing which showed the manufacturing method of the solid-state image sensor in the 2nd Embodiment of this invention. It is sectional drawing which showed the structure of the conventional solid-state image sensor, (a) is the top view, (b) is sectional drawing along VIIIb-VIIIb of Fig.8 (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Solid-state image sensor 11 Semiconductor substrate 12 Pixel area 13 Element isolation area 13a Groove part 13b Base protective film 13c Insulating film 13d Side wall protective film 14 Charge storage area 15a Gate area 15b Read-out area 16 Well area 17 White defect suppression area 18 Separation diffusion layer 19 , 19a Interlayer insulating film 20, 20a Gate electrode 21 Read electrode

Claims (9)

A first conductivity type semiconductor substrate;
A charge storage region of a second conductivity type formed in the semiconductor substrate;
A first conductivity type gate region formed on the charge storage region;
A second conductivity type readout region disposed inside the gate region and connected to the charge storage region;
A solid-state imaging device, wherein a charge applied to the charge storage region is controlled to be read out to the readout region by a voltage applied to the gate region.   The solid-state imaging device according to claim 1, wherein a charge accumulated in the charge accumulation region is read out to the read region by applying a predetermined potential to the gate region to deplete the read region.   3. The solid-state imaging device according to claim 1, wherein an impurity concentration of the readout region is lower than an impurity concentration of the charge storage region.   4. The solid-state imaging device according to claim 1, wherein the readout region is connected to the charge accumulation region at a portion around the charge accumulation region.   5. The solid-state imaging device according to claim 1, wherein a gate electrode that applies a voltage to the gate region is formed in a ring shape on a periphery of the gate region. Ion implantation of a second conductivity type first impurity into a first conductivity type semiconductor substrate to form a charge storage region having a peak impurity concentration distribution inside the substrate;
A step of ion-implanting a second impurity of a second conductivity type above the charge storage region to form a read region having a predetermined impurity concentration on the surface of the charge storage region;
And a step of selectively ion-implanting a third impurity of the first conductivity type above the charge storage region to form a gate region surrounding the readout region on the charge storage region. A method for manufacturing a solid-state imaging device.   7. The method of manufacturing a solid-state imaging device according to claim 6, wherein a concentration of the second impurity ion-implanted in the readout region is lower than a peak concentration of the first impurity ion-implanted in the charge storage region. .   The method for manufacturing a solid-state imaging device according to claim 6, further comprising a step of forming a gate electrode in a ring shape on the periphery of the gate region. A step of forming an interlayer insulating film on the semiconductor substrate;
The method for manufacturing a solid-state imaging element according to claim 6, wherein the gate electrode is formed in the interlayer insulating film.

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