JP2008097098A - Information processor and interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor and an interface circuit for effectively reducing latency when a bus mater performs access to a peripheral module such as a register. <P>SOLUTION: This information processor is provided with a bus master (1100) operating synchronously with a first clock signal; a peripheral module (1200) operating synchronously with a second clock signal; and a dual port RAM (1210) as a storage means having a first access port for transferring data with a bus master synchronously with the first clock signal and a second access port for transferring data with the peripheral module synchronously with the second clock signal, wherein data transfer between the bus master (1100) and the peripheral module (1200) is executed via the dual port RAM. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information processing apparatus and an interface circuit using a multiport RAM.

  Conventionally, in an information processing apparatus such as a system LSI, a bus master such as a CPU and peripheral modules such as registers are connected by a bus, and data transfer is performed via this bus. In general, since the operation clock frequency of the bus master is different from the operation clock frequency of the peripheral modules, it is necessary to synchronize the data signals when performing data transfer between them.

  FIG. 8 shows a configuration example of an information processing apparatus having a function of synchronizing the above-described data signal. As shown in the figure, the bus master 810 and the peripheral module 820 are connected via a bus 830, and the register unit 822 in the peripheral module 820 is connected to the bus 830 via a synchronization circuit 821.

  According to this information processing apparatus, a data signal sent from the bus master 810 to the peripheral module 820 via the bus 830 is a data signal synchronized with the operation clock signal PCLK of the register unit 822 by the synchronization circuit 821 in the peripheral module 820. And is supplied to the register unit 822. By providing the synchronization circuit 821 in this manner, data transfer between the bus master 810 operating at different clock frequencies and the register unit 822 is enabled.

This will be described in more detail with reference to FIGS.
FIG. 9 shows a detailed configuration of an information processing apparatus according to the related art. The bus master 9100 and the peripheral module 9200 shown in FIG. 9 correspond to the bus master 810 and the peripheral module 820 shown in FIG. 8, respectively, and the synchronization circuits 9211, 9221, 9240, 9250, and 9260 shown in FIG. 9 are shown in FIG. Corresponding to the synchronization circuit 821, the register 9230 shown in FIG. 9 corresponds to the register 822 shown in FIG.

  Here, the state machine 9210 shown in FIG. 9 functions as an interface to the bus master 9100 and operates in synchronization with the operation clock signal SCLK of the bus master 9100. The state machine 9220 functions as an interface to the register 9230 and operates in synchronization with the operation clock signal PCLK of the register 9230.

  Between the state machine 9210 and the state machine 9220, various control signals corresponding to the contents of data transfer from the bus master 9100 to the register 9230 are transmitted by handshaking. In order to enable transmission of this control signal, one state machine 9210 includes a synchronization circuit 9211 for synchronizing signals input from the state machine 9220, and the other state machine 9220 includes the state machine 9210. A synchronization circuit 9221 is provided for synchronizing input signals.

Next, the operation of the information processing apparatus according to the above-described prior art will be described with reference to FIGS. 10 is a state transition diagram of the state machine 9210 and the state machine 9220. FIGS. 11 and 12 are timing charts of a write operation and a read operation from the bus master 9100 to the register unit 9230, respectively.
In the description of the operation, refer to FIG. 10 for the state transition of each state machine, and appropriately refer to FIGS. 11 and 12 for the operation at each time.

First, the write operation will be described with reference to FIGS.
When a preset signal is input to the state machine 9210 in the peripheral module 9200, the state machine 9210 makes a state transition to an idle state SIDLE waiting for access from the bus master 9100.

  From this idle state SIDLE, the bus master 9100 starts a write transaction. When the write signal WRN is set to low level at time t1 and the chip select signal CSN is set to low level, the state machine 9210 that inputs this detects the write transaction. Then, the state transitions to the wait state SWWAIT (FIG. 10; B), and the wait signal WAIT is asserted to the high level at time t2 (FIG. 11; B). This puts a wait on the bus master 9100.

  On the other hand, when the state machine 9220 detects that the state machine 9210 transitions to the wait state SWWAIT at time t3, the state machine 9220 transitions to the write state PWRITE at time t4, which is two clocks after time t3 (FIGS. 10 and 11; C) Then, at time t6 after one clock, the synchronized write data WDATA is written to the register 9230, and the state transitions to the wait state PWAIT (FIG. 11; D). By this operation, the setup time tSU of the write data WDATA for the address signal ADDR is ensured.

  On the other hand, when the state machine 9210 detects that the state machine 9220 transitions to the write state PWRITE (or wait state PWAIT) at time t5, the state machine 9210 transitions from the wait state SWWAIT to the write state SWRITE in two clocks (FIGS. 10 and 10). 11; E), at time t7, the wait signal WAIT is negated to a low level (FIG. 11; F). By this operation, the hold time tHD of the write data WDATA for the address signal ADDR is ensured.

When the bus master 9100 detects that the wait signal WAIT is negated to the low level, the bus master 9100 negates the write signal WRN and the chip select signal CSN to the high level at time t8 (G in FIG. 11), and ends the write transaction.
Thereafter, when the state machine 9220 detects that the state machine 9210 is not in the wait state SWWAIT at time t9, the state machine 9220 transitions from the wait state PWAIT to the idle state PIDLE at time t10 two clocks later (FIGS. 10 and 11). H), preparing for the next transaction.

Next, the read operation will be described with reference to FIGS.
Similarly to the above, it is assumed that the state machine 9210 in the peripheral module 9200 is in the idle state SIDLE in the initial state.

  From this state, the bus master 9100 starts a read transaction, and when the read signal RDN and the chip select signal CSN are asserted to a low level at time t1, the state machine 9210 detects the read transaction and enters the wait state SRWAIT at time t2. State transition is made (FIGS. 10 and 12; a), and the wait signal WAIT is asserted to a high level (FIG. 12; b). As a result, the bus master 9100 is put into a wait state for the peripheral module 9200.

  On the other hand, when the state machine 9220 detects that the state machine 9210 has transitioned to the wait state SWWAIT at time t3, the state machine 9220 transitions to the read state PREAD at time t4 after two clocks (FIGS. 10 and 12; c). The read data RDATA is fetched from the register 9230 to the flip-flop 9280, and then the state transitions to the wait state PWAIT (FIG. 10; h). By the operation so far, the setup time tSUA of the address signal ADDR is secured.

  On the other hand, when the state machine 9210 detects that the state machine 9220 transitions to the wait state PWAIT at time t5 thereafter, the state machine 9210 transitions to the read state SREAD at time t7 two clocks later (FIGS. 10 and 12). D) The wait signal WAIT is negated to a low level (FIG. 12; e). The read data RDATA is output from the peripheral module 9200 to the bus in synchronization with the clock signal SCLK at time t6. This operation secures the setup time tSUD for the read data RDATA.

When detecting that the wait signal WAIT is negated to the low level, the bus master 9100 negates the read signal RDN and the chip select signal CSN to the high level at time t9 (FIG. 12; f), and ends the read transaction.
On the other hand, when the state machine 9220 detects that the state machine 9210 is not in the wait state SRWAIT at time t8, the state machine 9220 transitions from the wait state PWAIT to the idle state PIDLE at time t10 two clocks later (FIG. 12; g). Prepare for the next transaction.
Japanese Patent Laid-Open No. 9-044395

  By the way, in general, even if a peripheral module is connected to a bus master via a high-speed bus, if the peripheral module is low speed, many cycles are spent for one data transfer to the peripheral module. Therefore, there is a problem that a lot of latency occurs when the bus master accesses a low-speed peripheral module, and the meaning of speeding up the bus is lost.

  Speaking of the information processing apparatus according to the above-described prior art, there are two main causes for the increase in the latency. One is that an asynchronous clock signal PCLK different from the bus operation clock signal SCLK is used as the operation clock signal of the peripheral module. Another is that the operation clock frequency of the peripheral module is lower than the operation clock frequency of the bus. In any case, the delay time required for data synchronization when transferring data between the bus master and the peripheral module and the setup / hold time of the data increase the latency.

  As a result of the occurrence of latency as described above, the write operation shown in FIG. 11 requires seven wait cycles from time t2 to time t6, and the read operation shown in FIG. 12 from time t2 to time t6. 6 wait cycles are required, the latency is increased by that amount, and the start of the next transaction is delayed.

  In addition, as in the above-described prior art, if the peripheral module is designed so that the register is operated by the clock signal for the bus master only when the bus master accesses the register in the peripheral module, the above-described latency problem can be solved. It can be avoided. However, recently, peripheral modules are designed on the premise that they are applied to various products. Therefore, if they are designed specifically for a specific system, the versatility of the peripheral modules is impaired. For this reason, even a register is usually designed to be synchronized with a clock signal for a peripheral module, and thus the above problem still exists.

  The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an information processing apparatus and an interface circuit capable of effectively reducing latency when a bus master accesses a peripheral module containing a register or the like. And

  An information processing apparatus according to the present invention includes a bus master that operates in synchronization with a first clock signal, a peripheral module that operates in synchronization with a second clock signal, and the bus master in synchronization with the first clock signal. Storage means having a first access port for transferring data and a second access port for transferring data to and from the peripheral module in synchronization with the second clock signal, via the storage means And an interface circuit that performs data transfer between the bus master and the peripheral module.

  In the information processing apparatus, for example, the interface circuit generates a first control signal to be supplied to the first access port based on an access from the bus master, and the access from the bus master is a write operation. A first state machine that generates a flag indicating that the access has occurred, a flag register that stores the flag, a flag search circuit that searches for a flag stored in the flag register, and a search result by the flag search circuit And a second state machine for generating a second control signal to be supplied to the second access port.

    In the information processing apparatus, for example, the peripheral module includes a plurality of first registers, the flag register includes a plurality of second registers corresponding to the plurality of first registers, and the flag search circuit includes: An address signal for designating a register corresponding to the first register in which the flag is stored among the plurality of second registers is output.

  In the information processing apparatus, for example, the flag search circuit cyclically generates a count value corresponding to each address of the plurality of second registers and supplies the count value to the peripheral module and the storage unit, and the count A value is synchronized with the first clock signal and supplied to the flag register as a flag pointer, and a register pointer indicating that the flag is stored in the flag register designated by the flag pointer is set to the second clock signal. And a comparator for comparing the register pointer synchronized with the synchronization circuit with the count value and supplying the comparison result to the second state machine. In the second state machine, the comparison result indicates that the register pointer matches the count value. If you, and wherein the generating and outputting a control signal related to the read operation as said second control signal.

  In the information processing apparatus, for example, each of the plurality of second registers includes a register that stores a flag indicating a type of access from the bus master, and a register that stores a flag indicating that the bus master has accessed The information processing apparatus according to any one of claims 1 to 4, wherein the information processing apparatus comprises:

  In the information processing apparatus, for example, the first and second state machines lock the other of the first and second state machines when one of the first and second state machines accesses the storage unit. It is characterized by making a state transition to a state.

  In the information processing apparatus, for example, the storage unit includes a multi-port RAM including a plurality of access ports as the second access port, and the plurality of access ports of the multi-port RAM include the peripheral module. A plurality of modules are connected to each other.

  An interface circuit according to the present invention is an interface circuit that performs data transfer between a bus master that operates in synchronization with a first clock signal and a peripheral module that operates in synchronization with a second clock signal. A first access port for transferring data to and from the bus master in synchronization with a clock signal; and a second access port for transferring data to and from the peripheral module in synchronization with the second clock signal. A storage means and a first control signal to be supplied to the first access port based on an access from the bus master, and a flag indicating that the access has occurred when the access from the bus master is a write operation A generated first state machine, a flag register for storing the flag, and the flag register A configuration of an interface circuit comprising: a flag search circuit that searches for a flag stored in the second search machine; and a second state machine that generates a second control signal to be supplied to the second access port based on a search result by the flag search circuit Have

  According to the present invention, data transfer between a bus master and a peripheral module via a storage means having a first access port for receiving access from the bus master and a second access port for receiving access from the peripheral module Thus, the latency when the bus master accesses a peripheral module such as a register can be effectively reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a schematic configuration of an information processing apparatus according to an embodiment of the present invention. In the figure, reference numeral 1100 denotes a bus master such as a CPU that operates in synchronization with a bus clock signal (first clock signal) SCLK, and reference numeral 1200 operates in synchronization with a peripheral clock signal (second clock signal) PCLK. Indicates peripheral modules to be used. The bus master 1100 and the peripheral module 1200 are connected to each other via a bus 1300.

  The peripheral module 1200 provides a register function to the bus master 1100, and includes a dual port RAM 1210, which is a kind of multi-port RAM, and a register group 1220. The register group 1220 includes a plurality of registers RA to RZ. Is done. The dual port RAM 1210 includes data storage areas MA to MZ corresponding one-to-one with the plurality of registers RA to RZ, and all the values of the registers RA to RZ are stored in the data storage areas MA to MZ. That is, the dual port RAM 1210 functions as a mirror circuit that stores the mirror values of the registers RA to RZ.

  The dual port RAM 1210 also functions as an interface circuit between the bus master 1100 and the register group 1220. As described in detail below, the dual port RAM 1210 is connected between the bus master 1100 and the register group 1220 via the dual port RAM 1210. Data transfer is performed.

FIG. 2 shows a detailed configuration of the peripheral module 1200. In the figure, the same elements as those shown in FIG.
In FIG. 2, reference numerals 1211 and 1212 indicate first and second access ports provided in the dual port RAM 1210. Among them, the first access port 1211 is for transferring data to and from the bus master 1100 in synchronization with the bus clock signal SCLK. The first access port 1211 has a first state machine (SFSM) to be described later. ) 1230 is supplied with an address signal mADDR and various control signals (CSN, WRN, RDN).

  The second access port 1212 is for transferring data to and from the peripheral module 1200 in synchronization with the peripheral clock signal PCLK. The second access port 1212 is supplied with an address signal “maddr” from a flag search circuit 1260 described later, Various control signals (mcsn, mwrn, mrdn) are supplied from a two-state machine (PFSM) 1240.

  Reference numeral 1230 indicates a first state machine (SFSM) for accessing the dual port RAM 1210 via the first access port 1211. The first state machine 1230 is supplied with an address signal ADDR, a chip select signal CSN, a write signal WRN, and a read signal RDN from the bus master 1100. Reference numeral 1240 denotes a second state machine (PFSM) for accessing the dual port RAM 1210 via the second access port 1212.

  Reference numeral 1250 indicates a flag register. The flag register 1250 is for storing a flag, which will be described later, generated by the first state machine 1230, and is composed of two types of register groups, a plurality of registers SA to SZ and a plurality of registers FA to FZ. . Here, the registers SA to SZ are for storing a flag indicating the type of transaction issued by the bus master 1100 (write transaction / read transaction, etc.), and the registers FA to FZ are flags indicating the presence / absence of the transaction. Is for storing.

  These two types of registers SA to SZ and registers FA to FZ have a one-to-one correspondence with the registers RA to RZ of the register group 1220 and have a one-to-one correspondence with the data storage areas MA to MZ of the dual port RAM 1210. It corresponds. For example, the register SA and the register FA in the flag register 1250 correspond to the register RA in the register group 1220 and also correspond to the data storage area MA of the dual port RAM 1210. Similarly, two types of registers in the flag register 1250 and each data storage area in the dual port RAM 1210 correspond to each register in the register group 1220.

  Here, when data is written from the bus master 1100 to the dual port RAM 1210, the first state machine 1230 sets a flag in a register in the flag register 1250 corresponding to the data storage area in the dual port RAM 1210 to which this data has been written. To do. The second state machine 1240 clears the flag when the data is read from the dual port RAM 1210. This flag has a meaning of prohibiting the write operation to the dual port RAM 1210 for the first state machine 1230 and has a meaning of permitting a read operation from the dual port RAM 1210 to the second state machine 1240. is doing.

  For example, as described later, the first state machine 1230 refers to the flag register 1250 when writing data to the dual port RAM 1210, and when the flag is set, the data storage area of the dual port RAM 1210 corresponding to the flag. Cancels the write operation for. This prevents updating (destruction) of data that has not been read from the dual port RAM 1210, that is, data that has not been transferred to the register group 1220.

  When the flag is set in the flag register 1250, the second state machine 1240 performs a read operation of the data storage area of the dual port RAM 1210 corresponding to the flag and clears the flag. By clearing the flag in this way, the write operation to the data storage area in the dual port RAM 1210 corresponding to the register in which the flag is stored is permitted thereafter.

  Reference numeral 1260 denotes a flag search circuit. The flag search circuit 1260 includes a synchronization circuit 1261, a comparator 1262, and a counter 1263. The flag search circuit 1260 searches for a flag in the flag register 1250, and stores the position of the searched flag (the flag is stored) as a search result. The address signal “maddr” for designating the register in the register group 1220 corresponding to the register in the flag register 1250 and the data storage area in the dual port RAM 1210 is generated.

Reference numeral 1221 denotes a decoder. The decoder 1221 selectively specifies one register in the register group 1220 based on the address signal maddr. The data input section of each register in the register group 1220 is connected to the second access port 1212 of the dual port RAM 1210 via a read data rdata bus.
Reference numeral 1222 denotes a multiplexer. The output section of each register in the register group 1220 is connected to the input section of the multiplexer 1222, and the output section of the multiplexer 1222 is connected to the second access port 1212 via the bus for write data wdata. ing.

  The dual port RAM 1210, the first state machine 1230, the second state machine 1240, the flag register 1250, and the flag search circuit 1260 described above receive data between the bus master 1100 and the register group 1220 in the peripheral module via the dual port RAM 1210. It functions as an interface circuit that performs transfer. The interface circuit does not need to be built in the peripheral module 1200, and may be provided alone outside the peripheral module 1200.

Next, the operation of the information processing apparatus according to the present embodiment will be described with reference to FIGS.
FIG. 3 is a state transition diagram of the first state machine 1230 and the second state machine 1240 of the information processing apparatus, and FIGS. 4 and 5 are timing charts of the write operation and the read operation of the information processing apparatus, respectively. is there.
In the description of the operation, refer to FIG. 3 for the state transition of each state machine, and appropriately refer to FIGS. 4 and 5 for the operation at each time.

First, the meaning of each state shown in the state transition diagram of FIG. 3 will be described.
(1) State of first state machine 1230 (SCLK synchronization)
SIDE: Idle state waiting for a write transaction and a read transaction by the bus master 1100.
SWAIT; a wait state for applying a wait to the bus master 1100. The state transition is made when the register flag REG_FLG of the flag register 1250 corresponding to the register to be accessed is in the flag set state FLGSET.
SWRITE: Write state recognized by the first state machine 1230. In the next cycle, the bus master 1100 ends the write transaction.
SREAD: Read state recognized by the first state machine 1230. In the next cycle, the bus master 1100 ends the read transaction.

(2) State of flag register 1250 (SCLK synchronization)
FLGCLR: a state in which the register flag REG_FLG of the flag register 1250 is cleared.
FLGSET: a state in which the register flag REG_FLG of the flag register 1250 is set.

(3) State of second state machine 1240 (PCLK synchronization)
PIDLE: an idle state waiting for a write transaction and a read transaction by the first state machine 1230.
PREAD: Read state recognized by the second state machine 1240.
PFCLR; a write state recognized by the second state machine 1240.
The meaning of each state has been described above.

Next, a write operation (data transfer from the bus master 1100 to the register group 1220) from the bus master 1100 to the dual port RAM 1210 and a read operation (data transfer from the register group 1220 to the bus master 1100) will be described in order.
(1) Write Operation A write operation to the dual port RAM 1210 will be described with reference to FIGS.
In the initial state, it is assumed that the first state machine 1230 is in the idle state SIDLE waiting for a transaction (access) from the bus master 1100 and that all the registers in the flag register 1250 are cleared.

  When the bus master 1100 starts a write transaction from this state, at time t1, the write signal WRN supplied to the first state machine 1230 becomes low level, the chip select signal CSN becomes low level, and the address signal ADDR is The value changes to a value that designates the data storage area MZ corresponding to the register RZ.

  When the first state machine 1230 detects a write transaction by the bus master 1100 from these signal states, the first state machine 1230 first refers to the flag register 1250 to check whether the flag is set. In this case, since all the flags are cleared, the write operation to the dual port RAM 1210 is not prohibited. Therefore, the first state machine 1230 makes a transition to the write state SWRITE at time t2, and writes the write data WDATA in the data storage area MZ of the dual port RAM 1210 (FIG. 4; A).

  Then, at time t3, one cycle after time t2, the first state machine 1230 transitions from the write state WRITE to the idle state SIDE to complete the writing to the data storage area MZ. At this time, the first state machine 1230 sets a flag in the register FZ in the flag register 1250 corresponding to the register RZ (FIG. 4B), and sets a flag indicating that writing has been performed in the register SZ. To do.

  When the value of the address signal ADDR changes to a value specifying the data storage area MA at time t3, the first state machine 1230 similarly makes a state transition to the write state SWRITE at time t4 with reference to the flag register 1250. Write data WDATA is written in the data storage area MA (FIG. 4C). At time t5, the state transition from the write state SWRITE to the idle state SIDE is completed to complete the write to the data storage area MA, and a flag indicating the completion of the write is displayed in the register FA in the flag register 1250 corresponding to the register RA. (FIG. 4; D), a flag indicating that the transaction is a write access is set in the register SA.

  Similarly, when the value of the address signal ADDR changes to a value specifying the data storage area MB at time t5, the first state machine 1230 similarly makes a transition to the write state SWRITE at time t6 with reference to the flag register 1250. Write data WDATA is written in the data storage area MB (FIG. 4E). At time t7, the state transition from the write state SWRITE to the idle state SIDLE completes the writing to the data storage area MB, and a flag indicating that the writing is completed is displayed in the register FB in the flag register 1250 corresponding to the register RB. (FIG. 4; F), a flag indicating that the transaction is a write access is set in the register SB.

  Furthermore, at time t7, when the value of the address signal ADDR again changes to a value that designates the data storage area MZ, the first state machine 1230 detects the write transaction for the register RZ again, and sets the flag register 1250. With reference to it, it is checked whether or not a flag is set in the registers FZ and SZ. In this case, since flags are already set in these registers, writing to the data storage area MZ is prohibited. Therefore, at time t8, the first state machine 1230 makes a state transition from the idle state IDLE to the wait state SWAIT, asserts the wait signal WAIT, and applies a wait to the bus master 1100 (FIG. 4; G).

  After that, at time t9, when the data in the data storage area MZ is read, the second state machine 1240 clears the flags of the registers FZ and SZ of the flag register 1250. When detecting that the flags of the registers FZ and SZ are cleared, the first state machine 1230 makes a transition from the wait state SWAIT to the write state SWRITE at time t10, and negates the wait signal WAIT to a low level (FIG. 4; H). Thereafter, the bus master 1100 can again perform the write operation on the data storage area RZ. Therefore, the first state machine 1230 transitions to the write state, finishes writing to the data storage area MZ in one cycle, and sets the flags in the registers FZ and SZ (FIG. 4; J).

  As described above, the access to the dual port RAM 1210 by the first state machine 1230 and the second state machine 1240 is always performed with reference to the flag register 1250, and access of each state machine is permitted / prohibited depending on the state of the flag. .

  Here, data transfer from the dual port RAM 1210 to the register group 1220 will be described. As described above, when data is written from the bus master 1100 to the dual port RAM 1210, a flag is set in the corresponding register in the flag register 1250. The flag in the flag register 1250 is always the flag search circuit 1260. Is being monitored by.

  That is, the counter 1263 in the flag search circuit 1260 cyclically generates count values corresponding to the addresses of the registers RA to RZ in the register group 1220. This count value is supplied as the address signal “maddr” to the second access port 1212 and the decoder 1221 of the dual port RAM 1210, and is used as a flag pointer fp for designating a register in the flag register 1250.

  The flag pointer fb is synchronized with the bus clock signal SCLK by the synchronization circuit 1261 and then supplied to the flag register 1250 as the flag pointer FP. When a flag is set in the register specified by the flag pointer FP, the flag register 1250 outputs a read pointer RP corresponding to the address of the data storage area in the dual port RAM 1210 corresponding to the stored flag register. .

  The read pointer RP is synchronized with the peripheral clock signal PCLK by the synchronization circuit 1261 and supplied to the comparator 1262. The comparator 1262 compares the value of the flag pointer synchronized by the synchronization circuit 1261 with the count value from the counter 1263, and asserts the coincidence detection signal mat if they match. The address signal madr output from the counter 1263 when the coincidence detection signal mat is asserted becomes the address of the data storage area in the dual port RAM 1210 where the data to be written to the register group 1220 exists.

  Therefore, the second state machine 1240 asserts the read signal mrdn to the second access port 1212 of the dual port RAM 1210 when the match detection signal mat is asserted, and the dual port designated by the address signal mrdn at this time. Read data rdata is read from the data storage area in the RAM 1210. The read data rdata is sent to the registers RA to RZ of the register group 1220. The decoder 1221 selects one of the registers RA to RZ based on the address signal “maddr” from the counter 1263, and stores the read data “rdata” in the register.

  As described above, data is transferred from the bus master 1100 to the register group 1220 via the dual port RAM 1210. At this time, from the perspective of the bus master 1100, the dual port RAM 1210 operates with the same bus clock signal SCLK as the bus master operation clock signal, so data is transferred from the bus master 1100 to the dual port RAM 1210 at high speed without requiring latency. Therefore, the apparent data transfer rate from the bus master 1100 to the register group 1220 can be improved.

  In this write operation, when the peripheral module is reading data from the data storage area of the dual port RAM 1210 and the bus master 1100 tries to write data to this data storage area, access to the dual port RAM 1210 competes. In such a case, a weight is applied to the bus master 1100. However, in the process executed by the CPU, in practice, it is extremely rare that the values once set in the registers RA to RZ in the register group 1220 are continuously rewritten. As a result, it can be said that there is virtually no decrease in data transfer efficiency.

(2) Read Operation Next, a read operation from the dual port RAM 1210 by the bus master 1100 will be described with reference to FIGS.
Here, a case will be described in which data is sequentially read from the data storage areas MA, MB, and MZ after data is written to the data storage area MZ of the dual port RAM 1210 by the above-described write operation.

  When the bus master 1100 starts a write transaction prior to the read transaction, at time t1, the write signal WRN and the chip select signal CSN supplied to the first state machine 1230 become low level, and the address signal ADDR corresponds to the register RZ. The data storage area MZ to be changed is changed to a specified value.

  From these signal states, when the first state machine 1230 detects a write transaction, the first state machine 1230 refers to the flag register 1250 in the same manner as described above to check whether or not the flag is set. In this case, since the flags of the registers FZ and SZ in the flag register 1250 are cleared, the first state machine 1230 changes to the write state SWRITE at time t2 and writes the write data WDATA in the data storage area MZ ( FIG. 5; A). Then, at time t3 after one cycle, the state transitions from the write state SWRITE to the idle state SIDE, and the writing to the data storage area MZ is completed. At this time, the first state machine 1230 sets a flag in the registers FZ and SZ. (Fig. 5; B)

  Thereafter, when the bus master 1100 starts a read transaction at time t8, the write signal WRN is negated to a high level, the read signal RDN is asserted to a low level, and the address signal ADDR changes to a value designating the data storage area MZ. . From these signal states, when the first state machine 1230 detects a read transaction, the first state machine 1230 refers to the flag register 1250 in the same manner as described above, and checks whether or not the flags are set in the registers FA and SA. In this case, since the flags are set in the registers FZ and SZ, the first state machine 1230 makes a transition to the wait state SWAIT, asserts the wait signal WAIT to a high level, and puts a wait on the bus master 1100. (FIG. 5; C).

  In FIG. 5, for example, at time t10, the flags of the registers FZ and SA are cleared by the second state machine 1240, and when the first state machine 1230 detects clearing of the flag FZ, the first state machine 1230 is detected at time t11. Changes from the wait state SWAIT to the read state SREAD (FIG. 5; D). The first state machine 1230 reads data from the dual port RAM 1210 in the read state SREAD, and finishes the read access in two cycles from time t10.

  When first state machine 1230 detects an access to data storage area MA (storage area corresponding to register RA) in dual port RAM 1210 in idle state SIDLE in the cycle at time t 3, register in flag register 1250 Refer to FA. In this case, since the register FA is in a cleared state (access permission state), the first state machine 1230 makes a transition to the read state SREAD (FIG. 5E) and reads the read data RDATA from the dual port RAM 1210. . At the time of reading by the bus master 1100, it is not necessary to set a flag in the flag register 1250 (FIG. 5; F).

In this read operation, access to the dual port RAM 1210 competes when the bus master 1100 tries to read data from the data storage area while the peripheral module is writing data to the data storage area of the dual port RAM 1210. In such a case, a wait is applied to the bus master 1100.
The write operation and read operation have been described above.

  Next, referring to the state transition diagram of FIG. 6, an access conflict prevention operation when both the bus master 1100 and the peripheral module 1200 attempt to rewrite the dual port RAM 1210 simultaneously will be described. In general, in this access contention prevention operation, the first state machine 1230 and the second state machine 1240 have the first and second state machines when one of the first and second state machines accesses the dual port RAM 1210. The other of the two-state machines is changed to the lock state.

First, the meaning of each state shown in the state transition diagram of FIG. 6 will be described.
FLGCLR: a state in which the register flag REG_FLG of the flag register 1250 is cleared.
(1) State SIDLE of the first state machine 1230: A state waiting for a write transaction and a read transaction by the bus master 1100.
SWAIT; a wait state for applying a wait to the bus master 1100. When the register flag REG_FLG of the register to be accessed is in the flag set state FLGSET, the state is changed.
SWRITE: Write state recognized by the first state machine 1230. In the next cycle, the bus master 1100 ends the write transaction.
SREAD: Read state recognized by the first state machine 1230. In the next cycle, the bus master 1100 ends the read transaction.

(2) State of flag register 1250 FLGCLR; State in which register flag REG_FLG is cleared.
FLGSET: a state in which the register flag REG_FLG is set.
When a lock request is received from the second state machine 1240 in the flag clear state, the state transitions to this state. When a read / write transaction from the bus master 1100 is started in this state, a wait signal is output to put a wait on the bus master 1100. During this period, the second state machine 1240 writes the value of the interrupt flag register to the dual port RAM 1210.

(3) State PIDLE of the second state machine 1240; a state waiting for a write transaction and a read transaction by the first state machine 1230.
PLOCKREQ; When the update of the value of the interrupt flag register is detected, the state transitions to this state, and a lock request is issued to the register flag REG_FLG.
PWRITE: The state transition is made to this state while the register flag REG_FLG is locked, and the value of the interrupt flag register is written to the dual port RAM 1210.
PUNLOCK; When writing of the value of the interrupt flag register to the dual port RAM 1210 is completed, the state transitions to this state, and an unlock request is issued to the register flag REG_FLG.
PREAD: Read state recognized by the second state machine 1240.
PFCLR; a write state recognized by the second state machine 1240.

An access conflict prevention method based on the above states will be described.
The second state machine 1240 in the peripheral module 1200 shown in FIG. 2 makes a transition to the idle state PIDLE in response to the preset signal PRESET (FIG. 6; A). When the update of the interrupt flag register is detected in this state, the second state machine 1240 A state transition is made to the request state PLOCKCKREQ, and a lock request is issued to the register flag REG_FLG in the flag register 1250.

  When the register request REG_FLG in the flag register 1250 receives the lock request from the second state machine 1240 in the flag clear state FLGCLR, the state shifts from the flag clear state FLGCLR to the flag lock state FLGLOCK (FIG. 6; B). The first state machine 1230 detects that the flag register 1250 has made a state transition to the flag lock state FLGLOCK, and when it detects a write transaction from the bus master 1100 in that state, makes a transition to the wait state SWAIT (FIG. 6; C ), A wait is applied to the bus master 1100.

  When detecting that the register flag REG_FLG has transitioned to the flag lock state FLGLOCK in the lock request state PLOCKREQ, the second state machine 1240 transitions to the write state PWRITE (FIG. 6; D), and interrupts the dual port RAM 1210. Write the value of the flag register. When the second state machine 1240 finishes writing the interrupt flag to the dual port RAM 1210 in the write state PWRITE, the second state machine 1240 transitions to the unlock state PUNLOCK (FIG. 6; E), and the register flag REG_FLG in the flag register 1250 Issue an unlock request.

  When the register flag REG_FLG receives the unlock request from the second state machine 1240, the state shifts from the flag lock state FLGLOCK to the flag clear state FLGCLR (FIG. 6; F), and the lock is released. When the lock is released, the first state machine 1230 releases the wait and accepts and executes a transaction from the bus master 1100.

  As described above, by causing the register flag REG_FLG of the flag register 1250 to have the flag lock state FLGLOCK that locks the access from the bus master 1100, contention of access to the dual port RAM 1210 is prevented.

The characteristics of the information processing apparatus according to the above-described embodiment will be summarized.
In this information processing apparatus, a dual port RAM 1210 exists as a mirror circuit between the register group 1220 forming the main body of the peripheral module 1200 and the bus master 1100, and data transfer is performed via this mirror circuit. The control related to the data transfer is performed by the first state machine 1230 that operates in synchronization with the bus clock signal SCLK and the second state machine 1240 that operates in synchronization with the peripheral clock signal PCLK. When the bus master 1100 performs a register write to the mirror circuit, the first state machine 1230 sets a write flag in a register in the corresponding flag register 1250.

  When the write flag is set, the second state machine 1240 detects a register flag write event. When this event is detected, the second state machine 1240 reads the data written in the mirror circuit and updates the value of the register in the corresponding register group 1220. At this time, the corresponding address is determined by determining the address of the flag register 1250 in which the flag is set by the flag search circuit 1260, and the second state machine 1240 is specified by the determined address. Data is read from the data storage area of the dual port RAM 1210. The address search by the flag search circuit 1260 is performed by comparing the count value of the counter in the flag search circuit 1260 with the read pointer RP indicating the register address.

  When the update of the register value is completed, the second state machine 1240 clears the flag of the corresponding register. If simultaneous access to the same address is performed, the data in the dual port RAM 1210 may be destroyed. However, according to the information processing apparatus according to the present embodiment, when access occurs simultaneously, a wait is applied to the bus master 1100 with reference to the flag register 1250, so that data destruction can be avoided. Further, since the set register value is not frequently rewritten, the data transfer efficiency is not sacrificed by the wait.

  According to this information processing transmission, since read / ride access to the dual port RAM 1210 by the bus master 1100 is performed using the bus clock signal SCLK, synchronization of asynchronous data that causes an increase in latency, It is not necessary to secure setup / hold time for special data. Accordingly, it is possible to greatly reduce the latency at the time of register access as viewed from the bus master 1100. As a result, the higher the bus speed, the lower the occupancy rate of the bus master in register access, and the overall system performance can be improved.

Next, a modification of the present embodiment will be described with reference to FIG.
In the above embodiment, the case where the dual port RAM 1210 is incorporated in the peripheral module 1200 and the one-to-one data transfer is performed between the peripheral module 1200 and the bus master 1100 has been described. A case where data transfer is performed between a plurality of peripheral modules 720, 730, 740, and 750 including a bus master 710 such as a CPU via a 5-port RAM 700 which is a kind of multi-port RAM will be described.

  In this modification, the 5-port RAM 700 includes data storage areas corresponding to all the registers of the peripheral modules 720 to 750, and the values of all the registers of the peripheral modules 720 to 750 are stored in this data storage area. Each access port of the 5-port RAM 700 includes a bus master 710 such as a CPU that operates with the clock signal CLK, a peripheral module 720 that operates with the clock signal CLKA, a peripheral module 730 that operates with the clock signal CLKB, and a clock signal. A peripheral module 740 operating with CLKC and a peripheral module 740 operating with the clock signal CLKD are connected, and this 5-port RAM 700 functions as an interface circuit that performs data transfer between the bus master 710 and the peripheral modules 720-750. .

  The 5-port RAM 700 has a configuration corresponding to the first state machine 1230, the second state machine 1240, the flag register 1250, and the flag search circuit 1260 described above, and a state machine is provided for each access port of the 5-port RAM 700. . Among these, the state machine provided in the access port to which the bus master 710 is connected has the same function as the first state machine 1230 described above, and is provided in other access ports to which the peripheral modules 720 to 750 are connected. Has the same function as the second state machine 1240 described above. The configuration corresponding to the flag search circuit 1260 has a function of searching for a flag register corresponding to the flag register 1250 and notifying the search result for each module.

  According to such a modification, even if the clock signal used in the peripheral modules 720 to 750 is completely asynchronous with the clock signal used in the bus master 710 and is low in speed, the bus master 710 may Can complete access to all the registers of the peripheral modules 720 to 750 in a time corresponding to two cycles of the clock signal SCLK. For this reason, as in the above-described embodiment, the latency when the bus master 710 accesses each peripheral module can be effectively reduced, and the performance of the entire system can be improved.

It is a figure which shows schematic structure of the information processing apparatus which concerns on embodiment of this invention. It is a figure which shows the detailed structure of the peripheral module with which the information processing apparatus which concerns on embodiment of this invention is provided. It is a state transition diagram of the state machine with which the information processing apparatus which concerns on embodiment of this invention is provided. 6 is a timing chart for explaining a write operation of the information processing apparatus according to the embodiment of the present invention. 5 is a timing chart for explaining a read operation of the information processing apparatus according to the embodiment of the present invention. It is a state transition diagram of each state machine for preventing access conflict according to an embodiment of the present invention. It is a figure for demonstrating the modification of the information processing apparatus which concerns on embodiment of this invention. It is a figure which shows schematic structure of the information processing apparatus of a prior art. It is detail drawing of the peripheral module which comprises the information processing apparatus which concerns on a prior art. It is a state transition diagram of the state machine with which the information processing apparatus of a prior art is provided. It is a timing chart for demonstrating the write operation of the information processing apparatus of a prior art. It is a timing chart for demonstrating the read operation | movement of the information processing apparatus of a prior art.

Explanation of symbols

  1100; bus master, 1200; peripheral module, 1210; dual port RAM, 1211; first access port, 1212; second access port, 1230; first state machine, 1240; second state machine, 1250; flag register, 1260; Flag search circuit, 1220; register group, 1221; decoder, 1222; multiplexer, 700; 5-port RAM, 710; bus master (CPU), 720 to 750;

Claims (8)

A bus master that operates in synchronization with the first clock signal;
A peripheral module operating in synchronization with the second clock signal;
A first access port for transferring data to and from the bus master in synchronization with the first clock signal and a second access port for transferring data to and from the peripheral module in synchronization with the second clock signal And an interface circuit for performing data transfer between the bus master and the peripheral module via the storage means. The interface circuit is
Generating a first control signal to be supplied to the first access port based on an access from the bus master, and generating a flag indicating that the access has occurred when the access from the bus master is a write operation; A state machine,
A flag register for storing the flag;
A flag search circuit for searching for a flag stored in the flag register;
The information processing apparatus according to claim 1, further comprising: a second state machine that generates a second control signal to be supplied to the second access port based on a search result by the flag search circuit. The peripheral module includes a plurality of first registers,
The flag register includes a plurality of second registers corresponding to the plurality of first registers,
3. The flag search circuit is configured to output an address signal designating a register corresponding to the first register in which the flag is stored among the plurality of second registers. Information processing device. The flag search circuit
A counter that cyclically generates a count value corresponding to each address of the plurality of second registers and supplies the count value to the peripheral module and the storage unit;
The count value is synchronized with the first clock signal and supplied to the flag register as a flag pointer, and a register pointer indicating that the flag is stored in the flag register specified by the flag pointer is A synchronization circuit for synchronizing with the clock signal;
A comparator that compares the register pointer synchronized with the synchronization circuit with the count value and supplies the comparison result to the second state machine;
The second state machine generates and outputs a control signal related to a read operation as the second control signal when the comparison result indicates a match between the register pointer and the count value. 3. The information processing apparatus according to 3. Each of the plurality of second registers is
A register for storing a flag indicating the type of access from the bus master;
5. The information processing apparatus according to claim 1, further comprising a register that stores a flag indicating that the bus master has accessed.   The first and second state machines, when one of the first and second state machines accesses the storage means, causes the other of the first and second state machines to transition to the lock state. The information processing apparatus according to any one of claims 1 to 5. The storage means is composed of a multi-port RAM having a plurality of access ports as the second access port,
6. The information processing apparatus according to claim 1, wherein a plurality of modules as the peripheral modules are connected to the plurality of access ports of the multi-port RAM, respectively. An interface circuit that performs data transfer between a bus master that operates in synchronization with a first clock signal and a peripheral module that operates in synchronization with a second clock signal,
A first access port for transferring data to and from the bus master in synchronization with the first clock signal and a second access port for transferring data to and from the peripheral module in synchronization with the second clock signal Storage means comprising:
Generating a first control signal to be supplied to the first access port based on an access from the bus master, and generating a flag indicating that the access has occurred when the access from the bus master is a write operation; A state machine,
A flag register for storing the flag;
A flag search circuit for searching for a flag stored in the flag register;
An interface circuit comprising: a second state machine that generates a second control signal to be supplied to the second access port based on a search result by the flag search circuit.

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