JP2008090554A - Information processing apparatus, control apparatus, and memory management method - Google Patents

Abstract

An information processing apparatus, a control apparatus, and a memory management method capable of efficiently copying only frequently accessed data to a high-speed memory and referencing the data efficiently are provided.
Each page of a low-speed memory is assigned to a virtual address, and a file having a high access frequency among a plurality of files stored in each page of the low-speed memory is copied to a page of the high-speed memory. Assign to a virtual address.
[Selection] Figure 2

Description

  The present invention relates to a virtual memory management technique, and more particularly to an information processing apparatus, a control apparatus, and a memory management method provided with two memories, a high speed memory and a low speed memory.

In general, as a virtual memory management technology including two memories, a high-speed memory and a low-speed memory, for example, as disclosed in Patent Document 1, data is updated according to the execution status of data processing, and data There is a control technology that prevents excessive data transfer due to an error in determining the usefulness of data and stores optimum data in each memory).
JP-A-5-341912

  However, in the above-described technique, since the contents of the low-speed memory are always copied to the high-speed memory and the data in the high-speed memory is referred to, copy time loss occurs.

  An object of the present invention is to provide an information processing apparatus, a control apparatus, and a memory management method capable of copying only frequently accessed data to a high-speed memory and referencing the data efficiently.

  In order to achieve the above object, according to one aspect of the present invention, a first memory, a second memory having a slower read / write speed than the first memory, and each page of the second memory Of the plurality of files assigned to the virtual address and stored in each page of the second memory, a file having a high access frequency is copied to a predetermined page of the first memory. There is provided an information processing apparatus comprising an assigning unit that assigns a page to the virtual address.

  By using the present invention, it is possible to copy only frequently accessed data to a high-speed memory and efficiently refer to the data.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a perspective view of an information processing apparatus according to an embodiment of the present invention. This information processing apparatus is realized as a battery-driven notebook computer 10. The present invention comprises two memories, a high-speed memory and a low-speed memory. When virtual memory management is performed, a virtual address is directly assigned to the low-speed memory, and a file with high access frequency is copied to the high-speed memory. A virtual address is assigned.

  As shown in FIG. 1, the computer 10 includes a main body 16 and a display 11. The display 11 incorporates a display device made up of an LCD (Liquid Crystal Display), and the display screen 12 of the LCD is located almost at the center of the display 11.

  The display 11 is attached to the computer 10 so as to be openable and closable between a release position and a closed position. The main body side of the computer 10 has a thin box-shaped casing. On the top surface thereof, there is a keyboard 13, a touch pad 14 on the palm rest, left and right buttons 14a and 14b, various shortcut buttons such as mail, A power button, a volume control button 18, a speaker 29, and the like are arranged. Further, an optical drive 15 or the like is provided on the side surface of the main body 16.

  FIG. 2 is a block diagram showing a main configuration of the information processing apparatus according to the embodiment of the present invention.

  The computer 10 includes a CPU (Central Processing Unit) 20, a Root Complex 21, a main memory 24, a graphics controller (End Point) 23, a PCI Express Link 22 that connects the Root Complex (chipset) 21 and the graphics controller 23, a display ( LCD) display device 11, main memory (high-speed memory: first memory) 24, embedded controller / keyboard controller IC (EC / KBC) 27, hard disk drive (HDD) 25, BIOS-ROM 26, memory (low-speed memory: A second memory) 17, a keyboard 13, a touch pad 14, an AC power source 19, a speaker 29, and the like. The main memory 24 uses a memory such as a RAM or a DDR SD-RAM, and the memory 17 uses an SD-RAM or the like that is slower than the main memory 24 connected on the bus.

  The Root Complex 21, the graphics controller 23, and the like are devices that comply with the PCI EXPRESS standard. Communication between the Root Complex 21 and the graphics controller 23 is executed via a PCI Express Link 22 disposed between the Root Complex 21 and the graphics controller 23.

  The CPU 20 is a processor that controls the operation of the computer 10, and executes various programs (an operating system, application programs such as a memory management program to be operated later) loaded from the HDD 25 to the main memory 24. The CPU 20 also executes a basic input / output system (BIOS) stored in the BIOS-ROM 26. The BIOS is a program for controlling hardware.

  The root complex 21 is a bridge device that connects the local bus of the CPU 20 and the graphics controller 23. The Root Complex 21 also has a function of executing communication with the graphics controller 23 via the PCI Express Link 22.

  The graphics controller 23 is a display controller that controls the display device 11 that is a display used as a display monitor of the computer.

  The EC / KBC 27 is a one-chip microcomputer in which an embedded controller for power management and a keyboard controller for controlling the keyboard 13, touch pad 14, battery 28, AC power source 19 and the like are integrated. The EC / KBC 27 has a function of powering on / off the computer 10 in cooperation with the power controller in accordance with the operation of the power button by the user.

  Next, the configuration and operation of the virtual memory management operating system when performing virtual memory management will be described.

  The virtual memory management operating system provides a virtual address space for applications operating on the memory management and file system, which are components of the operating system. For example, when accessing a file system file A and file B on the low-speed memory 17 from a predetermined application, the file system maps the file to a virtual address space managed by the operating system.

  FIG. 3 is a schematic diagram showing a virtual address space of an application operating on the virtual memory management operating system. An operating system provides a virtual address space to an application, and the virtual address space is managed as a set of units of a predetermined size called a page. In the present embodiment, pages with a high access frequency (reference frequency) are stored in the high-speed memory 24 and the high-speed memory 24 is directly referenced. Also, pages with low access frequency are stored in the low speed memory 17 and the low speed memory 17 is directly referred to. When a page assigned to the high speed memory 24 is updated (written), writing to the corresponding low speed memory 17 is not performed each time, and writing is performed when allocation is changed from the high speed memory 24 to the low speed memory 17.

  When virtual memory management is performed by a computer or the like, a virtual address space as described above is set, and memories corresponding to the respective virtual addresses 1 to 6 are allocated. As the memory to be allocated, for example, the high speed memory (main memory) 24 and the low speed memory (memory) 17 are used. The low speed memory 17 stores a predetermined file. Of the files stored in the low-speed memory 17, a frequently accessed file is copied to the high-speed memory 24. Since the access frequency is not counted at the first stage, for example, there are four storage areas of the high-speed memory 24, for example, addresses 1 to 4, so that the addresses 2, 4, and 5 of the low-speed memory 17 are assigned to the high-speed memory. 24 is copied to addresses 4, 2, and 1 (address 3 of high-speed memory 24 is not used at this time). Then, addresses 3, 1, and 4 in the virtual address space are assigned to addresses 1, 2, and 4 in the high-speed memory 24.

  Next, FIG. 4 is a flowchart illustrating a memory management method to which an information processing apparatus and a control apparatus according to an embodiment of the present invention are applied.

  The CPU 20 of the computer 10 reads a memory management program from the HDD 25 (step S101). The read memory management program operates on the high-speed memory 24, for example, and is thereafter controlled by the CPU 20. The memory management program creates a page table. For example, as described above, as shown in FIG. 3, a page table is created, and the addresses of the high speed memory 24 and the low speed memory 17 are assigned to the virtual address space. The page table is, for example, a table as shown in FIG.

  Next, access to the files stored in the high-speed memory 24 and the low-speed memory 17 is started (step S103), and at the same time, an access count for each address of the high-speed memory 24 and the low-speed memory 17 (hereinafter also referred to as a reference count). Is started (step S104). At this time, if a page assigned to the high-speed memory 24 is updated (written), writing to the corresponding low-speed memory 17 is not performed each time, and a Dirty (D) flag is given to the high-speed memory 24 to When the allocation is changed from 24 to the low-speed memory 17, writing is performed (after writing, the flag is returned to (C)). The flag is given the clean (C) flag before the D flag. With this flag, it is possible to determine whether the contents of the low-speed memory 17 corresponding to the high-speed memory 24 are the same “flag: (C)” or different from each other, “flag: (D)”.

  As shown in FIG. 5, the above-described table uses a virtual address as an index, a flag indicating whether the content of the low-speed memory 17 corresponding to the high-speed memory 24 is the same flag: (C) or different flag (D), real memory Consists of address and reference count. In the case of the high-speed memory 24, the actual memory address is described in parentheses for the address of the corresponding low-speed memory 17.

  The update of the reference count in step S104 is monitored for a predetermined fixed time by the memory management program. For example, when a fixed time of several hundred ms to several seconds elapses (step S105), it is determined whether or not the reference count of the low speed memory 17 is larger than the reference count of the high speed memory 24 (step S106). In step S106, all the reference counts are sorted by the memory management program and arranged in descending order. Then, by the memory management program, the number of pages in the high-speed memory 24, that is, four is selected from the top. For example, in the table shown in FIG. 5, reference count 15 (high-speed memory address 1: low-speed memory address 5), reference count 11 (low-speed memory address 3), reference count 8 (high-speed memory address 2: low-speed memory) Address 4) and reference count 3 (high-speed memory address 4: low-speed memory address 2) are selected. Among these, the memory management program determines whether there is a reference count of the low-speed memory 17 that is larger than the reference count of the high-speed memory 24. It is determined that the reference count 11 (low-speed memory address 3) is larger than the reference count 3 (high-speed memory address 4: low-speed memory address 2) and reference count 8 (high-speed memory address 2: low-speed memory address 4). (YES in step S106). At this time, reference count 3 (high-speed memory address 4: low-speed memory address 2) and reference count 8 (high-speed memory address 2: low-speed memory address 4) have a reference count 3 (high-speed memory address 4: low-speed memory address 4). Since the reference count of the memory address 2) is smaller, if the address 4 of the high-speed memory 24 is Dirty of the flag (D) (step S107), the contents of the address 4 of the high-speed memory are changed to the address 2 of the low-speed memory. (Step S108), the virtual address assigned to the address 4 of the high speed memory is changed to be assigned to the address 2 of the low speed memory, and the address 4 of the high speed memory is released as Free (step S109). The memory management program copies the address 3 of the low-speed memory to the address 4 of the high-speed memory that becomes Free, and changes the allocation of the virtual address 2 (see FIG. 6) from the address 3 of the low-speed memory to the address 4 of the high-speed memory. (Step S110), the reference count is cleared, and the initial value is set to zero. The flag is changed from (D) to (C). The table whose assignment has been changed as described above is the table shown in FIG.

  As described above in detail, by using this embodiment, for pages with high access frequency, copying to a high-speed main memory provides high-speed access, and for pages with low access frequency. In this case, the memory usage can be reduced by directly referring to the actual memory of the low-speed file system. That is, it is possible to efficiently refer to data by copying only frequently accessed data to a high-speed memory.

  The above-described memory management method can be realized as a control device of one microchip, and can also be realized as software as a program.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

The perspective view showing the appearance of the information processor concerning one embodiment of the present invention. The block diagram which shows the principal part structure of the information processing apparatus which concerns on one Embodiment of this invention. The schematic diagram which showed the virtual address space of the application which operate | moves on a virtual memory management operating system. The flowchart explaining the memory management method to which the information processing apparatus and control apparatus which are one Embodiment of this invention are applied. The schematic diagram which showed an example of the page table. The schematic diagram which showed an example of the page table after the replacement of the virtual address assignment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Computer, 11 ... LCD, 12 ... Display screen, 13 ... Keyboard, 14 ... Touchpad, 14a. 14b ... button, 15 ... optical drive, 16 ... main body, 17 ... memory, 18 ... power button, 19 ... AC power supply, 20 ... CPU, 23 ... graphics controller, 24 ... main memory, 25 ... HDD, 26 ... BIOS- ROM, 27 ... EC / KBC, 28 ... Battery

Claims (9)

A first memory;
A second memory having a slower read / write speed than the first memory;
Each page of the second memory is assigned to a virtual address, and a frequently accessed file among a plurality of files stored in each page of the second memory is copied to a predetermined page of the first memory. Allocating means for allocating a predetermined page of the first memory to the virtual address;
An information processing apparatus comprising: The information processing apparatus according to claim 1,
The allocating means takes an access count for each virtual address, selects the number of virtual addresses in the first memory from the one having a large access count, and all the selected virtual addresses are allocated to the first memory. An information processing apparatus characterized by that. The information processing apparatus according to claim 2,
An information processing apparatus, wherein after the file is replaced, the access count is cleared to an initial value. The information processing apparatus according to claim 2,
When the page assigned to the first memory is updated, the assigning means changes the assignment from the first memory to the corresponding second memory, and changes the assignment from the first memory to the corresponding second. An information processing apparatus for writing to a memory. A control device for controlling a first memory and a second memory having a slower read / write speed than the first memory,
Each page of the second memory is assigned to a virtual address, and a frequently accessed file among a plurality of files stored in each page of the second memory is copied to a predetermined page of the first memory. A control device that allocates a predetermined page of the first memory to the virtual address. A memory management method used in an information processing apparatus including a first memory and a second memory having a slower read / write speed than the first memory,
Each page of the second memory is assigned to a virtual address, and a frequently accessed file among a plurality of files stored in each page of the second memory is copied to a predetermined page of the first memory. A memory management method comprising allocating a predetermined page of the first memory to the virtual address. The memory management method according to claim 6.
An access count is taken for each virtual address, and the number of virtual addresses in the first memory is selected from those having a large access count so that all the selected virtual addresses are assigned to the first memory. Memory management method. The memory management method according to claim 7,
A memory management method, comprising: clearing the access count to an initial value after replacing the file. The memory management method according to claim 7,
When the page assigned to the first memory is updated, the allocation from the first memory to the corresponding second memory is changed when the allocation is changed from the first memory to the corresponding second memory. A memory management method comprising performing writing.

Images