JP2008078175A - Method for manufacturing trench MOS type silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a voltage-driven (MOS power) silicon carbide semiconductor device such as a MOSFET or IGBT having a trench gate structure using a silicon carbide (hereinafter also referred to as SiC) crystal substrate as a semiconductor material.

  Since silicon carbide semiconductor material has a larger band gap than silicon semiconductor material, it has high breakdown field strength. Since the on-resistance, which is the resistance in the conductive state of the semiconductor device, is inversely proportional to the cube of the dielectric breakdown field strength of the semiconductor material, for example, silicon carbide using a widely used crystal substrate called 4H type In a semiconductor device, there is a possibility that its on-resistance can be reduced to 1 / 100th of that of a silicon semiconductor. Combined with the large thermal conductivity characteristics showing good heat dissipation, it is expected as a next-generation low-loss power semiconductor device. In recent years, metal oxide semiconductor field effect transistors (MOSFETs), bipolar transistors, junction field effect types, which greatly exceed the characteristics of silicon semiconductor devices, coupled with the improvement in quality of silicon carbide wafers (semiconductor substrates) and the increase in diameter. Development of transistors (JFET) and the like is active. In particular, MOSFETs are voltage-driven devices, so that gate drive circuits are not only costly, but they are majority carrier devices with only electrons or holes, and there is no accumulation of carriers in the device when conducting, so they are not turned on at turn-off. For example, it has a feature that high-speed switching is possible as compared with a bipolar device in which both electrons and holes contribute to conduction.

FIG. 5 shows a cross-sectional structure of a one-cell pitch of a conventional trench MOSFET having a general trench gate structure (a MOSFET having a trench gate with a sidewall perpendicular to the main surface, the same applies hereinafter). A high-resistance n-type drift layer 22 and a p-type base layer 23 are sequentially formed on the n-type low-resistance silicon carbide substrate (drain layer) 21 by epitaxial SiC growth, and then ion implantation from the surface of the p-type base layer 23 is performed. An n ⁺ type source region 24 is formed. Next, a vertical trench 25 reaching the n-type drift layer 22 is formed by RIE using an Al film formed from the main surface on the n ⁺ -type source layer 24 side through an oxide film as a mask. Further, a gate oxide film 26, a gate electrode 27, a source / base electrode 28, and the like are formed on the trench 25 side, and a trench gate structure is formed on the silicon carbide wafer 30. Thereafter, drain electrode 29 is formed on the back surface side to complete the trench type silicon carbide MOSFET.

In the trench type MOSFET, when the source / base electrode 28 is set to the ground potential in the off state and a sufficiently large negative bias is applied to the gate electrode 27, the p base sandwiched between the n ⁺ type source region 24 and the drift layer 22 is applied. In the region of the layer 23 near the interface with the gate oxide film 26, holes are induced and accumulated, and the path of electrons as conduction carriers is blocked, so no current flows. When a positive high voltage is applied to the drain electrode 29, the junction between the p base layer 23 and the drift layer 22 is in a reverse bias state, so that the depletion layer extends into the p base region 23 and the drift layer 22, and the high voltage is maintained. Is done.

  In addition, when a positive bias equal to or higher than the threshold value is applied to the gate electrode 27 in the on state, an inverted state is generated in which electrons are induced in a region near the surface of the trench 25 of the p base layer 23 sandwiched between the source region 24 and the drift layer 22. Thus, electrons flow in the order of the source electrode 28, the source region 24, the inversion layer (not shown) in contact with the gate oxide film 26 of the p base layer 23, the drift layer 22, the substrate 21, and the drain electrode 29.

  Regarding the resistance in the on state, in the structure of a general DIMOSFET as shown in FIG. 6, the accumulation layer resistance when electrons move near the interface between the drift layer 32 and the gate oxide film 36 added, and the drift layer FIG. 5 shows the JFET resistance that easily occurs when the n-type drift layer 32 is sandwiched between the adjacent p-type base layers 33 when flowing from the vicinity of the gate oxide film 36 to the lower drain. The trench gate type trench MOSFET shown in FIG. For this reason, when the cell pitch is decreased in the DIMOSFET, the JFET resistance appears from a certain cell pitch distance and the on-resistance increases, whereas in the trench MOSFET, the on-resistance decreases monotonically as the cell pitch is decreased. There is an advantage. In particular, in a MOSFET having a withstand voltage of about 3 kV or less, since the MOS channel resistance cannot be ignored, the cell pitch must be reduced by miniaturization, and it is preferable to use a trench MOSFET.

However, the trench MOSFET has a problem that the electric field strength applied to the SiO ₂ film 26 at the bottom of the trench becomes very large as shown in FIG. FIG. 7 is a cross-sectional view showing an enlarged structure within a broken line of the trench MOSFET of FIG. 5, and a pn structure portion and a MOS structure portion indicated by a broken line frame corresponding to the cross-sectional view in the thickness direction of the substrate. The vertical axis is combined with the vertical axis, and the horizontal axis is a diagram showing an electric field intensity distribution diagram showing the electric field intensity in the off-voltage applied state. As can be seen from FIG. 7, a large electric field strength is applied to the oxide film 26 in the MOS structure. As shown in FIG. 7, the electric field strength applied to the SiO ₂ film at the bottom of the trench increases because of the relative dielectric constant of silicon carbide (9.7 for 4H—SiC) and the relative dielectric constant of the SiO ₂ film (3. This is because the difference from 8) is smaller than the relative dielectric constant difference between Si (11.9) and SiO ₂ film (3.8). Further, although not shown in FIG. 7, the electric field strength applied to the SiO ₂ film in the trench corner portion is often further increased due to electric field concentration. It is ideal that the peak electric field strength at the pn junction (between 23/22) shown in FIG. 7 reaches the breakdown electric field strength of silicon carbide and causes breakdown in breakdown voltage. In the case of a trench MOSFET, Before the pn junction (between 23/22) reaches its breakdown field strength, the SiO ₂ film 26 at the bottom of the trench reaches its breakdown field strength (about 10 MV / cm) first, which is lower than the theoretical breakdown voltage. There is a problem that breakdown occurs due to voltage. In silicon semiconductors, the breakdown field strength is 0.2 MV / cm, which is two orders of magnitude lower than 10 MV / cm of the SiO ₂ film, so breakdown occurs almost at the pn junction, but in the case of silicon carbide (4H crystal) , dielectric breakdown field strength is as large as 2 MV / cm, since due solely breakdown field and one digit of the SiO ₂ film, is the problem of breakdown in the SiO ₂ film becomes more pronounced. As a countermeasure, a method for avoiding this by increasing the thickness of the SiO ₂ film at the bottom of the trench is already known. As a specific method for increasing the thickness of the SiO ₂ film, for example, a method of using a (0001) carbon surface having a high oxidation rate on the bottom surface of the trench (Patent Document 1), or damaging the bottom surface with an ion beam to form the bottom surface. A method for increasing the thickness of the insulating film (Patent Document 2) has been announced.
JP-A-7-326755 JP 2000-31003 A

Although the present invention relates to a method of increasing the SiO ₂ film thickness at the bottom of the trench in order to avoid the problem of dielectric breakdown of the SiO ₂ film at the bottom of the trench as described above, An object of the present invention is to provide a method of manufacturing a trench MOS type silicon carbide semiconductor device capable of easily and surely increasing the thickness of the SiO ₂ film.

  According to the first aspect of the present invention, the first conductivity type epitaxial silicon carbide thin film and the other conductivity type epitaxial silicon carbide thin film are formed on the one conductivity type silicon carbide semiconductor substrate having the Si surface as the main surface. After forming the second one-conductivity-type epitaxial silicon carbide thin film in this order, an Al film mask is used to form a trench reaching the first one-conductivity-type epitaxial silicon carbide thin film, and the re-formed Al film mask is used. A method of manufacturing a trench MOS type silicon carbide semiconductor device having a step of forming irregularities at the bottom of the trench and a subsequent thermal oxidation step, wherein the step of forming irregularities is changed to an oxide film by a subsequent thermal oxidation step. A method for manufacturing a trench MOS type silicon carbide semiconductor device, which is a step of processing into a concavo-convex shape having a convex portion interval such that the projected portions contact each other. More, the object of the present invention can be achieved.

According to the invention of claim 2, the convex part of the trench bottom is periodically formed in parallel with either the short side direction or the long side direction of the trench bottom part. Preferably, the method of manufacturing a trench MOS type silicon carbide semiconductor device according to claim 1 is used.
According to the third aspect of the present invention, the length in the long side direction of the trench is Lt, the width is Wt, the length of the bottom convex portion is L, the width is W, and the height. Where h is the number, n is the number, the thermal oxide film thickness at the time of forming the oxide film at the bottom of the trench is tox, and the convex portions are periodically formed in the short side direction of the trench,
Lt = L, Wt = (2n + 1) × W, h ≧ tox ≧ W
It is desirable to use the method for manufacturing a trench MOS type silicon carbide semiconductor device according to claim 2, wherein the relationship is established.

According to the invention of claim 4, in the long side direction of the trench, the length is Lt, the width is Wt, the length of the bottom convex portion is L, the width is W, and the height. Is h, the number is n, the thermal oxide film thickness at the time of forming the oxide film at the bottom of the trench is tox, and the convex portions are periodically formed in the long side direction of the trench, Wt = W, Lt = (2n + 1) ) × L, h ≧ tox ≧ W
It is also desirable to adopt a method for manufacturing a trench MOS type silicon carbide semiconductor device according to claim 2, wherein the relationship is established.

According to the present invention, a trench MOS type carbonization that can increase the dielectric breakdown strength by increasing the thickness of the SiO ₂ film at the bottom of the trench without using damage to the crystal plane caused by a fast oxidation rate or an ion beam. A method for manufacturing a silicon semiconductor device can be provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
FIG. 1 shows a MOS type silicon carbide semiconductor substrate according to Example 1 of the present invention, in which a method of forming irregularities parallel to the long side of the trench at the bottom of the trench is sequentially shown by (a), (b), (c). It is sectional drawing which cut | disconnected this trench part with the line orthogonal to a trench long side. FIG. 2 is a plan view (a) of a trench portion of a MOS type silicon carbide semiconductor substrate for explaining a method of forming a thick oxide film at the bottom of the trench according to Embodiment 1 of the present invention, and is orthogonal to the long side of the trench. It is sectional drawing (b), (c) cut | disconnected by the line. FIG. 3 shows a MOS type silicon carbide semiconductor according to a second embodiment of the present invention, showing a method of forming a concavo-convex shape in which a plurality of concavo-convex formed in the direction orthogonal to the long side of the trench is repeated in the long side direction in parallel with each other. It is sectional drawing (a), (b) which cut | disconnected the trench part of the board | substrate with the line parallel to a trench long side. FIG. 4 is a plan view (a) of a trench portion of a MOS type silicon carbide semiconductor substrate showing a method of forming a thick oxide film at the bottom of the trench according to Example 2 of the present invention, and a line parallel to the long side of the trench. It is sectional drawing (b) and (c) which cut | disconnected.

As shown in FIG. 1A, an n-type silicon carbide semiconductor substrate 1 having a Si surface as a main surface, an n-type epitaxial silicon carbide thin film 2 serving as a drift layer having a thickness of 10 μm, and a p-type epitaxial silicon carbide serving as a p base layer. A thin film 3 is formed with a thickness of 2 μm, and an n-type epitaxial silicon carbide thin film 4 serving as an n ⁺ -type source region is formed with a thickness of 0.5 μm in this order. After this laminated semiconductor substrate is pyrogenic oxidized at 1100 ° C. for 1 hour, an Al film is sputtered by 0.2 μm, and the Al film is patterned by a photo process to form an Al film mask 5. Using this Al film mask 5, anisotropic etching is performed by ICP plasma using SF ₆ and O ₂ gas to form a trench 6 that reaches the n-type epitaxial silicon carbide thin film 2 perpendicularly from the surface. The trench 6 has a long side length of 100 μm and a short side length of 0.3 μm. A plurality of trenches are arranged in the element.

Next, as shown in FIG. 1B, after the Al film 5 is temporarily removed, a new Al film is sputtered again by 0.2 μm, and the Al film is patterned by a photo process to form an Al film mask 7. . Next, as shown in FIG. 1C, by using this Al film mask 7, ICP plasma etching is again performed using SF ₆ and O ₂ gas to form an uneven portion 8 at the bottom of the trench.
As shown in the plan view of the trench portion in FIG. 2A and the cross-sectional view in FIG. 2B, the uneven portion 8 has a shape having a convex portion formed in parallel to the trench long side direction at the bottom of the trench. The convex portions are formed at a distance of 0.1 μm from the side wall in the long side direction of the trench. The width of the convex portion in the short side direction of the trench is 0.1 μm, and the length of the convex portion in the long side direction of the trench is the same as the length in the long side direction of the trench.

A thermal oxidation film 9 having a thickness of 0.1 μm is formed by thermally oxidizing the laminated semiconductor substrate having the uneven portion 8 at the bottom of the trench in a wet atmosphere (FIG. 2C). During thermal oxidation, 0.05 μm oxidation proceeds on the SiC side of the protrusion, and a 0.05 μm SiO ₂ film grows (or expands) outside the SiC. By this way the SiO ₂ film of the convex portion is in contact with the SiO ₂ film and mutual convex portions adjacent to grow the trench short side direction, is completed structure unevenness of the trench bottom to form all thick SiO ₂ film . Here, it is important to set the depth of the trench and the shape of the uneven portion so that the upper surface of the newly formed SiO ₂ film at the bottom of the trench is located deeper than the p base layer 3 of the trench MOSFET. is there.

In addition, the various numerical values used for description of the above Example 1 are examples, and can be changed in the range which satisfies the relational expression demonstrated below. The length of the long side direction of the trench is Lt, the width is Wt, the length of the bottom protrusion is L, the width is W, the height is h, the number is n, and the thermal oxide film thickness at the time of forming the trench bottom oxide film Let tox be a mutual,
Lt = L, Wt = (2n + 1) × W, h ≧ tox ≧ W
It is preferable that the numerical value has a relationship satisfying the above.

  Furthermore, in Example 1, the first silicon carbide semiconductor substrate has the Si surface as the main surface, but the same effect can be obtained by using other crystal surfaces. The same effect can be obtained by changing the direction of the long side and the short side of the trench.

An n-type epitaxial silicon carbide thin film 2 serving as a drift layer is formed to 10 μm on an n-type silicon carbide semiconductor substrate 1 having a Si surface as a main surface, and a p-type epitaxial silicon carbide thin film 3 serving as a P base layer is formed to 2 μm. ^An n-type epitaxial silicon carbide thin film 4 to be a ⁺ -type source region is formed in the order of 0.5 μm. After this laminated semiconductor substrate is pyrogenic oxidized at 1100 ° C. for 1 hour, an Al film is sputtered by 0.2 μm, and the Al film is patterned by a photo process to form an Al film mask 5. Using this Al film mask 5, anisotropic etching by ICP plasma is performed using SF ₆ and O ₂ gas to form a trench 6 that reaches the n-type epitaxial silicon carbide thin film 2 perpendicularly from the surface.

  The trench has a long side length Lt of 100 μm and a short side length Wt of 0.15 μm. A plurality of trenches are arranged in the element. After removing the Al film, the Al film is again sputtered to a thickness of 0.2 μm, and the Al film is patterned by a photo process. The Al films perpendicular to the long side of the bottom of the trench are repeatedly arranged in parallel in the long side direction. A shaped Al film pattern 7 is formed (FIG. 3A).

Using this Al film mask 7, anisotropic etching is performed perpendicularly from the bottom surface by ICP plasma using SF ₆ and O ₂ gas to form the uneven portion 8 at the bottom of the trench (FIG. 3B).
As shown in the trench plan view of FIG. 4A, the uneven portion 8 at the bottom of the trench has an uneven portion 8 in which convex portions orthogonal to the long sides of the trench are formed in parallel with each other at the bottom of the trench. It has a shape that is repeatedly arranged in the side direction. Protrusions are present at intervals of 0.1 μm from the side walls of the short sides of the trenches, and the next protrusions are arranged in parallel with each other at an interval of 0.1 μm. In other words, the width of the convex portions is 0.1 μm and is arranged in parallel with each other at intervals of 0.1 μm in the trench long side direction, and the width of the convex portions in the trench short side direction is the same as the width in the trench short side direction 0 .15 μm.

A thermal oxidation film 9 having a thickness of 0.1 μm is formed by thermally oxidizing the laminated semiconductor substrate having the uneven portion 8 at the bottom of the trench in a wet atmosphere (FIG. 4C). At this time, 0.05 μm oxidation proceeds on the SiC side (convex portion side), and a 0.05 μm SiO ₂ film grows (expands) outside the SiC. This SiO ₂ film of the convex portion is in contact with the SiO ₂ film and mutual convex portions adjacent to grow to the trench long side direction a structure to form a thick SiO ₂ film of the trench bottom.

Here, as in the first embodiment, the depth of the trench and the shape of the uneven portion are set so that the upper surface of the SiO ₂ film at the bottom of the trench is located deeper than the p base layer 3 of the trench MOSFET. This is very important.
In addition, the various numerical values used for description of the above Example 2 are an example, and can be changed in the range which satisfies the relational expression demonstrated below similarly to Example 1. FIG. The length of the long side direction of the trench is Lt, the width is Wt, the length of the bottom protrusion is L, the width is W, the height is h, the number is n, and the thermal oxide film thickness at the time of forming the trench bottom oxide film Let tox be a mutual,
Wt = W, Lt = (2n + 1) × L, h ≧ tox ≧ W
It is preferable that the numerical value has a relationship satisfying the above.

  Further, in this Example 2, the Si surface is the main surface, but the same effect can be obtained even if another crystal surface is used.

It is principal part sectional drawing of the MOS type silicon carbide semiconductor device board | substrate which shows the method concerning Example 1 of this invention and forming the unevenness | corrugation parallel to the long side of a trench in the bottom part of a trench. It is principal part sectional drawing of the semiconductor substrate which shows the method concerning Example 1 of this invention and forms a thick oxide film in the bottom part of a trench. It is principal part sectional drawing of the semiconductor substrate which shows the method concerning Example 2 of this invention, and shows the method of forming the unevenness | corrugation formed in the direction orthogonal to the long side of a trench, and the unevenness | corrugation repeated in parallel in the long side direction. It is principal part sectional drawing of the semiconductor substrate which shows the method concerning Example 2 of this invention and forms a thick oxide film in the bottom part of a trench. It is sectional drawing of 1 cell pitch of the conventional trench type MOSFET. It is sectional drawing of 1 cell pitch of the conventional common DIMOSFET. It is a figure which shows together the principal part sectional drawing of the conventional trench type MOSFET, and the electric field strength distribution figure of a pn structure part and a MOS structure part.

Explanation of symbols

1, one conductivity type silicon carbide semiconductor substrate, n-type silicon carbide semiconductor substrate,
2, one conductivity type epitaxial silicon carbide thin film, n type epitaxial silicon carbide thin film, drift layer 3, other conductivity type epitaxial silicon carbide thin film, p type epitaxial silicon carbide thin film, p base layer 4, one conductivity type epitaxial silicon carbide Thin film, n ⁺ type epitaxial silicon carbide thin film, n ⁺ type source region 5, Al film pattern 6, Trench 7, Al film pattern 8, Uneven portion Lt Length of trench long side direction Wt Trench long side Width in direction L, ... Length of convex part W, ... Width of convex part tox ... Thermal oxide film thickness at the bottom of the trench.

Claims (4)

A first one conductivity type epitaxial silicon carbide thin film, another conductivity type epitaxial silicon carbide thin film, and a second one conductivity type epitaxial silicon carbide thin film were formed in this order on a one conductivity type silicon carbide semiconductor substrate having a Si surface as a main surface. Thereafter, a step of forming a trench reaching the first one-conductivity-type epitaxial silicon carbide thin film using an Al film mask, and forming irregularities on the bottom of the trench using a re-formed Al film mask, and subsequent thermal oxidation A method of manufacturing a trench MOS type silicon carbide semiconductor device having a step, wherein the step of forming the irregularities has a convex portion interval such that the convex portions changed into oxide films by a subsequent thermal oxidation step are in contact with each other. A method of manufacturing a trench MOS type silicon carbide semiconductor device, characterized by being a step processed into a concavo-convex shape. 2. The method of manufacturing a trench MOS type silicon carbide semiconductor device according to claim 1, wherein the convex portion at the bottom of the trench is periodically formed in parallel with either the short side direction or the long side direction of the trench bottom portion. . When forming the oxide film at the bottom of the trench, the length in the long side direction of the trench is Lt, the width is Wt, the bottom protrusion is L, the width is W, the height is h, and the number is n. If the thermal oxide film thickness is tox, and convex portions are periodically formed in the short side direction of the trench, Lt = L, Wt = (2n + 1) × W, h ≧ tox ≧ W
The method of manufacturing a trench MOS type silicon carbide semiconductor device according to claim 2, wherein: When forming the oxide film at the bottom of the trench, the length in the long side direction of the trench is Lt, the width is Wt, the bottom protrusion is L, the width is W, the height is h, and the number is n. If the thermal oxide film thickness is tox and convex portions are periodically formed in the long side direction of the trench, Wt = W, Lt = (2n + 1) × L, h ≧ tox ≧ W
The method of manufacturing a trench MOS type silicon carbide semiconductor device according to claim 2, wherein:

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