JP2008077750A - Nonvolatile semiconductor memory device - Google Patents

Abstract

A non-volatile semiconductor memory device capable of preventing over-precharge and increasing the speed of reading information is provided.
A NOR flash memory (nonvolatile semiconductor memory device) 1 includes a memory cell array 11, a dummy memory cell array (reference circuit) 12, a sense amplifier 13, load circuits 14 and 15, a precharge circuit 16, and 17 and a reference voltage generation circuit 20. A control signal FX supplied from the regulator 21 of the reference voltage generation circuit 20 is supplied to the gate electrode of the transistor T20 of the precharge circuit 16, and this transistor T20 prevents over precharge to the sense node N1.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device that reads data stored in a memory cell by precharging a bit line with a sense amplifier.

  As shown in FIG. 6, the NOR flash memory 100 includes a memory cell array 101, a dummy memory cell array (reference circuit) 102, a sense amplifier 103, load circuits 104 and 105, and precharge circuits 106 and 107. ing. In the memory cell array 101, memory cells M1 that store 1-bit information are arranged at intersections between the bit lines BL1 and the word lines WL, and a plurality of the memory cells M1 are arranged in a matrix. In dummy memory cell array 102, dummy memory cell M0 is arranged between dummy bit line BL0 and select line SCT. A parasitic capacitance C1 is added to the bit line BL1, and a parasitic capacitance C0 is added to the dummy bit line BL0.

  The sense amplifier 103 supplies p-channel conductive transistors (MOSFETs) T9 and T11 sharing the source region, n-channel conductive transistors T10 and T12 sharing the source region, and p for supplying the power supply voltage Vdd to the transistors T9 and T11. And a channel conductivity type transistor T13. The drain region of the transistor T9 and the drain region of the transistor T10 are connected, and an output terminal OUT that outputs information stored in the memory cell M1 is connected to the drain region. The drain region of the transistor T11 and the drain region and gate electrode of the transistor T12 are connected. The gate electrode of the transistor T10 and the gate electrode of the transistor T12 are connected. The gate electrode of the transistor T9 is connected to the precharge circuit 106 through the sense node N1 of the sense amplifier 103, and the gate electrode of the transistor T11 is connected to the precharge circuit 107 through the dummy sense node N0.

  The load circuit 104 is configured by a series circuit of a p-channel conductivity type transistor T5 and an n-channel conductivity type transistor T6. The source region of the transistor T5 is connected to the source region of the transistor T9 of the sense amplifier 103, and the gate electrode is connected to the gate electrode of the transistor T9. That is, the transistors T5 and T9 are mirror circuits. The source region of the transistor T6 is connected to the bit line BL1. The drain regions of the transistors T5 and T6 are connected to the sense node N1 of the sense amplifier 103. The load circuit 105 is constituted by a series circuit of a p-channel conductivity type transistor T7 and an n-channel conductivity type transistor T8. The source region of the transistor T7 is connected to the source region of the transistor T11 of the sense amplifier 103, and the gate electrode is connected to the gate electrode of the transistor T11. Similarly, the transistors T7 and T11 are mirror circuits. The source region of the transistor T8 is connected to the dummy bit line BL0. The drain regions of the transistors T7 and T8 are connected to the dummy sense node N0 of the sense amplifier 103.

  The precharge circuit 106 is constituted by a series circuit of a p-channel conductivity type transistor T1 and a transistor T2. The source region of the transistor T1 is connected to the power supply voltage Vdd, and the drain region and gate electrode of the transistor T2 are connected to the sense node N1 of the sense amplifier 103. The precharge circuit 107 is constituted by a series circuit of p-channel conductivity type transistors T3 and T4. The source region of the transistor T3 is connected to the power supply voltage Vdd, and the drain region and gate electrode of the transistor T4 are connected to the dummy sense node N0 of the sense amplifier 103.

  Next, the information reading operation of the NOR flash memory 100 will be described with reference to FIG. Here, it is assumed that L (row) data is stored in the memory cell M1. First, in a steady state before data access, the bit lines BL1 and BL0, the sense node N1 of the sense amplifier 103 that is the output line of the load circuit 104, the dummy sense node N0 of the sense amplifier 103 that is the output line of the load circuit 105, All the output terminals OUT of the sense amplifier 103 are at L level.

  At the time of data access, when the word line WL is set to the H (high) level, the memory cell M1 connected to the word line WL is turned on. Similarly, when select line SCT is set to H level, dummy memory cell M0 connected to select line SCT is turned on. In the sense amplifier 103, when the signal SAONB changes from H level to L level, the transistor T13 changes from the OFF state to the ON state. As a result, the current i1 flows from the transistor T5 to the memory cell M1 through the bit line BL1, and the sense node N1 of the sense amplifier 103 changes from the L level to the level corresponding to the current i1. At the same time, in the sense amplifier 103, the current i0 flows from the transistor T7 to the dummy memory cell M0 through the dummy bit line BL0, and the dummy sense node N0 changes from the L level to the level corresponding to the current i0. When the amplitude difference between the sense node N1 and the dummy sense node N0 becomes about 100 mV, the H level is output to the output terminal OUT of the sense amplifier 103.

  When the power supply voltage Vdd is 1.6 V, about 0.95 V is output to the sense node N1 of the sense amplifier 103 in the DC state. About 1.25 V is output to the dummy sense node N0. A gate signal BS of about 0.8 V is applied to each of the gate electrode of the transistor T6 of the load circuit 104 and the gate electrode of the transistor T8 of the load circuit 105.

  The precharge circuit 106 precharges the sense node N1 of the sense amplifier 103 in advance. Since the parasitic capacitance C1 of the bit line BL1 is added to the sense node N1, and it takes time to charge the sense node N1 with a minute current i1, the output signal to the output terminal OUT of the sense amplifier 103 is delayed. This causes a delay in access time in the information read operation of the NOR flash memory 100. Similarly, the precharge circuit 107 precharges the dummy sense node N0 of the sense amplifier 103 in advance.

  The precharge circuit 106 changes the signal ACCB applied to the gate electrode of the transistor T1 from the H level to the L level at the timing when the word line WL connected to the memory cell M1 is activated, and changes the signal ACCB from the power supply voltage Vdd to the transistor. A precharge current is supplied to the sense node N1 at high speed through T2. Similarly, the precharge circuit 107 changes the signal ACCB applied to the gate electrode of the transistor T3 from the H level to the L level at the timing when the select line SCT connected to the dummy memory cell M0 is activated. A precharge current is supplied from the voltage Vdd to the dummy sense node N0 through the transistor T4 at high speed. As described above, in the information reading operation, by precharging each of the sense node N1 and the dummy sense node N0 in advance, the charging time can be shortened and the access time can be increased.

  Further, in each of the transistor T6 of the load circuit 104 and the transistor T8 of the load circuit 105, the threshold voltage is set to 0V and the gate signal BS is set to about 0.8V, so that the bit line BL1 and the dummy bit line BL0 are set. Neither of them exceeds 0.8V during precharge. That is, when the bit line BL1 becomes 0.8V or more, the transistor T6 is turned off, and when the dummy bit line BL0 becomes 0.8V or more, the transistor T8 is turned off. By restricting the precharge voltage supplied to the bit line BL1, erroneous rewriting of data stored in the memory cell M1 can be prevented.

  A semiconductor memory device that performs a precharge operation is described in, for example, Patent Document 1 below.

JP-A-3-2636933

  In the above-described NOR flash memory 100, the following points have not been considered. In the transistors T1 and T2 of the precharge circuit 106 and the transistors T3 and T4 of the precharge circuit 107, the manufacturing process may vary, and the current driving capability may exceed the design value. In the NOR type flash memory 100 having such precharge circuits 106 and 107, as shown in FIG. 7, the sense node N1 and the dummy sense node N0 of the sense amplifier 103 rise and enter an overprecharge state at the beginning. When the power supply voltage Vdd is 1.6 V, as described above, when the amplitude difference between the sense node N1 of the sense amplifier 103 and the dummy sense node N0 is about 100 mV, the H level is output to the output terminal OUT of the sense amplifier 103. The However, in the over precharge state, it takes time until the amplitude difference becomes 100 mV, and as a result, the time until the H level is output to the output terminal OUT of the sense amplifier 103 becomes longer. For this reason, a delay occurs in the access time.

  Furthermore, since the transistor T2 of the precharge circuit 106 and the transistor T4 of the precharge circuit 107 are both configured by p-channel conductivity type transistors, the mobility of the transistors T2 and T4 is smaller than that of the n-channel conductivity type transistor. Accordingly, the transistor sizes of the transistors T2 and T4 are increased in order to ensure the current driving capability, and the parasitic capacitance is increased. Therefore, the time required to charge the sense node N1 and the dummy sense node N0 is increased, and as a result, There is a delay in access time.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to prevent non-precharge and to realize a high-speed information reading operation speed. Is to provide a device.

  Furthermore, an object of the present invention is to provide a nonvolatile semiconductor memory device that can reduce the parasitic capacitance of a precharge circuit and can realize an increase in information reading operation speed.

  A feature of one embodiment of the present invention is that in a nonvolatile semiconductor memory device, a memory cell and the memory cell are connected to a sense node via a bit line, and the voltage of the sense node is sensed and stored in the memory cell. A sense amplifier for reading data, a load element connected to the sense node, a precharge transistor for charging the sense node, and a voltage limiting transistor for limiting an overcharge voltage of the sense node. This voltage limiting transistor is also provided on the dummy sense node side. Furthermore, the voltage limiting transistor is formed of an n-channel conductivity type.

  The nonvolatile semiconductor memory device preferably further includes a reference voltage generation circuit that supplies a control voltage for controlling the overcharge voltage to the gate electrode of the voltage control transistor. The reference voltage generation circuit preferably further includes a band gap reference potential generation circuit that generates a reference voltage from the power supply voltage, and a regulator that generates a control voltage from the reference voltage output from the band gap reference potential generation circuit. .

  According to the present invention, it is possible to provide a non-volatile semiconductor memory device that can prevent over-precharge and realize an increase in information reading operation speed.

  Furthermore, according to the present invention, it is possible to provide a non-volatile semiconductor memory device that can reduce the parasitic capacitance of the precharge circuit and can realize an increase in information reading operation speed.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the present embodiment, an example in which the present invention is applied to a NOR flash memory (NOR EEPROM) will be described.

[Configuration of Nonvolatile Semiconductor Memory Device Circuit System]
As shown in FIG. 1, a NOR flash memory (nonvolatile semiconductor storage device) 1 according to an embodiment of the present invention includes a memory cell array 11, a dummy memory cell array (reference circuit) 12, a sense amplifier 13, Load circuits 14 and 15, precharge circuits 16 and 17, and a reference voltage generation circuit 20 are provided.

  In the memory cell array 11, memory cells M1 that store 1-bit information are arranged at intersections between the bit lines BL1 and the word lines WL, and a plurality of the memory cells M1 are arranged in a matrix. In the present embodiment, an n-channel conductivity type field effect transistor having a charge storage layer (floating gate electrode) and a control electrode (control gate electrode) can be practically used for the memory cell M1. The word line WL is integrated with and electrically connected to the control electrode of the memory cell M1. The bit line BL1 is connected to the drain region of the memory cell M1, and is composed of, for example, an aluminum alloy wiring that is above the word line WL. A source line (reference power supply Vss) is connected to the source region of the memory cell M1.

  In dummy memory cell array 102, dummy memory cell M0 is arranged at the intersection of dummy bit line BL0 and select line SCT. The dummy memory cell M0 is basically composed of an n-channel conductivity type field effect transistor, like the memory cell M0. A select line SCT is connected to the gate electrode of the dummy memory cell M0, a dummy bit line BL0 is connected to the drain region, and a source line (reference power supply Vss) is connected to the source region.

  A parasitic capacitance C1 is added to the bit line BL1, and a parasitic capacitance C0 is added to the dummy bit line BL0.

  The sense amplifier 13 includes p-channel conductive transistors (MISFETs) T9 and T11 that share a source region, n-channel conductive transistors T10 and T12 that share a source region, and transistors T9 and T11. And a p-channel conductive transistor T13 for supplying a power supply voltage Vdd. The drain region of the transistor T9 and the drain region of the transistor T10 are connected to each other, and an output terminal OUT that outputs information stored in the memory cell M1 is connected to the drain region. The drain region of the transistor T11 and the drain region and gate electrode of the transistor T12 are connected. The gate electrode of the transistor T10 and the gate electrode of the transistor T12 are connected. The gate electrode of the transistor T9 is connected to the precharge circuit 16 through the sense node N1 of the sense amplifier 13. Similarly, the gate electrode of the transistor T11 is connected to the precharge circuit 17 through the dummy sense node N0 of the sense amplifier 13.

  The load circuit 14 includes a series circuit of a p-channel conductivity type transistor (first load element) T5 and an n-channel conductivity type transistor T6. The source region of the transistor T5 is connected to the source region of the transistor T9 of the sense amplifier 13, and the gate electrode is connected to the gate electrode of the transistor T9. That is, the transistors T5 and T9 are mirror circuits. The source region of the transistor T6 is connected to the bit line BL1. The drain regions of the transistors T5 and T6 are connected to the sense node N1 of the sense amplifier 13. The load circuit 105 is configured by a series circuit of a p-channel conductivity type transistor (second load element) T7 and an n-channel conductivity type transistor T8. The source region of the transistor T7 is connected to the source region of the transistor T11 of the sense amplifier 103, and the gate electrode is connected to the gate electrode of the transistor T11. Similarly, the transistors T7 and T11 are mirror circuits. The source region of the transistor T8 is connected to the dummy bit line BL0. The drain regions of the transistors T7 and T8 are connected to the dummy sense node N0 of the sense amplifier 103.

  The precharge circuit 16 includes a p-channel conductive transistor (first precharge transistor) T1 that precharges the sense node N1, and an n-channel conductive transistor (first voltage) that limits the overcharge voltage of the sense node N1. It is constituted by a series circuit with a limiting transistor T20. The source region of the transistor T1 is connected to the power supply voltage Vdd, and the source region of the transistor T20 is connected to the sense node N1 of the sense amplifier 13. The gate electrode of the transistor T20 is connected to a reference voltage generation circuit 20 that supplies a control voltage FX that controls the overcharge voltage. Since the transistor T20 is formed of an n-channel conductivity type, and the electron mobility is larger than the hole mobility, the transistor size of the transistor T20 can be reduced when the equivalent current driving capability is ensured. . Then, by supplying the control voltage FX to the gate electrode of the transistor T20, the gate capacitance of the transistor T20 is not added to the sense node N1. That is, the parasitic capacitance added to the sense node N1 can be reduced, and the charging speed of the sense node N1 can be increased. The reduction in the parasitic capacitance of the transistor T20 results in a reduction in the overall parasitic capacitance of the precharge circuit 16.

  Similarly, the precharge circuit 17 includes a p-channel conductive transistor (second precharge transistor) T3 that precharges the dummy sense node N0 and an n-channel conductive transistor that controls the overcharge voltage of the dummy sense node N0. (Second voltage limiting transistor) It is constituted by a series circuit with T40. The source region of the transistor T3 is connected to the power supply voltage Vdd, and the source region of the transistor T40 is connected to the dummy sense node N0 of the sense amplifier 13. A reference voltage generation circuit 20 is connected to the gate electrode of the transistor T40, and a control voltage FX for controlling the overcharge voltage is supplied. Further, similarly, the transistor T40 is formed of an n-channel conductivity type, and the electron mobility is larger than the hole mobility. Therefore, in order to ensure an equivalent current driving capability, the transistor size of the transistor T40 is increased. Can be small. Then, by supplying the control voltage FX to the gate electrode of the transistor T40, the gate capacitance of the transistor T40 is not added to the dummy sense node N0. That is, the parasitic capacitance added to the dummy sense node N0 can be reduced, and the charging speed of the dummy sense node N0 can be increased. The reduction in the parasitic capacitance of the transistor T40 results in a reduction in the overall parasitic capacitance of the precharge circuit 17.

[Configuration of reference voltage generation circuit]
As shown in FIG. 2, the reference voltage generation circuit 20 includes a band gap reference potential generation circuit (BGR circuit) 22 that generates a reference voltage VREF from a power supply voltage VEXT outside the NOR flash memory (semiconductor chip) 1, and a band A regulator 21 for generating a control voltage FX supplied to the gate electrode of the transistor T20 of the precharge circuit 16 and the gate electrode of the transistor T40 of the precharge circuit 17 from the reference voltage VREF output from the gap reference potential generation circuit 22; It has.

  The band gap reference potential generation circuit 22 includes p-channel conductivity type transistors TB1 to TB7, n-channel conductivity type transistors TB11 to TB14, diodes D1 to D3, and resistors R1 and R2. In the bandgap reference potential generation circuit 22, as shown in FIG. 3, when the power supply voltage VEXT becomes equal to or higher than a predetermined voltage level, the reference voltage VREF becomes a constant voltage level that does not depend on the voltage level of the power supply voltage VEXT.

  The regulator 21 includes p-channel conductive transistors TB8 to TB10, n-channel conductive transistors TB15 to TB17, and resistors R3 and R4. The control voltage (control signal) FX output from the regulator 21 is supplied to the gate electrode of the transistor T20 of the precharge circuit 16 and the gate electrode of the transistor T40 of the precharge circuit 17.

At the time of data access of the memory cell M1, the control voltage FX supplied from the regulator 21 is given a voltage level equal to that of the dummy sense node N0 of the sense amplifier 13. As shown in FIG. 4, the regulator 21 outputs a control voltage FX having a slightly higher voltage level in the present embodiment in accordance with the voltage level of the reference voltage VREF. The voltage level of the control voltage FX can be expressed by the following equation (1).

For example, when the voltage level V (VREF) of the reference voltage VREF output from the regulator 21 is 1.2 V, when the resistance ratio between the resistors R3 and R4 is set as in the following equation (2), the control voltage FX The voltage level V (FX) becomes 1.25V.

[Information reading operation of nonvolatile semiconductor memory device]
Next, in the information reading operation of the NOR flash memory 1 according to the present embodiment, it is assumed that L data is stored in the memory cell M1, and FIG. 5 is used with reference to FIGS. 1 to 4 described above. I will explain.

  First, as shown in FIG. 5, in a steady state before data access, the bit line BL1 and dummy bit line BL0, the sense node N1 and dummy sense node N0 of the sense amplifier 13, and the output terminal OUT of the sense amplifier 13 are all at L level. It is in. Here, in FIG. 5, a plurality of voltage levels are shown together, and the portions of the same voltage level are shown slightly shifted for the sake of convenience.

  At the time of data access, when the word line WL is set to H level, the gate electrode of the memory cell M1 becomes H level, and the memory cell M1 is turned on. At the same time, the select line SCT is set to H level, the gate electrode of the dummy memory cell M0 becomes H level, and the dummy memory cell M0 is turned on.

  In the sense amplifier 13, when the signal SAONB changes from H level to L level, the transistor T13 changes from OFF state to ON state. As a result, the current i1 flows from the transistor T5 to the memory cell M1 through the bit line BL1, and the sense node N1 of the sense amplifier 13 changes from the L level to the level corresponding to the current i1. At the same time, in the sense amplifier 13, the current i0 flows from the transistor T7 to the dummy memory cell M0 through the dummy bit line BL0, and the dummy sense node N0 changes from the L level to the level corresponding to the current i0. At this time, since the current driving capability of the dummy memory cell M0 is set so that the relationship of current i0 <current i1 is established, the relationship between the voltage level of the sense node N1 of the sense amplifier 13 and the voltage level of the dummy sense node N0. N1 <N0.

  Here, when the power supply voltage Vdd is 1.6 V, when the amplitude difference between the sense node N1 of the sense amplifier 13 and the dummy sense node N0 is about 100 mV, the output terminal OUT of the sense amplifier 13 which has been at the L level. Changes to H level. When the power supply voltage Vdd is 1.6V, the dummy sense node N0 is about 1.25V and the sense node N1 is about 0.95V in the DC state. Then, a signal BS of about 0.8 V is supplied to the gate electrodes of the transistor T6 of the load circuit 14 and the transistor T8 of the load circuit 15.

  Next, the precharge circuit 16 precharges the sense node N1 of the sense amplifier 13, and the precharge circuit 17 precharges the dummy sense node N0 of the sense amplifier 13. The precharge circuit 16 changes the signal ACCB applied to the gate electrode of the transistor T1 from the H level to the L level at the timing when the word line WL connected to the memory cell M1 is activated, and changes the signal ACCB from the power supply voltage Vdd to the transistor. (First voltage limiting transistor) A precharge current is supplied to the sense node N1 at high speed through T20. Since the parasitic capacitance of the sense node N1 is reduced, the precharge current can be supplied even faster.

  At this time, the transistor T20 of the precharge circuit 16 is supplied with the control voltage FX of a constant voltage that does not reach the overcharge voltage to the gate electrode, and is therefore supplied from the power supply voltage Vdd to the sense node N1 through the transistor T1. Current can be limited to prevent over precharge. Specifically, the external power supply voltage VEXT shown in FIG. 2 is converted into the reference voltage VREF in the band gap reference potential generation circuit 22 of the reference voltage generation circuit 20, and the stable control voltage FX, for example, in the regulator 21 is converted from the reference voltage VREF. Since 1.25V is generated, the threshold voltage Vth of the transistor T20 can be controlled to 0V, and the sense node N1 is not precharged exceeding 1.25V. When the sense node N1 exceeds 1.25 V, the transistor T20 is turned off in the precharge circuit 16, and no current is supplied from the power supply voltage Vdd to the sense node N1 through the transistor T1.

  Similarly, the precharge circuit 17 changes the signal ACCB applied to the gate electrode of the transistor T3 from the H level to the L level at the timing when the select line SCT connected to the dummy memory cell M0 is activated. A precharge current is supplied from the voltage Vdd to the dummy sense node N0 through the transistor T4 at high speed. Since the parasitic capacitance of the dummy sense node N0 is reduced, the precharge current can be supplied even faster. At this time, the transistor T40 of the precharge circuit 17 is supplied with the control voltage FX having a constant voltage that does not reach the overcharge voltage to the gate electrode thereof, and is supplied from the power supply voltage Vdd to the dummy sense node N0 through the transistor T3. Current can be limited to prevent over precharge. Specifically, since a stable control voltage FX, for example, 1.25V is generated from the reference voltage generation circuit 20, the threshold voltage Vth of the transistor T40 can be controlled to 0V, and the dummy sense node N0 has 1.25V. It is not precharged beyond. When the dummy sense node N0 exceeds 1.25V, the transistor T40 is turned off in the precharge circuit 17, and no current is supplied from the power supply voltage Vdd to the dummy sense node N0 through the transistor T3.

  In the NOR flash memory 1 according to the present embodiment configured as described above, the charging time is shortened by precharging each of the sense node N1 and the dummy sense node N0 in advance in the information reading operation. The transistor T20 of the precharge circuit 16 can prevent the sense node N1 from being overprecharged, and the transistor T40 of the precharge circuit 17 can prevent the dummy sense node N0 from being overprecharged. As a result, it is possible to prevent the access time from being delayed due to the overprecharge, so that the access time of the information read operation of the NOR flash memory 1 can be increased.

  Furthermore, since the transistor T20 of the precharge circuit 16 and the transistor T40 of the precharge circuit 17 are each composed of an n-channel conductivity type transistor, the parasitic capacitance added to each of the precharge circuits 16 and 17 can be reduced. Therefore, the access time of the information read operation of the NOR flash memory 1 can be increased.

(Other embodiments)
The present invention is not limited to the one embodiment described above, and various modifications can be made without departing from the scope of the invention. For example, the present invention can be applied to a NAND flash memory in which a plurality of memory cells are connected in series in a bit configuration unit as a nonvolatile semiconductor memory device.

  Further, the present invention is not limited to a single device in which only flash memory (including peripheral circuits of flash memory) is mounted on a semiconductor chip, but also includes flash memory, logic, other nonvolatile memory, and volatile memory on the same semiconductor chip. It can be applied to a composite device such as a CPU or MPU.

1 is a system circuit diagram of a NOR type flash memory according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a reference voltage generation circuit of the NOR flash memory shown in FIG. 1. FIG. 3 is a diagram showing output characteristics of a reference voltage with respect to an external power supply voltage in the reference voltage generation circuit shown in FIGS. 1 and 2. FIG. 3 is a diagram showing output characteristics of a reference voltage and a control voltage with respect to an external power supply voltage in the reference voltage generation circuit shown in FIGS. 1 and 2. 2 is a time chart showing an information reading operation in the NOR flash memory shown in FIG. 1 is a system circuit diagram of a NOR type flash memory for explaining the prior art of the present invention. FIG. 7 is a time chart showing an information reading operation in the NOR flash memory shown in FIG. 6.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 NOR type flash memory 11 Memory cell array 12 Dummy memory cell array 13 Sense amplifier 14, 15 Load circuit 16, 17 Precharge circuit 20 Reference voltage generation circuit 21 Regulator 22 Band gap reference potential generation circuit T1, T3, T5-T13, T20, T40, TB1 to TB17 Transistor M1 memory cell M0 dummy memory cell N1 sense node N0 dummy sense node

Claims (5)

A memory cell;
A sense amplifier which is connected to a sense node via a bit line, senses the voltage of the sense node, and reads data stored in the memory cell;
A first load element connected to the sense node;
A first precharge transistor for charging the sense node;
A first voltage limiting transistor for limiting an overcharge voltage of the sense node;
A nonvolatile semiconductor memory device comprising: A dummy memory cell;
The sense amplifier connected to the dummy sense node via a dummy bit line to the dummy memory cell, and amplifies a difference between the voltage of the dummy sense node and the voltage of the sense node;
A second load element connected to the dummy sense node;
A second precharge transistor for charging the dummy sense node;
A second voltage limiting transistor for limiting an overcharge voltage of the dummy sense node;
The nonvolatile semiconductor memory device according to claim 1, further comprising: The first voltage limiting transistor is an n-channel conductive transistor connected in series between the sense node and the first precharge transistor,
3. The n-channel conductivity type transistor connected in series between the dummy sense node and the second precharge transistor, the second voltage limiting transistor according to claim 1 or 2. The nonvolatile semiconductor memory device described.   A reference voltage generation circuit for supplying a control voltage for limiting an overcharge voltage to each of the gate electrode of the first voltage control transistor and the gate electrode of the second voltage control transistor is further provided. The non-volatile semiconductor memory device according to claim 1.   The reference voltage generation circuit further includes a bandgap reference potential generation circuit that generates a reference voltage from a power supply voltage, and a regulator that generates the control voltage from a reference voltage output from the bandgap reference potential generation circuit. 5. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is a non-volatile semiconductor memory device.

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