JP2008072024A - Mounting structure of semiconductor device - Google Patents

Abstract

The present invention relates to a mounting structure of a semiconductor device, and by making a simple modification to an electrode layout or the like on a circuit wiring board, it is possible to suppress a circuit open defect in a package outer peripheral portion that easily occurs when lead-free solder is used. Thus, a highly reliable mounting structure of a semiconductor device is provided.
In a mounting structure of a semiconductor device, a lead-free solder bump 16 is interposed between an electrode 15 in a package type semiconductor device 14 and an electrode 12 in a circuit wiring board 11, and the both are connected. Positioning bumps 17 provided at any location in the mounting area of the semiconductor device 14, preferably at least one location near the center, and electrodes of the circuit wiring board 11 connected corresponding to the respective electrodes 15 of the semiconductor device 14 12 is selected in advance so that the center coordinates of each electrode 12 substantially coincide with the center coordinates of each electrode 15 of the semiconductor device 14 when heated to reach the solder solidification point for solder reflow connection. It is formed.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device or a mounting structure of a semiconductor device in which a package type semiconductor device such as a BGA (ball grid array) or CSP (chip size package) called an area array type is connected to a circuit wiring board.

  With the miniaturization, high density, and high performance of portable electronic devices and the like, there is a demand for miniaturization and high density mounting of semiconductor devices. To meet these demands, plastic package types called area array types such as BGA and CSP are required. The demand for semiconductor devices has increased significantly.

  Such a plastic package type semiconductor device adopts a structure in which a semiconductor device is connected to a circuit wiring board such as a printed circuit board via a solder bump, and in the conventional structure, the bottom surface of the package is used. Then, solder bumps are formed at a constant pitch, and the solder bumps and desired electrodes on the circuit wiring board side are aligned, and then reflow soldering is performed.

  6 to 8 are cutaway side views showing a main part of a mounting structure composed of a circuit wiring board and a BGA package type semiconductor device for explaining a conventional example, and FIG. 6 aligns the circuit wiring board and the semiconductor device. 7 shows a state where both the circuit wiring board and the BGA package expand by performing reflow heating, and FIG. 8 shows a state where the circuit wiring board and the BGA package contract after being cooled from the state of FIG. Yes.

  In the figure, 11 is a circuit wiring board, 12 is an electrode (land) on the circuit wiring board, 12A is a center electrode, 12B is an outermost peripheral electrode, 13 is a solder resist, 14 is a BGA package type semiconductor device, 15 is Electrodes in a BGA package type semiconductor device, 15A is a center electrode, 15B is an outermost peripheral electrode, 16 is a solder made of Sn-Pb solder, Sn-Ag-Cu (for example, Sn-3.0Ag-0.5Cu) solder, etc. Bumps 16B indicate the outermost solder bumps.

  When a mounting structure as shown in the figure is manufactured, the semiconductor device 14 is used as it is regardless of the presence or absence of warpage in the circuit wiring board 11 on which the electrodes 12 are formed and the thermal expansion characteristics of the circuit wiring board 11. And connected. As the solder material, a material based on Sn—Pb eutectic solder, which has a large elongation and excellent fatigue life characteristics at the solder connection portion, is often used.

  Since the BGA package type semiconductor device 14 to be mounted in this case is electrically connected to the circuit wiring board 11 via the solder bumps 16, it is conductively connected as compared with the case where it is connected to the circuit wiring board 11 via the leads. Since the length is shortened, the high-speed operation characteristics are excellent, and the solder bumps 16 can be formed over the entire bottom surface of the BGA package, which is suitable for a multi-pin structure.

  In this mounting structure, the smaller the diameter of the solder bump 16, the finer the bump pitch. At present, the size of the diameter is about 1 to 1.5 mm with respect to the diameter of 600 to 750 .mu.m. Yes.

  Now, in the circuit wiring board 11 and the BGA package type semiconductor device 14 aligned as shown in FIG. 6, Sn-3.0Ag-0.5Cu is used as the material of the solder bump 16 and is, for example, 50 mm □. In order to solder-connect the BGA package type semiconductor device 14 and the circuit wiring board 11, when the solder bump 16B is heated from room temperature to the solder freezing point, the temperature difference ΔT, BGA when the solder bump 16B on the outermost periphery is cooled from the melting point to room temperature. Due to the relationship between the thermal expansion coefficient and the package size in the package and substrate materials, as shown in FIG. 7, deformation of about 100 μm occurs in the peripheral direction, for example, in the diagonal direction from the package center. In the case of Sn—Ag—Cu solder, the temperature difference ΔT is about 192 ° C. as 221 ° C. → 25 ° C.

  That is, as shown in FIG. 6, at room temperature, the solder bumps are arranged in a layout in which the center coordinates of the electrodes 12 on the circuit wiring board 11 and the electrodes 15 on the BGA package type semiconductor device 14 are matched. As shown in FIG. 7, a reflow connection is performed with 16 interposed.

  Here, for example, when considering the outermost peripheral electrode 12B in the circuit wiring board 11 and the outermost peripheral electrode 15B in the BGA package type semiconductor device 14, both the circuit wiring board 11 and the BGA package type semiconductor device 14 are shown by arrows. However, since the BGA package type semiconductor device 14 is less extended than the circuit wiring board 11, the solder bumps 16B are deformed as shown in FIG. End up.

  When the circuit board 11 and the BGA package type semiconductor device 14 return to room temperature after the reflow connection is finished, as shown by the arrows in FIG. 8, the shrinkage occurs as the cooling progresses. As indicated by the arrow S, the solder bump 16B concentrates on the portion where the cross-sectional area of the cross section is the smallest, and breakage occurs there.

  FIG. 9 is an explanatory side view of the main part showing the amount of misalignment and the solder bump shape at the outermost peripheral part of the circuit wiring board and the BGA package type semiconductor device, and the symbols used in FIGS. Parts designated with the same symbols shall represent identical or equivalent parts. In addition, R and r shall show the cross-sectional area of a solder bump.

  FIG. 9A is an enlarged view of the main part in the state shown in FIG. 8, and L shown in the figure is a circuit wiring board at the time of solder melting of the outermost solder bump 16B. 11 represents the amount of positional deviation between the center of the outermost peripheral electrode 12B in FIG. 11 and the center of the outermost peripheral electrode 15B in the BGA package type semiconductor device 14, and the positional deviation amount L reaches about 100 μm. Then, when cooling to room temperature after solder connection, the same amount of deformation as that when heating from the solder solidification point to the solder melting point is applied to the connection portion of the solder bump 16B.

  As shown in the figure, the longitudinal cross-sectional shape of the solder bump 16B is a shape extending in a parallelogram shape, and is initially spherical and R <r is locally small, that is, R≈r or R> r. FIG. 9B is a diagram for explaining a portion where the stress generated in the solder bump is concentrated. The stress after cooling deformation at the portion indicated by the arrow S in FIG. Since stress concentration occurs, it is easy to break. As a result of simulation, the maximum stress reached 63 MPa in the case of SnAgCu.

  Also, in recent years, consideration has been required for the influence of lead contained in solder on the environment, and its use is regulated. Therefore, it does not contain lead, that is, a solder material containing Sn as a main component as lead-free solder. For example, use of a solder material made of Sn—Ag—Cu or the like has been promoted.

Such a solder material is a material having a melting point of 217 ° C., which is about 40 ° C. higher than the melting point of conventional Sn—Pb eutectic solder, 183 ° C., and when a package is mounted and connected to a circuit wiring board, The following problems occur.
(1) The temperature difference between the melting point and room temperature is about 200 ° C and higher than 40 ° C, compared to conventional Sn-Pb eutectic solder, resulting in deformation due to the thermal expansion difference between the circuit wiring board and the package. In particular, the outer periphery of the package is greatly affected by deformation, and a circuit open defect occurs in a large package exceeding 30 mm □.
(2) While the mechanical properties of the material, such as the elastic modulus (Young's modulus) and tensile strength, are larger than those of conventional Sn-Pb eutectic solder, the elongation properties that affect fatigue life properties are reduced. Thus, the stress applied to the solder joint interface increases. As a result, as in the case (1), a circuit open defect occurs in the outer periphery of the package.

  By the way, when mounting a semiconductor device on a circuit wiring board, in order to accurately align the semiconductor device and the circuit wiring board, auxiliary members for mounting such as positioning bumps are provided, and both are accurately used by using them. A number of patent documents are disclosed and known for connection to the Internet (see, for example, Patent Document 1, Patent Document 2, Patent Document 3, etc.).

However, in the inventions disclosed in these patent documents, when the semiconductor device is mounted on the circuit wiring board, it is assumed that the bonding is based on the Sn—Pb eutectic solder, and any misalignment between the two occurs. With the theme of investigating whether or not to connect, various measures are taken such as positioning auxiliary members on the outer periphery of the package, and lead-free as described in (1) and (2) above. There is no mention of any technology for solving the open circuit failure when using solder.
Japanese Patent Laid-Open No. 10-74792 JP 2000532885 A JP 53-48469 A

  In the present invention, by making a simple modification to the solder bump manufacturing method and the layout of the electrodes on the circuit wiring board, a circuit open failure at the package outer periphery that is likely to occur when lead-free solder is used. To achieve a highly reliable mounting structure of a semiconductor device.

  In the mounting structure of a semiconductor device according to the present invention, a semiconductor in which a lead-free solder bump is interposed between an electrode in a semiconductor element or a semiconductor package and an electrode in a circuit wiring board. In the mounting structure of the apparatus, it corresponds to a positioning bump provided at any location in the mounting area of the semiconductor element or semiconductor package, preferably at least one location near the center, and each electrode of the semiconductor element or semiconductor package. When the electrodes of the circuit wiring board to be connected are heated for solder reflow connection and reach the solder solidification point, the center coordinates of the respective electrodes substantially coincide with the center coordinates of the respective electrodes of the semiconductor element or the semiconductor package. It is basically formed by selecting an electrode arrangement pattern.

  By adopting the above means, after reflow heating, solder solidification, and room temperature cooling, there will be no significant difference in the shape of all bumps in the package surface, so the amount of deformation due to stress concentration and warping of the substrate etc. should be reduced. Therefore, the stress due to the difference in thermal expansion between the package type semiconductor device and the circuit wiring board can be alleviated. In addition, as a result of the simulation by the finite element method, the stress generated in the solder connection portion is 63 MPa according to the conventional technique, whereas the stress according to the present invention shows a value of 40 MPa, and the maximum stress. It was confirmed that the value can be reduced to about 2/3.

  As described above, the connection between the package type semiconductor device and the circuit wiring board with greatly different thermal expansion differences depends on devising the structure of the solder bump in addition to the layout of the electrode and solder resist considering the thermal expansion behavior. As a result, it is possible to form a good solder connection portion without warping, and thus sufficient connection reliability can be ensured.

  The present invention provides a mounting structure for a semiconductor device in which a lead-free solder bump is interposed between an electrode in a semiconductor element or package type semiconductor device and a wiring or electrode in a circuit wiring board. The solder bump includes Sn as a main component and an additive component composed of at least one metal selected from Bi, In, Zn, Ag, Sb, and Cu, and includes a semiconductor element or a package type semiconductor device and a circuit wiring board. In order to minimize the influence of the stress on the solder bump caused by the difference in thermal expansion and the resulting shape change as much as possible, the layout of the solder resist formed on the circuit wiring board has been devised.

  FIG. 1 to FIG. 3 are main part cut side views showing a mounting structure composed of a circuit wiring board and a BGA package type semiconductor device for explaining the present invention, and FIG. 4 is a main part plan view. 1 shows a state where the circuit wiring board and the semiconductor device are aligned, FIG. 2 shows a state where the reflow connection is performed, FIG. 3 shows a state where the reflow connection is finished and the room temperature is cooled, and FIG. Shows the state where the BGA package type semiconductor device is mounted on the circuit wiring board. In FIG. 4, the resist opening layout is designed in consideration of the expansion deformation of the board at the reflow temperature, and the pitch size is all at room temperature. It is not the same as the conventional matrix pattern that becomes the same. The parts indicated by the same symbols as those used in FIGS. 6 to 9 represent the same or equivalent parts.

  In the present invention, as shown in the drawing, the center coordinates of the electrode 12 of the circuit wiring board 11 and the electrode 15 of the BGA package type semiconductor device 14 are at the room temperature, that is, in the alignment state of FIG. Although the center coordinates of the electrodes 12A and 15A located at the center coincide with each other, they are shifted in position toward the outer peripheral portion. For example, when focusing on the outermost peripheral electrodes 12B and 15B, it can be seen that the outermost peripheral solder bump 16B fixed in advance to the outermost peripheral electrode 15B is opposed to the solder resist 13 instead of the outermost peripheral electrode 12B. Like. This point can be easily understood by looking at the enlarged drawing of the portion surrounded by a circle in FIG. 1, but the displacement L is about 100 μm.

  In order to perform the reflow connection shown in FIG. 2 from the state seen in FIG. 1, when the solder bump 16 is heated from room temperature to the freezing point, both the circuit wiring board 11 and the package type semiconductor device 14 are thermally expanded and stretched. However, the extension of the circuit wiring board 11 is larger than the extension of the package type semiconductor device 14, and the arrangement of the electrodes 12 and 15 is a layout that takes into account the deformation due to the thermal expansion in advance. In the solder freezing point (melting point), the center coordinates of the electrode 15 in the BGA package type semiconductor device 14 (or semiconductor element) and the center coordinates of the electrode 12 in the circuit wiring board 11 are substantially as shown in FIG. It becomes a state that matches.

  FIG. 5 is an enlarged side sectional view illustrating the main part in the vicinity of the outermost peripheral electrode of the circuit wiring board and the outermost peripheral electrode of the BGA package type semiconductor device in the state of FIG. The parts indicated by the same symbols as those used in the above are the same or equivalent parts.

  According to the present invention, since the center coordinates of the electrode 15 and the center coordinates of the electrode 12 are substantially coincident with each other, the solder solidifying point is the outermost solder bump 16B as shown in FIG. However, it is not in the state of the parallelogram shape as shown in FIG. 9, and it is possible to maintain a stable shape close to a substantially spherical body, and R <r, and an arrow indicates According to the simulation results, the maximum stress applied to the spot was 40 MPa in the case of SnAgCu.

  Thereafter, when cooling to room temperature, the same amount of deformation is applied to the solder bump connection portion as when heating from the solder solidification point to the melting point, but in the case of the present invention, the solder bump 16 Since the spherical shape is maintained from the beginning to the end, the reduced area of the cross-sectional area does not occur, and it is a shape suitable for stress relaxation with R <r, so when cooled to room temperature, Compared with the conventional technique, the generated stress is small and the connection reliability is improved.

  In the mounting structure and mounting method of the semiconductor device according to the present invention, Sn, Bi, In, Zn, Ag, Sb, Cu or the like is used as the material of the semiconductor element or the solder bump in the package. Solder balls composed of materials selected from them, and solder pastes containing these materials as metal components are formed on the electrodes of the circuit wiring board, and these are heated and fused to form solder bumps. Mounting is performed by connecting a semiconductor device and a circuit wiring board.

  In this example, bonding was performed using Sn-3.0Ag-0.5Cu (freezing point: 217 ° C.). As shown in FIG. 1, the opening layout of the solder resist 13 of the circuit wiring board 11 is positioned outside the package corner portion by a maximum of about 100 μm as compared with the electrode 15 of the opposite package type semiconductor device 14 at room temperature. The state is shifted.

  In the package type semiconductor device, at least one or more positioning bumps 17 (see FIG. 4) are provided in advance in the mounting area, preferably in the vicinity of the central portion where the influence of deformation due to the difference in thermal expansion coefficient is the least.

  The positioning bump 17 is made of a material having a higher freezing point than that of Sn-3.0Ag-0.5Cu, such as an Sn-based alloy, Sn-Sb, Au-Sn, or Au.

  When the circuit wiring board 11 and the package type semiconductor device 14 are mounted, thermo-compression temporary fixing is performed using the positioning bumps 17, and then the solder ball composition has a melting point of Sn-3.0Ag-0.5Cu. Connection was performed by reflow heating under conditions of a maximum of 217 ° C. and a maximum temperature of 250 ° C. and a melting point of 2 minutes in a nitrogen atmosphere.

  This mounting structure was subjected to a temperature cycle test of −40 ° C. (30 minutes) ← → 120 ° C. (30 minutes), and as a result, it was confirmed that the fatigue life was 200 cycles or more.

  In the embodiment of the present invention described above, the BGA package type semiconductor device has been described as the object to be reflow-connected to the circuit wiring board. However, this may be a semiconductor element, that is, a semiconductor chip. Of course, the electrode has been described as an object to be connected to the solder bump in the circuit wiring board, but it is needless to say that this may be a part of the circuit wiring.

It is a principal part cutting side view showing the mounting structure which consists of a circuit wiring board and a BGA package type semiconductor device. It is a principal part cutting side view showing the mounting structure which consists of a circuit wiring board and a BGA package type semiconductor device. It is a principal part cutting side view showing the mounting structure which consists of a circuit wiring board and a BGA package type semiconductor device. It is a principal part top view showing the mounting structure which consists of a circuit wiring board and a BGA package type semiconductor device. It is principal part cut side explanatory drawing which expanded and represented the vicinity of the outermost periphery electrode of a circuit wiring board, and the outermost periphery electrode of a BGA package type semiconductor device. It is a principal part cutting side view showing the mounting structure which consists of a circuit wiring board for explaining a prior art example, and a BGA package type semiconductor device. It is a principal part cutting side view showing the mounting structure which consists of a circuit wiring board for explaining a prior art example, and a BGA package type semiconductor device. It is a principal part cutting side view showing the mounting structure which consists of a circuit wiring board for explaining a prior art example, and a BGA package type semiconductor device. FIG. 4 is a side cutaway explanatory view showing a misalignment amount and a solder bump shape in an outermost peripheral portion between a circuit wiring board and a BGA package type semiconductor device.

Explanation of symbols

11 Circuit Wiring Board 12 Electrode (Land) on Circuit Wiring Board
12A Central electrode 12B Outermost peripheral electrode 13 Solder resist 14 BGA package type semiconductor device 15 Electrode in BGA package type semiconductor device 15A Central electrode 15B Outermost peripheral electrode 16 Solder bump 16B Outermost peripheral solder bump 17 Positioning bump

Claims (4)

In a semiconductor device mounting structure in which a lead-free solder bump is interposed between an electrode in a semiconductor element or semiconductor package and an electrode in a circuit wiring board,
Positioning bumps provided at any location in the mounting area of the semiconductor element or semiconductor package, preferably at least one location near the center;
The electrodes of the circuit wiring board connected correspondingly to the respective electrodes of the semiconductor element or the semiconductor package are heated for solder reflow connection and when the solder solidification point is reached, the center coordinates of the respective electrodes are the respective coordinates of the semiconductor element or the semiconductor package. A mounting structure of a semiconductor device, which is formed by selecting an electrode arrangement pattern in advance so as to substantially coincide with the center coordinates of the electrode. 2. The semiconductor according to claim 1, wherein the positioning bump maintains the center coordinates of the semiconductor element or semiconductor package and the center coordinates of the circuit wiring board at room temperature and when the temperature of solder reflow connection rises. Device mounting structure. The positioning bump is formed of a material that does not melt even when the solder bump melts when reflow heating is performed to connect the semiconductor element or semiconductor package and the circuit wiring board with the solder bump. Semiconductor device mounting structure. 2. The mounting of a semiconductor device according to claim 1, wherein the solder bump contains Sn as a main component and an additive component made of at least one metal selected from Bi, In, Zn, Ag, Sb, and Cu. Construction.

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