JP2008071850A - Manufacturing method of semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device in which a conductive layer mainly composed of Cu is formed in a recess in a state where embedding characteristics by the reflow process are improved without performing a reflow process at a high temperature of 400 ° C. or higher. provide.
First, a step of forming a wiring trench 16 in an interlayer insulating film 15 provided on a substrate 11 is performed. Next, the process of forming the alloy layer 21 which consists of a CuMn alloy in the state which covers the inner wall of the wiring groove | channel 16 is performed. Next, the alloy layer 21 is made to flow by reflow treatment so that the wiring groove 16 is filled with the alloy layer 21, and Mn in the alloy layer 21 is reacted with the constituent components of the interlayer insulating films 12 and 15, thereby A method of manufacturing a semiconductor device comprising performing a step of forming a self-formed barrier film 22 made of a Mn compound having a diffusion barrier property of Cu at an interface with the films 12 and 15.
[Selection] Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a damascene structure in which a self-formed barrier film is provided between a wiring or a via and an interlayer insulating film.

  In a copper (Cu) wiring formation process of a semiconductor device, a damascene method for forming a wiring pattern by embedding wiring grooves provided in an interlayer insulating film is generally performed. When forming a Cu wiring by the damascene method, in order to prevent Cu from diffusing into the interlayer insulating film, the tantalum (Ta) or tantalum nitride film is usually covered with the inner wall of the wiring trench before embedding Cu. A barrier film such as (TaN) is formed to a thickness of about 10 nm. Thereafter, a Cu layer is embedded in the wiring trench provided with the barrier film by electrolytic plating.

In addition to the method of embedding the Cu layer by the electrolytic plating method described above, embedding of the Cu layer by a sputter reflow method has also been proposed (see, for example, Patent Document 1 and Non-Patent Document 1). This method will be described with reference to FIG. First, as shown in FIG. 9A, an interlayer insulating film 12 made of silicon oxide (SiO ₂ ) is formed on a substrate 11 made of a silicon wafer, and then the interlayer insulating film 12 reaches the substrate 11. A connection hole 13 is formed, and a via 14 made of, for example, tungsten (W) is embedded in the connection hole 13.

Next, an interlayer insulating film 15 made of SiO ₂ is formed on the interlayer insulating film 12 including the vias 14. Next, after forming the wiring groove 16 reaching the interlayer insulating film 12 and the via 14 in the interlayer insulating film 15, a barrier made of a metal compound such as Ta or a metal compound such as TaN in a state of covering the inner wall of the wiring groove 16. A film 17 is formed.

  Next, as shown in FIG. 9B, a conductive layer 18 made of pure Cu is formed by a sputtering method so as to cover the inner wall of the wiring groove 16 covered with the barrier film 17. The conductive layer 18 is formed with a film thickness sufficient to fill the wiring trench 16 by a reflow process performed in a later step.

  Next, as shown in FIG. 9C, the conductive layer 18 is made to flow by reflow processing, and the wiring groove 16 is filled with the conductive layer 18. Thereafter, although not shown here, the conductive layer 18 and the barrier film 17 which are not necessary as a wiring pattern are removed by a chemical mechanical polishing (CMP) method to expose the exposed interlayer insulation. Wiring is formed in the wiring groove 16 by cutting the surface side of the film 15.

JP 2000-353705 A Transactions of the Japan Society of Mechanical Engineers (B) 1998, Vol. 64, No. 627, p. 297-303

  However, in the manufacturing method as described above, the barrier film 17 made of metal or metal compound and the conductive layer 18 made of Cu have good wettability and high adhesion. 18 is difficult to flow. For this reason, the fluidity of the conductive layer 18 on the barrier film 17 side is low, the surface side is higher in fluidity than the barrier film 17 side, and the fluidity varies depending on the location, so the embedding characteristics in the wiring trench 16 are poor. Become. As a result, a void V is generated in the conductive layer 18 in the wiring groove 16, and there is a problem that the wiring reliability is deteriorated.

  Further, in order to cause the conductive layer 18 to flow, a reflow process at 400 ° C. or higher is required. However, when a high temperature of 400 ° C. or higher is applied, the semiconductor element provided on the substrate 11 is thermally damaged. In addition, since thermal stress is applied by reflow processing every time the wiring layer is laminated, a stress concentration portion is formed in the wiring, causing a conduction failure due to disconnection or void generation. This also reduces the wiring reliability. Furthermore, degassing from the interlayer insulating films 12 and 15 in a high-temperature processing atmosphere of 400 ° C. or higher causes the barrier film 17 to change in quality, resulting in poor adhesion to the wiring, thereby reducing the electromigration (EM) resistance of the wiring. There is also a problem of deterioration.

  From the above, the present invention forms a conductive layer containing Cu as a main component in the recess in a state in which the embedding property by the reflow process is improved without performing the reflow process at a high temperature of 400 ° C. or higher. An object of the present invention is to provide a method for manufacturing a semiconductor device.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is characterized by sequentially performing the following steps. First, in a 1st process, the process of forming a recessed part in the insulating film provided on the board | substrate is performed. Next, in a 2nd process, the process of forming the alloy layer which consists of copper and metals other than copper is performed in the state which covers the inner wall of a recessed part. Next, in the third step, the alloy layer is made to flow by reflow treatment to fill the recesses with the alloy layer, and the metal in the alloy layer is reacted with the constituent components of the insulating film, so that at the interface between the alloy layer and the insulating film, A step of forming a barrier film made of a metal compound having a copper diffusion barrier property is performed.

  According to such a method for manufacturing a semiconductor device, after forming the alloy layer in a state of covering the inner wall of the recess provided in the insulating film, the alloy layer is flowed by reflow treatment to fill the recess with the alloy layer. For this reason, the alloy layer generally flows on an insulating film having low adhesion to the metal layer. Thereby, even if it does not perform a reflow process at the high temperature of 400 degreeC or more, the embedding to the recessed part of an alloy layer is improved. For this reason, the electrical conductivity failure by the generation | occurrence | production of the disconnection and void resulting from the damage to a semiconductor element by a high temperature process or a thermal history is prevented. In addition, since the barrier film is formed by reacting the metal in the alloy layer with the constituent components of the insulating film together with the reflow process, the barrier film is prevented from being deteriorated due to the high temperature process. Furthermore, by segregating the metal in the alloy layer toward the interface with the insulating film, it is possible to form a conductive layer mainly composed of Cu in the recess.

  As described above, according to the method for manufacturing a semiconductor device of the present invention, a conductive layer containing Cu as a main component is embedded in the recess by reflow processing without performing reflow processing at a high temperature of 400 ° C. or higher. It becomes possible to form. Therefore, when the recess is a wiring groove and the conductive layer is a wiring, wiring reliability can be improved, and the quality and performance of the semiconductor device can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
The present embodiment is an example of an embodiment of a method for manufacturing a semiconductor device according to the present invention, and relates to the formation of a single damascene wiring structure. Hereinafter, the first embodiment of the present invention will be described with reference to the cross-sectional views of the manufacturing steps shown in FIGS. In addition, the same number is attached | subjected and demonstrated to the structure similar to a background art.

First, as shown in FIG. 1A, after an interlayer insulating film 12 made of, for example, SiO ₂ is formed on a substrate 11 made of a silicon wafer on which elements such as transistors are formed, connection in a state of reaching the substrate 11 A hole 13 is formed, and a via 14 made of, for example, W is embedded in the connection hole 13.

Next, by using, for example, plasma enhanced chemical vapor deposition (PECVD), silane (SiH ₄ ) is used as a film forming gas, on the interlayer insulating film 12 including the via 14, for example, An interlayer insulating film 15 made of SiO ₂ is formed.

  Next, a resist pattern (not shown) having a wiring groove pattern is formed on the interlayer insulating film 15, and a wiring groove 16 (concave portion) is formed in the interlayer insulating film 15 by etching using this resist pattern as a mask. The opening width of the wiring groove 16 is 75 nm.

  Subsequently, as shown in FIG. 1B, the inner wall of the wiring groove 16 is formed by, for example, a physical vapor deposition (PVD) method such as a sputtering method using an alloy target made of CuMn. In the covered state, an alloy layer 21 made of CuMn is formed on the interlayer insulating film 15. Here, Mn in the alloy layer 21 reacts with the constituent components of the interlayer insulating films 12 and 15 to form a self-forming barrier film by performing a heat treatment in a subsequent process.

  For this reason, the Mn concentration in the alloy layer 21 is equal to or higher than the Mn concentration capable of forming a continuous self-forming barrier film at the interface between the alloy layer 21 and the interlayer insulating films 12 and 15 by heat treatment performed in a later step, and the wiring. The wiring resistance when Mn remains in the wiring formed in the groove 16 is defined in the range of the Mn concentration within the allowable range. Specifically, the Mn concentration in the alloy layer 21 is 1 atomic% or more and 10 atomic% or less, and preferably 2 atomic% or more and 6 atomic% or less. Furthermore, since Mn is contained in Cu, the melting point is lower than that of the pure Cu layer, so that the fluidity in the reflow process performed in the subsequent process is increased.

  The alloy layer 21 is thick enough to fill the wiring groove 16 by a reflow process described later. When the opening width of the wiring groove 16 is 75 nm as described above, the wiring groove pattern It is preferable that it is 100 nm or more with no smooth part. Here, the alloy layer 21 is formed with a film thickness of 200 nm, for example.

  Next, as shown in FIG. 1C, the alloy layer 21 (see FIG. 1B) is caused to flow by reflow treatment in a reducing gas such as hydrogen or a mixed gas atmosphere of a reducing gas and an inert gas. Then, the wiring groove 16 is filled with the alloy layer 21. This reflow treatment is performed in a temperature range of 250 ° C. or higher and lower than 400 ° C., preferably 250 ° C. or higher and 300 ° C. or lower, with a treatment time of 30 seconds to 30 minutes. Here, for example, a reflow process is performed at 300 ° C. for 5 minutes. At this time, since the alloy layer 21 flows on the interlayer insulating film 15 having low adhesion to the alloy layer 21, the conductive layer 18 described with reference to FIG. 9B in the background art is made of a metal or a metal compound. Compared with the case of flowing on the barrier film 17, the embedding characteristic of the alloy layer 21 in the wiring groove 16 is improved. Also, when the alloy layer 21 contains Mn in addition to Cu, the fluidity is higher than that of pure Cu, so that the embedding property is improved.

Further, by this reflow treatment, Mn in the alloy layer 21 reacts with the constituent components of the interlayer insulating films 12 and 15, and the self-preventing property of preventing Cu diffusion at the interface between the alloy layer 21 and the interlayer insulating films 12 and 15. A formation barrier film 22 is formed. Here, since the interlayer insulating films 12 and 15 are made of SiO ₂ , the self-forming barrier film 22 is made of Mn such as silicon-containing Mn oxide (MnSi _x O _y ) or Mn oxide (Mn _x O _y ). It is composed of a compound and formed with a film thickness of 2 nm to 3 nm. Note that the constituent components of the interlayer insulating films 12 and 15 include oxygen or moisture from the atmosphere adsorbed on the surfaces of the interlayer insulating films 12 and 15. Furthermore, by this heat treatment, Mn is segregated also on the surface side of the alloy layer 21, whereby the MnO layer M is formed. In addition, due to the above reaction, Mn in the alloy layer 21 is segregated on the interface side and the surface side with the interlayer insulating films 12 and 15, so that the alloy layer 21 after the heat treatment becomes a Cu layer 21 ′. However, this Cu layer 21 ′ may contain a trace amount of Mn.

  Here, the self-formed barrier film 22 is formed in the same process as the reflow process. However, when the continuous self-formed barrier film 22 is not reliably formed by the reflow process, the reflow process is used for wiring. It is preferable to form the self-forming barrier film 22 surely by filling the groove 16 with the alloy layer 21 and then performing heat treatment again.

  Subsequently, as shown in FIG. 2D, two-step polishing is performed by, for example, a CMP method. In the first step, unnecessary portions of the wiring pattern are formed together with the MnO layer M (see FIG. 1C). The Cu layer 21 ′ (see FIG. 1C) is removed. Subsequently, in the second stage polishing, the self-formed barrier film 22 is removed, and the exposed interlayer insulating film 15 is etched by 100 nm. As a result, a wiring 21 ″ made of Cu is formed in the wiring groove 16.

Next, by performing organic acid cleaning using a citric acid aqueous solution, an oxalic acid aqueous solution, or the like, corrosion prevention of Cu such as an oxide film on the wiring 21 ″ and a benzotriazole derivative remaining on the surface of the wiring 21 ″ in the CMP step is performed. Remove the agent. Thereafter, for example, silicon carbonitride (SiCN) is formed on the wiring 21 ″ and the interlayer insulating film 15 by a CVD method using a silicon-containing material such as trimethylsilane (3MS) and ammonia (NH ₃ ) as a film forming gas. A cap film 23 made of is formed with a film thickness of 50 nm.

  According to such a method for manufacturing a semiconductor device, as described with reference to FIGS. 1B to 1C, the alloy layer 21 is formed so as to cover the inner wall of the wiring groove 16, and then the alloy is reflowed. Since the layer 21 is caused to flow and the wiring groove 16 is filled with the alloy layer 21, the alloy layer 21 flows on the interlayer insulating film 15. Thereby, even if it does not perform a reflow process at the high temperature of 400 degreeC or more, embedding of the wiring groove | channel 16 of the alloy layer 21 is improved. For this reason, poor electrical conduction is prevented by the occurrence of disconnection and voids due to damage to the semiconductor element due to high-temperature treatment and thermal history. Further, since the self-forming barrier film 22 is formed by reacting Mn in the alloy layer 21 with the constituent components of the interlayer insulating films 12 and 15 together with the embedding by the reflow process, the deterioration of the barrier film due to the high temperature process is prevented. Further, Mn in the alloy layer 21 is segregated to the interface side of the interlayer insulating films 12 and 15 and the surface side of the alloy layer 21 by this reflow treatment, so the alloy layer 21 after the heat treatment becomes a Cu layer 21 ′. . Therefore, since the Cu layer 21 ′ can be formed in the wiring trench 16 with good filling characteristics, the wiring reliability can be improved, and the quality and performance of the semiconductor device can be improved.

  Further, according to the method for manufacturing a semiconductor device of the present embodiment, the degassing component (mainly oxidizing gas component) from the interlayer insulating films 12 and 15 is consumed for forming the self-forming barrier film 22. An adverse effect due to degassing can be suppressed.

  Here, the wiring groove 16 is embedded by performing the reflow process once after the alloy layer 21 is formed, but the wiring groove 16 is not embedded by the single film formation and the reflow process. In some cases, the film formation and the reflow process may be repeated. However, since the second and subsequent depositions do not contribute to the formation of the self-forming barrier film 22, it is preferable to deposit a conductive layer mainly composed of Cu, such as a pure Cu layer.

Although the example in which the interlayer insulating films 12 and 15 are formed of SiO ₂ has been described here, the present invention is not limited to this, and for example, the interlayer insulating films 12 and 15 are formed of a low dielectric constant film having a lower relative dielectric constant than SiO _2. Alternatively, a hybrid structure including an organic insulating film and an inorganic insulating film may be used. In particular, the present invention is preferably used when a porous insulating film that increases the amount of degassed components by heat treatment is used.

(Modification 1)
Next, Modification 1 of the first embodiment will be described with reference to the manufacturing process sectional view of FIG. Note that the process up to the step of forming the wiring trench 16 in the interlayer insulating film 15 is performed in the same manner as in the first embodiment.

  First, as shown in FIG. 3A, an alloy layer 21 a is formed on the interlayer insulating film 15 so as to cover the inner wall of the wiring groove 16. In this case, the alloy layer 21a is formed with a film thickness that does not bury the wiring groove 16 even if a reflow process is performed in a later process, and is formed with a smooth portion having no wiring groove pattern at a thickness of 10 nm to 50 nm. . Here, the alloy layer 21a is formed with a thickness of 30 nm. Further, the Mn concentration in the alloy layer 21a is 1 atomic% or more and 10 atomic% or less, preferably 2 atomic% or more and 6 atomic% or less, similarly to the alloy layer 21 described with reference to FIG. 1B in the first embodiment. Suppose that

  Next, as shown in FIG. 3B, a conductive layer 21b made of pure Cu, for example, is formed in a state of covering the inner wall of the wiring groove 16 covered with the alloy layer 21a. The thickness of the conductive layer 21b is such that the wiring groove 16 is filled with the alloy layer 21a and the conductive layer 21b by a reflow process performed in a later step. For example, when the wiring groove 16 is formed with an opening width of 75 nm, the conductive layer 21b is preferably formed with a film thickness of 70 nm or more in a smooth portion having no wiring groove pattern, and here, formed with a thickness of 200 nm. It will be done.

  Here, an example in which the conductive layer 21b is made of pure Cu will be described. However, the conductive layer 21b only needs to contain Cu as a main component. For example, a CuAg alloy with a small increase in specific resistance is used. May be.

  Next, as shown in FIG. 3C, reflow treatment is performed at 300 ° C. for 5 minutes, for example, in a reducing gas atmosphere such as hydrogen or a mixed gas atmosphere of a reducing gas and an inert gas. By flowing the layer 21b, the wiring groove 16 is filled with the alloy layer 21a and the conductive layer 21b. In addition, by this reflow treatment, Mn in the alloy layer 21a (see FIG. 1B) reacts with the constituent components of the interlayer insulating films 12 and 15, and at the interface between the alloy layer 21a and the interlayer insulating films 12 and 15 A self-forming barrier film 22 made of a Mn compound is formed. Furthermore, by this heat treatment, Mn is segregated also on the surface side of the conductive layer 21b, whereby the MnO layer M is formed. Further, due to the above reaction, Mn in the alloy layer 21a is segregated on the interface side with the interlayer insulating films 12 and 15 and on the surface side of the conductive layer 21b, so that the wiring groove 16 after the heat treatment is filled with the Cu layer 21 ′. It will be in the state. Here, in this embodiment, since the reflow process is performed in the state where the conductive layer 21b made of pure Cu is formed on the alloy layer 21a, the remaining amount of Mn in the Cu layer 21 ′ in the wiring groove 16 is reduced. It can be reduced.

  The subsequent steps are performed in the same manner as the steps described using FIGS. 2D to 2E in the first embodiment. That is, by performing two-step polishing by the CMP method, the unnecessary portion of the Cu layer 21 ′ as a wiring pattern together with the MnO layer M, the self-formed barrier film 22 and the exposed interlayer insulating film 15 are etched. A wiring 21 ″ made of Cu is formed in the groove 16. Subsequently, an organic acid cleaning is performed to remove the oxide film on the wiring 21 ″ and the Cu anticorrosive, and then a cap film 23 made of, for example, SiCN is formed on the wiring 21 ″ and the interlayer insulating film 15. Form.

  Even in such a method of manufacturing a semiconductor device, the alloy layer 21a made of CuMn and the conductive layer 21b made of pure Cu are sequentially laminated in a state of covering the inner wall of the wiring groove 16 provided in the interlayer insulating film 15. Since the reflow process is performed later, the same effects as in the first embodiment can be obtained.

  In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the remaining amount of Mn in the Cu layer 21 ′ in the wiring groove 16 is formed by forming the conductive layer 21 b mainly composed of Cu on the alloy layer 21 a. Can be reliably suppressed. Thereby, increase of wiring resistance can be suppressed.

(Third embodiment)
Next, a third embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional views of FIGS. Here, an example in which a dual damascene wiring structure is formed on the cap film described in the first embodiment will be described.

First, as shown in FIG. 4A, an interlayer insulating film 24 made of, for example, SiO ₂ is formed to a thickness of 350 nm on the cap film 23 by, eg, PE-CVD. Subsequently, a resist pattern (not shown) having a connection hole pattern is formed on the interlayer insulating film 24, and a connection hole 25a reaching the cap film 23 is formed by etching using this resist pattern as a mask.

  Next, as shown in FIG. 4B, a resist R is applied on the interlayer insulating film 24 in a state where the connection holes 25a are embedded. Subsequently, an SOG (Spin On Glass) film is formed on the resist R, a resist pattern (not shown) having a wiring groove pattern is formed on the SOG film, and then SOG is performed by etching using the resist pattern as a mask. The hard mask 26 is formed by processing the film.

  Next, as shown in FIG. 4C, the resist R (see FIG. 4B) is processed by etching using the hard mask 26 as a mask to form a resist pattern R ′ having a wiring groove pattern. To do. Further, the resist R covering the bottom side of the connection hole 25a is left.

  Subsequently, as shown in FIG. 5D, a connection hole is formed on the upper side of the interlayer insulating film 24 by etching using the hard mask 26 (see FIG. 4C) and the resist pattern R ′ as a mask. A wiring groove 25b that communicates with 25a is formed. As a result, a dual damascene opening 25 (concave portion) is formed which includes the wiring groove 25b and the connection hole 25a communicating with the bottom thereof. At this time, the depth of the wiring trench 25b is controlled by controlling the etching time. Here, the opening width of the connection hole 25a is 75 nm, the depth is 110 nm, the opening width of the wiring groove 25b is 75 to 100 nm, and the depth is 150 nm. Further, by leaving the resist R inside the connection hole 25a, the side wall of the connection hole 25a is prevented from being etched, and the side wall is kept vertical.

  Thereafter, as shown in FIG. 5E, the resist pattern R ′ (see FIG. 5D) and the resist R (see FIG. 5D) are removed by ashing and chemical cleaning, and then connected. The cap film 23 at the bottom of the hole 25a is exposed.

  Next, as shown in FIG. 5F, the cap film 23 at the bottom of the connection hole 25a is removed, and the surface of the wiring 21 ″ is exposed.

  Next, as shown in FIG. 6G, an alloy layer 27 made of a CuMn alloy is formed on the interlayer insulating film 24 so as to cover the inner wall of the dual damascene opening 25 by, for example, sputtering. Here, as in the first embodiment, the Mn concentration of the alloy layer 27 is not less than 1 atomic% and not more than 10 atomic%, and preferably not less than 2 atomic% and not more than 6 atomic%. Moreover, the film thickness of the alloy layer 27 is 100 nm or more in a smooth portion having no wiring groove pattern.

Subsequently, as shown in FIG. 6 (h), the alloy layer 27 (see FIG. 6 (g)) is flowed by, for example, a reflow process at 300 ° C. for 5 minutes to fill the dual damascene opening 25, and the alloy Mn in the layer 27 is reacted with the constituents of the interlayer insulating film 24 to form a self-formed barrier film 28 made of a Mn compound having a Cu diffusion preventing property between the alloy layer 27 and the interlayer insulating film 24. Here, as in the first embodiment, since the interlayer insulating film 24 is made of SiO ₂ , the self-forming barrier film 28 is made of silicon-containing Mn oxide (MnSi _x O _y ) or Mn oxide (Mn _x consists of O _y), is formed in a thickness of 2 nm to 3 nm. Further, a Mn oxide (MnO) layer M is also formed on the surface of the alloy layer 27 by this reflow treatment. Note that the alloy layer 27 becomes a Cu layer 27 ′ by segregating Mn.

  Thereafter, as shown in FIG. 6 (i), two-step polishing is performed by, for example, a CMP method, and in the first step, an unnecessary portion of Cu as a wiring pattern is formed together with the MnO layer M (see FIG. 6 (h)). The layer 27 ′ (see FIG. 6H) is removed. Subsequently, in the second stage polishing, the self-formed barrier film 28 is removed, and the exposed interlayer insulating film 24 is etched by 100 nm. As a result, a via 27a ″ in communication with the wiring 21 ″ is formed in the connection hole 25a, and a wiring 27b ″ is formed in the wiring groove 25b.

  Next, organic oxide cleaning is performed to remove the oxide film on the wiring 27b ″ and the Cu anticorrosive remaining on the surface of the wiring 27b ″ in the CMP process. Thereafter, a cap film 29 made of, for example, SiCN is formed to a thickness of 50 nm on the wiring 27b ″ and the interlayer insulating film 24.

  Even in such a method of manufacturing a semiconductor device, as described with reference to FIGS. 6G to 6H, the inner wall of the dual damascene opening 25 provided in the interlayer insulating film 24 is covered. Since the reflow process is performed after forming the alloy layer 27 made of CuMn, the same effects as those of the first embodiment can be obtained.

(Third embodiment)
In the present embodiment, an example in which the interlayer insulating film 24 described with reference to FIG. 4A in the second embodiment has a hybrid structure including an organic insulating layer and an inorganic insulating layer will be described. In addition, the same number is attached | subjected and demonstrated to the structure similar to 2nd Embodiment.

First, as shown in FIG. 7A, on the cap film 23, an inorganic insulating layer 24a ′ made of, for example, a SiOC film, an organic insulating layer 24b ′ made of, for example, a PAE film, and a hard mask layer 24c made of SiO ₂ film. Then, an interlayer insulating film 24 ′ is formed by sequentially stacking “and”.

  Next, a dual damascene opening 25 composed of a connection hole 25a and a wiring groove 25b reaching the cap film 23 is formed in the interlayer insulating film 24 'of this structure. Here, connection holes 25a are formed in the inorganic insulating layer 24a ', and wiring grooves 25b are formed in the hard mask layer 24c' and the organic insulating layer 24b '.

  As a method of forming the dual damascene opening 25, a method of opening the connection hole 25a first and then opening the wiring groove 25b can be used. Further, after forming a wiring groove pattern in a laminated hard mask (not shown) formed on the interlayer insulating film 24 ′, a connection hole 25a is opened partway in the interlayer insulating film 24 ′, and then the laminated hard mask is formed. A manufacturing method in which the wiring groove 25b and the connection hole 25a are completely opened using the above may be used. This detailed forming method is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-63859.

  As described above, after the connection hole 25a and the wiring groove 25b are formed in the interlayer insulating film 24 ', the cap film 23 at the bottom of the connection hole 25a is removed to expose the wiring 21' '.

  Subsequent steps are performed in the same manner as the steps described in the second embodiment with reference to FIGS. That is, as shown in FIG. 7B, an alloy layer 27 made of CuMn is formed on the hard mask layer 24c ′ by sputtering to cover the inner wall of the dual damascene opening 25.

Subsequently, as shown in FIG. 7C, the alloy layer 27 (see FIG. 7B) is flowed by, for example, a reflow process at 300 ° C. for 5 minutes to fill the dual damascene opening 25 and the alloy. Mn in the layer 27 is reacted with a constituent component of the interlayer insulating film 24 ′ to form a self-formed barrier film 28 made of a Mn compound having a Cu diffusion preventing property between the alloy layer 27 and the interlayer insulating film 24 ′. . Here, since the interlayer insulating film 24 ′ is configured by sequentially laminating a SiOC film, a PAE film, and a SiO ₂ film, and the cap film 23 is composed of SiCN, the self-formed barrier film 28 is composed of silicon-containing Mn oxide. things (MnSi _x O _y), Mn oxide (Mn _x O _y), is composed in a state containing either Mn carbide (Mn _x C _y), it is formed in a thickness of 2 nm to 3 nm. Further, by this reflow treatment, Mn is segregated also on the surface side of the alloy layer 27 to form the MnO layer M. Note that the alloy layer 27 becomes a Cu layer 27 ′ by segregating Mn.

  Thereafter, as shown in FIG. 8, two-step polishing is performed by, for example, a CMP method, and in the first step, an unnecessary portion of the Cu layer 27 ′ as a wiring pattern is formed together with the MnO layer M (see FIG. 7C). (See FIG. 7C). Subsequently, in the second stage polishing, the self-formed barrier film 28 is removed, and the exposed interlayer insulating film 24 ′ is etched by 100 nm. As a result, a via 27a ″ in communication with the wiring 21 ″ is formed in the connection hole 25a, and a wiring 27b ″ is formed in the wiring groove 25b.

  Next, an organic acid cleaning is performed to remove the oxide film on the wiring 27b ″ and the Cu anticorrosive. Thereafter, a cap film 29 made of, for example, SiCN is formed to a thickness of 50 nm on the wiring 27b ″ and the interlayer insulating film 24 ′.

  Even in such a method of manufacturing a semiconductor device, as described with reference to FIGS. 7B to 7C, the inner wall of the dual damascene opening 25 provided in the interlayer insulating film 24 ′ is covered. Since the reflow process is performed after forming the alloy layer 27 made of CuMn, the same effects as those of the first embodiment can be obtained. In addition, in the method for manufacturing a semiconductor device according to the present embodiment, since the organic insulating layer 24b 'having low heat resistance is used, the present invention can be preferably used.

  In addition, it is also possible to apply the modification 1 of 1st Embodiment to 2nd Embodiment and 3rd Embodiment which were mentioned above.

In the first to third embodiments described above, the example in which the alloy layers 21 and 27 are made of CuMn has been described. However, as the metal other than Cu constituting the alloy layers 21 and 27, the above-described Mn In addition, for example, aluminum (Al), zinc (Zn), chromium (Cr), vanadium (V), titanium (Ti), and tantalum (Ta) can be exemplified. For example, when the alloy layers 21 and 27 are made of CuAl, in the first and second embodiments, as the self-forming barrier films 22 and 28, for example, a silicon-containing Al oxide (AlSi _x O _y ) or Al oxide ( Al _x O _y ) is formed, and in the third embodiment, at least one of the above compounds including Al carbide (Al _x C _y ) is formed. Further, when the alloy layers 21 and 27 are made of CuZn, in the first and second embodiments, as the self-forming barrier films 22 and 28, for example, silicon-containing Al oxide (AlSi _x O _y ) or Al oxide ( Al _x O _y ) is formed, and in the third embodiment, at least one of the above compounds including Al carbide (Al _x C _y ) is formed.

FIG. 6 is a manufacturing process cross-sectional view (No. 1) for describing the first embodiment of the semiconductor device manufacturing method of the present invention; FIG. 6 is a manufacturing process sectional view (No. 2) for describing the first embodiment of the manufacturing method of the semiconductor device of the invention; It is manufacturing process sectional drawing for demonstrating the modification 1 of 1st Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 1) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 2) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 3) for describing 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing for demonstrating 3rd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention (the 1). It is manufacturing process sectional drawing (the 2) for demonstrating 3rd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing for demonstrating the manufacturing method and subject of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Board | substrate, 12, 15, 24, 24 '... Interlayer insulating film, 16, 25b ... Wiring groove, 21, 21a, 27 ... Alloy layer, 21b ... Conductive layer, 22, 28 ... Self-forming barrier film, 25 ... Dual Damascene opening, 25a ... connection hole, 21 ", 27b" ... wiring, 27a '... via

Claims (3)

A first step of forming a recess in an insulating film provided on the substrate;
A second step of forming an alloy layer made of copper and a metal other than copper in a state of covering the inner wall of the recess;
The alloy layer is caused to flow by reflow treatment so that the concave portion is filled with the alloy layer, and the metal in the alloy layer is reacted with the constituent components of the insulating film to form an interface between the alloy layer and the insulating film. And a third step of forming a barrier film made of a metal compound having a copper diffusion barrier property. A method of manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
Between the second step and the third step,
In a state of covering the inner wall of the recess covered with the alloy layer, performing a step of forming a conductive layer mainly composed of copper,
In the third step, the recess is filled with the alloy layer and the conductive layer by a reflow process, and the barrier film is formed. In the manufacturing method of the semiconductor device according to claim 1,
In the third step, the barrier film is formed by filling the concave portion with the alloy layer by reflow treatment, and then forming the barrier film.

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