JP2008071170A - Floating point arithmetic unit and radar signal processing unit using this unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the processing time of an entire filter operation even when processing target data needs to be converted into a floating point format in a fixed point format.
A filter operation immediately after input is performed by a fixed-point operation, and the operation result is converted to a floating-point format. Here, paying attention to the fact that a DSP that can handle floating-point operations can execute calculation and floating-point conversion at the same time, the calculation instruction, memory access instruction, and floating-point conversion instruction are optimally combined. Floating point conversion processing that has been performed independently is simultaneously executed in subsequent filter operations. With this configuration, the efficiency of the floating point conversion process is increased and the processing time is minimized.
[Selection] Figure 1

Description

  The present invention relates to a floating point arithmetic unit that performs floating point arithmetic by software signal processing using a DSP (digital signal processor) or CPU (control processing unit), and a radar that realizes high-speed processing using this device. The present invention relates to a signal processing device.

  In a radar signal processing apparatus, for example, a filtering process such as MTI (Moving Target Indicator) requires a wide dynamic range, and in the fixed-point format, overflow occurs during the processing. For this reason, operations are generally performed in a floating-point format. Note that Patent Document 1 describes a calculation method of a floating-point arithmetic unit that performs high-speed calculation of a complicated function operation in which the number of significant digits is determined.

However, the data to be processed usually has a fixed-point format, and it is necessary to convert the format from fixed-point to floating-point at the beginning of processing. Since this conversion process is performed independently of the filter process for all data to be processed, the entire process takes time. The data length in the fixed point format is generally 8 to 16 bits. In this case, simply converting to the floating point format results in a 32-bit length even in the single precision floating point format. In this way, the required input buffer memory needs to be at least twice as large as the fixed-point format data.
Japanese Unexamined Patent Publication No. 04-67967

  As described above, in the conventional floating point arithmetic unit, the format conversion is performed on the processing target data in the fixed point format from the fixed point to the floating point at the beginning of the process. The processing time is required independently in a series of processing, and the input buffer memory for the next processing needs to be twice or more the size of the input fixed-point format data.

  The present invention has been made to solve the above problem, and even if the data to be processed needs to be converted into a floating-point format in a fixed-point format, the entire processing time can be shortened. A floating-point arithmetic unit capable of reducing the memory size of the input buffer memory required for the above processing and a radar signal processing device capable of realizing high-speed processing, miniaturization, and power saving using this device The purpose is to do.

  The floating-point arithmetic unit according to the present invention has a processor that simultaneously performs a calculation in a fixed-point format and a conversion to the floating-point format in the first stage, and the processor converts the calculation result in the previous fixed-point format into the floating-point format. It is characterized in that the following fixed-point format operation is executed during the period.

  Further, the radar signal processing apparatus according to the present invention has a processor that simultaneously performs the calculation in the fixed-point format and the conversion to the floating-point format in the first stage, and converts the calculation result in the previous fixed-point format into the floating-point format. A floating-point arithmetic unit that performs an operation in the next fixed-point format during a certain period, and a radar signal is input to the floating-point arithmetic unit to perform filter processing by coefficient multiplication and phase shift.

  According to the present invention, even if the data to be processed needs to be converted into a floating-point format in a fixed-point format, the entire processing time can be shortened, and the memory size of the input buffer memory required for processing in the floating-point Can be provided, and a radar signal processing device capable of realizing high-speed processing, miniaturization, and power saving by using this device can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an MTI filter unit of a radar signal processing apparatus to which a floating point arithmetic unit according to the present invention is applied. In FIG. 1, fixed-point format processing target input data (here, the data length is 16 bits) is a digitized radar pulse reception signal, and this input data is input to the MTI filter processing unit 11. The MTI filter processing unit 11 performs an MTI filter operation on input data in a fixed-point format using a DSP that can handle a floating-point operation, removes clutter components, and extracts a target signal. A DSP that can handle this floating point operation has a function of converting to a floating point format simultaneously with the operation. The target signal obtained by the MTI filter processing unit 11 is sent to the target display unit 12, and the target position is displayed.

  The DSP used in the MTI filter processing unit 11 is specifically configured as shown in FIG. In FIG. 2, 111 is an ALU (Arithmetic and Logic Unit), 112 is a multiplier, 113 is a shifter, 114 is a register for temporarily storing an operation data file, and 115 is for storing a coefficient (weight). DAB (Data Buffer). The register 114 fetches calculation target data sent through the bus 116 and coefficient data stored in advance in the DAB 115, and sends designated data to the ALU 111, the multiplier 112, and the shifter 113 in accordance with the calculation program. The process of fetching the result is repeatedly executed, and the final calculation result is sent to the target display unit 12 through the bus 116.

  Here, the multiplier 112 sequentially multiplies the designated coefficient and the input operation target, and performs cumulative addition by repeating the multiplication. In addition, the ALU 111 has a function of converting the eigenpoint to a floating point for the processing result of the previous stage during the operation of the multiplier 112. The shifter 113 adjusts the memory write timing with respect to the input memory read of the register 114.

  In the above configuration, an embodiment will be described below with reference to FIGS.

FIG. 3 shows an example of MTI filter processing performed by the MTI filter processing unit 11. MTI filter processing is a process that removes fixed targets (I / Q data without phase change) and extracts only moving targets (I / Q data with phase change). Between PRI (Pulse Repeat Interval) In this process, the phases are inverted and added. In FIG. 3, it is configured by a combination of delay devices A1 and A2 having a delay time τ corresponding to PRI and arithmetic units (Σ) B1 and B2 for subtracting before and after the delay. Here, the MTI coefficients W ₁ , W ₂ , and W ₃ are defined as 1, −2, and 1, respectively, and these coefficients are multiplied and added for each PRI. However, signal level normalization is not performed. The MTI calculation method at this time is as follows. The first to third received pulse data used for MTI are P ₁ , P ₂ and P ₃ , and the weights for each received pulse data are W ₁ , W ₂ and W ₃ .
MTI _out = (W ₁ P ₁ + W ₂ P ₂ + W ₃ P ₃ ) · α
Pi = I / Q data (i is the PRI number)
Wi = MTI coefficient (i is the PRI number)
α = MTI gain adjustment coefficient (initial setting parameter)
Given in.

FIG. 4 shows that the received pulse data of PRI numbers 1 to 3 used for the MTI shown in FIG. 2 in the MTI filter processing are P ₁ , P ₂ , P ₃ , and the MTI coefficients are W ₁ , W ₂ , W ₃ .
MTI _out = W ₁ P ₁ + W ₂ P ₂ + W ₃ P ₃
The flow of processing when calculating is shown. Note that () in the figure is an unnecessary operation, but it is assumed to be executed to simplify the program. In addition, α = 1 is assumed here for the sake of simplicity.

First, in the input memory read by the register 114, at the [1] -th read, the multiplier 112 uses the data obtained at the [0] -th read.
MTI _out [0] = W ₁ P ₁ [0] + W ₂ P ₂ [0] + W ₃ P ₃ [0]
Is calculated.

Subsequently, at the time of the [2] -th read, the multiplier 112 uses the data obtained at the time of the [1] -th read.
MTI _out [1] = W ₁ P ₁ [1] + W ₂ P ₂ [1] + W ₃ P ₃ [1]
Is calculated. At this time, the ALU 111 takes in the multiplication result MTI _out [0] (fixed point in this state) of the multiplier 112 at the time of [1] read and converts it into a floating point.

Similarly, a loop is formed from i = 2 to N, and at the [i + 1] th read, the multiplier 112
MTI _out [i] = W ₁ P ₁ [i] + W ₂ P ₂ [i] + W ₃ P ₃ [i]
Is calculated. At this time, the ALU 111 takes in the multiplication result MTI _out [i−1] (in this state, fixed point) of the multiplier 112 at the time of [i−1] read, and converts it into a floating point. At this point, the shifter 113 performs memory write processing on the floating-point MTI _out [i-2].

Next, at the [i + 2] -th read, the multiplier 112
MTI _out [i + 1] = W ₁ P ₁ [i + 1] + W ₂ P ₂ [i + 1] + W ₃ P ₃ [i + 1]
Is calculated. At this time, the ALU 111 takes in the multiplication result MTI _out [i] (in this state, fixed point) of the multiplier 112 at the time of [i] reading, and converts it into a floating point. At this point, the shifter 113 performs memory write processing on the floating-point MTI _out [i−1].

  The above processing is repeated until i = N.

  In other words, the floating point arithmetic unit according to the present invention is configured to perform the filter operation immediately after input by fixed point arithmetic and convert the arithmetic result to the floating point format. Here, in a DSP that can handle floating point operations, calculation and floating point conversion can be executed simultaneously, and a calculation instruction, a memory access instruction, and a floating point conversion instruction can be optimally combined. Therefore, the floating point conversion processing that has been performed independently immediately after the input is performed simultaneously in the subsequent filter operation. With this configuration, the efficiency of the floating point conversion process is increased and the processing time is minimized.

  Therefore, according to the above processing configuration, the processing time required for the floating-point calculation can be minimized. In addition, the memory size can be reduced by the fixed-point format. As a result, the radar signal processing apparatus using the floating-point arithmetic unit having the above configuration can be configured with a smaller number of processors than the conventional one, and the effects of speeding up the processing, miniaturization and power saving can be obtained. It is done.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. For example, in the above-described embodiment, the case where the MTI filter process is performed has been described, but the present invention can be similarly applied to a filter process that performs other floating-point operations. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

The block diagram which shows the structure of the MTI filter part of the radar signal processing apparatus with which the floating point arithmetic unit which concerns on this invention is applied. FIG. 2 is a block circuit diagram showing a specific configuration of a DSP used in the MTI filter processing unit shown in FIG. 1. The conceptual diagram which shows the example of the MTI filter process performed in the said MTI filter process part. The figure for demonstrating the flow of a process in the case of calculating the said MTI filter process.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... MTI filter process part, 12 ... Target display part, 111 ... ALU (logical operation unit), 112 ... Multiplier, 113 ... Shifter, 114 ... Register, 115 ... DAB (data buffer)

Claims (2)

A processor that simultaneously performs operations in fixed-point format and conversion to floating-point format is placed in the first stage,
A floating-point arithmetic unit that performs an operation in the next fixed-point format during a period in which the arithmetic result in the previous fixed-point format is converted into the floating-point format in the processor. A processor that performs operations in the fixed-point format and conversion to the floating-point format at the same time is placed in the first stage, and the operation in the next fixed-point format is executed during the period when the previous operation result in the fixed-point format is converted to the floating-point format. A floating point arithmetic unit
A radar signal processing apparatus, wherein a radar signal is input to the floating point arithmetic unit to perform filter processing by coefficient multiplication and phase shift.

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