JP2008071018A - Memory interface circuit - Google Patents

Abstract

A memory interface circuit that does not erroneously latch a data signal even when transmission conditions are deteriorated or mismatched is provided.
A memory interface circuit including an oscillation circuit, a delay circuit, a phase comparator, and a data latch, and connected to a DDR-SDRAM that outputs a DQS signal and a data signal in synchronization with a clock. The delay circuit 16 delays the clock output from the oscillation circuit 50 and outputs it as the read clock 53. The phase comparator 60 measures the phase difference between the input data strobe signal 57 and the read clock 53, and delays the delay. The circuit 16 adjusts the delay time of the read clock 53 according to the measured phase difference, and the data latch 17 captures the data signal 13 in synchronization with the read clock 53.
[Selection] Figure 10

Description

  The present invention relates to a memory interface circuit having a memory interface for connecting a synchronous memory, and more particularly to a technique for latching a data signal of a synchronous memory.

  Since synchronous memory performs burst transfer of data at high speed, a technique for correctly controlling the timing of a read clock for latching a data signal is essential. The DDR-SDRAM is characterized in that a signal called DQS is added to generate a read clock for latching a data signal, and that the data signal changes in synchronization with the rise and fall of the DQS signal. Patent Document 1 relates to a semiconductor integrated circuit having a DDR-SDRAM interface, and a delay time of a delay element is spread on the assumption that a DQS signal is delayed by a quarter of one clock period and used as a read clock. A method has been proposed in which a delay time of one-fourth of one clock cycle is correctly created even when there is variation due to variations.

  11 is a diagram showing the path of the read clock in the configuration of Patent Document 1. In FIG. 11, 11 is a DDR-SDRAM, 12 is a DQS signal, 13a and 13b are data signals, 15 is an input buffer, and 16 is a delay circuit. , 17 is a data latch, 18 is read data, 21 is a memory interface circuit, 22 is a read clock generation circuit, 57 is a data strobe signal, and 53 is a read clock.

  Hereinafter, the latch operation of the data signal 13 in the configuration of Patent Document 1 will be described with reference to FIG. The DDR-SDRAM 11 is connected to the memory interface circuit 21. When the DDR-SDRAM 11 is read-accessed, the DDR-SDRAM 11 outputs the DQS signal 12 and the data signal 13a simultaneously. The memory interface circuit 21 takes in the DQS signal 12 and the data signal 13 a through the input buffer 15. Since the DQS signal 12 that has passed through the input buffer 15 is a signal that is inverted every word of data, it can be used as a data strobe signal 57 for latching data. The read clock generation circuit 22 receives the data strobe signal 57 and delays it by the delay circuit 16 to generate a read clock 53. In Patent Document 1, the delay circuit 16 has a configuration in which a plurality of delay circuits are combined. However, the read clock 53 is generated by delaying the data strobe signal 57.

  The delay circuit 16 generates the read clock 53 by delaying the data strobe signal 57 by a phase of 90 degrees when the data strobe signal 57 is regarded as a clock, in other words, a quarter cycle. This delay amount is half of the data update interval with reference to the data update interval. Since the DDR-SDRAM 11 changes the DQS signal 12 and the data signal 13a simultaneously, the rising edge and falling edge of the read clock 53 are The change point of the data signal 13b passing through the input buffer 15 is located at the center of the change point. The data latch 17 latches the data signal 13b with the read clock 53 to obtain read data 18.

  FIG. 12 is a waveform diagram showing signal waveforms on the circuit in the configuration of Patent Document 1, in which the external DQS is the DQS signal 12 output from the DDR-SDRAM 11, the external data is the data signal 13a output from the DDR-SDRAM 11, The internal DQS indicates the waveform of the data strobe signal 57 output from the input buffer 15, the internal data indicates the data signal 13b output from the input buffer 15, and the read clock indicates the waveform of the read clock 53 output from the delay circuit 16.

  The DDR-SDRAM 11 outputs external DQS and external data simultaneously. The external data changes in synchronization with the rise and fall of the external DQS, and the time difference between the change point of the external DQS and the change point of the external data is within the standard. External DQS and external data are taken into the memory interface circuit 21 via the input buffer 15. Since the buffers at close positions on the same chip have the same characteristics, the relative relationship between the external DQS output from the DDR-SDRAM 11 and the waveform of the external data becomes the internal DQS and the internal data via the input buffer 15. Almost preserved. If the delay circuit 16 delays the internal DQS by one-fourth cycle to form a read clock, the rise and fall of the read clock are located near the data change point and the center of the change point, so that stable internal data latch Is expected to be possible.

  However, there are some problems that the SDRAM interface circuit of Patent Document 1 cannot cope with, and one of them is that the duty ratio of the DQS signal is not necessarily 50%.

  FIG. 13 is a waveform diagram when the duty ratio of the external DQS changes. First, the external DQS output from the DDR-SDRAM 11 may have a duty ratio deviated from 50% within the allowable range of the standard. If the rise time and fall time of the external DQS are sufficiently short, the amount of change in the duty ratio is limited. However, in mobile devices, a design that suppresses the change rate of the signal line is preferred to reduce power consumption and unnecessary radiation. In addition, an SDRAM having an option of extending the MRS register set to reduce the drive current of the signal line is also used. When the drive current of the signal line is reduced, the external DQS changes gently, and therefore the duty ratio may be shifted due to the difference in drive current at the rise time and fall time.

  Next, when the external DQS passes through the input buffer 15 and becomes the internal DQS, the duty ratio of the internal DQS may shift due to the difference between the output voltage of the DDR-SDRAM 11 and the threshold voltage of the input buffer 15. In this case as well, if the change in the external DQS is gentle, the duty ratio changes greatly due to a slight difference between the output voltage of the DDR-SDRAM 11 and the threshold voltage of the input buffer 15.

  Moreover, since the breakdown voltage of the internal logic core portion has been reduced due to recent miniaturization of the semiconductor process, the power supply voltage of the logic core portion is lowered than the input / output buffer portion, and a level conversion circuit (not shown) is interposed therebetween. The sandwiching structure is generalized. In this case, the duty ratio may change even in the level conversion circuit. Since the delay circuit 16 also has a large number of delay elements arranged, if the delay time for the rise and fall of the signal is different for each delay element, the duty ratio may change while passing through the many elements. is there.

  FIG. 13 shows an example in which the width of the H period is widened and the width of the L period is narrowed in the process in which the external DQS is changed to the internal DQS via the input buffer 15 and further to the read clock via the delay circuit 16. Then, the rising edge is earlier than the optimum timing, and the falling edge is delayed later. Although illustration is omitted, even when the width of the H period becomes narrower than the width of the L period, the edge moves in the reverse direction and deviates from the ideal latch timing.

  In the specification of the DDR-SDRAM 11, the clock supply from the memory interface circuit to the DDR-SDRAM 11 is transmitted by a two-phase clock of a normal phase and a reverse phase, so that the duty ratio does not change, and the external data of the DDR-SDRAM 11 Change points are equally spaced. Therefore, the optimal data latch timing in the memory interface circuit is best at regular intervals. However, if the duty ratio changes in the process until the read clock is generated, the rising edge and falling edge, which are the data latch timing, are reversed. Therefore, the optimum data latch timing deviates.

  Furthermore, there is a problem that the changing point of the external DQS fluctuates due to a voltage drop or ground bounce due to a simultaneous change in signal. In the DDR-SDRAM 11 called the x32 type, four external DQSs are output for 32 external data. Considering the situation where 31 external data and 4 external DQS change from L to H at the same time, and only one external data changes from H to L, the drive current is 35 signal lines from the power supply line of the DDR-SDRAM 11. Since the power input to the output buffer (not shown) of the DDR-SDRAM 11 temporarily drops in voltage, the rise of the external DQS is delayed. On the other hand, one piece of external data that changes from H to L is boosted by the voltage drop of the power input of the output buffer, and therefore falls quickly. As another example, considering the situation where 32 external data changes from H to L and the external DQS changes from L to H, the output buffer of the DDR-SDRAM 11 sucks charges from the load capacity of 32 external data. Since the current flows to the ground, the ground voltage in the DDR-SDRAM 11 temporarily increases. This phenomenon is called grand bounce. External data slows down from H to L due to a rise in ground voltage, whereas external DQS is boosted and changes quickly from L to H.

  Thus, the timing at which the signal changes may change due to a voltage drop or ground bounce, and the timing change between the external DQS and the external data may be in the same direction or in the opposite direction. When the read clock is generated by delaying the external DQS, there is a possibility that the external data cannot be latched correctly depending on the width of the timing change when the timing change between the external DQS and the external data is in the opposite direction. Voltage drops and ground bounces can be suppressed by using a multilayer board to make the power line and ground line patterns wider and thicker, but small and light portable devices use small, thin, and light boards, so voltage drops and ground bounces can be reduced. It may not be sufficiently suppressed.

The edge of the read clock generated by delaying the external DQS in this way may be before or after the optimum latch timing, and external data may be erroneously latched.
JP 2006-107352 A

  The problem to be solved by the present invention is to erroneously latch the data signal when there is a deterioration or mismatch in transmission conditions.

  In order to solve the above problems, a memory interface circuit of the present invention is a memory interface circuit including a clock generation circuit, a delay circuit, a phase difference measurement circuit, and a memory circuit, and outputs a data strobe signal and a data signal in synchronization with the clock. The delay circuit delays the clock output from the clock generation circuit and outputs it as a read clock, and the phase difference measurement circuit outputs the data strobe signal input to the read clock and the read clock. The phase difference is measured, the delay circuit adjusts the delay time of the read clock according to the measured phase difference, and the memory circuit captures the data signal in synchronization with the read clock.

  According to the present invention, a clock for latching a data signal is a clock generation circuit even if the duty ratio changes due to mismatch between the output signal of the SDRAM and the threshold value of the input buffer or level conversion between the input buffer and the internal circuit. Therefore, the change of the duty ratio does not affect the latch timing. Even if the timing of the DQS signal changes due to voltage drop or ground bounce, the phase difference measurement circuit outputs the result of measuring the edge timing of the DQS signal multiple times as a phase difference. The width that the timing fluctuates becomes narrower. As described above, since the timing for latching the data signal becomes equal, and it becomes difficult to react to the disturbance, a more stable and reliable latch operation of the data signal can be performed.

   The propagation delay time of the gate and I / O buffer that propagates clocks and data changes according to temperature changes and power supply voltage fluctuations, but the temperature changes slowly in seconds, and the power supply voltage design is appropriate for the power supply circuit. If there is, it is controlled to change slowly within a certain operating voltage range. Therefore, the delay time from the clock output to the SDRAM to the data signal input is essentially constant in a short time, and the fluctuation can be handled as a disturbance.

  Disturbances include voltage drop and ground bounce due to simultaneous signal changes, duty ratio change due to level conversion, crosstalk between signal lines, and noise wraparound from power supply and ground. If these always change the delay time of the data signal and the DQS signal in the same direction, the data signal is latched after a certain time from the clock output to the SDRAM when the DQS signal is delayed for a certain time. It can be said that it is more advantageous. However, as described above, the effect of the duty ratio deviation is in the reverse direction at the rise and fall, and the effect of the timing fluctuation due to the voltage drop and ground bounce may work in the same direction for the data signal and the DQS signal. Since the DQS signal may be delayed for a certain time and used as a read clock, it is disadvantageous to latch the data signal. For simplification, if the data signal is delayed by ΔT due to a disturbance, the DQS signal will be the best latch timing if the data signal is delayed by ΔT. However, if the DQS signal is delayed by ΔT, the data signal is doubled by ΔT. Since the data is latched at an earlier timing, the error rate is lower when the data signal that is delayed by ΔT is latched at a certain timing.

   Since changes in temperature and power supply voltage are gradual, the phase of the read clock can be made to follow the change by measuring the delay time of the data signal or DQS signal. By processing the delay time with a filter having a high-frequency cutoff characteristic, it is possible to obtain an optimum read clock phase that is not affected by disturbance, and the output of the clock generator is delayed to have a stable phase. By latching the data signal with the read clock, highly reliable data transfer can be realized.

  Embodiments of the present invention will be described below. FIG. 1 is a block diagram of a read clock generation circuit in an embodiment of the present invention. In FIG. 1, 50 is an oscillation circuit, 51 is a main shifter, 52 is a frequency divider, 53 is a read clock, 54 is a sub-shifter, 55 is a cascade delay circuit, 56 is a frequency divider, 57 is a data strobe signal, and 58 is a selector. , 59 is a trigger signal, 60 is a phase comparator, 61 is an integrating circuit (configured by an IIR filter in this embodiment), 62 is a control circuit, 63 is a save register, 64 is a data latch, 65 is a main delay amount, 67 Is a correction delay amount. Hereinafter, the operation of the read clock generation circuit will be described with reference to FIG.

  The oscillation circuit 50 generates a clock having a frequency twice that of the SDRAM clock. The generated clock is output to the main shifter 51 and the frequency divider 56. The main shifter 51 delays the output clock by a specified time by changing the combination of delay elements that pass the input clock. The delay time of the main shifter must be designed to exceed at least half of the SDRAM clock period.

  The delayed clock output from the main shifter 51 is frequency-divided by 2 by the frequency divider 52 to become a read clock 53 having the same frequency as the SDRAM clock. The read clock 53 is input to the sub-shifter 54 at the same time as the output of the read clock generation circuit. Similar to the main shifter 51, the sub shifter 54 delays the output clock by a specified time by changing the combination of delay elements that pass the input clock. However, the delay time is smaller than that of the main shifter and is at least equal to the period of the SDRAM clock. Design to exceed a quarter. The standard delay time of the sub-shifter 54 is 1/8 of the period of the SDRAM clock, in other words, it corresponds to a phase shift of 45 degrees. The clock delayed by the sub-shifter 54 is input to the column delay circuit 55.

  The column delay circuit 55 is formed by cascading delay elements, and has a plurality of output taps with slightly different delay times. A plurality of outputs of the column delay circuit 55 are input to the phase comparator 60 in parallel. The delay time of the column delay circuit 55 is designed so that the delay time of the center output tap is typically one-eighth of the SDRAM clock cycle. As a result, the delay time from the input of the sub-shifter 54 to the center output tap of the column delay circuit 55 is equivalent to a phase shift of 90 degrees as a standard.

  The data strobe signal 57 is a synchronization signal sent at the same timing as the data signal. In the DDR-SDRAM, the DQS signal is input as the data strobe signal 57. The selector 58 switches between the data strobe signal 57 and the output of the frequency divider 56. The frequency divider 56 is a counter that divides the frequency by 2, similarly to the frequency divider 52, and the frequency of the output clock is the same as that of the SDRAM clock. The read clock generation circuit has two modes, an optimization mode and a calibration mode. In the optimization mode, the data strobe signal 57 is selected, and in the calibration mode, the output of the frequency divider 56 is selected and output as a trigger signal 59.

  The phase comparator 60 measures the phase difference between the clock and the trigger signal by latching the outputs of the plurality of taps of the column delay circuit 55 in synchronization with the edge of the trigger signal 59. FIG. 2 is a block diagram of the cascade delay circuit 55 and the phase comparator 60 in the embodiment of the present invention. In FIG. 2, 55 is a cascade delay circuit, 59 is a trigger signal, 60 is a phase comparator, 41 is a clock input, 42 is a delay element, 43 is a differential output buffer, 44 is an FF group for inverted clock operation, and 45 is non-inverted. FF group for clock operation, 46a and 46b are adders, 47 is a subtractor, and 48 is a data latch. The phase comparison operation will be described below with reference to FIG. The cascade delay circuit 55 is formed by connecting delay elements 42 in cascade, and has a plurality of output taps with slightly different delay times. The phase comparator 60 latches the plurality of outputs of the cascade delay circuit 55 by the FF group 44 for the inverted clock operation and the FF group 45 for the non-inverted clock operation. The two groups of FF clocks are obtained by distributing the trigger signal 59 to two inverted and non-inverted clocks by the differential output buffer 43.

  When the clock input 41 rises from L to H, the output E0, E1, E2, E3, E4 of each tap of the column delay circuit 55 rises from L to H sequentially from the left, and the right end tap changes most slowly. When the state of each tap is latched by the FF group 45 of the non-inverted clock operation of the phase comparator 60, the time difference between the rising edge of the trigger signal 59 and the falling edge of the clock input 41 is the output Q0 of the FF in FIG. Of Q1, Q2, Q3, and Q4, it is quantified as the number of bits that are H. The adder 46b converts the number of FFs whose output is H into a multi-bit numerical value (ΣQ = Q0 + Q1 + Q2 + Q3 + Q4). Similarly, when the state of each tap of the column delay circuit 55 is latched by the FF group 44 of the inverted clock operation of the phase comparator 60, the time difference between the falling edge of the trigger signal 59 and the rising edge of the clock input 41 is shown in FIG. Of the outputs P0, P1, P2, P3, and P4 of the FF, it is digitized as the number of bits that are H. The adder 46a converts the number of FFs whose output is H into a multi-bit numerical value (ΣP = P0 + P1 + P2 + P3 + P4). The subtractor 47 calculates the sum of the time difference between the rising edges and the time difference between the falling edges (R = ΣQ−ΣP). The output of the phase comparator 60 is updated by the data latch 48 in synchronization with the rising edge of the trigger signal 59.

  FIG. 3 is a waveform diagram showing a time change of each signal of the read clock generation circuit. 3, A is the output of the oscillation circuit 50 of FIG. 1, B is the output of the main shifter 51 of FIG. 1, C is the read clock 53 which is also the output of the frequency divider 52 of FIG. 1, and Z is the frequency divider of FIG. 56, D is the trigger signal 59 which is the output of the selector 58 of FIG. 1, E0 is the output of the leftmost tap of the column delay circuit 55 of FIG. 2, and E1 is the second from the left end of the column delay circuit 55 of FIG. Tap output, E2 is the output of the center tap of the column delay circuit 55 of FIG. 2, E3 is the output of the second tap from the right end of the column delay circuit 55 of FIG. 2, and E4 is the right end of the column delay circuit 55 of FIG. The signal waveforms of the tap outputs are shown.

  FIG. 3 shows signal waveforms in the optimization mode, and the data strobe signal 57 is selected as the trigger signal 59. The output B of the main shifter 51 delayed from the output A of the oscillation circuit 50 and the output B of the main shifter 51 divided by 2 by the frequency divider 52 are C. The read clock 53 is delayed by C and the sub shifter 54 delays E0, E0. E1, E2, E3, and E4 are sequentially delayed by the column delay circuit 55.

  As shown by the waveforms C and E2 in FIG. 3, the C waveform as the read clock 53 and the output E2 of the center tap of the column delay circuit 55 are out of phase by 90 degrees. The trigger signal 59, D, has a duty ratio that deviates from 1: 1, and the L period is longer than the H period.

  Q0 to Q4 in FIG. 3 are values obtained by sampling E0 to E4 in synchronization with the rising edge of D which is the trigger signal 59. Also, P0 to P4 in FIG. 3 are values obtained by sampling E0 to E4 in synchronization with the falling edge of D as the trigger signal 59. In FIG. 2, the trigger signal 59 is inverted and non-inverted by the differential output buffer 43 in FIG. 2, and the FF group 44 of the inverted clock operation synchronized with the edge of the trigger signal 59 and the FF group 45 of the non-inverted clock operation are latched. Represented as: As shown in FIG. 2, P0 to P4 and Q0 to Q4 are added by adders 46a and 46b such that ΣP = P0 + P1 + P2 + P3 + P4 and ΣQ = Q0 + Q1 + Q2 + Q3 + Q4, respectively, and the subtracter 47 calculates the difference between the data. The output latched by the latch 48 is the output of the phase comparator 60 (R = ΣQ−ΣP).

  Here, referring back to FIG. 3, the relationship between the timing D of the trigger signal 59 and the output of the phase comparator 60 (R = ΣQ−ΣP) will be described. In the state of FIG. 3, when the phase difference between the output E2 of the center tap of the cascade delay circuit 55 and D which is the trigger signal 59 is viewed, the duty ratio of the trigger signal 59 deviates from 1: 1 and the width of the H period. The H period of D, which is the trigger signal 59, enters the middle of the L period of the output E2 of the center tap of the column delay circuit 55. Hereinafter, the description will be made assuming that the phase difference between the output E2 of the center tap of the column delay circuit 55 and the trigger signal D in the state of FIG. 3 is zero.

  Looking at the values of Q0 to Q4 in the state of FIG. 3, since three are L and two are H, the value of ΣQ = Q0 + Q1 + Q2 + Q3 + Q4) is 2. Similarly, since the value of ΣP = P0 + P1 + P2 + P3 + P4 is also 2, the output of the phase comparator 60 (R = ΣQ−ΣP) is 0. That is, if the phase difference between the output E2 of the center tap of the column delay circuit 55 and the trigger signal 59, D, is zero, the output of the phase comparator 60 (R = ΣQ−ΣP) is zero.

  FIG. 4 is a waveform diagram when the timing of D which is the trigger signal 59 is slightly delayed from the state of FIG. 3, and the symbols in the figure are the same as those in FIG. In FIG. 4, the timing of D which is the trigger signal 59 is slightly delayed and Q3 is changed from H to L, so the value of ΣQ = Q0 + Q1 + Q2 + Q3 + Q4 is decreased to 1. The falling timing of D, which is the trigger signal 59, is also delayed by the same amount, and P2 changes from L to H. Therefore, the value of ΣP = P0 + P1 + P2 + P3 + P4 increases to 3. Then, the output (R = ΣQ−ΣP) of the phase comparator 60 decreases from 0 to −2 from R = 1−3 = −2. Thus, if the phase delay of D as the trigger signal 59 with respect to the output E2 of the center tap of the column delay circuit 55 is positive, the output of the phase comparator 60 (R = ΣQ−ΣP) becomes a negative value. .

  Conversely, FIG. 5 is a waveform diagram when the phase delay of D, which is the trigger signal 59, is negative from the state of FIG. 3, that is, when the timing of D, which is the trigger signal 59, is slightly advanced. Since the trigger signal 59 is accelerated, the value of ΣQ = Q0 + Q1 + Q2 + Q3 + Q4 increases from 2 to 3, and the value of ΣP = P0 + P1 + P2 + P3 + P4 decreases from 2 to 1, so the output of the phase comparator 60 (R = ΣQ−ΣP) Increases from 0 to 2. Thus, if the phase delay of D, which is the trigger signal 59, with respect to the output E2 of the center tap of the column delay circuit 55 is negative, the output of the phase comparator 60 (R = ΣQ−ΣP) becomes a positive value. .

  As can be seen by comparing the cases of FIG. 3, FIG. 4 and FIG. 5, the phase comparator 60 numerically outputs the phase difference with respect to the output E2 of the center tap of the column delay circuit 55 at the timing D, which is the trigger signal 59. can do. When the output of the phase comparator 60 (R = ΣQ−ΣP) is negative, the phase of the trigger signal 59 is delayed, and when the output of the phase comparator 60 (R = ΣQ−ΣP) is positive, the trigger is triggered. The phase of D which is the signal 59 is earlier. As described above, since the phase of the waveform C of the read clock 53 and the output E2 of the center tap of the column delay circuit 55 are shifted by 90 degrees, the trigger E and the trigger E2 of the center tap of the column delay circuit 55 are shifted. If the phase difference between D as the signal 59 is zero, the phase difference between C as the read clock 53 and D as the trigger signal 59 is 90 degrees. Therefore, if the output of the phase comparator 60 (R = ΣQ−ΣP) is zero, the rising edge and falling edge of C, which is the read clock 53, are the middle of the rising edge and falling edge of D, which is the trigger signal 59. Located in. If the phase difference between C as the read clock 53 and D as the trigger signal 59 is 90 degrees or less, the output of the phase comparator 60 (R = ΣQ−ΣP) becomes positive, and It can be said from the comparison between FIG. 4 and FIG. 5 that the output (R = ΣQ−ΣP) of the phase comparator 60 becomes negative if the phase difference of D which is the trigger signal 59 is 90 degrees or more.

  Finally, consider a case where the duty ratio of D, which is the trigger signal 59, has changed. FIG. 6 is a waveform diagram in the case where the phase of D which is the trigger signal 59 does not change and only the duty ratio is changed from the state of FIG. 3, and the H period of D which is the trigger signal 59 is longer than the L period. It is. Since the H period becomes longer due to the change in the duty ratio, the rising edge of D, which is the trigger signal 59, becomes faster, and the value of ΣQ = Q0 + Q1 + Q2 + Q3 + Q4 increases from 2 to 3. Conversely, since the falling edge is delayed, the value of ΣP = P0 + P1 + P2 + P3 + P4 increases from 2 to 3. Since ΣP and ΣQ increase by the same amount, the output of the phase comparator 60 (R = ΣQ−ΣP) remains zero. Thus, the phase comparator 60 can perform phase comparison without being affected by the duty ratio of D, which is the trigger signal 59.

  Returning to FIG. 1 again, the operation after the phase comparator 60 will be described. The output of the phase comparator 60 is input to the integrating circuit 61. The output of the integrating circuit 61 gradually increases when the state where the output of the phase comparator 60 is on average zero or more continues, and gradually when the state where the output of the phase comparator 60 is on average less than zero continues. If the output of the phase comparator 60 is zero on average, it does not greatly increase or decrease while pointing to a stable value. During the read cycle, the SDRAM outputs a DQS signal that becomes the data strobe signal 57, and this becomes the trigger signal 59. The DQS signal, which is a signal passed between chips, is a disturbance such as noise, crosstalk, and ground bounce. Depending on the case, the position of the edge may move back and forth. The purpose of inserting the integrating circuit 61 is to remove the disturbance and stabilize the circuit operation thereafter.

  The output of the integrating circuit 61 is latched by the data latch 64. The data latch 64 operates in accordance with an instruction from the control circuit 62. In the optimization mode, the control circuit 62 instructs the data latch 64 not to change the output by holding the output. The reason for doing so is that the output of the data latch 64 instructs the main shifter 51 to set the main delay amount 65. However, if the instruction is changed, a glitch may occur in the output of the main shifter 51. This is because the read clock 53 is disturbed if it malfunctions. The phase comparator 60 measures the phase of the trigger signal 59 in the optimization mode, but the data latch 64 waits for the end of the read cycle to update the output, so the result of the phase measurement of the trigger signal 59 is the phase of the read clock 53. Is reflected in the next read cycle.

  If the time at which the main delay amount 65 is reflected is ignored, it can be said that the main shifter 51 adjusts the delay amount according to the output of the integration circuit 61. Since the output of the integrating circuit 61 is obtained by integrating the output of the phase comparator 60, if the phase difference between the read clock 53 and the trigger signal 59 is 90 degrees or less, the output of the phase comparator 60 becomes positive. The output gradually increases and the delay amount of the main shifter 51 also gradually increases. When the delay amount of the main shifter 51 is increased, the phase of the read clock 53 is delayed. Therefore, the phase difference between the read clock 53 and the trigger signal 59 increases and gradually approaches 90 degrees, and when the phase difference reaches 90 degrees, the phase comparator 60. The output of the integration circuit 61 stops increasing / decreasing. On the contrary, if the phase difference between the read clock 53 and the trigger signal 59 is 90 degrees or more, the output of the phase comparator 60 becomes negative, the output of the integrating circuit 61 gradually decreases, and the delay amount of the main shifter 51 gradually increases. To decrease. When the delay amount of the main shifter 51 decreases, the phase of the read clock 53 advances. Therefore, the phase difference between the read clock 53 and the trigger signal 59 decreases and gradually approaches 90 degrees, and when the phase difference reaches 90 degrees, the phase comparator 60. The output of the integration circuit 61 stops increasing / decreasing.

  Thus, by feeding back the output of the phase comparator 60 to the delay amount of the main shifter 51, the phase difference between the read clock 53 and the trigger signal 59 can be controlled to be 90 degrees. In the optimization mode, the data strobe signal 57 selected by the selector 58 is used as the trigger signal 59, so that the phase difference of the read clock 53 with respect to the data strobe signal 57 is controlled to 90 degrees. An advantageous phase read clock 53 is obtained.

  Up to this point, the operation in the optimization mode has been described, but the read clock generation circuit of the embodiment of the present invention has a calibration mode in addition to the optimization mode. The mode switching is controlled by the control circuit 62, and the mode is switched to the calibration mode when not in the read cycle. The reason for providing the calibration mode is to cope with the diffusion variation of the delay circuit.

  Of the read clock generation circuit, the three circuits of the main shifter 51, the sub shifter 54, and the cascade delay circuit 55 are configured using delay elements. The delay time due to the delay element varies depending on the characteristics of the transistors making up the circuit and the amount of capacitance components parasitic on the circuit, so there is little relative variation when compared within the same LSI chip, but the characteristics and parasitic capacitance vary from lot to lot. Due to variations, there may be a large difference when the delay times of the delay elements are compared between LSI chips with different production lots. The purpose of the calibration mode is to obtain a necessary delay amount by adjusting the number of delay elements through which the clock passes in the main shifter 51 and the sub shifter 54.

  In the calibration mode, the control circuit 62 switches the selector 58 to select the output of the frequency divider 56 as the trigger signal 59. The output of the frequency divider 56 is obtained by dividing the output of the oscillation circuit 50 by 2 and has the same frequency as the read clock 53. As described above, the read clock generation circuit is a feedback control system as a whole, and the output of the phase comparator 60 becomes zero when the phase difference between the output of the center tap of the cascade delay circuit 55 and the trigger signal 59 is zero. And stable. The condition for stabilizing the state in the calibration mode is that the sum of the delay amount of the main shifter 51, the delay amount of the sub shifter 54, and the delay amount from the input of the column delay circuit 55 to the output of the center tap is a half cycle. That is, the edges of the output of the peripheral 56 and the output of the center tap of the column delay circuit 55 overlap each other.

  The three circuits of the main shifter 51, the sub shifter 54, and the cascade delay circuit 55 all use delay elements having the same characteristics, and differ only in the number of stages through which the clock passes. Therefore, the number of delay elements through which the clock passes in the main shifter 51 and the number of delay elements through which the clock passes through the path from the input of the sub shifter 54 to the center tap of the column delay circuit 55 are adjusted to be the same. If the delay amount is controlled, when the feedback control system is stabilized in the calibration mode, the delay amount of the main shifter 51 becomes the 90-degree phase of the read clock 53, and from the input of the sub shifter 54 to the center tap of the column delay circuit 55. The amount of delay is the 90-degree phase of the read clock 53.

  In order to make such adjustment, the data latch 64 has two outputs. In the calibration mode, the main delay amount 65 that is an instruction of the delay amount to the main shifter 51 and a correction delay amount 67 that is an instruction of the delay amount to the sub shifter 54 are provided. Control both. The main delay amount 65, which is an instruction of the delay amount to the main shifter 51, is specifically the number of delay elements that allow the clock to pass between the input and output. In the calibration mode, the data latch 64 determines the output of the integrating circuit 61 as the main delay. A quantity of 65 is given as an indication. Although the output of the same integration circuit 61 is given to the sub shifter 54 as an instruction of the correction delay amount 67, the operation of the sub shifter 54 is slightly different from that of the main shifter 51. The sub-shifter 54 passes the clock between the input and output of the sub-shifter 54 so that the number of delay elements through which the clock passes through the path from the input of the sub-shifter 54 to the center tap of the column delay circuit 55 matches the indicated value. The number of delay elements to be operated is configured to be a value obtained by subtracting half of the number of delay elements in the column delay circuit 55 from the instructed value.

  By adopting such a configuration and control, the value indicated by the output of the integration circuit 61 when the feedback control system is stabilized becomes the number of delay elements necessary to obtain a delay amount corresponding to the 90-degree phase of the read clock 53. The phase difference from the input of the sub-shifter 54 to the center tap of the column delay circuit 55 is calibrated to 90 degrees. The data latch 64 updates the output to the sub-shifter 54 in the calibration mode, but retains the output to the sub-shifter 54 when not in the calibration mode. Therefore, during the optimization mode, the center tap of the column delay circuit 55 is input from the input of the sub-shifter 54. The phase difference up to is maintained at 90 degrees.

  So far, the optimization mode and the calibration mode have been described separately for the sake of simplicity.However, since it is actually necessary to perform calibration between read cycles, each calibration mode and optimization mode can be switched alternately. It is necessary to devise so that the feedback control system operates stably in the mode. The save register 63 in FIG. 1 is a component for realizing the device.

  FIG. 7 is a block diagram of the internal configuration of the integrating circuit 61 and the data latch 64 and peripheral circuits. In FIG. 7, 51 is a main shifter, 54 is a sub-shifter, 60 is a phase comparator, 61 is an integration circuit, 63 is a save register, 64 is a data latch, 65 is a main delay amount, 67 is a correction delay amount, and 71 is a phase comparison. 60 is an adder, 73 is a selector, 74 is a register, 75 is an output of the integrating circuit 61, 76 is a register, 77 is a selector, and 78 is a register. Hereinafter, the operations in the optimization mode and the calibration mode except for the mode transition of the integration circuit 61 and the data latch 64 will be described with reference to FIG.

  In the optimization mode except during mode transition, the integration circuit 61 performs an integration operation. The adder 72 adds the output 71 of the phase comparator 60 and the output 75 of the integrating circuit 61, the selector 73 selects the output of the adder 72, and the register 74 latches the output of the selector 73. Each time the register 74 repeats latching, the output 71 of the phase comparator 60 continues to be added to the output 75 of the integrating circuit 61, so that the output 75 of the integrating circuit 61 takes the value obtained by integrating the output 71 of the phase comparator 60. Even in the calibration mode except during the mode transition, the integration circuit 61 performs integration in the same operation as in the optimization mode.

  In the calibration mode except during the mode transition, the selector 77 of the data latch 64 selects the output 75 of the integrating circuit 61, and both the register 76 and the register 78 latch the output 75 of the integrating circuit 61. Since the same value is fed back to the main shifter 51 and the sub-shifter 54 in the calibration mode, the register 76 and the register 78 continue to output the same value during the calibration mode. When a fixed time elapses after entering the calibration mode, the correction delay amount 67 output from the register 76 converges indicating the number of stages of delay elements corresponding to the 90-degree phase of the read clock.

  In the optimization mode except during the mode transition, the selector 77 selects the output 75 of the integration circuit 61, and the register 78 latches the output 75 of the integration circuit 61. However, the register 76 enters the hold state, and the same correction as in the calibration mode. Continue to hold the delay amount 67. As a result, the correction delay amount 67 becomes constant, and the delay amount of the sub shifter 54 is maintained at 90 degrees.

  Next, the operation when shifting from the optimization mode to the calibration mode will be described with reference to FIG. FIG. 8 is a signal path diagram when shifting from the optimization mode to the calibration mode, and ineffective signal paths are indicated by dotted lines. The symbols in the figure are the same as those in FIG. The register 76 takes in a correction delay amount 67 obtained by copying the output 75 of the integration circuit 61 during the calibration mode, and holds it during the optimization mode. Therefore, it can be said that the register 76 holds the state at the end of the previous calibration mode. . When shifting from the optimization mode to the calibration mode, the selector 77 selects the correction delay amount 67 and the register 78 copies the correction delay amount 67. The selector 73 also selects the correction delay amount 67, and the register 74 also copies the correction delay amount 67. As a result, the three registers are restored to the state at the end of the previous calibration mode.

  Since the register 74 has the main delay amount 65 of the main shifter 51 optimized during the optimization mode, the value of the register 74 is stored in the save register 63 at the same time as the register 74 copies the correction delay amount 67. Make a copy. As a result, when the calibration mode is changed to the optimization mode, it is possible to return to the last state in the previous read cycle.

  FIG. 9 is a signal path diagram when shifting from the calibration mode to the optimization mode, and ineffective signal paths are indicated by dotted lines. The symbols in the figure are the same as those in FIG. During the calibration mode, the save register 63 stores the main delay amount 65 of the main shifter 51 optimized during the immediately preceding optimization mode, and this value is stored in the register 74 and the register 78 when returning to the optimization mode. make a copy. Therefore, when shifting from the calibration mode to the optimization mode, the selector 73 and the selector 77 select the output of the save register 63, and the register 74 and the register 78 latch the value output by the save register 63. Since the register 76 holds the correction delay amount 67 until the next calibration mode starts, the output is held when the calibration mode is changed to the optimization mode.

  By using the data latch 64 and the save register 63 in this way, the last state in the calibration mode is saved, restored when returning to the calibration mode next, and the last state in the optimization mode is saved. Next, since it can be restored when returning to the optimization mode, the calibration mode and the optimization mode are mixed, and the feedback control operation in the optimization mode and the feedback control operation in the calibration mode are paralleled in a time-sharing manner as a whole. Can be executed.

  FIG. 10 is a simplified block diagram of a memory interface circuit using the read clock generation circuit of the present invention. In FIG. 10, 11 is a DDR-SDRAM, 12 is a DQS signal, 13a and 13b are data signals, 15 is an input buffer, 16 is a delay circuit, 17 is a data latch, 18 is read data, 21 is a memory interface circuit, 22 is A read clock generation circuit, 23 is a main state machine, 57 is a data strobe signal, 53 is a read clock, 50 is an oscillation circuit, 60 is a phase comparator, and 62 is a control circuit. Although the read clock generation circuit 22 shown in FIG. 10 is a simplified block diagram due to space limitations, the read clock generation circuit shown in FIG. 1 is actually used. It should be understood that only the minimum necessary blocks are extracted and described in FIG.

  Hereinafter, the latch operation of the data signal 13 in the memory interface circuit 21 using the read clock generation circuit 22 of the present invention will be described with reference to FIG. The DDR-SDRAM 11 is connected to the memory interface circuit 21. When the DDR-SDRAM 11 is read-accessed, the DDR-SDRAM 11 outputs the DQS signal 12 and the data signal 13a simultaneously. The memory interface circuit 21 takes in the DQS signal 12 and the data signal 13 a through the input buffer 15. The DQS signal 12 that has passed through the input buffer 15 is a data strobe signal 57 that is inverted every word of the data signal 13, and the read clock generation circuit 22 receives the data strobe signal 57 and generates a read clock 53. The read clock generation circuit 22 includes a phase comparator 60, a delay circuit 16, an oscillation circuit 50, and a control circuit 62 as main components. The oscillation circuit 50 is a source of all clocks in the read clock generation circuit 22 including the read clock 53.

  The main state machine 23 sends a read command to the control circuit 62 in the read clock generation circuit 22, and the control circuit 62 manages the timing based on the read command and outputs a correct read clock 53, and a delay circuit. The calibration mode for calibrating 16 is switched.

  In the calibration mode, the delay amount of the delay circuit 16 is corrected so that the delay amount of the delay circuit 16 is ¼ of the clock period. On the other hand, in the optimization mode, the phase comparator 60 measures the phase difference between the data strobe signal 57 and the clock output from the oscillation circuit 50, and the read clock 53 output from the delay circuit 16 is 90 degrees out of phase with the data strobe signal 57. The delay amount of the delay circuit 16 is optimized so as to be delayed. Then, the edge of the read clock 53 is located in the middle between the edges of the data strobe signal 57. Since the change point of the data signal 13b and the data strobe signal 57 is the same at the exit of the input buffer 15, the data latch 17 can be latched at the timing when the data signal 13b is most stable by the read clock 53 output from the read clock generation circuit 22. I can do it. With such a configuration and operation, the read data 18 output from the data latch 17 becomes reliable data without error.

  As described above, the read clock generation circuit according to the present invention controls so that the edge of the read clock is positioned at the center of the edge of the data strobe signal, so that even if the duty ratio of the data strobe signal changes, the latch The timing does not go back and forth from the optimal position. In addition, since the integration circuit is used in the feedback control loop, the latch timing does not move back and forth from the optimum position due to the influence of random disturbance. Furthermore, since it has a mechanism for calibrating the delay amount of the delay circuit, the latch timing does not move back and forth from the optimum position due to diffusion variation of the semiconductor integrated circuit. Therefore, by using the read clock generating circuit according to the present invention, the data signal can be latched in synchronization with a stable clock even in a situation where the data strobe signal waveform is deformed or disturbed by a disturbance.

  In this embodiment, the oscillation circuit 50 corresponds to the clock generation circuit of the present invention. The phase comparator 60, the integrating circuit 61, and the data latch 64 correspond to the phase difference measuring circuit of the present invention. The data latch 17 corresponds to the memory circuit of the present invention. The column delay circuit 55 corresponds to the multi-output delay circuit of the present invention. The FF group 44 for the inverted clock operation and the FF group 45 for the non-inverted clock operation correspond to the parallel latch circuit of the present invention.

  The memory circuit of the present invention may use a static RAM having a bit width corresponding to the data width of the synchronous memory connected to the memory interface circuit of the present invention in addition to the data latch 17 of the present embodiment. Good. If a static RAM is used, read data of a plurality of words can be held, so that read data can be supplied to the internal circuit with a certain time delay from the read command even if the phase of the read clock is changed.

  The phase difference measuring circuit of the present invention individually measures the phase difference of the rising edge of the data strobe signal with respect to the read clock and the phase difference of the falling edge of the data strobe signal with respect to the read clock, and measures the average of both. It may be output as a phase difference. Thus, even when a latch that operates on both the rising edge and the falling edge cannot be used due to circuit restrictions, a phase difference measurement circuit that meets the object of the present invention can be configured.

  The phase difference measurement circuit of the present invention measures the phase difference of the data strobe signal with respect to the read clock a plurality of times, and outputs a value obtained by averaging a plurality of measurement results as a measured phase difference. Also good. In this embodiment, the output of the phase difference measuring circuit is smoothed using an integrating circuit using an IIR filter, but the output of the phase difference measuring circuit is input to the shift register, and the FIR for calculating the addition average of each stage of the shift register. Even if a smoothing filter of the type is used, the same control characteristics as those of the integrating circuit can be obtained.

  In the present embodiment, the phase difference measuring circuit of the present invention measures the phase difference during the read cycle and holds the phase difference to be output when not in the read cycle. However, it may not be held. As shown in FIG. 7, the registers 78 and 76 immediately before the main shifter 51 and the sub-shifter 54, which are delay circuits, are portions that hold the phase difference. In this embodiment, the data latch 64 is included in the phase difference measurement circuit. However, the data latch 64 may be included on the delay circuit side due to the circuit configuration. In that case, the delay circuit stores the phase during the read cycle and ignores the output of the phase difference measurement circuit during the period not during the read cycle.

  The phase difference measuring circuit of the present invention includes a multi-output delay circuit having a plurality of outputs and a parallel latch circuit in this embodiment, and the input of the multi-output delay circuit is a clock output from the clock generation circuit. The circuit measures the phase difference by latching the states of multiple outputs of the multi-output delay circuit at the change point of the data strobe signal. However, if the method measures the phase difference between the data strobe signal and the read clock, Not limited to this.

  For example, the phase difference measurement circuit of the present invention includes a multi-output delay circuit having a plurality of outputs, a counter, and a parallel latch circuit. The input of the multi-output delay circuit is a clock output from the clock generation circuit, and the counter generates a clock. The parallel latch circuit measures the phase difference by latching the counter at the change point of the data strobe signal and the states of the plurality of outputs of the multi-output delay circuit. Good. Alternatively, the parallel latch circuit may measure the phase difference by latching the output state of the counter at the change point of the data strobe signal without using the multi-output delay circuit together.

  FIG. 14 is a block diagram of a phase difference measuring circuit using a Johnson counter instead of the multi-output delay circuit. In FIG. 14, 59 is a trigger signal, 60 is a phase comparator, 41 is a clock input, 43 is a differential output buffer, 44 is an FF group for inversion clock operation, 45 is an FF group for non-inversion clock operation, and 46a and 46b are additions. , 47 is a subtractor, 48 is a data latch, 80a is a Johnson counter, 81 is an FF group of the Johnson counter 80a, and 82 is an inverter of the Johnson counter 80a. Hereinafter, the phase comparison operation will be described with reference to FIG. The Johnson counter 80a includes an FF group 81 and an inverter 82. The Johnson counter 80a inverts the last stage of the FF group 81 by the inverter 82 and inputs it to the first stage FF. The output of the Johnson counter 80a is 00000 → 10000 → 11000 → 11100 → 11110 → 11111 → 01111 → 00111 → 00011 → It goes around with 10 clocks like 00001 → 00000. Since the outputs E0, E1, E2, E3, and E4 of the FF group 81 of the Johnson counter 80a are obtained by dividing the clock input 41 by 10, the clock input 41 must have a frequency 10 times that of the read clock.

  For each clock of the clock input 41, the outputs E0, E1, E2, E3, E4 of the FF group 81 of the Johnson counter 80a rise from L to H sequentially from the left, and the right end output E4 changes most slowly. When the output state of the FF group 81 of the Johnson counter 80a is latched by the FF group 45 of the non-inverted clock operation of the phase comparator 60, the time of the rising edge of the trigger signal 59 is the FF group of the non-inverted clock operation in FIG. Of the 45 outputs Q0, Q1, Q2, Q3, and Q4, it is quantified as the number of bits that are H. The adder 46b converts the number of FFs whose output is H into a multi-bit numerical value (ΣQ = Q0 + Q1 + Q2 + Q3 + Q4). Similarly, when the output state of the FF group 81 of the Johnson counter 80a is latched by the FF group 44 of the inversion clock operation of the phase comparator 60, the time of the falling edge of the trigger signal 59 becomes the FF of the inversion clock operation in FIG. Of the outputs P0, P1, P2, P3, and P4 of the group 44, they are digitized as the number of bits that are H. The adder 46a converts the number of FFs whose output is H into a multi-bit numerical value (ΣP = P0 + P1 + P2 + P3 + P4). The subtractor 47 calculates the average of the rising edge time and the falling edge time (R = ΣQ−ΣP).

  FIG. 15 is a waveform diagram showing a time change of each signal of the phase difference measuring circuit using the Johnson counter 80a. In FIG. 15, A is a clock input 41, D is a trigger signal 59, E0 to E4 are signal waveforms of outputs of the FF group 81 of the Johnson counter 80a.

  As can be seen by comparing the waveforms from E0 to E4 in FIG. 3 with the waveforms from E0 to E4 in FIG. 15, using the Johnson counter 80a, a signal waveform similar to that obtained when the multi-output delay circuit is used can be obtained. Therefore, if the value obtained by latching the output of the FF group 81 of the Johnson counter 80a and the values P0 to P4 and Q0 to Q4 are processed in the same manner as the phase difference measuring circuit using the multi-output delay circuit of FIG. Is obtained numerically.

  As can be seen from the waveform diagram of FIG. 15, the Johnson counter has the property of changing one bit at a time, so that the correct value can be latched at any time when the output is latched. For example, if the output of the 2-bit binary counter changes from 00 → 01 → 10 → 11 → 00 and the counter output is latched when changing from 01 to 10, an incorrect value such as 00 or 11 is latched. However, the Johnson counter does not read the wrong value.

  As with the Johnson counter, there is a Gray code counter as a counter having the property that the output changes one bit at a time. For example, the 3-bit gray code counter changes from 000 → 001 → 011 → 010 → 110 → 111 → 101 → 100 → 000. FIG. 16 is a block diagram of a phase difference measuring circuit when a Gray code counter is used instead of the Johnson counter. The output of the Gray code counter 80b does not monotonously increase or decrease the number of bits that are 1 unlike the output of the multi-output delay circuit or the output of the Johnson counter. Therefore, the Gray code is calculated numerically as in 83a and 83b. Requires a decoder that converts to a suitable binary code. Since the processing after decoding is the same as that in the case of using the Johnson counter, the detailed description is omitted.

  Although the case where the multi-output delay circuit is not used together has been introduced here, it may be used together. If a counter is used, the number of transistors may be reduced as compared with arranging delay elements. However, in order to measure a small time difference, it is necessary to increase the clock frequency. When a multi-output delay circuit is used, a small time difference of less than one clock cycle can be measured, and using both a counter and a multi-output delay circuit may reduce both the number of transistors and the clock frequency within a reasonable range. .

  The present invention can be applied to a memory interface circuit for connecting a DDR-SDRAM, and can also be applied to a memory interface circuit for connecting a DDR2-SDRAM, a DDR3-SDRAM, or the like, which is an extension of the DDR-SDRAM.

1 is a block diagram of a read clock generation circuit in an embodiment of the present invention. Block diagram of cascade delay circuit and phase comparator in an embodiment of the present invention Waveform diagram showing time variation of each signal of read clock generation circuit Waveform diagram when the trigger signal timing is slightly delayed Waveform diagram when the timing of the trigger signal is slightly advanced Waveform diagram when the H period of the trigger signal is longer than the L period Internal configuration of integration circuit and data latch, and block diagram of peripheral circuit Signal path diagram when shifting from optimization mode to calibration mode Signal path diagram when shifting from calibration mode to optimization mode Simplified block diagram of a memory interface circuit using the read clock generation circuit of the present invention The figure which shows the path | route of the read clock in the structure of patent document 1 Waveform diagram showing signal waveform on circuit in configuration of Patent Document 1 Waveform diagram when the duty ratio of the DQS signal changes Block diagram of phase difference measurement circuit using Johnson counter Waveform diagram showing time variation of each signal of phase difference measurement circuit using Johnson counter Block diagram of phase difference measurement circuit using gray code counter

Explanation of symbols

11 SDRAM
12 DQS signal 13a, 13b Data signal 15 Input buffer 16 Delay circuit 17 Data latch 18 Read data 21 Memory interface circuit 22 Read clock generation circuit 23 Main state machine 41 Clock input 42 Delay element 43 Differential output buffer 44 FF of inverted clock operation Group 45 FF group of non-inverted clock operation 46a, 46b Adder 47 Subtractor 48 Data latch 50 Oscillator 51 Main shifter 52 Divider 53 Read clock 54 Sub shifter 55 Cascade delay circuit 56 Divider 57 Data strobe signal 58 Selector 59 Trigger signal 60 Phase comparator 61 Integration circuit 62 Control circuit 63 Save register 64 Data latch 65 Main delay amount 67 Correction delay amount 71 Output of phase comparator 72 Adder 73 Selector 7 Register 75 integrator output 76 register 77 Selector 78 register 80a Johnson counter 80b gray code counter 81 counters FF group 82 inverters 83a, 83 b decoder

Claims (9)

A memory interface circuit comprising a clock generation circuit, a delay circuit, a phase difference measurement circuit, and a memory circuit,
Synchronous memory that outputs data strobe signal and data signal in synchronization with the clock can be connected.
The delay circuit delays the clock output from the clock generation circuit and outputs it as a read clock,
The phase difference measuring circuit measures a phase difference between the input data strobe signal and the read clock,
The delay circuit adjusts the delay time of the read clock according to the measured phase difference,
The memory interface circuit, wherein the memory circuit captures the data signal in synchronization with the read clock. 2. The memory interface circuit according to claim 1, wherein the memory circuit is a latch circuit or a static RAM having a bit width corresponding to a data width of a synchronous memory. The phase difference measurement circuit measures the phase difference of the rising edge of the data strobe signal with respect to the read clock and the phase difference of the falling edge of the data strobe signal with respect to the read clock, and the average of both is measured. 3. The memory interface circuit according to claim 1, further comprising a function of outputting as a phase difference. The phase difference measurement circuit measures a phase difference of the data strobe signal with respect to the read clock a plurality of times, and has a function of outputting a value obtained by averaging a plurality of measurement results as the measured phase difference. 4. The memory interface circuit according to claim 1, wherein: 5. The memory interface circuit according to claim 1, wherein the phase difference measuring circuit measures a phase difference during a read cycle and holds an output phase difference when the read cycle is not in progress. The phase difference measuring circuit includes a multi-output delay circuit having a plurality of outputs and a parallel latch circuit,
The input of the multi-output delay circuit is a clock output from the clock generation circuit,
6. The memory interface circuit according to claim 1, wherein the parallel latch circuit measures a phase difference by latching a plurality of output states of the multi-output delay circuit at a change point of the data strobe signal. The phase difference measuring circuit includes a multi-output delay circuit having a plurality of outputs, a counter, and a parallel latch circuit,
The input of the multi-output delay circuit is a clock output from the clock generation circuit,
The counter counts a clock output from the clock generation circuit,
6. The memory interface according to claim 1, wherein the parallel latch circuit measures a phase difference by latching a state of a plurality of outputs of the counter and the multi-output delay circuit at a change point of the data strobe signal. circuit. The phase difference measuring circuit includes a counter and a parallel latch circuit,
The counter counts a clock output from the clock generation circuit,
6. The memory interface circuit according to claim 1, wherein the parallel latch circuit measures a phase difference by latching an output state of the counter at a change point of the data strobe signal. 9. The memory interface circuit according to claim 7, wherein the counter included in the phase difference measuring circuit is a Johnson counter or a Gray code counter.

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