JP2008065862A - Semiconductor memory device - Google Patents

Abstract

Each memory core operates independently while suppressing the circuit scale.
A semiconductor memory device includes a row clock generator for generating a clock to be supplied to a first core and a column clock generator / burst counter, and a row clock for generating a clock to be supplied to a second core. 10B, a column clock generator / burst counter 20B, and a power supply system circuit 201 that supplies power to the first core 100A and the second core 100B.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor memory device having a plurality of memory cores.

Conventionally, a semiconductor memory device including a plurality of memory units such as DRAMs and an operation timing control signal output circuit that outputs an operation timing signal common to the plurality of memory units has been disclosed (for example, see Patent Document 1). ). Since the semiconductor memory device of Patent Document 1 includes one operation timing control signal output circuit regardless of the number of memory units, the circuit area can be reduced and the chip area can be reduced.
JP 2005-339041 A

  However, in Patent Document 1, in order to control a plurality of memory units with one operation timing control signal output circuit, the clock, command, address, and data input / output circuit of each memory unit must be made common. For this reason, the bit configuration of each memory unit cannot be changed or operated independently. On the other hand, even if each memory unit is made independent, there is a demand for making the circuit scale of the entire semiconductor memory device as small as possible.

  The present invention has been proposed to solve the above-described problems, and an object thereof is to provide a semiconductor memory device in which each memory core can operate independently while suppressing the circuit scale.

  The invention of claim 1 is a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction, a row decoder for selecting a memory cell in the row direction of the memory cell array, and a memory cell in the column direction of the memory cell array A plurality of memory cores including m memory banks (m is a natural number greater than or equal to 2), and data control means for writing or reading data to or from each memory bank. And a plurality of clock generating means for generating independent clocks supplied to the respective memory cores, and a single voltage generating means for generating a voltage to be supplied to each memory core.

  A memory core includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction, a row decoder that selects memory cells in the row direction of the memory cell array, and a column decoder that selects memory cells in the column direction of the memory cell array And m (m is a natural number greater than or equal to 2) memory banks, and data control means for writing / reading data to / from each memory bank.

  Each memory core can operate independently of the other, for example, can operate in different operation modes, clock frequencies, and input / output data bits. In order to realize this, the plurality of clock generation means generate independent clocks and supply these clocks to the respective memory cores.

  Further, the voltage generating means generates a voltage to be supplied to each memory core. The voltage generating means is a single one common to each memory core. As a result, as compared with the case where a plurality of voltage generating means corresponding to each memory core is provided, only one voltage generating means is required, so that the circuit scale can be suppressed.

  Here, the present invention may further comprise a single self-diagnosis control means for generating a self-diagnosis address, a self-diagnosis command and self-diagnosis data. At this time, the clock generation circuit generates a self-diagnosis clock based on a self-diagnosis command generated by the self-diagnosis control means, and each memory core generates a self-diagnosis generated by the self-diagnosis control means. Self-diagnosis may be performed based on the address, self-diagnosis command and self-diagnosis data, and the self-diagnosis clock generated by the clock generation means.

  The above invention may further comprise a single data compression instruction signal generating means for generating a data compression instruction signal for instructing compression of data input to each memory core.

  In the present invention, each memory core can operate independently while suppressing the circuit scale.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a chip configuration of a semiconductor memory device according to an embodiment of the present invention. The semiconductor memory device includes a silicon interposer 1 which is a circuit board on which wiring is formed, an ASIC (Application Specific Integrated Circuit) chip 2 and a memory chip 3 which are arranged on the silicon interposer 1 through micro bumps (not shown). Yes.

  The ASIC chip 2 is connected to the wiring of the silicon interposer 1 through a plurality of micro bumps. These micro bumps are provided in the micro bump region 2a of FIG.

  The memory chip 3 is connected to the wiring of the silicon interposer 1 through a plurality of micro bumps. These micro bumps are provided in the micro bump regions 3a, 3b, and 3c in FIG. The micro bump area 3a is a bump area where data of 0 to 255 bits is input / output, and the micro bump area 3b is a bump area where data of 256 to 511 bits is input / output. The micro bump region 3c is a micro bump region into which commands, addresses, and the like are input.

  FIG. 2 is a diagram showing a layout configuration of the memory chip 2 provided in the semiconductor memory device. The memory chip 2 has a first core 100A and a second core 100B. In the following, the circuit provided in the first core 100A is given an alphabet “A” together with a numeric symbol, and the circuit provided in the second core 100B is given an alphabet “B” together with a numeric symbol.

  The first core 100A has memory banks 80A and 90A composed of DRAM, and a peripheral circuit 98A related to the first core 100A. The second core 100B has memory banks 80B and 90B made of DRAM and a peripheral circuit 98B related to the second core 100B. Note that the DRAMs of the first core 100A and the second core 100B may have the same capacity or different capacities.

  The first core 100A and the second core 100B are configured to be able to operate independently. For example, even if the operation mode, the bit configuration of input / output data (128 bits or 256 bits), and the clock frequency are different, the first core 100A and the second core 100B can operate.

  The power supply system circuit 201 includes, for example, a reference potential generation circuit, a bias voltage generation circuit, a word line boost power supply generation circuit, an internal voltage reduction circuit, and the like. The reference potential generation circuit, the bias voltage generation circuit, the word line boost power supply generation circuit, the internal voltage reduction circuit, and the like do not serve as a noise transmission path, and even if they serve as a noise transmission path, their influence is small. Therefore, the power supply system circuit 201 supplies predetermined power to each of the first core 100A and the second core 100B. That is, the first core 100A and the second core 100B share the power supply system circuit 201. Thereby, the size of the memory chip 2 can be reduced.

  As will be described in detail later, the BIST / TEST circuit 202 controls the first core 100A and the second core 100B simultaneously by supplying predetermined signals to the first core 100A and the second core 100B. That is, the first core 100A and the second core 100B share the BIST / TEST circuit 202. Thereby, the size of the memory chip 2 can be further reduced.

  The wafer test pad 97 is shared by the first core 100A and the second core 100B, and receives a wafer test signal (WFT signal) and an external input signal from the outside as the first core 100A and the second core 100B. To supply.

  The input / output bump pad rows 99A and 99B are formed in the micro bump region shown in FIG. Here, the input / output bump pad row 99A is dedicated to the first core 100A, and supplies commands, addresses, and the like input from the outside to the first core 100A. The input / output bump pad 99 row B is dedicated to the second core 100B and supplies commands, addresses, and the like input from the outside to the second core 100B.

  FIG. 3 is a block diagram showing a configuration of the semiconductor memory device according to the embodiment of the present invention. The semiconductor memory device includes a first core 100A, a second core 100B, a test mode signal generator 51, and a BIST (Built In Self Test) sequencer 52. Since the first core 100A and the second core 100B have the same configuration, the configuration of the first core 100A will be mainly described below.

  The semiconductor memory device includes a row clock generator 10A that generates a row clock, a column clock generator / burst counter 20A that generates a column address or counts a burst, and a row that temporarily stores a row address or counts the number of refreshes. An address buffer / refresh counter 30A, a column address buffer 40A for temporarily storing column addresses, and a data mask buffer 50A for temporarily storing data masks are provided.

  In addition, the semiconductor memory device includes memory banks 80A and 90A for storing data, and a data control circuit 70A for performing control for writing or reading data to or from the memory banks 80A and 90A.

  Further, the semiconductor memory device reads from the input buffer 61A for temporarily accumulating data D inputted from the outside, the input buffer 62A for temporarily accumulating the test mode input signal TD inputted from the outside, and the data control circuit 70A. An output buffer 66A for temporarily accumulating the data Q, and an output buffer 62A for temporarily storing the test mode output signal TQ read from the data control circuit 70A.

  Here, the test mode input signal TD includes test data which is data to be written to the memory bank and an expected value of the test data read from the memory bank in the test mode. The test mode output signal TQ indicates a signal indicating a comparison result between the test data read from the memory bank and its expected value.

  The row clock generator 10A generates a row clock for synchronizing row addresses based on an externally supplied clock (CLK), chip select signal (CSB), act command (ACTB), and refresh signal (REF). The row clock is supplied to the row address buffer / refresh counter 30A and the memory banks 80A and 90A. Further, the row clock generator 10A generates a test diagnosis row clock when a predetermined command in the test mode is supplied from a BIST sequencer 52 described later.

  The column clock generator / burst counter 20A synchronizes column addresses based on a clock (CLK), a chip select signal (CSB), an act command (ACTB), a refresh signal (REF), and a write enable signal (WEB). A column clock is generated to supply the column clock to the column address buffer 40A and the memory banks 80A and 90A. Further, the column clock generator / burst counter 20A generates a test diagnosis column clock when a predetermined command in the test mode is supplied from a BIST sequencer 52 described later.

  The row address buffer / refresh counter 30A temporarily stores the row address Ai (i = 4 to 15) supplied from the outside in synchronization with the row clock generated by the row clock generator 10A, and then stores the row address. This is supplied to the memory banks 80A and 90A. The row address buffer / refresh counter 30A counts the number of refreshes of the memory banks 80A and 90A.

  The column address buffer 40A temporarily stores the column address Ai (i = 0-3) supplied from the outside in synchronization with the column clock generated by the column clock generator / burst counter 20A, and then stores the column address. This is supplied to the memory banks 80A and 90A.

  The data mask buffer 50A temporarily stores a data mask supplied from the outside, and then supplies the data mask to the data control circuit 70A. The test mode control circuit 51 performs control for setting the input buffers 61A and 62A and the data control circuit 70A to the test mode or the normal mode based on a test mode control signal (PTEST) supplied from the outside.

  In the normal mode, the input buffer 61A temporarily stores, for example, 256-bit data D to be written, which is input via 256 multi-bit input terminals, and then supplies the data D to the data control circuit 70A. To do. In the test mode, the input buffer 62A temporarily stores, for example, an 8-bit test mode input signal TD input via eight test data input terminals, and then performs data control on the test mode input signal TD. Supply to circuit 70A.

  On the other hand, the output buffer 66A temporarily stores 256-bit data Q output from the data control circuit 70A in the normal mode, and outputs this data Q to the outside through, for example, 256 multi-bit output terminals. . The output buffer 67A temporarily accumulates the test mode output signal TQk output from the data control circuit 70A during the test mode, and the test mode output signal TQk is externally connected via, for example, eight test data output terminals. Output to.

  The memory bank 80A is composed of DRAM. The memory bank 80A includes a memory cell array 81A composed of a plurality of memory cells arranged in a matrix, a row decoder 82A for selecting a row address (row address), and a column for selecting a column address (column address). A decoder 83A and a sense amplifier 84A for amplifying the voltage of the memory cell when reading data are provided.

  The memory cell array 81A is composed of a plurality of memory cells arranged in a matrix, and has a memory capacity of 16 M bits (= 64 k × 256 bits), for example.

  When a row address is supplied from the row address buffer / refresh counter 30A shown in FIG. 1, the row decoder 82A supplies a signal for selecting a memory cell corresponding to the row address to the memory cell array 81A. Further, when a column address is supplied, the column decoder 83A supplies a column address selection signal for selecting a memory cell corresponding to the column address to the memory cell array 81A. As a result, data is written or read in the memory cell of the memory cell array 81A based on the row address and the column address.

  The memory bank 80A having such a configuration has a large number of input / output pins, for example, 256 input pins and output pins capable of simultaneous input or output of 256-bit data. Or data is written in 256 bits. The memory bank 90A is configured in the same manner as the memory bank 80A, and includes a memory cell array 91A, a row decoder 92A for selecting a row address (row address), and a column decoder for selecting a column address (column address). 93A and a sense amplifier 94A for amplifying the voltage of the memory cell when reading data.

  In the normal mode (so-called x2 mode), the data control circuit 70A, when 512-bit data is supplied from the input buffer 61A in 256 bits in two portions, each has 256 bits to the memory bank 80A and the memory bank 90A. Write all data at once. Further, the data control circuit 70A reads 256-bit data at a time from the memory banks 80A and 90A, temporarily stores 512-bit data, and outputs the 256-bit data twice in bursts. Data Q is supplied to the output buffer 66A.

  In the test mode, when the 8-bit test mode input signal TD is supplied from the input buffer 62A in the test mode, the data control circuit 70A receives the test mode input signal TD obtained by compressing 64 bits of data into one bit. Test data is written to the memory banks 80A and 90A. The data control circuit 70A compares the test data read from the memory banks 80A and 90A with the expected value of the test mode input signal TD, and outputs a test mode output signal TQ representing the comparison result. This is supplied to the output buffer 67A.

  The BIST result output buffer 69 temporarily stores and outputs the test mode output signal TQ output from the first core 100A and the test mode output signal TQ output from the second core 100B. Also good.

  The data control circuit 70A switches between the normal mode and the test mode described above based on the signal from the test mode signal generator 51.

  The test mode signal generator 51 outputs a signal (PTEST) instructing to compress 64-bit data into 1 bit, and the data control circuit 70A of the first core 100A and the data control circuit 70B of the second core 100B. To PTEST. The test mode signal generator 51 is specifically configured as follows.

  FIG. 4 is a block diagram showing a configuration of the test mode signal generator 51. The test mode signal generator 51 includes a negation (NOT) circuit 51a that negates the DTEST signal, a NOT circuit 51b that negates the BIST signal, and a negation that calculates the negative logical product of the signals output from the NOT circuits 51a and 51b. A logical product (NAND) circuit 51c, a NOT circuit 51d that negates the signal output from the NAND circuit 51c, and a negation circuit 51e that negates the signal output from the NOT circuit 51e are provided.

  With such a configuration, the test mode signal generator 51 outputs a high-level PTEST signal when at least one of the DTEST signal and the BIST signal goes high, and the low level when both the DTEST signal and the BIST signal go low. The PTEST signal is output. Thus, the data control circuits 70A and 70B shown in FIG. 3 allow the test mode signal generator 51 to compress the 64-bit data into 1 bit when the BIST or other test mode, which will be described later, is performed. Run the test.

  FIG. 5 is a block diagram showing the configuration of the BIST sequencer 52. The BIST sequencer 52 generates a self-diagnosis address, a self-diagnosis command, and self-diagnosis data during a BIST (Built In Self Test). Specifically, the BIST sequencer 52 includes a sequencer 52a, an address generator 52b that generates a self-diagnosis address, a command generator 52c that generates a self-diagnosis command, and a data generator that generates self-diagnosis data. 52d.

  The sequencer 52a enables the BIST operation when a high-level BIST signal is input, and disables the BIST operation when a low-level BIST signal is input. When the clock is input, the BIST sequencer 52a causes the address generator 52b to generate a self-diagnosis address, causes the command generator 52c to generate a self-diagnosis command, and sends data to the self-diagnosis data generator 52d. generate.

  The signal output from the test mode signal generator 51 and the command, address, and data output from the BIST sequencer 52 are supplied to the following input circuit.

  FIG. 6 is a diagram illustrating the configuration of the input circuit. In FIG. 6, only representative bump pads of the input / output bump pad rows 99A and 99B are shown, and other bump pads are omitted.

  This input circuit outputs the address, data, and command generated by the BIST sequencer 52 during BIST, and the wafer test pad 97 and the input / output bump pad row 99A in other test modes than during BIST. , 99B is a circuit for outputting a signal inputted from 99B. The signals output here are supplied to the first core 100A and the second core 100B, respectively.

  The input / output bump pad row 99A is connected to the input terminal of the NAND circuit 106. The input / output bump pad row 99 </ b> B is connected to the input terminal of the NAND circuit 105. The input / output bump pad rows 99A and 99B are connected via the switch element 104. A core selection signal is supplied to one gate of the switch element 104 via the NOT circuits 101 and 102. A core selection signal is supplied to the other gate of the switch element 104 via NOT circuits 101, 102, and 103.

  Here, the high-level core selection signal indicates that the signal input to the input / output bump pad row 99A or 99B is supplied to the two cores (the first core 100A and the second core 100B) as the same signal. Signal. The low-level core selection signal is a signal indicating that a signal input to the input / output bump pad rows 99A and 99B is supplied to each core.

  A negative OR operation (NOR) circuit 112 calculates a negative logical sum of the BIST signal input via the NOT circuits 107 and 108 and the WFT signal from the wafer test pad 97 input via the NOT circuit 111. Calculate. The NOR circuit 109 calculates a negative OR of the BIST signal input via the NOT circuits 107 and 108 and the signal input from the NOR circuit 112.

  The NAND circuit 113 calculates a negative logical product of the signal A input from the wafer test pad 97 and the signal input from the NOR circuit 112. The NAND circuit 114 calculates a negative logical product of the signal (address, command, data) generated by the BIST sequencer 52 input via the NOT circuit 110 and the signal input from the NAND circuit 113.

  The NAND circuit 116 calculates a negative logical product of the signal input from the NAND circuit 105 and the signal input from the NAND circuit 114 via the NOT circuit 115. The output signal of the NAND circuit 116 is supplied to the second core 100B via the NOT circuits 117 and 118.

  The NAND circuit 119 calculates a negative logical product of the signal input from the NAND circuit 106 and the signal input from the NAND circuit 114 via the NOT circuit 115. The output signal of the NAND circuit 119 is supplied to the first core 100A via the NOT circuits 120 and 121.

  In the input circuit configured as described above, when the core selection signal becomes low (L) level (when one core is selected), the core selection signal is supplied to the switch element 104 via the negation circuits 101, 102, and 103. The At this time, the switch element 104 is turned on, and the bump pads in the input / output bump pad rows 99A and 99B are equipotential. As a result, even if the signal A is input to any bump pad of the input / output bump pad rows 99A and 99B, the same signal A is input to both the input / output bump pad rows 99A and 99B. Become.

  Therefore, when only one of the first core 100A and the second core 100B is operated (in the case of a single core), the signal A may be input to one of the bump pads 99A and 99B for input / output. .

  On the other hand, when the core selection signal becomes a high (H) level (when two cores are selected), the switch element 104 is turned off. As a result, the bump pads in the input / output bump pad rows 99A and 99B are independent from each other, and the signals input to the bump pads in the input / output bump pad rows 99A and 99B are sent to the first core 100A and the first core 100A, respectively. Used for 2-core 100B. Therefore, when the first core 100A and the second core 100B are operated simultaneously (in the case of a double core), a signal may be input to each bump pad of the input / output bump pad rows 99A and 99B.

  As described above, the semiconductor memory device according to the embodiment of the present invention includes the dedicated clock generators for the first core 100A and the second core 100B, respectively, and the power generated by the single power system circuit 201. Are supplied to the first core 100A and the second core 100B, respectively. As a result, the semiconductor memory device can operate the first core 100A and the second core 100B independently of each other and reduce the chip size compared to the case where the power supply circuit is not shared by the two memory cores. be able to.

  In addition, the semiconductor memory device supplies the signals generated by the test mode signal generator 51 and the BIST sequencer 52 to the first core 100A and the second core 100B, respectively. The chip size can be further reduced as compared with the case where the BIST sequencer is not shared.

  Note that the present invention is not limited to the above-described embodiment, and it is needless to say that the present invention can also be applied to a design modified within the scope of the claims.

  For example, in the above-described embodiment, the case of “two cores (double core)” using the first core 100A and the second core 100B has been described as an example, but the number of memory cores may be three or more. Of course.

1 is a diagram showing a chip configuration of a semiconductor memory device according to an embodiment of the present invention. 1 is a diagram showing a layout configuration of a memory chip provided in a semiconductor memory device. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention. 3 is a block diagram showing a configuration of a test mode signal generator 51. FIG. 3 is a block diagram showing a configuration of a BIST sequencer 52. FIG. It is a figure which shows the structure of an input circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon interposer 2 ASIC chip 3 Memory chip 51 Test mode signal generator 52 BIST sequencer 100A 1st core 100B 2nd core 201 Power supply system circuit

Claims (3)

A memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction; a row decoder that selects memory cells in the row direction of the memory cell array; a column decoder that selects memory cells in the column direction of the memory cell array; A plurality of memory cores including m memory banks (where m is a natural number of 2 or more) and data control means for writing or reading data to or from each of the memory banks;
A plurality of clock generating means for generating independent clocks respectively supplied to each memory core;
A single voltage generating means for generating a voltage to be supplied to each memory core;
A semiconductor memory device. A single self-diagnosis control means for generating a self-diagnosis address, a self-diagnosis command and self-diagnosis data;
The clock generation circuit generates a self-diagnosis clock based on a self-diagnosis command generated by the self-diagnosis control means;
Each of the memory cores performs self-diagnosis based on a self-diagnosis address, a self-diagnosis command and self-diagnosis data generated by the self-diagnosis control unit, and a self-diagnosis clock generated by the clock generation unit. The semiconductor memory device according to claim 1. The semiconductor memory device according to claim 1, further comprising a single data compression instruction signal generating unit that generates a data compression instruction signal instructing compression of data input to each memory core.

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