JP2008054075A - Semiconductor integrated circuit, and magnetic storage device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a chip occupation area of a capacitor incorporated in a semiconductor integrated circuit for amplifying an AC differential input voltage signal by a predetermined AC voltage amplification gain without DC amplifying a DC component by a high DC voltage gain. <P>SOLUTION: The AC differential input voltage signal superimposed on a DC current is supplied to non-inversion input terminals (+) of two main amplifiers Main_Amp 1 and 2, while both ends of a capacitor C1 and the outputs of loop amplifiers Loop_Amp 1 and 2 are connected to inversion input terminals (-) of the two main amplifiers. The output impedances Zout 1 and 2 of the Loop_Amp 1 and 2 are set to high values. A low-pass cutoff frequency fc3 is determined by either a first cutoff frequency fc1 determined by the Zout 1 and 2 of negative feedback signals DC & SLf_NFB 1 and 2 or a second cutoff frequency fc2 determined by the input impedances Zin 1 and 2 of the Main_Amp 1 and 2 for transmission signals LPF 1 and LPF 2, which is higher (fc2). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit provided with a differential amplifier and a magnetic storage device using the same, and more particularly to an AC difference in which a DC component is superimposed on a DC component without being amplified by a differential amplifier with a high DC voltage gain. The present invention relates to a technique effective for reducing the chip occupation area of a built-in capacitor of a semiconductor integrated circuit for amplifying a dynamic input voltage signal with a predetermined AC voltage amplification gain.

  Non-Patent Document 1 below discloses that a differential input signal at both ends of a magnetoresistive (MR) head or a giant magnetoresistive (GMR) head of a hard disk drive (HDD) is converted into a fully differential CMOS preamplifier via two coupling capacitors. Supplying is described.

  In Patent Document 1 below, a first method for supplying a differential input signal at both ends of a magnetoresistive (MR) head to the base of a differential pair transistor via two coupling capacitors and one integration are disclosed. A second system is described in which a differential input signal at both ends of a magnetoresistive (MR) head is directly supplied to the bases of a pair of transistors to which emitters are connected by an emitter coupling capacitor. In the first method, the time constant is obtained by the product of the emitter resistance of the differential pair transistor, the current amplification factor of the differential pair transistor, and the coupling capacitance. Therefore, if the emitter resistance is 5Ω, the current gain is 100, and the cut-off frequency fc is 3.2 MHz, the two coupling capacitances need to be 100 pF each, and although they are slightly larger, they can be integrated on the IC chip. ing. In the second method, the current amplification factor of the transistors is irrelevant, and the time constant can be obtained only by the product of the emitter resistance of a pair of transistors and one integrated emitter coupling capacitor. Accordingly, when the emitter resistance is 5Ω and the integrated emitter coupling capacitance is 500 pF, the cutoff frequency fc is 32 MHz, which is 10 times the cutoff frequency fc (3.2 MHz) of the first method. Yes.

  Further, Non-Patent Document 2 below describes a perpendicular magnetic recording system that enables a higher recording density than a general in-plane recording in a hard disk drive (HDD).

Zhiliang Zheng et al, "A 0.55nV / √Hz Gigabit Fully-Differential CMOS Preamplifier for MR / GMR Read Application", ISSCC 2002 / SESSION3 / DIGITAL SIGNAL PROCESSORS AND CIRCUITS / 3.7 2002 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICICAL PAPERS. Z. J. et al. Liu et al, “Dynamic Simulation of High-Density Perpendicular Recording Head and Media Combination”, IEEE TRANSACTIONS ON MAGNETICS, VOL. 42, NO. 4 APRIL 2006, PP. 943-946. US Patent No. 6,084,469

  Prior to the present invention, the inventor has been engaged in the development of a preamplifier for amplifying a weak signal of an MR head of a perpendicular magnetic recording type hard disk drive (HDD) that enables a high recording density.

  In a magnetic recording apparatus such as a storage tape drive or hard disk drive, a preamplifier is required to amplify a weak electric signal from the head to an appropriate amplitude. Currently, many magnetoresistive element heads (MR heads) are used as heads for converting magnetic signals into electrical signals.

  Since the MR head requires a DC current or voltage bias, the electrical signal obtained from the MR head becomes an AC differential voltage signal superimposed on the DC voltage. While this DC voltage is several tens to several hundred mV, the AC differential voltage signal is several mV or less peak-to-peak, so it is necessary to amplify only the AC voltage signal by blocking the DC component inside the preamplifier. There is.

  In recent years, in the field of magnetic disk devices typified by hard disk drives, the perpendicular magnetic recording method has been attracting attention as a technique for exceeding the limit of recording density in the conventional longitudinal magnetic recording (in-plane magnetic recording) method. Yes. However, the cut-off frequency required for this perpendicular magnetic recording system is about 100 KHz, which is much lower than the cut-off frequency of about 600 KHz in the conventional longitudinal magnetic recording system for in-plane recording.

  Based on an analogy from the description of Non-Patent Document 1 below, the present inventor supplies differential input signals at both ends of the MR head to both bases of the differential bipolar transistor via two coupling capacitors prior to the present invention. I examined that. A constant current source is connected to both emitters of the differential bipolar transistor, two coupling capacitors are connected to both bases of the differential bipolar transistor, and an equal bias voltage is supplied through two bias resistors.

  When the current of the constant current source is set to 5 mA, the low-frequency cutoff frequency required for magnetic recording by the conventional longitudinal magnetic recording method is 600 KHz, and the current amplification factor of the differential bipolar transistor is 100. Each value of about 260 pF is required. For example, the total of two coupling capacitors using a silicon oxide film having a thickness of 12 nm was calculated as a square chip occupation area of 0.42 mm × 0.42 mm square. On the other hand, if the low-frequency cut-off frequency in the perpendicular magnetic recording system is 100 KHz and the current of the constant current source is 5 mA, the values of the two coupling capacitors each need 1500 pF. This corresponds to a square chip occupation area of 1 mm × 1 mm square.

  In recent years, there has been a great demand for reducing the manufacturing cost of semiconductor integrated circuits, and it is possible to reduce the manufacturing cost by reducing the total chip area of the semiconductor integrated circuit by using the built-in capacitor of the semiconductor integrated circuit as a small chip occupation area. There is a strong demand.

  The present invention has been made on the basis of the matters clarified by the inventors' studies prior to the present invention as described above, and the object of the present invention is to provide a direct current by a differential amplifier of a semiconductor integrated circuit. Semiconductor integrated circuit for amplifying an AC differential input voltage signal with a predetermined AC voltage amplification gain without amplifying the DC component with a high DC voltage gain when amplifying the AC differential input voltage signal superimposed on the component It is to reduce the chip occupation area of the built-in capacitor.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  A semiconductor integrated circuit according to one aspect of the present invention includes a first differential amplifier (Main_Amp1), a second differential amplifier (Main_Amp2), an inverting input terminal (−) of the first differential amplifier (Main_Amp1), and the The capacitor (C1) connected between the inverting input terminal (−) of the second differential amplifier (Main_Amp2), the output of the first differential amplifier (Main_Amp1), and the first differential amplifier (Main_Amp1) By being connected to the inverting input terminal (−), a first negative voltage is output from the output of the first differential amplifier (Main_Amp1) to the inverting input terminal (−) of the first differential amplifier (Main_Amp1). A first negative feedback circuit (Loop_Amp1) for transmitting a feedback signal (DC & SLf_NFB1), and the second differential amplifier (Main_ The second differential amplifier from the output of the second differential amplifier (Main_Amp2) by being connected between the output of the Amp2) and the inverting input terminal (−) of the second differential amplifier (Main_Amp2). A second negative feedback circuit (Loop_Amp2) for transmitting a second negative feedback signal (DC & SLf_NFB2) to the inverting input terminal (−) of (Main_Amp2) is provided on the semiconductor chip.

  The first differential amplifier (Main_Amp1) includes a first amplifying element (Q1) and a second amplifying element (Q2) that are differentially connected, and the second differential amplifier (Main_Amp2) is differentially connected. The third amplifying element (Q3) and the fourth amplifying element (Q4) are included.

  Non-inverting of an AC differential input signal superimposed on a DC component on a non-inverting input terminal (+) of the first differential amplifier (Main_Amp1) and a non-inverting input terminal (+) of the second differential amplifier (Main_Amp2) An input signal (+ Vin) and an inverted input signal (−Vin) are supplied.

  The amount of transmission of the first negative feedback signal (DC & SLf_NFB1) to the inverting input terminal (−) of the first differential amplifier (Main_Amp1) and the inverting input terminal (− of the second differential amplifier (Main_Amp2)). ) And the second negative feedback circuit (Loop_Amp1) and the second negative feedback circuit (DC & SLf_NFB2) are attenuated at a frequency higher than the first cutoff frequency (fc1). The feedback circuit (Loop_Amp2) is the first amplification element (Q1), the second amplification element (Q2), and the third amplification element (the first differential amplifier (Main_Amp1)) and the second differential amplifier (Main_Amp2). Q3) and a first output impedance (predetermined resistance value) having a resistance higher than the internal resistance (Re) of the fourth amplifying element (Q4). out1) and having a second output impedance (Zout2) and, respectively.

  The first input impedance (Zin1) between the non-inverting input terminal (+) and the inverting input terminal (−) of the first differential amplifier (Main_Amp1) and the non-inverting of the second differential amplifier (Main_Amp2). The input resistance of the second input impedance (Zin2) between the inverting input terminal (+) and the inverting input terminal (−), the first negative feedback circuit (Loop_Amp1), and the second negative feedback circuit (Loop_Amp2) The first differential amplifier (Main_Amp1) is a product of the resistance value of at least one of the first output impedance (Zout1) and the output resistance of the second output impedance (Zout2) and the capacitance value of the capacitor (C1). And the AC differential input signal (+ Vin, Main_Amp2) of the second differential amplifier (Main_Amp2). Low cutoff frequency when the amplification of Vin) (fc3) is set (see FIGS. 1 and 2).

  On the other hand, in the second method described in Patent Document 1, differential input signals at both ends of a magnetoresistive (MR) head are connected to the bases of a pair of transistors whose emitters are connected by one integrated emitter coupling capacitor. Was directly supplied. Therefore, one integrated emitter coupling capacitor is driven in the form of an emitter follower by a pair of transistors. The output impedance of this emitter follower drive is a very low resistance determined by the nonlinear emitter resistance Re of a pair of transistors. Therefore, the time constant for determining the cutoff frequency is determined by the product of the capacitance value of the integrated emitter coupling capacitance and the low resistance value of the nonlinear emitter resistance Re. It was necessary to increase the capacitance value of the emitter coupling capacitance.

  The means according to the one aspect of the present invention is similar to the second method described in the above-mentioned Patent Document 1, and a pair of differential amplifiers (Main_Amp1, Main_Amp2) are connected to both ends of one capacitor (C1). Drive. However, the negative from the pair of outputs of the pair of differential amplifiers (Main_Amp1, Main_Amp2) to both ends of one capacitor (C1) and the inverting input terminal (−) of the pair of differential amplifiers (Main_Amp1, Main_Amp2) The feedback signal is transmitted through negative feedback circuits (Loop_Amp1, Loop_Amp2) having output impedances (Zout1, Zout2) of predetermined resistance values having resistances higher than the internal resistances (Re) of the amplifying elements (Q1, Q2, Q3, Q4). ).

  As a result, according to the means according to the one aspect of the present invention, the time constant for determining the cutoff frequency is the capacitance value of the capacitor (C1) as in the second method described in the Patent Document 1. And the first input impedance of the first differential amplifier (Main_Amp1) is not determined only by the product of the low resistance value of the internal resistance (Re) of the amplification elements (Q1, Q2, Q3, Q4). (Zin1) and the input resistance of the second input impedance (Zin2) of the second differential amplifier (Main_Amp2) and the first output of the first negative feedback circuit (Loop_Amp1) and the second negative feedback circuit (Loop_Amp2). Resistance value of at least one of impedance (Zout1) and output resistance of the second output impedance (Zout2) A low-frequency cutoff frequency (fc3) when the AC differential input signal of the first differential amplifier (Main_Amp1) and the second differential amplifier (Main_Amp2) is amplified by the product of the capacitance value of the capacitor (C1). ) Has been set. In this way, the capacitance value of the capacitor (C1) can be reduced (see FIGS. 1 and 2).

  A semiconductor integrated circuit according to another embodiment of the present invention includes a first differential amplifier (Main_Amp1), a second differential amplifier (Main_Amp2), and a non-inverting input terminal (+ of the first differential amplifier (Main_Amp1)). ) And the inverting input terminal (−) to the non-inverting input terminal (+) and the inverting input terminal (−), respectively, and the second differential amplifier (Main_Amp2). A second negative feedback circuit (Loop_Amp2) in which a non-inverting input terminal (+) and an inverting input terminal (-) are connected to a non-inverting input terminal (+) and an inverting input terminal (-), respectively, and the first difference A capacitor (C1) connected between the inverting input terminal (−) of the dynamic amplifier (Main_Amp1) and the inverting input terminal (−) of the second differential amplifier (Main_Amp2). Comprising the door on a semiconductor chip.

  The output of the first negative feedback circuit (Loop_Amp1) is connected to the inverting input terminal (−) of the first differential amplifier (Main_Amp1) and one end of the capacitor (C1), and the second negative feedback circuit (Loop_Amp2). Is connected to the inverting input terminal (−) of the second differential amplifier (Main_Amp2) and the other end of the capacitor (C1).

  The first differential amplifier (Main_Amp1) includes a first amplifying element (Q1) and a second amplifying element (Q2) that are differentially connected, and the second differential amplifier (Main_Amp2) is differentially connected. The third amplifying element (Q3) and the fourth amplifying element (Q4) are included.

  An AC differential input signal superimposed on a DC component on the non-inverting input terminal (+) of the first differential amplifier (Main_Amp1) and the non-inverting input terminal (+) of the second differential amplifier (Main_Amp2). A non-inverting input signal (+ Vin) and an inverting input signal (-Vin) are supplied.

  The amount of transmission of the first negative feedback signal (DC & SLf_NFB1) to the inverting input terminal (−) of the first differential amplifier (Main_Amp1) and the inverting input terminal (− of the second differential amplifier (Main_Amp2)). The first negative feedback circuit (Loop_Amp1) and the second negative feedback circuit (Loop_Amp2) so that the amount of transmission of the second negative feedback signal to the first frequency) is attenuated at a frequency higher than the first cutoff frequency (fc1). Is the first amplifying element (Q1), the second amplifying element (Q2), the third amplifying element (Q3), and the first amplifying element (Q1) of the first differential amplifier (Main_Amp1) and the second differential amplifier (Main_Amp2). A first output impedance (Zout1) having a resistance value higher than the internal resistance (Re) of the four amplifier elements (Q4) and a second output impedance Each has a dance (Zout2).

  The first input impedance (Zin1) between the non-inverting input terminal (+) and the inverting input terminal (−) of the first differential amplifier (Main_Amp1) and the non-inverting of the second differential amplifier (Main_Amp2). The input resistance of the second input impedance (Zin2) between the inverting input terminal (+) and the inverting input terminal (−), the first negative feedback circuit (Loop_Amp1), and the second negative feedback circuit (Loop_Amp2) The first differential amplifier (Main_Amp1) is a product of the resistance value of at least one of the first output impedance (Zout1) and the output resistance of the second output impedance (Zout2) and the capacitance value of the capacitor (C1). And the AC differential input signal (+ Vin, Main_Amp2) of the second differential amplifier (Main_Amp2). Low cutoff frequency when the amplification of Vin) (fc3) is set (Fig. 5, 6, see Fig. 7).

  As a result, according to the means according to the other embodiment of the present invention, the time constant for determining the cut-off frequency is the same as that of the second method described in the Patent Document 1 of the capacitor (C1). The first input of the first differential amplifier (Main_Amp1) is not determined only by the product of the capacitance value and the resistance value of the internal resistance (Re) of the amplification element (Q1, Q2, Q3, Q4). The impedance (Zin1) and the input resistance of the second input impedance (Zin2) of the second differential amplifier (Main_Amp2) and the first negative feedback circuit (Loop_Amp1) and the first negative feedback circuit (Loop_Amp2) of the first A resistance value of at least one of an output impedance (Zout1) and an output resistance of the second output impedance (Zout2) A low-frequency cutoff frequency (fc3) when the AC differential input signal of the first differential amplifier (Main_Amp1) and the second differential amplifier (Main_Amp2) is amplified by the product of the capacitance value of the capacitor (C1). ) Has been set. In this way, the capacitance value of the capacitor (C1) can be reduced (see FIGS. 5, 6, and 7).

  In a semiconductor integrated circuit according to one preferred embodiment of the present invention, the input of the first input impedance (Zin1) and the second input impedance (Zin2) in the one embodiment or the other embodiment of the present invention. One resistance value of the output resistor of the first output impedance (Zout1) and the second output impedance (Zout2) of the resistor and the first negative feedback circuit (Loop_Amp1) and the second negative feedback circuit (Loop_Amp2) is The input resistance of the first input impedance (Zin1) and the second input impedance (Zin2), the first output impedance (Zout1) of the first negative feedback circuit (Loop_Amp1) and the second negative feedback circuit (Loop_Amp2), and Said second output impedance (Zout2) lower than or substantially equal to the other resistance value of the output resistance, the resistance value of the low resistance or the resistance value of the substantially equal resistance and the capacitor (C1) The low-frequency cutoff frequency (fc3) is set by the product with the capacitance value (see FIGS. 1, 2, 5, 6, and 7).

  In a semiconductor integrated circuit according to a specific form of the present invention, in the one preferred form of the present invention, the non-inverting input terminal (+) and the inverting input terminal (+) of the first differential amplifier (Main_Amp1) −) Is a product of the internal resistance (Re) and the current amplification factor (hfe) of the first amplifying element (Q1) and the second amplifying element (Q2). The second input impedance (Zin2) between the non-inverting input terminal (+) and the inverting input terminal (−) of the second differential amplifier (Main_Amp2) is proportional to the third amplifying element. (Q3) and the fourth amplifying element (Q4) are proportional to the product of the internal resistance (Re) and the current amplification factor (hfe).

  The input resistance of the first input impedance (Zin1) and the second input impedance (Zin2) proportional to the product of the internal resistance (Re) and the current amplification factor (hfe) is the first negative feedback circuit (Loop_Amp1). ) And the second negative feedback circuit (Loop_Amp2) having a resistance value lower than the output resistance of the first output impedance (Zout1) and the second output impedance (Zout2), and the first differential amplifier (Main_Amp1) The amount of transmission from the non-inverting input terminal (+) to the inverting input terminal (−) of the first differential amplifier (Main_Amp1) via the first input impedance (Zin1) and the second differential amplifier ( Main_Amp2) through the second input impedance (Zin2). The second cutoff frequency (the transmission amount from the non-inverting input terminal (+) to the inverting input terminal (−) of the device (Main_Amp2) is set to a frequency higher than the first cutoff frequency (fc1). Attenuating at a frequency higher than fc2), the low-frequency cutoff frequency (fc3) is set by the second cutoff frequency (fc2) (see FIGS. 1, 2, 8, and 9).

  According to the means of the one specific form of the present invention, the transmission amount of the first negative feedback signal (DC & SLf_NFB1) to the inverting input terminal (−) of the first differential amplifier (Main_Amp1) The transmission amount of the second negative feedback signal (DC & SLf_NFB2) to the inverting input terminal (−) of the second differential amplifier (Main_Amp2) is a frequency lower than the first cutoff frequency (fc1). About 100% negative feedback is obtained for certain DC signals and very low frequency signals. Furthermore, from the non-inverting input terminal (+) of the first differential amplifier (Main_Amp1) to the inverting input terminal (−) via the first input impedance (Zin1) of the first differential amplifier (Main_Amp1). And the non-inverting input terminal (+) of the second differential amplifier (Main_Amp2) through the second input impedance (Zin2) of the second differential amplifier (Main_Amp2) to the inverting input terminal (− ) Is a transmission amount of approximately 100% in a DC signal and a low frequency signal having a frequency lower than the second cutoff frequency (fc2).

  As a result, both ends of the capacitor (C1), that is, the inverting input terminal (−) of the first differential amplifier (Main_Amp1) and the inverting input terminal (−) of the second differential amplifier (Main_Amp2) The non-inverting input signal (+ Vin) supplied to the non-inverting input terminal (+) of the first differential amplifier (Main_Amp1) and the non-inverting input terminal (+) of the second differential amplifier (Main_Amp2), respectively. The inverting input signal (−Vin) DC signal, ultra-low frequency signal and low-frequency signal are transmitted at approximately 100%. Accordingly, the non-inverting input terminal (+) and the inverting input terminal (−) of the first differential amplifier (Main_Amp1) are a DC signal, an ultra-low frequency signal, and a low-frequency signal of the non-inverting input signal (+ Vin). The non-inverting input terminal (+) and the inverting input terminal (−) of the second differential amplifier (Main_Amp2) are driven by a DC signal of the inverting input signal (−Vin), Driven by the low-frequency signal and the low-frequency signal with the same phase and the same amplitude. As a result, the output of the first negative feedback circuit (Loop_Amp1) and the DC signal, the very low frequency signal, and the low frequency signal of the inverting input terminal (−) of the first differential amplifier (Main_Amp1) are non-inverted. The level of the DC signal of the input signal (+ Vin), the very low frequency signal, and the low frequency signal is maintained substantially the same, and the output of the second negative feedback circuit (Loop_Amp2) and the inversion of the second differential amplifier (Main_Amp2) The voltages of the DC signal, the ultra-low frequency signal, and the low-frequency signal at the input terminal (−) are maintained substantially the same as the levels of the DC signal, the ultra-low frequency signal, and the low-frequency signal of the inverted input signal (−Vin).

  In the state of the DC signal, the ultra-low frequency signal, and the low-frequency signal, the first differential amplifier (Main_Amp1) and the second differential amplifier (Main_Amp2) have a negative feedback of about 100% and a transmission of about 100%. The voltage gain is approximately 1 (0 dB), and neither DC amplification of a DC signal with a high voltage gain nor low frequency amplification of an ultra-low frequency signal or a low frequency signal is performed.

  Further, according to the means according to the one specific form of the present invention, the transmission of the first negative feedback signal (DC & SLf_NFB1) to the inverting input terminal (−) of the first differential amplifier (Main_Amp1). And the amount of transmission of the second negative feedback signal (DC & SLf_NFB2) to the inverting input terminal (−) of the second differential amplifier (Main_Amp2) is far more than the first cutoff frequency (fc1). The negative feedback is substantially 0% at a very high frequency (fc2 ′). Furthermore, from the non-inverting input terminal (+) of the first differential amplifier (Main_Amp1) to the inverting input terminal (−) via the first input impedance (Zin1) of the first differential amplifier (Main_Amp1). And the non-inverting input terminal (+) of the second differential amplifier (Main_Amp2) through the second input impedance (Zin2) of the second differential amplifier (Main_Amp2) to the inverting input terminal (− ) Is a transmission amount of approximately 0% at a frequency (fc2 ′) higher than the second cutoff frequency (fc2).

  The inverting input terminal (−) of the first differential amplifier (Main_Amp1) and the inverting input terminal (−) of the second differential amplifier (Main_Amp2) are the non-inverting input signal (+ Vin) and the inverting input signal ( −Vin), the non-inverting input terminal (+) and the second difference of the first differential amplifier (Main_Amp1) are maintained at the levels of the DC signal, the ultra-low frequency signal, and the low-frequency signal. The non-inverting input terminal (+) of the dynamic amplifier (Main_Amp2) has a frequency (fc2 ′) higher than the second cutoff frequency (fc2) of the non-inverting input signal (+ Vin) and the inverting input signal (−Vin). And driven by a signal having a higher frequency.

  In the driving state by the signal of the frequency (fc2 ′) and the signal of higher frequency, the first differential amplifier (Main_Amp1) and the second differential are transmitted by approximately 0% negative feedback and approximately 0% transmission. The voltage gain of the amplifier (Main_Amp2) is, for example, a high voltage gain of about 47 dB, and it is possible to amplify the intermediate frequency signal and the high frequency signal with a high voltage gain.

  In a semiconductor integrated circuit according to one more specific form of the present invention, in the one specific form of the present invention, the first amplifying element (Q1) and the second amplifying element (Q1) of the first differential amplifier (Main_Amp1). The third amplifying element (Q3) and the fourth amplifying element (Q4) of the amplifying element (Q2) and the second differential amplifier (Main_Amp2) are bipolar transistors, and the first amplifying element (Q1) and the The internal resistance of the second amplifying element (Q2), the third amplifying element (Q3), and the fourth amplifying element (Q4) is an emitter nonlinear resistance (Re), and the first amplifying element (Q1) and the The current amplification factors of the two amplifying elements (Q2), the third amplifying element (Q3), and the fourth amplifying element (Q4) are grounded emitter current amplifying factors (hfe), and the base of the bipolar transistor A base current compensation circuit (BC_CC) that compensates the flow includes the non-inverting input terminal (+) and the inverting input terminal (−) of the first differential amplifier (Main_Amp1) and the second differential amplifier (Main_Amp2). The non-inverting input terminal (+) and the inverting input terminal (−) are connected (see FIG. 3).

  In a semiconductor integrated circuit according to another more specific form of the present invention, in the one specific form of the present invention, the first amplifier element (Q1, Q01) of the first differential amplifier (Main_Amp1). And the second amplifying element (Q2, Q02) and the third amplifying element (Q3, Q03) and the fourth amplifying element (Q4, Q04) of the second differential amplifier (Main_Amp2) are respectively MOS current mirrors. Of the first amplifying element (Q1, Q01), the second amplifying element (Q2, Q02), the third amplifying element (Q3, Q03), and the fourth amplifying element (Q4, Q04). The internal resistance is a gate-source nonlinear resistance (Rgs), and the first amplifying element (Q1, Q01), the second amplifying element (Q2, Q02), and the third amplifying element (Q3, Q03). The current amplification factor of the fourth amplifying element (Q4, Q04) is a mirror ratio (Rm) of the MOS current mirror, and a current mirror input current compensation circuit (CMC_CC) for compensating the input current of the MOS current mirror The non-inverting input terminal (+) and the inverting input terminal (−) of the first differential amplifier (Main_Amp1) and the non-inverting input terminal (+) and the inverting input terminal (of the second differential amplifier (Main_Amp2)). -) (See FIG. 17).

  In a semiconductor integrated circuit according to another preferred embodiment of the present invention, in the one embodiment or the other embodiment of the present invention, the non-inverting input terminal (+) of the first differential amplifier (Main_Amp1). The first input impedance (Zin1) between the inverting input terminal (−) and the non-inverting input terminal (+) and the inverting input terminal (−) of the second differential amplifier (Main_Amp2). The first output impedance (Zout1) and the second output impedance (Zout2) of the first negative feedback circuit (Loop_Amp1) and the second negative feedback circuit (Loop_Amp2) rather than the input resistance of the second input impedance (Zin2) The output resistance of the low-frequency resistor has a low resistance value, and the low-frequency cutoff frequency is determined by the first cutoff frequency (fc1). Set frequency (fc3) (FIG. 5, FIG. 6, refer to FIG. 7).

  In a semiconductor integrated circuit according to another more specific form of the present invention, in the another specific form of the present invention, the first differential amplifier (Main_Amp1) and the second differential amplifier (Main_Amp2) ) Of the first amplifying element (Q1), the second amplifying element (Q2), the third amplifying element (Q3), and the fourth amplifying element (Q4) are MOS transistors, respectively, and the first negative feedback The first differential amplifier (Main_Amp1) having a resistance higher than the output resistance of the first output impedance (Zout1) and the second output impedance (Zout2) of the circuit (Loop_Amp1) and the second negative feedback circuit (Loop_Amp2) The first input impedance (Zin) between the non-inverting input terminal (+) and the inverting input terminal (−) ) And the input resistance of the second input impedance (Zin2) between the non-inverting input terminal (+) and the inverting input terminal (−) of the second differential amplifier (Main_Amp2) is the MOS transistor ( Q1, Q2, Q3, and Q4) (refer to FIGS. 5, 6, and 7).

  In a semiconductor integrated circuit according to one more specific form of the present invention, a first constant current source (I1) is connected to the first differential amplifier (Main_Amp1) and a second differential amplifier (Main_Amp2) is connected to a second. A constant current source (I2) is connected, a third constant current source (I3, I5) is connected to the first negative feedback circuit (Loop_Amp1), and a fourth constant current source (Loop_Amp2) is connected to the fourth constant current source (Loop_Amp2). I4, I6) are connected.

  In a read mode (READ MODE) in which the first differential amplifier (Main_Amp1) and the second differential amplifier (Main_Amp2) perform an amplification operation, the first constant current source (I1) and the second constant current source ( I2), the third constant current source (I3, I5), and the fourth constant current source (I4, I6) are respectively supplied with constant currents flowing through the first differential amplifier (Main_Amp1) and the second differential amplifier ( Main_Amp2), the first negative feedback circuit (Loop_Amp1), and the second negative feedback circuit (Loop_Amp2) (see FIG. 15).

  In the idle mode (IDLE MODE) in which the first differential amplifier (Main_Amp1) and the second differential amplifier (Main_Amp2) stop the amplification operation, the first differential amplifier (Main_Amp1) and the second differential amplifier The constant currents flowing through the amplifier (Main_Amp2), the first negative feedback circuit (Loop_Amp1), and the second negative feedback circuit (Loop_Amp2) are cut off (see FIG. 15).

  According to the means according to the one preferred embodiment of the present invention, it is possible to reduce the power consumption of the semiconductor integrated circuit in the idle mode (IDLE MODE).

  In a semiconductor integrated circuit according to one more preferred embodiment of the present invention, the first differential amplifier (Main_Amp1) and the second differential amplifier (Main_Amp2) are switched from the idle mode (IDLE MODE) to the read mode (READ MODE). ), The constant currents flowing through the third constant current sources (I3, I5) and the fourth constant current sources (I4, I6) are temporarily increased (SW3, SW4 in FIG. 15). reference).

  According to the means according to the one more preferred mode of the present invention, the inverting input of the first differential amplifier (Main_Amp1) when transitioning from the idle mode (IDLE MODE) to the read mode (READ MODE). The voltage level of the terminal (−) and the inverting input terminal (−) of the second differential amplifier (Main_Amp2) can be recovered at high speed.

  The semiconductor integrated circuit according to one more preferable aspect of the present invention is a transition from the idle mode (IDLE MODE) to the read mode (READ MODE) or from the read mode (READ MODE) to the idle mode (IDLE MODE). The first constant current source (I1), the second constant current source (I2), the third constant current source (I3, I5), and the fourth constant current source (I4, I6) Includes a controller (SW_CNT) for controlling the current value of each of the currents flowing in each (see FIGS. 3, 4, 7, 10, and 17).

  In a semiconductor integrated circuit according to one more preferred embodiment of the present invention, a first switch (SW5) is provided between the non-inverting input terminal (+) and the inverting input terminal (−) of the first differential amplifier (Main_Amp1). ), A second switch (SW6) is connected between the non-inverting input terminal (+) and the inverting input terminal (−) of the second differential amplifier (Main_Amp2), and the first differential When the amplifier (Main_Amp1) and the second differential amplifier (Main_Amp2) transition from the idle mode (IDLE MODE) to the read mode (READ MODE), the first switch (SW5) and the second switch ( SW6) is temporarily turned on and then turned off (see FIG. 15).

  In a semiconductor integrated circuit according to one more preferred embodiment of the present invention, the first differential amplifier (Main_Amp1) and the second differential amplifier (Main_Amp2) are switched from the idle mode (IDLE MODE) to the read mode (READ MODE). ), The controller (SW_CNT) responds to the transition from the idle mode (IDLE MODE) to the read mode (READ MODE) by the first switch (SW5) and the second switch (SW6). ) Are temporarily turned on and then turned off (see FIGS. 3 and 15).

  In the semiconductor integrated circuit according to one more preferable aspect of the present invention, the first negative feedback circuit (Loop_Amp1) and the second negative feedback circuit (Loop_Amp2) are the first output impedance (Zout1) and the second output impedance ( And amplifiers (Q39, Q40, M11, M12, M13, M14, M15, and M16) that generate Zout2) (see FIGS. 11 and 12).

  A magnetic recording apparatus according to one embodiment of the present invention includes a semiconductor integrated circuit (Preamp IC) of any one of the above forms (see FIG. 18), and drives the magnetic recording medium (20) to record the head (21C). (RP, RC, RY) performs perpendicular magnetic recording on the magnetic recording medium (20), and a read signal of the magnetic recording medium (20) from the reproducing head (GMR) of the head (21C) is transmitted to the semiconductor integrated circuit. Process by using (Preamp IC). Both ends of the reproducing head (GMR) are connected to the non-inverting input terminal (+) of the first differential amplifier (Main_Amp1) of the semiconductor integrated circuit (Preamp IC) and the non-inverting input terminal of the second differential amplifier (Main_Amp2). It is connected to the inverting input terminal (+) without a coupling capacitor (see FIGS. 18, 19, and 20).

  In a magnetic recording apparatus according to one preferred embodiment of the present invention, the reproducing head (GMR) is a magnetoresistive head.

  In the magnetic recording apparatus according to one more preferable aspect of the present invention, a shield (RSL2) is formed between the recording head (RP, RC, RY) and the magnetoresistive head (GMR) inside the head (21C). (See FIG. 19).

  In the magnetic recording apparatus according to one specific form of the present invention, the semiconductor integrated circuit (Preamp IC) of any one of the above forms is mounted on the arm (21A) on which the head (21C) is mounted (FIG. 18). reference).

  In the magnetic recording apparatus according to one more specific form of the present invention, the magnetic recording medium (20) is a magnetic disk or a magnetic tape (see FIG. 20).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, when the AC differential input voltage signal superimposed on the DC component is amplified by the differential amplifier of the semiconductor integrated circuit, the AC differential input is performed without DC amplification of the DC component with a high DC voltage gain. It is possible to reduce the chip occupation area of the built-in capacitor of the semiconductor integrated circuit for amplifying the voltage signal with a predetermined AC voltage amplification gain.

≪Basic configuration of preamplifier≫
(First embodiment of the present invention)
FIG. 1 is a block diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention including a preamplifier having a basic configuration for amplifying a weak signal of a magnetoresistive head RMR of a perpendicular magnetic recording type hard disk drive (HDD). .

  As shown in the figure, one end of the magnetoresistive head RMR is connected to one end 1 of the constant current source 5_1 of the bias circuit 5, and the other end of the magnetoresistive head RMR is connected to one end 2 of the constant current source 5_2 of the bias circuit 5. Has been. In the bias circuit 5, the power supply voltage Vcc is supplied to the other end of the constant current source 5_1, and the ground voltage GND is supplied to the other end of the constant current source 5_2. The currents of the constant current source 5_1 and the constant current source 5_2 are set to equal sense current values in the range of 4 to 10 mA. Although depending on the characteristics of the magnetoresistive head RMR, the DC voltage across the magnetoresistive head RMR is several tens to several hundred mV, and the AC differential voltage signal due to the resistance change of the magnetoresistive head RMR due to the magnetic flux change is It is several mV or less from peak to peak.

  In the figure, the inside of the broken line indicates a circuit formed on the semiconductor chip of the semiconductor integrated circuit. The preamplifier for amplifying the weak signal of the magnetoresistive head RMR includes a main amplifier Main_Amp1 as a first differential amplifier, a main amplifier Main_Amp2 as a second differential amplifier, and an inverting input terminal (−) of the main amplifier Main_Amp1. The capacitor C1 connected between the inverting input terminal (−) of the main amplifier Main_Amp2 and the output between the main amplifier Main_Amp1 and the inverting input terminal (−) of the main amplifier Main_Amp1 are connected to the main amplifier Main_Amp1. Loop amplifier Loop_Amp1 as a first negative feedback circuit that transmits the first negative feedback signal DC & SLf_NFB1 from the output to the inverting input terminal (−) of the main amplifier Main_Amp1, and the output of the main amplifier Main_Amp2 and the main The second negative feedback signal that transmits the second negative feedback signal DC & SLf_NFB2 from the output of the main amplifier Main_Amp2 to the inverting input terminal (−) of the main amplifier Main_Amp2 by being connected to the inverting input terminal (−) of the amplifier Main_Amp2. A loop amplifier Loop_Amp2 as a circuit is included.

  From both ends of the magnetoresistive head RMR, the non-inverting input signal + Vin of the AC differential input signal superimposed on the DC component on the non-inverting input terminal (+) of the main amplifier Main_Amp1 and the non-inverting input terminal (+) of the main amplifier Main_Amp2 is inverted. An input signal -Vin is supplied.

  The transmission amount of the first negative feedback signal DC & SLf_NFB1 to the inverting input terminal (−) of the main amplifier Main_Amp1 and the transmission amount of the second negative feedback signal DC & SLf_NFB2 to the inverting input terminal (−) of the main amplifier Main_Amp2 The loop amplifier Loop_Amp1 and the loop amplifier Loop_Amp2 respectively have output impedances Zout1 and Zout2 having predetermined resistance values so as to attenuate at a frequency higher than one cut-off frequency fc1.

  FIG. 2 is a diagram showing the frequency dependence characteristics of the transmission amount of each circuit in the preamplifier shown in FIG.

  The first part of FIG. 2 shows the frequency characteristics of the main amplifiers Main_Amp1 and Main_Amp2 themselves, and has a DC component and a high voltage gain from a very low frequency region to a high frequency region.

  The second part of FIG. 2 shows the frequency characteristics of the transfer amounts of the negative feedback signals DC & SLf_NFB1, DC & SLf_NFB2 by the output impedances Zout1 and Zout2 of the loop amplifiers Loop_Amp1 and Loop_Amp2 and the capacitor C1, and the first cut-off frequency fc1 In the region of the direct current component and the ultra-low frequency up to, the transmission amount is high, but at a frequency higher than the first cut-off frequency fc1, it is reduced to 1 (0 dB). The first cut-off frequency fc1 is determined by the product of extremely high resistance values of the output impedances Zout1 and Zout2 of the loop amplifiers Loop_Amp1 and Loop_Amp2 and the capacitance value of the capacitor C1.

  As shown in FIG. 3, the main amplifier Main_Amp1 includes a first bipolar transistor Q1 and a second bipolar transistor Q2 that are differentially connected to each other, so that the non-inverting input terminal (+) and the inverting input terminal (+) of the main amplifier Main_Amp1 -) Is proportional to the product of the emitter resistance Re, which is the internal resistance of the first bipolar transistor Q1 and the second bipolar transistor Q2, and the emitter ground current amplification factor hfe. Similarly, the main amplifier Main_Amp2 includes a third bipolar transistor Q3 and a fourth bipolar transistor Q4 that are differentially connected, so that the main amplifier Main_Amp2 is connected between the non-inverting input terminal (+) and the inverting input terminal (−) of the main amplifier Main_Amp2. The second input impedance Zin2 is proportional to the product of the emitter resistance Re, which is the internal resistance of the third bipolar transistor Q3 and the fourth bipolar transistor Q4, and the grounded emitter current amplification factor hfe. As is well known, the emitter nonlinear resistance Re, which is the internal resistance of the bipolar transistor, is given by the following relationship from the Boltzmann constant K, the absolute temperature T, the electron charge q, and the emitter current Ie.

Re = KT / qIe = 26 mV / Ie (1 formula)
That is, the emitter nonlinear resistance Re decreases in inverse proportion to the increase in the emitter current Ie.

  Therefore, the first input impedance Zin1 of the main amplifier Main_Amp1 and the second input impedance Zin2 of the main amplifier Main_Amp2 are given by the following equations when the current amplification factor of the bipolar transistor is hfe.

Zin1 = Zin2 = hfe · Re = hfe · KT / qIe (2 formulas)
As a result, the transmission amount LPF1 from the non-inverting input terminal (+) of the main amplifier Main_Amp1 to the inverting input terminal (−) and the second input impedance Zin2 of the main amplifier Main_Amp2 via the first input impedance Zin1 of the main amplifier Main_Amp1. The first input impedance Zin1 and the second input so that the transmission amount LPF2 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp2 attenuates at a frequency higher than the second cutoff frequency fc2. The impedance Zin2 has a predetermined impedance. The second cutoff frequency fc2 is set to be approximately equal to the first cutoff frequency fc1 or higher than the first cutoff frequency fc1.

  The third part of FIG. 2 shows the amount of transmission from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp1 via the first input impedance Zin1 of the main amplifier Main_Amp1 and the second input impedance of the main amplifier Main_Amp2. The frequency characteristic of the amount of transmission from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp2 via Zin2 is shown. These transmission amounts are large values up to the second cutoff frequency fc2, but rapidly attenuate at a frequency fc2 ′ higher than the second cutoff frequency fc2. The second cutoff frequency fc2 is determined by the product of the relatively high resistance value of the first input impedance Zin1 of the main amplifier Main_Amp1 and the second input impedance Zin2 of the main amplifier Main_Amp2 and the capacitance value of the capacitor C1.

  Therefore, the transmission amount of the first negative feedback signal DC & SLf_NFB1 to the inverting input terminal (−) of the main amplifier Main_Amp1 and the transmission amount of the second negative feedback signal DC & SLf_NFB2 to the inverting input terminal (−) of the main amplifier Main_Amp2. Is substantially 100% negative feedback for DC signals and very low frequency signals that are lower than the first cutoff frequency fc1. Further, via the first input impedance Zin1 of the main amplifier Main_Amp1, the transmission amount LPF1 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp1 and the second input impedance Zin2 of the main amplifier Main_Amp2 The transmission amount LPF2 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp2 is approximately 100% transmission in a DC signal and a low frequency signal having a frequency lower than the second cutoff frequency fc2. Amount.

  As a result, both ends of the capacitor C1, that is, the inverting input terminal (−) of the main amplifier Main_Amp1 and the inverting input terminal (−) of the main amplifier Main_Amp2 are non-inverting input terminals (+) of the main amplifier Main_Amp1 and non-inverting of the main amplifier Main_Amp2. The DC signal, the ultra-low frequency signal, and the low-frequency signal of the non-inverted input signal + Vin and the inverted input signal −Vin supplied to the input terminal (+) are transmitted at approximately 100%. Therefore, the non-inverting input terminal (+) and the inverting input terminal (−) of the main amplifier Main_Amp1 are driven with substantially the same phase and the same amplitude by the DC signal of the non-inverting input signal + Vin, the ultra-low frequency signal, and the low-frequency signal. The non-inverting input terminal (+) and the inverting input terminal (−) of the amplifier Main_Amp2 are driven with substantially the same phase and the same amplitude by a DC signal, an ultra low frequency signal, and a low frequency signal of the inverting input signal −Vin. As a result, the output of the loop amplifier Loop_Amp1 and the DC signal of the inverting input terminal (−) of the main amplifier Main_Amp1, the voltage of the very low frequency signal and the low frequency signal are the non-inverting input signal + Vin DC signal, the very low frequency signal and the low frequency signal. The voltage of the output of the loop amplifier Loop_Amp2 and the DC signal of the inverting input terminal (−) of the main amplifier Main_Amp2, the very low frequency signal and the voltage of the low frequency signal are the same as those of the inverting input signal (−Vin). The voltages of the DC signal, the ultra-low frequency signal, and the low-frequency signal are maintained substantially the same as the levels of the DC signal, the ultra-low frequency signal, and the low-frequency signal of the inverted input signal -Vin.

  In the state of the DC signal, the ultra-low frequency signal, and the low frequency signal, the main amplifier Main_Amp1 and the loop amplifier Loop_Amp1 are constituted by the negative feedback of about 100% and the transmission of about 100% as shown in the fourth part of FIG. The voltage gain of the second amplifier AMP2 composed of the first amplifier AMP1, the main amplifier Main_Amp2, and the loop amplifier Loop_Amp2 is approximately 1 (0 dB), and the DC amplification of the DC signal with a high voltage gain is also possible for the ultra-low frequency signal and the low frequency signal. Low frequency amplification is not performed by the amplifiers AMP1 and AMP2. A sense current RMR Isense set to 4 to 10 mA flows from the constant current source 5_1 of the bias circuit 5 to the magnetoresistive head RMR, and a sense set to 4 to 10 mA from the magnetoresistive head RMR to the constant current source 5_2 of the bias circuit 5. A current RMR Isense flows. Since the current of the constant current source 5_1 of the bias circuit 5 and the current of the constant current source 5_2 of the bias circuit 5 are equal to each other, the voltage at the intermediate point of the magnetoresistive head RMR is Vcc / 2 which is half of the power supply voltage Vcc. When a DC voltage of several tens to several hundred mV between both ends of the magnetoresistive head RMR is ΔV, the voltage at the terminal 1 of the magnetoresistive head RMR is Vcc / 2 + ΔV / 2, and the voltage at the terminal 2 of the magnetoresistive head RMR is Becomes Vcc / 2−ΔV / 2. Since the voltage gain of the first amplifier AMP1 and the second amplifier AMP2 is approximately 1 (0 dB) in the DC signal, the ultra-low frequency signal, and the low frequency signal, the inverting input terminal (−) of the main amplifier Main_Amp1 and one end of the capacitor C1 Is Vcc / 2 + ΔV / 2, and the voltage between the inverting input terminal (−) of the main amplifier Main_Amp2 and the other end of the capacitor C1 is Vcc / 2−ΔV / 2.

  Thus, a DC voltage of several tens to several hundred mV across the magnetoresistive head RMR is directly applied across the capacitor C1. Incidentally, a negative voltage power source, for example, −Vcc, may be supplied to the other end of the constant current source 5-2 of the bias circuit 5 and the ground terminal of FIG. 3 instead of the ground voltage GND. In this case, the magnetoresistive head The voltage at the intermediate point of the RMR is 0 V, which is the same as the ground voltage GND, the voltage at the terminal 1 of the magnetoresistive head RMR is + ΔV / 2, and the voltage at the terminal 2 of the magnetoresistive head RMR is −ΔV / 2. Also, the amount of transmission of the first negative feedback signal DC & SLf_NFB1 to the inverting input terminal (−) of the main amplifier Main_Amp1 and the amount of transmission of the second negative feedback signal DC & SLf_NFB2 to the inverting input terminal (−) of the main amplifier Main_Amp2. Is substantially 0% negative feedback at a frequency much higher than the first cutoff frequency fc1. Further, via the first input impedance Zin1 of the main amplifier Main_Amp1, the transmission amount LPF1 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp1 and the second input impedance Zin2 of the main amplifier Main_Amp2 The transmission amount LPF2 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp2 is a transmission amount of approximately 0% at a frequency fc2 ′ higher than the second cutoff frequency fc2.

  The inverting input terminal (−) of the main amplifier Main_Amp1 and the inverting input terminal (−) of the main amplifier Main_Amp2 are maintained at the levels of the DC signal, the very low frequency signal, and the low frequency signal of the non-inverting input signal + Vin and the inverting input signal −Vin. On the other hand, the non-inverting input terminal (+) of the main amplifier Main_Amp1 and the non-inverting input terminal (+) of the main amplifier Main_Amp2 are based on the second cutoff frequency fc2 of the non-inverting input signal + Vin and the inverting input signal −Vin. Is driven by a signal having a high frequency fc2 ′ or higher.

  In the state of a signal having a frequency fc2 ′ or higher that is higher than the second cutoff frequency fc2, the main amplifier Main_Amp1 and the loop amplifier Loop_Amp1 as shown in the fourth in FIG. 2 by the negative feedback of about 0% and the transmission of about 0%. The voltage gain of the first amplifier AMP1 and the second amplifier AMP2 consisting of the main amplifier Main_Amp2 and the loop amplifier Loop_Amp2 is a high voltage gain of about 47 dB, for example, and amplifies the amplification of the intermediate frequency signal and the high frequency signal with a high voltage gain. This can be performed by AMP1 and AMP2.

  As a result, the preamplifier shown in FIG. 1 constituted by the amplifiers AMP1 and AMP2 generates a weak signal from the magnetoresistive head RMR of the HDD of about 44 dB from an intermediate frequency of about 100 KHz (fc3) down to −3 dB to a high frequency of 845 MHz (fc4). Therefore, when amplifying with a high voltage gain of about 47 dB, it is only necessary to incorporate one capacitor C1 having a capacitance value smaller than 1000 pF in the semiconductor chip of the semiconductor integrated circuit. An intermediate frequency fc3 of about 100 KHz at which the voltage gain is reduced by -3 dB is a low-frequency cut-off frequency fc3 when the AC differential input signals + Vin and -Vin are amplified by the first amplifier AMP1 and the second amplifier AMP2. .

  In FIG. 1, since the relationship Zout ≧ Zin is set between the output impedance Zout of the loop amplifiers Loop_Amp1 and Loop_Amp2 and the input impedance Zin of the main amplifiers Main_Amp1 and Main_Amp2, it depends on the output impedances Zout of the loop amplifiers Loop_Amp1 and Loop_Amp2. The relationship of fc1 ≦ fc2 is established between the first cut-off frequency fc1 and the second cut-off frequency fc2 depending on the input impedance Zin of the main amplifiers Main_Amp1 and Main_Amp2. As a result, the low-frequency cutoff frequency fc3 is determined by the higher second cutoff frequency fc2 and frequency fc2 ′. Conversely, if the relationship of Zout <Zin is set, the relationship of fc1> fc2 is established, and is determined by the higher first cutoff frequency fc1.

≪Specific configuration of preamplifier≫
(Second embodiment of the present invention)
FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to a second preferred embodiment of the present invention including a preamplifier having a specific configuration for amplifying a weak signal of a magnetoresistive head RMR of a perpendicular magnetic recording type hard disk drive (HDD). FIG.

  The configuration and operation of the preamplifier having the specific configuration shown in FIG. 3 are basically the same as the basic configuration of the preamplifier shown in FIG. 1 and the basic operation shown in FIG. In FIG. 3, the main amplifiers Main_Amp1 and Main_Amp2 and the loop amplifiers Loop_Amp1 and Loop_Amp2 shown in FIG. The output differential amplifier 6, the base current compensation circuit BC_CC for compensating the base current of the NPN bipolar transistor as the semiconductor amplifying element constituting the main amplifiers Main_Amp 1 and Main_Amp 2, and the operation mode signal MODE of the hard disk drive (HDD). In response, a switch controller SW_CNT for controlling on / off of the plurality of switches SW1... SW9 is added.

  The main amplifier Main_Amp1 includes differential amplifier transistors Q1 and Q2 for signal amplification, differential transistor transistors Q5 and Q6 for driving the loop amplifier, grounded base transistors Q9, Q10, Q11, and Q12 for improving high frequency characteristics, and a load. It comprises resistors R1, R3, R4, a constant current source I1, switches SW5, SW7, and resistors R7, R9. The bases of the transistors Q1 and Q5 function as a non-inverting input terminal (+) of the main amplifier Main_Amp1, while the bases of the transistors Q2 and Q6 function as an inverting input terminal (−) of the main amplifier Main_Amp1. The weak signals at both ends of the magnetoresistive head RMR are current-amplified by differential pair transistors Q1 and Q2 for signal amplification, and the load resistance R1 and the load resistance of the main amplifier Main_Amp2 via the grounded base transistors Q9 and Q12 for improving high frequency characteristics. The voltage is amplified by being converted into a voltage by R2, and the amplified voltage signal is supplied to the differential input of the output differential amplifier 6. The weak signals at both ends of the magnetoresistive head RMR are amplified by the differential pair transistors Q5 and Q6 for driving the loop amplifier, and converted to a voltage by the load resistors R3 and R4 via the common base transistors Q10 and Q11 for improving the high frequency characteristics. Voltage conversion is performed by the conversion, and the amplified voltage signal is supplied to the inverting input terminal 8 (−) and the non-inverting input terminal 7 (+) of the loop amplifier Loop_Amp1, and the output 9 of the loop amplifier Loop_Amp1 is the main amplifier Main_Amp1. Are connected to the bases of the transistors Q2 and Q6 as the inverting input terminal (−) and one end of the capacitor C1.

  FIG. 11 is a circuit diagram showing a configuration of a preamplifier loop amplifier Loop_Amp1 having the specific configuration shown in FIG.

  As shown in the figure, the loop amplifier Loop_Amp1 includes differential pair transistors Q39 and Q40 driven by the inverting input signal of the inverting input terminal 8 (−) and the non-inverting input signal of the non-inverting input terminal 7 (+). , Two P-MOS current mirrors composed of P-channel MOS transistors M11, M12, M13 and M14, one N-MOS current mirror composed of N-channel MOS transistors M15 and M16, and two constant currents It consists of sources I1 and I5 and two switches SW1 and SW3. By setting the channel length of the six MOS transistors M11 to M16 constituting two P-MOS current mirrors and one N-MOS current mirror to be large and the current flowing through them to be small, the output of the loop amplifier Loop_Amp1 The output resistance of the impedance Zout can be set very high. As described above, the first cutoff frequency f1 is set by the product of the high resistance of the output impedance Zout1 of the loop amplifier Loop_Amp1 and the capacitance of the capacitor C1. In order to further reduce the first cut-off frequency f1, it is recommended to connect three capacitors to two P-MOS current mirrors and one N-MOS current mirror as shown in FIG. The first negative feedback circuit and the second negative feedback circuit are not limited to the circuit configurations of the loop amplifiers Loop_Amp1 and Loop_Amp2 shown in FIG. The first negative feedback circuit and the second negative feedback circuit are connected between the collector of the transistor Q11 of the main amplifier Main_Amp1 of FIG. 3 and the bases of the transistors Q2 and Q6 functioning as the inverting input terminal (−) of the main amplifier Main_Amp1. A high resistance negative feedback resistor and a high resistance negative feedback resistor connected between the collector of the transistor Q14 of the main amplifier Main_Amp2 and the bases of the transistors Q3 and Q7 functioning as the inverting input terminal (−) of the main amplifier Main_Amp2. It is also possible to do. The first cut-off frequency f1 is set by the product of the high resistance of these negative feedback resistors and the capacitance of the capacitor C1.

  In FIG. 3, the weak signals at both ends of the magnetoresistive head RMR are current amplified by the signal amplification differential pair transistors Q1 and Q2 of the main amplifier Main_Amp1. At this time, the emitter nonlinear resistance Re of the internal resistance of the differential pair transistors Q1 and Q2 is given by the above (formula 1), and the first input impedance Zin1 of the main amplifier Main_Amp1 is related to the current amplification factor hfe of the bipolar transistor ( (Equation 2).

  As described above, the second cutoff frequency f2 is determined by the product of the resistance value of the input resistance of the first input impedance Zin1 of the main amplifier Main_Amp1 and the capacitance value of the capacitor C1. In order to realize the relatively low second cutoff frequency f2 with the capacitor C1 having a small capacitance value, a high input resistance of the first input impedance Zin1 of the main amplifier Main_Amp1 is required. Usually, since the current amplification factor hfe of the bipolar transistor is a high value of about 100, the high current amplification factor hfe of the differential pair bipolar transistors Q1 and Q2 is the first input impedance of the main amplifier Main_Amp1 given by the above (Equation 2). This contributes significantly to the improvement of the resistance value of Zin1.

  Like the main amplifier Main_Amp1, the main amplifier Main_Amp2 includes a differential pair transistors Q3 and Q4 for signal amplification, a differential pair transistors Q7 and Q8 for driving a loop amplifier, and base-grounded transistors Q13 and Q14 for improving high-frequency characteristics. Q15, Q16, load resistors R2, R5, R6, a constant current source I2, switches SW6, SW8, resistors R8, R10. The bases of the transistors Q4 and Q8 function as a non-inverting input terminal (+) of the main amplifier Main_Amp2, while the bases of the transistors Q3 and Q7 function as an inverting input terminal (−) of the main amplifier Main_Amp2. The weak signals at both ends of the magnetoresistive head RMR are current-amplified by the differential pair transistors Q3 and Q4 for signal amplification, and the load resistance R2 and the load resistance of the main amplifier Main_Amp1 via the grounded base transistors Q13 and Q16 for improving high frequency characteristics. The voltage is amplified by being converted into a voltage by R1, and the amplified voltage signal is supplied to the differential input of the output differential amplifier 6. The weak signals at both ends of the magnetoresistive head RMR are amplified by the differential pair transistors Q7 and Q8 for driving the loop amplifier, and converted to a voltage by the load resistors R5 and R6 via the common base transistors Q14 and Q15 for improving the high frequency characteristics. The voltage is amplified by the conversion, and the amplified voltage signal is supplied to the inverting input terminal 11 (−) and the non-inverting input terminal 10 (+) of the loop amplifier Loop_Amp2, and the output 12 of the loop amplifier Loop_Amp2 is the main amplifier Main_Amp2. Are connected to the bases of the transistors Q3 and Q7 as the inverting input terminal (−) and the other end of the capacitor C1. Similarly to the loop amplifier Loop_Amp1, the loop amplifier Loop_Amp2 includes the circuit shown in FIG.

  The second cutoff frequency f2 of the transmission amount from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp2 is the resistance value of the input resistance of the second input impedance Zin2 of the main amplifier Main_Amp2 and the capacitor C1. Determined by the product of the capacitance value. Similar to the main amplifier Main_Amp1, the high current amplification factor hfe of the differential pair bipolar transistors Q3 and Q4 of the main amplifier Main_Amp2 is conspicuous in improving the resistance value of the second input impedance Zin2 of the main amplifier Main_Amp2 given by the above (Equation 2). Contribute to.

  The first cutoff frequency fc1 of the amount of transmission of the second negative feedback signal to the inverting input terminal (−) of the main amplifier Main_Amp2 is the high resistance value of the output impedance Zout2 of the loop amplifier Loop_Amp2 and the capacitance value of the capacitor C1. Set by product. In order to further reduce the first cut-off frequency f1, it is recommended to connect three capacitors to the P-MOS current mirror and one N-MOS current mirror of the loop amplifier Loop_Amp2.

Amplifier Main_Amp1, as 4I ₀ a constant current of the constant current source I1, I2 of Main_Amp2, differential pair transistors Q1, Q2 and the differential pair transistors Q5, Q6 and the differential pair transistors Q3, Q4 and the differential pair transistors Q7 , Q8 is balanced, a base current I _B of I ₀ / hfe flows through the bases of these transistors Q1 to Q8. As the base current _{I B} of the transistor Q1~Q8 it does not affect the sensing current 4~10mA magnetoresistive head RMR, the main amplifier of the preamplifier Main_Amp1, base current compensation circuit BC_CC is connected to Main_Amp2.

  The base current compensation circuit BC_CC includes a differential transistor Q1, a replica transistor Q17 of Q2,... Q8, a replica transistor Q18 of a common base transistor Q9. , M3, M4, and M5, a constant current source I7, and a switch SW9.

The constant current amount of the constant current source I7 of the base current compensation circuit BC_CC is set to 2I ₀ which is half of the constant current amount 4I ₀ of the constant current sources I1 and I2 of the main amplifiers Main_Amp1 and Main_Amp2. Then, a base current of 2I ₀ / hfe flows through the base of the replica transistor Q17. When the device sizes of the N-channel MOS transistors M1, M2, M3, M4, and M5 of the current mirror are set equal to each other, the base current of 2I ₀ / hfe of the replica transistor Q17 is input to the input N-channel MOS transistor via the base current supply transistor Q19. An output current 2I ₀ / hfe equal to the input current flows through each of the output MOS transistors M1, M2, M3, and M4. Output current _2I 0 / hfe of the output MOS transistor M1 is compensated and a base current _I B of the base current _I B _(I 0 / hfe) and the differential transistors Q5 of the differential transistors Q1 of the main amplifier Main_Amp1 _(I 0 / hfe) , the output MOS transistor M2 of the output current _2I 0 / hfe is the base current _I B of the base current _I B _(I 0 / hfe) and the differential transistors Q6 of the differential transistors Q2 of the main amplifier Main_Amp1 _(I 0 / hfe) to compensate the door, output current _2I 0 / hfe is the base current _I B _{(I 0} of the base current _I B _(I 0 / hfe) and the differential transistor Q7 of the differential transistors Q3 main amplifier Main_Amp2 of the output MOS transistor M3 / Hfe) to compensate for the output current of the output MOS transistor M4. 2I ₀ / hfe compensates for the base current _I B of the base current _I B _(I 0 / hfe) and the differential transistors Q8 differential transistor Q4 of the main amplifier Main_Amp2 _(I 0 / hfe).

  FIG. 15 is a diagram for explaining an on / off control operation by the switch controller SW_CNT of the plurality of switches SW1... SW9 of the preamplifier shown in FIG.

  In response to a sleep command from the host device, the hard disk drive (HDD) enters a sleep mode Sleep Mode with minimum power consumption. In the sleep mode Sleep Mode, power to most circuits of the HDD other than the host interface that accepts a reset interrupt command from the host device is shut off. In response to a standby command from the host device, the HDD enters a standby mode Standby Mode with ultra-low power consumption. In the standby mode Standby Mode, the power to the spindle motor that rotates the magnetic disk of the HDD and the power to the spindle motor control circuit are cut off, and the CPU that controls the spindle motor control circuit enters a sleep state during power supply. In response to an idle command from the host device, the HDD enters an idle mode IDLE MODE with low power consumption. In the idle mode IDLE MODE, the power to the spindle motor that rotates the magnetic disk of the HDD and the power to the spindle motor control circuit are supplied and the rotation of the spindle motor does not stop, but the arm mounted with the recording head and reproducing head is driven. The power to the voice coil motor (VCM) control circuit (actuator) is cut off. In response to a read command or a write command from the host device, the HDD enters a read mode READ MODE or a write mode WRITE MODE that consumes a large amount of power, power is supplied to most of the circuits of the HDD, and the spindle motor rotates. The arm is also driven.

  The switch controller SW_CNT shown in FIG. 3 recognizes a state transition between the plurality of operation modes from a change in the operation mode signal MODE indicating the plurality of operation modes of the HDD.

  In the continuous read mode READ MODE, the switch controller SW_CNT controls the switches SW7 and SW8 connected to the main amplifiers Main_Amp1 and 2 and the switch SW9 of the base current compensation circuit BC_CC to be in an ON state, thereby allowing the differential of the main amplifier Main_Amp1. The pair transistors Q1, Q2, Q5, and Q6 operate, and the differential pair transistors Q3, Q4, Q7, and Q8 of the main amplifier Main_Amp2 operate. At this time, the switch controller SW_CNT controls the switches SW1 and SW2 connected to the loop amplifiers Loop_Amp1 and 2 to an on state, and controls the other switches SW3 and SW4 connected to the loop amplifiers Loop_Amp1 and 2 to an off state. Therefore, the loop amplifiers Loop_Amp1, 2 have relatively high resistance output impedances Zout1, Zout2 due to the relatively small constant currents of the constant current sources I3, I4. At this time, the switch controller SW_CNT makes the differential pair of the equalizing switch SW5 and the main amplifier Main_Amp2 equal to the base input voltage of the differential pair transistors Q1 and Q5 of the main amplifier Main_Amp1 and the base input voltage of the differential pair transistors Q2 and Q6. The equalize switch SW6 that equalizes the base input voltage of the transistors Q3 and Q7 and the base input voltage of the differential pair transistors Q4 and Q8 is controlled to be in an OFF state. Further, at this time, a sense current RMR Isense set to 4 to 10 mA is supplied to the magnetoresistive head RMR.

  When the operation mode of the HDD transitions from the read mode READ MODE to the write mode WRITE MODE, the switch controller SW_CNT controls all the switches SW1.

  When the HDD operation mode transitions from the write mode WRITE MODE to the read mode READ MODE, the switch controller SW_CNT turns on the switches SW7 and SW8 connected to the main amplifiers Main_Amp1 and 2, and the switch SW9 of the base current compensation circuit BC_CC. By controlling the state, the differential pair transistors Q1, Q2, Q5, and Q6 of the main amplifier Main_Amp1 operate, and the differential pair transistors Q3, Q4, Q7, and Q8 of the main amplifier Main_Amp2 operate. At this time, the switch controller SW_CNT controls the switches SW1 and SW2 connected to the loop amplifiers Loop_Amp1 and 2 to an on state, and controls the other switches SW3 and SW4 connected to the loop amplifiers Loop_Amp1 and 2 to an off state. Therefore, the loop amplifiers Loop_Amp1, 2 have relatively high output impedances Zout1, Zout2 due to the currents of the constant current sources I3, I4. At this time, the switch controller SW_CNT makes the differential pair of the equalizing switch SW5 and the main amplifier Main_Amp2 equal to the base input voltage of the differential pair transistors Q1 and Q5 of the main amplifier Main_Amp1 and the base input voltage of the differential pair transistors Q2 and Q6. The equalize switch SW6 that equalizes the base input voltage of the transistors Q3 and Q7 and the base input voltage of the differential pair transistors Q4 and Q8 is temporarily controlled to be in an on state, and then controlled to be in an off state.

  Next, the operation mode of the HDD changes from the write mode WRITE MODE to the idle mode IDLE MODE. In the idle mode IDLE MODE, the rotation of the spindle motor that rotates the magnetic disk of the HDD is not stopped, but the drive of the voice coil motor (VCM) that drives the arm (suspension) on which the magnetoresistive head RMR is mounted is stopped. The sense current RMR Isense supplied to the resistance head RMR is also zero amperes. When the state transitions from the write mode WRITE MODE to the idle mode IDLE MODE, the switch controller SW_CNT controls all the switches SW1... SW9 to the off state.

  When the operation mode of the HDD changes from the idle mode IDLE MODE to the read mode READ MODE, the sense current RMR Isense supplied to the magnetoresistive head RMR is also set to 4 to 10 mA again. The switch controller SW_CNT controls the switches SW7 and SW8 connected to the main amplifiers Main_Amp1 and 2 and the switch SW9 of the base current compensation circuit BC_CC to be in an on state, whereby the differential pair transistors Q1, Q2, and Q5 of the main amplifier Main_Amp1 , Q6 operate, and the differential pair transistors Q3, Q4, Q7, Q8 of the main amplifier Main_Amp2 operate. At this time, the switch controller SW_CNT controls the switches SW1 and SW2 connected to the loop amplifiers Loop_Amp1 and 2 to be in an on state, while temporarily setting the other switches SW3 and SW4 connected to the loop amplifiers Loop_Amp1 and 2 to an on state. Control. Accordingly, the loop amplifiers Loop_Amp1, 2 have output impedances Zout1, Zout2 having relatively low resistance due to the large constant currents of the constant current sources I3, I4, I5, I6. Therefore, when the state transitions from the idle mode IDLE MODE to the read mode READ MODE due to the low output impedances Zout1 and Zout2 of the loop amplifiers Loop_Amp1 and 2, the voltage across the capacitor C1 is between the both ends of the magnetoresistive head RMR from the discharge state. Can be followed at high speed toward a DC voltage of several tens to several hundred mV. Thereafter, the other switches SW3 and SW4 connected to the loop amplifiers Loop_Amp1 and 2 are controlled to be turned off, and the loop amplifiers Loop_Amp1 and 2 are returned to the high output impedances Zout1 and Zout2. The switch controller SW_CNT also includes an equalize switch SW5 and a differential pair transistor of the main amplifier Main_Amp2 that equalize the base input voltage of the differential pair transistors Q1 and Q5 of the main amplifier Main_Amp1 and the base input voltage of the differential pair transistors Q2 and Q6. The equalizing switch SW6 that equalizes the base input voltages of Q3 and Q7 and the base input voltages of the differential pair transistors Q4 and Q8 is temporarily controlled to be in an on state, and then controlled to be in an off state.

≪Electrical characteristics of preamplifier with specific configuration≫
FIG. 13 is a diagram showing frequency characteristics of the voltage gain Gv of the preamplifier shown in FIG.

  The frequency characteristic of the voltage gain Gv of the preamplifier when the capacitance value of the capacitor C1 is 566 pF in the preamplifier of FIG. 3 is a characteristic L1 of FIG. The maximum value of the voltage gain Gv is about 47 dB, and the frequency band of −3 dB is from 100 KHz to 845 MHz. The characteristic L2 in FIG. 13 is that the signals at both ends of the magnetoresistive head are applied to the base of the differential transistor via two coupling capacitors, and the capacitance values of the two coupling capacitors are each set to 283 pF. This is a frequency characteristic of the voltage gain Gv of the preamplifier when the total capacitance value is 566 pF. The maximum value of the voltage gain Gv is about 47 dB, and the frequency band of −3 dB is 550 KHz to 745 MHz, which is a narrower frequency band than the characteristic L1.

  FIG. 14 is a diagram showing the frequency characteristics of the input conversion noise of the preamplifier shown in FIG. The input equivalent noise is a value obtained by dividing the output noise by the voltage gain Gv.

  The frequency characteristic of the input conversion noise of the preamplifier when the capacitance value of the capacitor C1 is 566 pF in the preamplifier of FIG. 3 is the characteristic L1 of FIG. The characteristic L2 in FIG. 14 is that the signals at both ends of the magnetoresistive head are applied to the base of the differential transistor through two coupling capacitors, and the capacitance values of the two coupling capacitors are each set to 283 pF. It is a frequency characteristic of the input conversion noise of the preamplifier when the total capacitance value of the capacitance is 566 pF.

  As shown by the characteristic L1 in FIG. 13, the voltage gain Gv of the preamplifier shown in FIG. 3 is improved in the lower frequency band than the characteristic L2 in FIG. The frequency characteristics of the input equivalent noise of the preamplifier are improved in the low frequency band as compared with the characteristic L2 of FIG. 14, and the characteristic L1 of FIG. 14 is a low level input equivalent noise.

≪Multiple preamplifiers that amplify signals from multiple heads≫
(Third embodiment of the present invention)
FIG. 4 shows a semiconductor integrated circuit according to a third preferred embodiment of the present invention, which includes two preamplifiers for amplifying weak signals of two magnetoresistive heads RMR1 and RMR2 of a perpendicular magnetic recording type hard disk drive (HDD). It is a circuit diagram which shows a circuit.

  The preamplifier shown in FIG. 4 has two preamplifiers shown in FIG. 3, but the two preamplifiers share the loop amplifiers Loop_Amp1 and Amp2. Furthermore, since there are two preamplifiers, two base current compensation circuits BC_CC1 and BC_CC2 are connected to the two preamplifiers.

  The main amplifiers Main_Amp1 and Main_Amp2 of the preamplifier for amplifying the signal of the magnetoresistive head RMR1 of FIG. 4 are configured in exactly the same way as the main amplifiers Main_Amp1 and Main_Amp2 of the preamplifier shown in FIG. The main amplifier Main_Amp1 and the main amplifier Main_Amp3 share the load resistors R1, R3, and R4, and the main amplifier Main_Amp2 and the main amplifier Main_Amp4 share the load resistors R2, R5, and R6.

  The main amplifier Main_Amp3 for amplifying the non-inverted signal of the magnetoresistive head RMR2 of FIG. 4 is a differential pair transistor Q20, Q21 for signal amplification, a differential pair transistor Q24, Q25 for driving a loop amplifier, and for improving high frequency characteristics. The common base transistors Q28, Q29, Q30, and Q31, load resistors R1, R3, and R4, a constant current source I8, switches SW10 and SW12, and resistors R11 and R13. The bases of the transistors Q20 and Q24 function as a non-inverting input terminal (+) of the main amplifier Main_Amp3, while the bases of the transistors Q21 and Q25 function as an inverting input terminal (−) of the main amplifier Main_Amp3. The weak signals at both ends of the magnetoresistive head RMR2 are current-amplified by differential pair transistors Q20 and Q21 for signal amplification, and the load resistance R1 and the load resistance of the main amplifier Main_Amp2 via the grounded base transistors Q28 and Q31 for improving high frequency characteristics. The voltage is amplified by being converted into a voltage by R2, and the amplified voltage signal is supplied to the differential input of the output differential amplifier 6. The weak signal at both ends of the magnetoresistive head RMR2 is amplified by the differential pair transistors Q24 and Q25 for driving the loop amplifier, and is converted to a voltage by the load resistors R3 and R4 via the grounded base transistors Q29 and Q30 for improving the high frequency characteristics. The voltage is amplified by the conversion, and the amplified voltage signal is supplied to the inverting input terminal 8 (−) and the non-inverting input terminal 7 (+) of the loop amplifier Loop_Amp1, and the output 9 of the loop amplifier Loop_Amp1 is supplied to the switch SW21. To the bases of the transistors Q21 and Q25 as the inverting input terminal (−) of the main amplifier Main_Amp3 and one end of the capacitor C2.

  Like the main amplifier Main_Amp3, the main amplifier Main_Amp4 includes a differential amplifier transistor Q22, Q23 for signal amplification, a differential transistor pair Q26, Q27 for driving a loop amplifier, and a grounded base transistor Q32, Q33 for improving high frequency characteristics. Q34, Q35, load resistors R2, R5, R6, a constant current source I9, switches SW11, SW13, resistors R12, R14. The bases of the transistors Q23 and Q27 function as a non-inverting input terminal (+) of the main amplifier Main_Amp4, while the bases of the transistors Q22 and Q26 function as an inverting input terminal (−) of the main amplifier Main_Amp4. The weak signals at both ends of the magnetoresistive head RMR2 are current-amplified by differential pair transistors Q22 and Q23 for signal amplification, and the load resistance R2 and the load resistance of the main amplifier Main_Amp1 via the grounded base transistors Q32 and Q35 for improving high frequency characteristics. The voltage is amplified by being converted into a voltage by R1, and the amplified voltage signal is supplied to the differential input of the output differential amplifier 6. The weak signal at both ends of the magnetoresistive head RMR2 is amplified by the differential pair transistors Q26 and Q27 for driving the loop amplifier, and is converted to a voltage by the load resistors R5 and R6 via the common base transistors Q33 and Q34 for improving the high frequency characteristics. The voltage is amplified by the conversion, and the amplified voltage signal is supplied to the inverting input terminal 11 (−) and the non-inverting input terminal 10 (+) of the loop amplifier Loop_Amp2, and the output 12 of the loop amplifier Loop_Amp2 is supplied to the switch SW22. To the bases of the transistors Q22 and Q26 as the inverting input terminal (−) of the main amplifier Main_Amp4 and the other end of the capacitor C2. Similarly to the loop amplifier Loop_Amp1, the loop amplifier Loop_Amp2 includes the circuit shown in FIG. 11 or the circuit shown in FIG.

  FIG. 12 is a circuit diagram showing a configuration of a preamplifier loop amplifier Loop_Amp1 having the specific configuration shown in FIG.

  As shown in the figure, the loop amplifier Loop_Amp1 includes differential pair transistors Q39 and Q40 driven by the inverting input signal of the inverting input terminal 8 (−) and the non-inverting input signal of the non-inverting input terminal 7 (+). , Two P-MOS current mirrors composed of P-channel MOS transistors M11, M12, M13 and M14, one N-MOS current mirror composed of N-channel MOS transistors M15 and M16, and an inverting input terminal 8 ( 2 composed of differential pair transistors Q41 and Q42 driven by the inverting input signal of −) and the non-inverting input signal of the non-inverting input terminal 7 (+), and P-channel MOS transistors M17, M18, M19 and M20. One composed of a P-MOS current mirror and N-channel MOS transistors M21 and M22 And N-MOS current mirror, and two constant current sources I1, I5, is composed of a two switches SW1, SW3. By setting the channel lengths of the twelve MOS transistors M11 to M16 and M17 to M22 constituting the four P-MOS current mirrors and the two N-MOS current mirrors to be large and the current flowing through them to be small, The output impedance Zout of the loop amplifier Loop_Amp1 can be set very high. As described above, the first cutoff frequency f1 is set by the product of the high resistance of the output impedance Zout1 of the loop amplifier Loop_Amp1 and the capacitance of the capacitor C1. In order to further reduce the first cut-off frequency f1, it is recommended to connect six capacitors to four P-MOS current mirrors and two N-MOS current mirrors as shown in FIG. The

  FIG. 16 is a diagram for explaining an on / off control operation by the switch controller SW_CNT of the plurality of switches SW1 to SW22 of the preamplifier corresponding to the selection operation of the two magnetoresistive heads RMR1 and RMR2 shown in FIG.

  When the magnetoresistive head RMR1 is selected and the magnetoresistive head RMR2 is not selected, the switches SW3 and SW4 of the loop amplifiers Loop_Amp1 and Loop_Amp2 are controlled to be turned off, and the equalizing switches SW5 and SW6 of the main amplifiers Main_Amp1 and Main_Amp2 are also turned off. Controlled. On the other hand, the switches SW7 and SW8 of the main amplifiers Main_Amp1 and Main_Amp2 that amplify the weak signal from the magnetoresistive head RMR1 and the switch SW9 of the base current compensation circuit BC_CC1 are controlled to be on, and the switch SW15 connected to the magnetoresistive head RMR1. , SW16 are controlled to be on, and switches SW19, SW20 connected between the outputs of the loop amplifiers Loop_Amp1, Loop_Amp2 and the inverting input terminals (−) of the main amplifiers Main_Amp1, Main_Amp2 are also controlled to be on.

  The equalizing switches SW10 and SW11 of the main amplifiers Main_Amp3 and Main_Amp4 that amplify a weak signal from the magnetoresistive head RMR2 are also controlled to be in an off state. On the other hand, the switches SW12 and SW13 of the main amplifiers Main_Amp3 and Main_Amp4 and the switch SW14 of the base current compensation circuit BC_CC2 are controlled to be in an off state, and the switches SW17 and SW18 connected to the magnetoresistive head RMR2 are controlled to be in an off state. The switches SW21 and SW22 connected between the outputs of Loop_Amp1 and Loop_Amp2 and the inverting input terminals (−) of the main amplifiers Main_Amp3 and Main_Amp4 are also controlled to be in the OFF state.

  When the magnetoresistive head RMR1 is not selected and the magnetoresistive head RMR2 is selected, the switches SW3 and SW4 of the loop amplifiers Loop_Amp1 and Loop_Amp2 are temporarily turned on and then controlled to the off state, and the main amplifier Main_Amp1 , Main_Amp2 equalizing switches SW5 and SW6 are also controlled to be in an off state. On the other hand, the switches SW7 and SW8 of the main amplifiers Main_Amp1 and Main_Amp2 that amplify the weak signal from the magnetoresistive head RMR1 and the switch SW9 of the base current compensation circuit BC_CC1 are controlled to be in the off state, and the switch SW15 connected to the magnetoresistive head RMR1. , SW16 are controlled to be in an off state, and switches SW19 and SW20 connected between the outputs of the loop amplifiers Loop_Amp1 and Loop_Amp2 and the inverting input terminals (−) of the main amplifiers Main_Amp1 and Main_Amp2 are also controlled to be in an off state.

  The equalizing switches SW10 and SW11 of the main amplifiers Main_Amp3 and Main_Amp4 for amplifying a weak signal from the magnetoresistive head RMR2 are controlled to be turned off after being temporarily turned on. On the other hand, the switches SW12 and SW13 of the main amplifiers Main_Amp3 and Main_Amp4 and the switch SW14 of the base current compensation circuit BC_CC2 are controlled to be on, and the switches SW17 and SW18 connected to the magnetoresistive head RMR2 are controlled to be on. The switches SW21 and SW22 connected between the outputs of Loop_Amp1 and Loop_Amp2 and the inverting input terminals (−) of the main amplifiers Main_Amp3 and Main_Amp4 are also controlled to be in the on state.

  When the magnetoresistive head RMR1 is selected again and the magnetoresistive head RMR2 is not selected, the switches SW3 and SW4 of the loop amplifiers Loop_Amp1 and Loop_Amp2 are temporarily turned on and then controlled to the off state, and the main amplifiers Main_Amp1 and Main_Amp2 are controlled. The equalize switches SW5 and SW6 are also turned on after being temporarily turned on.

≪Other preamp configurations≫
(Fourth embodiment of the present invention)
FIG. 5 is a block diagram showing a semiconductor integrated circuit according to a fourth embodiment of the present invention including a preamplifier having another basic configuration for amplifying a weak signal of a magnetoresistive head RMR of a perpendicular magnetic recording type hard disk drive (HDD). It is.

  The configuration of the preamplifier shown in FIG. 5 differs from the configuration of the preamplifier shown in FIG. 1 in that the non-inverting input terminal (+) and the inverting input terminal (−) of the loop amplifiers Loop_Amp1 and Loop_Amp2 in FIG. In contrast to being connected to the non-inverting output terminal (+) and inverting output terminal (−) of Main_Amp1 and Main_Amp2, in FIG. 5, the non-inverting input terminal (+) and inverting input terminal (−) of the loop amplifiers Loop_Amp1 and Loop_Amp2 ) Is connected in parallel with the non-inverting input terminal (+) and the inverting input terminal (−) of the main amplifiers Main_Amp1 and Main_Amp2. Further, since the differential transistors of the main amplifiers Main_Amp1 and Main_Amp2 are composed of MOS transistors Q1, Q2, Q3, and Q4 having insulated gates as shown in FIG. 7, the non-inverting input terminals (+ of the main amplifiers Main_Amp1 and Main_Amp2) ) And the inverting input terminal (−), input impedances Zin1 and Zin2 are set to extremely high resistance values. Conversely, the output impedances of the loop amplifiers Loop_Amp1 and Loop_Amp2 are set to relatively low resistance values.

  FIG. 6 is a diagram showing the frequency dependence characteristics of the transmission amount of each circuit in the preamplifier shown in FIG.

  The first part of FIG. 6 shows the frequency characteristics of the main amplifiers Main_Amp1 and Main_Amp2 themselves, and has a DC component and a high voltage gain from a very low frequency region to a high frequency region.

  The second part of FIG. 6 shows the frequency characteristics of the transfer amounts of the negative feedback signals DC & SLf_NFB1 and DC & SLf_NFB2 due to the relatively low output impedances Zout1 and Zout2 of the loop amplifiers Loop_Amp1 and Loop_Amp2 and the capacitor C1. Although the DC component up to the first cut-off frequency fc1 and the ultra low frequency region have a high transmission amount, the frequency fc1 ′ higher than the first cut-off frequency fc1 decreases to 1 (0 dB). The first cut-off frequency fc1 is determined by the product of a relatively low resistance value of the output impedances Zout1 and Zout2 of the loop amplifiers Loop_Amp1 and Loop_Amp2 and the capacitance value of the capacitor C1.

  The third part of FIG. 6 shows the amount of transmission from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp1 through the extremely high first input impedance Zin1 of the main amplifier Main_Amp1 and the extremely high level of the main amplifier Main_Amp2. The amount of transmission and frequency characteristics from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp2 via the second input impedance Zin2 are shown. These transmission amounts are large values up to a very low second cutoff frequency fc2, but are rapidly attenuated at frequencies higher than the second cutoff frequency fc2. The second cutoff frequency fc2 is determined by the product of the extremely high resistance value of the first input impedance Zin1 of the main amplifier Main_Amp1 and the second input impedance Zin2 of the main amplifier Main_Amp2 and the capacitance value of the capacitor C1.

  Also, the amount of transmission of the first negative feedback signal DC & SLf_NFB1 to the inverting input terminal (−) of the main amplifier Main_Amp1 and the amount of transmission of the second negative feedback signal DC & SLf_NFB2 to the inverting input terminal (−) of the main amplifier Main_Amp2. Is approximately 0% negative feedback at a frequency much higher than the relatively high first cutoff frequency fc1. Further, via the first input impedance Zin1 of the main amplifier Main_Amp1, the transmission amount LPF1 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp1 and the second input impedance Zin2 of the main amplifier Main_Amp2 The transmission amount LPF2 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp2 is a transmission amount of approximately 0% at a frequency fc2 ′ higher than the relatively low second cutoff frequency fc2. .

  The inverting input terminal (−) of the main amplifier Main_Amp1 and the inverting input terminal (−) of the main amplifier Main_Amp2 are maintained at the levels of the DC signal, the very low frequency signal, and the low frequency signal of the non-inverting input signal + Vin and the inverting input signal −Vin. On the other hand, the non-inverting input terminal (+) of the main amplifier Main_Amp1 and the non-inverting input terminal (+) of the main amplifier Main_Amp2 are based on the first cutoff frequency fc1 of the non-inverting input signal + Vin and the inverting input signal −Vin. Is driven by a signal having a high frequency fc1 ′.

  In the state of the DC signal, the ultra-low frequency signal, and the low frequency signal, the main amplifier Main_Amp1 and the loop amplifier Loop_Amp1 are formed by the negative feedback of about 100% and the transmission of about 100%, as shown in the fourth part of FIG. The voltage gain of the second amplifier AMP2 including the first amplifier AMP1, the main amplifier Main_Amp2, and the loop amplifier Loop_Amp2 is approximately 1 (0 dB), and the DC amplification of the DC signal with a high voltage gain is also performed for the ultra-low frequency signal and the low frequency signal. Low frequency amplification is not performed by the amplifiers AMP1 and AMP2.

  Further, the transmission amount of the first negative feedback signal DC & SLf_NFB1 to the inverting input terminal (−) of the main amplifier Main_Amp1 and the transmission amount of the second negative feedback signal DC & SLf_NFB2 to the inverting input terminal (−) of the main amplifier Main_Amp2. Is substantially 0% negative feedback at a frequency fc1 ′ higher than the first cutoff frequency fc1. Further, via the first input impedance Zin1 of the main amplifier Main_Amp1, the transmission amount LPF1 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp1 and the second input impedance Zin2 of the main amplifier Main_Amp2 The transmission amount LPF2 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp2 is a transmission amount of approximately 0% at a frequency fc2 ′ higher than the relatively low second cutoff frequency fc2. .

  The inverting input terminal (−) of the main amplifier Main_Amp1 and the inverting input terminal (−) of the main amplifier Main_Amp2 are maintained at the levels of the DC signal, the very low frequency signal, and the low frequency signal of the non-inverting input signal + Vin and the inverting input signal −Vin. On the other hand, the non-inverting input terminal (+) of the main amplifier Main_Amp1 and the non-inverting input terminal (+) of the main amplifier Main_Amp2 are based on the first cutoff frequency fc1 of the non-inverting input signal + Vin and the inverting input signal −Vin. Is driven by a signal having a high frequency fc1 ′.

  In the state of the intermediate frequency signal (100 KHz) and the high frequency signal, the first consisting of the main amplifier Main_Amp1 and the loop amplifier Loop_Amp1 as shown in the fourth part of FIG. 6 by the negative feedback of about 0% and the transmission of about 0%. The voltage gain of the second amplifier AMP2 including the amplifier AMP1, the main amplifier Main_Amp2, and the loop amplifier Loop_Amp2 is, for example, a high voltage gain of about 47 dB, and the amplifiers AMP1 and AMP2 amplify the intermediate frequency signal and the high frequency signal with a high voltage gain. It becomes possible.

  FIG. 7 is a circuit diagram showing a semiconductor integrated circuit according to a preferred embodiment of the present invention including a preamplifier having a specific configuration for amplifying a weak signal of a magnetoresistive head RMR of a perpendicular magnetic recording type hard disk drive (HDD). .

  The configuration and operation of the preamplifier with the specific configuration shown in FIG. 7 are basically the same as the basic configuration of the preamplifier shown in FIG. 5 and the basic operation shown in FIG. 6, but the main amplifier Main_Amp1, In order to set the input impedances Zin1 and Zin2 between the non-inverting input terminal (+) and the inverting input terminal (−) of Main_Amp2 to an extremely high resistance value, an insulating gate is provided to the differential pair transistors Q1, Q2, Q3, and Q4. The MOS transistor which has is used. In FIG. 10, the main amplifiers Main_Amp1 and Main_Amp2 and the loop amplifiers Loop_Amp1 and Loop_Amp2 shown in FIG. 5 are specifically composed of MOS semiconductor amplification elements and semiconductor passive elements, and output signals from the main amplifiers Main_Amp2 and Main_Amp2 An output differential amplifier 6 to be amplified and a switch controller SW_CNT for controlling on / off of a plurality of switches SW1... SW9 in response to an operation mode signal MODE of a hard disk drive (HDD) are added.

  The main amplifier Main_Amp1 includes differential pair MOS transistors Q1 and Q2 for signal amplification, gate-grounded MOS transistors Q9 and Q12 for improving high frequency characteristics, a load resistor R1, a constant current source I1, switches SW5 and SW7, It consists of a resistor R7. The gate of the MOS transistor Q1 functions as a non-inverting input terminal (+) of the main amplifier Main_Amp1, while the gate of the MOS transistor Q2 functions as an inverting input terminal (−) of the main amplifier Main_Amp1. The weak signals at both ends of the magnetoresistive head RMR are current-amplified by the differential pair MOS transistors Q1 and Q2 for signal amplification, and are connected to the load resistor R1 and the main amplifier Main_Amp2 via the gate-grounded MOS transistors Q9 and Q12 for improving high-frequency characteristics. Voltage amplification is performed by converting the voltage to the load resistor R2, and the amplified voltage signal is supplied to the differential input of the output differential amplifier 6. The weak signals at both ends of the magnetoresistive head RMR are supplied to the non-inverting input terminal 7 (+) and the inverting input terminal 8 (−) of the loop amplifier Loop_Amp1, and the output 9 of the loop amplifier Loop_Amp1 is the inverting input terminal (of the main amplifier Main_Amp1). -) Is connected to the gate of the MOS transistor Q2 and one end of the capacitor C1.

  Like the main amplifier Main_Amp1, the main amplifier Main_Amp2 includes a differential pair MOS transistors Q3 and Q4 for signal amplification, gate-grounded MOS transistors Q13 and Q16 for improving high frequency characteristics, a load resistor R2, a constant current source I2, and a switch. SW6, SW8 and resistor R8 are included. The gate of the MOS transistor Q4 functions as a non-inverting input terminal (+) of the main amplifier Main_Amp2, while the gate of the MOS transistor Q3 functions as an inverting input terminal (−) of the main amplifier Main_Amp2. The weak signals at both ends of the magnetoresistive head RMR are current-amplified by the differential pair MOS transistors Q3 and Q4 for signal amplification, and are connected to the load resistor R2 and the main amplifier Main_Amp1 via the gate-grounded MOS transistors Q13 and Q16 for improving high-frequency characteristics. The voltage is amplified by being converted into a voltage by the load resistor R1, and the amplified voltage signal is supplied to the differential input of the output differential amplifier 6. The weak signals at both ends of the magnetoresistive head RMR are supplied to the non-inverting input terminal 10 (+) and the inverting input terminal 11 (−) of the loop amplifier Loop_Amp2, and the output 12 of the loop amplifier Loop_Amp2 is the inverting input terminal (of the main amplifier Main_Amp2). -) Connected to the gate of the transistor Q3 and the other end of the capacitor C1. Similarly to the loop amplifier Loop_Amp1, the loop amplifier Loop_Amp2 is configured by a circuit shown in FIG. 11, for example.

(Fifth embodiment of the present invention)
FIG. 8 is a block diagram showing a semiconductor integrated circuit according to a fifth embodiment of the present invention including a preamplifier having another basic configuration for amplifying a weak signal of a magnetoresistive head RMR of a perpendicular magnetic recording type hard disk drive (HDD). It is.

  The configuration of the preamplifier shown in FIG. 8 is different from the configuration of the preamplifier shown in FIG. 1 in that the non-inverting input terminal (+) and the inverting input terminal (−) of the loop amplifiers Loop_Amp1 and Loop_Amp2 in FIG. 8 is connected to the non-inverting output terminal and the inverting output terminal of Main_Amp1 and Main_Amp2, whereas in FIG. 8, the non-inverting input terminal (+) and the inverting input terminal (−) of the loop amplifiers Loop_Amp1 and Loop_Amp2 are the main amplifier Main_Amp1. , Main_Amp2 are connected in parallel to the non-inverting input terminal (+) and the inverting input terminal (−), and the other components are the same as those in FIG. Further, in FIG. 5, the input impedances Zin1 and Zin2 between the non-inverting input terminal (+) and the inverting input terminal (−) of the main amplifiers Main_Amp1 and Main_Amp2 are set to extremely high resistance values. 8, the input impedances Zin1 and Zin2 between the non-inverting input terminal (+) and the inverting input terminal (−) of the main amplifiers Main_Amp1 and Main_Amp2 are set to relatively low resistance values.

  FIG. 9 is a diagram showing the frequency dependence characteristics of the transmission amount of each circuit in the preamplifier shown in FIG.

  The first part of FIG. 9 shows the frequency characteristics of the main amplifiers Main_Amp1 and Main_Amp2 themselves, and has a DC component and a high voltage gain from a very low frequency region to a high frequency region.

  The second part of FIG. 9 shows the frequency characteristics of the transfer amounts of the negative feedback signals DC & SLf_NFB1 and DC & SLf_NFB2 due to the output impedances Zout1 and Zout2 of the loop amplifiers Loop_Amp1 and Loop_Amp2 and the capacitor C1, and the first cut is relatively low. Although the DC component up to the off frequency fc1 and the ultra low frequency region have a high transmission amount, the frequency is lower than 1 (0 dB) at a frequency higher than the first cutoff frequency fc1. The first cut-off frequency fc1 is determined by the product of extremely high resistance values of the output impedances Zout1 and Zout2 of the loop amplifiers Loop_Amp1 and Loop_Amp2 and the capacitance value of the capacitor C1.

  The third part of FIG. 9 shows the amount of transmission from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp1 via the first input impedance Zin1 of the main amplifier Main_Amp1 and the second input impedance of the main amplifier Main_Amp2. The amount of transmission and frequency characteristics from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp2 via Zin2 are shown. These transmission amounts are large values up to a relatively high second cutoff frequency fc2, but rapidly attenuate at a frequency fc2 ′ higher than the second cutoff frequency fc2. The second cutoff frequency fc2 is determined by the product of the relatively low resistance value of the first input impedance Zin1 of the main amplifier Main_Amp1 and the second input impedance Zin2 of the main amplifier Main_Amp2 and the capacitance value of the capacitor C1.

  Further, the amount of transmission of the first negative feedback signal DC & SLf_NFB1 to the inverting input terminal (−) of the main amplifier Main_Amp1, and the amount of transmission of the second negative feedback signal DC & SLf_NFB2 to the inverting input terminal (−) of the main amplifier Main_Amp2. Is a negative feedback of approximately 0% at a frequency fc1 ′ higher than the relatively low first cutoff frequency fc1. Further, via the first input impedance Zin1 of the main amplifier Main_Amp1, the transmission amount LPF1 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp1 and the second input impedance Zin2 of the main amplifier Main_Amp2 The transmission amount LPF2 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp2 is a transmission amount of approximately 0% at a frequency fc2 ′ higher than the relatively high second cutoff frequency fc2. .

  The inverting input terminal (−) of the main amplifier Main_Amp1 and the inverting input terminal (−) of the main amplifier Main_Amp2 are maintained at the levels of the DC signal, the very low frequency signal, and the low frequency signal of the non-inverting input signal + Vin and the inverting input signal −Vin. In contrast, the non-inverting input terminal (+) of the main amplifier Main_Amp1 and the non-inverting input terminal (+) of the main amplifier Main_Amp2 have a relatively high second cutoff of the non-inverting input signal + Vin and the inverting input signal −Vin. It is driven by a signal having a frequency fc2 ′ higher than the frequency fc2.

  In the state of the DC signal, the ultra-low frequency signal, and the low frequency signal, the main amplifier Main_Amp1 and the loop amplifier Loop_Amp1 are constituted by the negative feedback of about 100% and the transmission of about 100%, as shown in the fourth part of FIG. The voltage gain of the second amplifier AMP2 composed of the first amplifier AMP1, the main amplifier Main_Amp2, and the loop amplifier Loop_Amp2 is approximately 1 (0 dB), and the DC amplification of the DC signal with a high voltage gain is also performed for the ultra-low frequency signal and the low frequency signal. Low frequency amplification is not performed by the amplifiers AMP1 and AMP2.

  Further, the amount of transmission of the first negative feedback signal DC & SLf_NFB1 to the inverting input terminal (−) of the main amplifier Main_Amp1, and the amount of transmission of the second negative feedback signal DC & SLf_NFB2 to the inverting input terminal (−) of the main amplifier Main_Amp2. Is substantially 0% negative feedback in the intermediate frequency signal and the high frequency signal that are higher than the first cut-off frequency fc1. Further, via the first input impedance Zin1 of the main amplifier Main_Amp1, the transmission amount LPF1 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp1 and the second input impedance Zin2 of the main amplifier Main_Amp2 The transmission amount LPF2 from the non-inverting input terminal (+) to the inverting input terminal (−) of the main amplifier Main_Amp2 is a transmission amount of approximately 0% at a frequency fc2 ′ higher than the second cutoff frequency fc2.

  The inverting input terminal (−) of the main amplifier Main_Amp1 and the inverting input terminal (−) of the main amplifier Main_Amp2 are maintained at the levels of the DC signal, the very low frequency signal, and the low frequency signal of the non-inverting input signal + Vin and the inverting input signal −Vin. In contrast, the non-inverting input terminal (+) of the main amplifier Main_Amp1 and the non-inverting input terminal (+) of the main amplifier Main_Amp2 have a relatively high second cutoff of the non-inverting input signal + Vin and the inverting input signal −Vin. It is driven by a signal having a frequency fc2 ′ higher than the frequency fc2.

  In the state of driving with a signal having a frequency fc2 ′ higher than the relatively high second cut-off frequency fc2, the main amplifier has a negative feedback of about 0% and a transmission of about 0% as shown in the fourth part of FIG. The voltage gain of the first amplifier AMP1 composed of Main_Amp1 and the loop amplifier Loop_Amp1 and the second amplifier AMP2 composed of the main amplifier Main_Amp2 and the loop amplifier Loop_Amp2 becomes a high voltage gain of about 47 dB, for example, and the intermediate frequency signal and the high frequency with a high voltage gain. Signal amplification can be performed by the amplifiers AMP1 and AMP2.

≪Specific configuration of other preamplifiers≫
FIG. 10 is a circuit diagram showing a semiconductor integrated circuit according to a preferred embodiment of the present invention including a preamplifier having a specific configuration for amplifying a weak signal of a magnetoresistive head RMR of a perpendicular magnetic recording type hard disk drive (HDD). .

  The configuration and operation of the preamplifier having the specific configuration shown in FIG. 10 are basically the same as the basic configuration of the preamplifier shown in FIG. 8 and the basic operation shown in FIG. In FIG. 10, the main amplifiers Main_Amp1 and Main_Amp2 and the loop amplifiers Loop_Amp1 and Loop_Amp2 shown in FIG. 8 are specifically composed of semiconductor amplifying elements and semiconductor passive elements, and the output signals from the main amplifiers Main_Amp1 and Main_Amp2 are amplified. The output differential amplifier 6, the base current compensation circuit BC_CC for compensating the base current of the NPN bipolar transistor as the semiconductor amplifying element constituting the main amplifiers Main_Amp 1 and Main_Amp 2, and the operation mode signal MODE of the hard disk drive (HDD). In response, a switch controller SW_CNT for controlling on / off of the plurality of switches SW1... SW9 is added.

  The main amplifier Main_Amp1 includes differential amplifier transistors Q1 and Q2 for signal amplification, common base transistors Q9 and Q12 for improving high frequency characteristics, a load resistor R1, a constant current source I1, switches SW5 and SW7, and a resistor R7. , R9. The base of the transistor Q1 functions as a non-inverting input terminal (+) of the main amplifier Main_Amp1, while the base of the transistor Q2 functions as an inverting input terminal (−) of the main amplifier Main_Amp1. The weak signals at both ends of the magnetoresistive head RMR are current-amplified by the differential pair transistors Q1 and Q2 for signal amplification, and the load resistance R1 and the load resistance of the main amplifier Main_Amp2 through the grounded base transistors Q9 and Q12 for improving the high frequency characteristics. The voltage is amplified by being converted into a voltage by R2, and the amplified voltage signal is supplied to the differential input of the output differential amplifier 6. The weak signals at both ends of the magnetoresistive head RMR are supplied to the non-inverting input terminal 7 (+) and the inverting input terminal 8 (−) of the loop amplifier Loop_Amp1, and the output 9 of the loop amplifier Loop_Amp1 is the inverting input terminal (of the main amplifier Main_Amp1). -) Connected to the base of the transistor Q2 and one end of the capacitor C1.

  Like the main amplifier Main_Amp1, the main amplifier Main_Amp2 includes a differential pair transistors Q3 and Q4 for signal amplification, a grounded base transistor Q13 and Q16 for improving high frequency characteristics, a load resistor R2, a constant current source I2, a switch SW6, It consists of SW8 and resistors R8 and R10. The base of the transistor Q4 functions as a non-inverting input terminal (+) of the main amplifier Main_Amp2, while the base of the transistor Q3 functions as an inverting input terminal (−) of the main amplifier Main_Amp2. The weak signals at both ends of the magnetoresistive head RMR are current-amplified by the differential pair transistors Q3 and Q4 for signal amplification, and the load resistance R2 and the load resistance of the main amplifier Main_Amp1 via the grounded base transistors Q13 and Q16 for improving high frequency characteristics. The voltage is amplified by being converted into a voltage by R1, and the amplified voltage signal is supplied to the differential input of the output differential amplifier 6. The weak signals at both ends of the magnetoresistive head RMR are supplied to the non-inverting input terminal 10 (+) and the inverting input terminal 11 (−) of the loop amplifier Loop_Amp2, and the output 12 of the loop amplifier Loop_Amp2 is the inverting input terminal (of the main amplifier Main_Amp2). -) Connected to the base of the transistor Q3 and the other end of the capacitor C1. Similarly to the loop amplifier Loop_Amp1, the loop amplifier Loop_Amp2 is configured by a circuit shown in FIG. 11, for example.

  The switch controller SW_CNT of the base current compensation circuit BC_CC in FIG. 10 is exactly the same as the switch controller SW_CNT of the base current compensation circuit BC_CC in FIG.

  FIG. 17 is a circuit diagram showing a semiconductor integrated circuit according to another preferred embodiment of the present invention including a preamplifier having a specific configuration for amplifying a weak signal of a magnetoresistive head RMR of a perpendicular magnetic recording type hard disk drive (HDD). It is. The differential transistors of the main amplifiers Main_Amp1 and Main_Amp2 shown in FIG. 7 are composed of MOS transistors Q1, Q2, Q3, and Q4 having insulated gates, so that the non-inverting input terminals (+) and the inverting inputs of the main amplifiers Main_Amp1 and Main_Amp2 The input impedances Zin1 and Zin2 between the terminal (−) are set to extremely high resistance values, whereas the differential transistors of the main amplifiers Main_Amp1 and Main_Amp2 shown in FIG. The input impedances Zin1 and Zin2 between the non-inverting input terminal (+) and the inverting input terminal (−) of the main amplifiers Main_Amp1 and Main_Amp2 are set to relatively low resistance values while being configured by Q2, Q3, and Q4. It is. The output impedances of the loop amplifiers Loop_Amp1 and Loop_Amp2 are set to relatively high resistance values.

  In the preamplifier having the specific configuration shown in FIG. 17, the differential pair bipolar transistors Q1, Q2, Q3, Q4 of the main amplifiers Main_Amp1, Main_Amp2 of the preamplifier shown in FIG. 10 are N-channel MOS transistors Q1, Q01, Q2, Q02, It is replaced with a current mirror composed of Q3, Q03, Q4, and Q04. Although the bipolar transistor has a current amplification function for amplifying the base current, the DC impedance of the gate of the MOS transistor is extremely high and does not have a current amplification function. In order to cause the MOS transistor to perform current amplification, a current mirror composed of the MOS transistor is used. For example, the element size (channel width W / channel length L) of diode-connected N-channel MOS transistors Q01, Q02, Q03, and Q04 that are input transistors of the current mirror is set to the output transistors Q1, Q2, Q3, and Q4 of the current mirror. Set to 1 / 100th of the element size (channel width W / channel length L). Then, an output current that is 100 times the input current flowing in the N-channel MOS transistors Q01, Q02, Q03, and Q04 of the current mirror input transistor flows in the output transistors Q1, Q2, Q3, and Q4 of the current mirror. A function equivalent to the grounded emitter current amplification factor hfe of the bipolar transistor is realized by dividing the element size of the output transistor of the current mirror, which is the mirror ratio Rm of the current mirror, by the element size of the input transistor of the current mirror. can do.

As is well known, the current I _DS of the drain / source path of a MOS transistor operating in the saturation region has a channel width of W, a channel length of L, a conductance of β ₀ , a gate-source voltage Vgs, and a threshold voltage. Where Vth is given by:

_{I DS = (W / L)} · (β 0/2) · (Vgs-Vth) 2 ... (3 type)
From this equation, a non-linear resistance Rgs between the gate and the source of the MOS transistor is obtained as in the following equation.

∂I _DS / ∂Vgs = (W / L) · β ₀ · (Vgs−Vth)
_{Rgs = ∂Vgs / ∂I DS = 1} / ((W / L) · β 0 · (Vgs-Vth)) ... (4 type)
Therefore, high input impedances Zin1 and Zin2 having a value obtained by multiplying the gate-source nonlinear resistance Rgs of the differential pair MOS transistors Q1, Q2, Q3, and Q4 given by (Equation 4) and the mirror ratio Rm of the current mirror, It is obtained between the non-inverting input terminal (+) and the inverting input terminal (−) of the main amplifiers Main_Amp1 and Main_Amp2.

  Further, a current mirror current compensation circuit CMC_CC for compensating for a current mirror input current flowing through the N-channel MOS transistors Q01, Q02, Q03, and Q04 of the current mirror input transistor is connected to the main amplifiers Main_Amp1 and Main_Amp2.

  The current mirror current compensation circuit CMC_CC includes a replica MOS transistor Q17 of differential pair MOS transistors Q1, Q2, Q3, and Q4, and a replica input MOS transistor Q017 of N-channel MOS transistors Q01, Q02, Q03, and Q04 as input transistors of the current mirror. A current mirror composed of a replica MOS transistor Q18 of the common-gate MOS transistors Q9, Q12, Q13, and Q16, a current mirror input current supply MOS transistor Q19, and N-channel MOS transistors M1, M2, M3, M4, and M5. The constant current source I7 and the switch SW9 are included.

The constant current amount of the constant current source I7 of the current mirror current compensation circuit CMC_CC is set to I ₀ which is half of the constant current sources I1 and I2 of the main amplifiers Main_Amp1 and Main_Amp2 being 2I ₀ . Then, a current of I ₀ / Rm flows through replica input MOS transistor Q017. When the device sizes of the N-channel MOS transistors M1, M2, M3, M4, and M5 of the current mirror are set to be equal to each other, the current I ₀ / Rm of the replica input MOS transistor Q017 is input via the current mirror input current supply MOS transistor Q19. An output current I ₀ / hfe equal to the input current flows through each of the output MOS transistors M1, M2, M3, and M4. Output Output current _I 0 / Rm of the MOS transistor M1 is to compensate for the current _I 0 / Rm input MOSMOS transistor Q01 of the main amplifier Main_Amp1, the output current _I 0 / Rm of the output MOS transistor M2 is input MOS transistor of the main amplifier Main_Amp1 to compensate for the current _I 0 / Rm of Q02, the output MOS output current _I 0 / Rm of the transistor M3 to compensate for the current _I 0 / Rm of the input MOS transistor Q03 of the main amplifier Main_Amp2, the output current of the output MOS transistor M4 I ₀ / Rm compensates for the current I ₀ / Rm of the input MOS transistor Q04 of the main amplifier Main_Amp2.

≪Magnetic storage device≫
(Sixth embodiment of the present invention)
FIG. 18 is a diagram showing a chip-on-suspension in which the preamplifier of any one of the above-described embodiments of the present invention, for example, the preamplifier of FIG. 4 is mounted on an arm (suspension) of a hard disk drive (HDD). is there.

  As shown in the figure, the four arms 21_A detect a change in magnetic flux from a recording head that performs recording by a perpendicular magnetic recording method that enables high recording density and from a recording head that is recorded by a perpendicular magnetic recording method. Four heads Head1... Head4 composed of magnetoresistive heads as reproducing heads are mounted, and the above-described embodiment of the present invention, for example, the preamplifier chip Preamp IC (21_B) of FIG. The chip-on-suspension shown in FIG. 18 reduces the inductance of the wiring between the magnetoresistive heads as the reproducing heads of the four heads Head1... Head4 and the preamplifier chip Preamp IC (21_B), and perpendicular magnetic recording. It is possible to improve the sensitivity of high-frequency signals having a high recording density by the method.

  FIG. 19 is a diagram showing a configuration of a head 21C (Head1... Head4) including a recording head and a reproducing head mounted on the arm 21_A shown in FIG.

  As shown in the figure, a perpendicular recording layer 20A is formed on the surface of the soft magnetic layer 20 of the recording disk.

  On the left side of the head 21 </ b> C, a recording head that performs recording by a perpendicular magnetic recording system including a recording coil RC, a recording magnetic pole RP, and a return magnetic pole RY is formed. As a result, four magnetic fluxes F1, F2, F3, and F4 are formed in a loop shape, and the direction of signal magnetization from the S pole to the N pole is perpendicular to the recording layer 20A as shown in the enlarged view on the right side. Recording is performed by the perpendicular magnetic recording method.

  On the right side of the head 21C, a reproducing head is formed by a giant magnetoresistive head GMR sandwiched between two reproducing shields RSL1 and RSL2. Note that the air gap AG between the upper surface of the perpendicular recording layer 20A of the recording disk and the lower surface of the head 21C is set to tens of nm, for example, 15 nm. Further, both ends of the giant magnetoresistive head GMR are connected to the non-inverting input terminal (+) of the main amplifier Main_Amp1 of the preamplifier chip Preamp IC and the non-inverting input of the main amplifier Main_Amp2 of any one of the above-described embodiments. It is connected to the terminal (+) without a coupling capacitor.

  20 shows PRML (Partial Response Maximum Likelihood, partial processing of the output signal of the preamplifier that amplifies the weak signal of high recording density by the perpendicular magnetic recording method detected by the giant magnetoresistive head GMR shown in FIGS. It is a figure which shows the read channel of the hard disk drive (HDD) using the response maximum likelihood) detection.

  As shown in the figure, the output signal of the preamplifier chip Prea IC (21_B) is converted into a digital signal via a variable gain amplifier 22, a low pass filter, a waveform equalizer 24, and an A / D converter 25. , And supplied to the Viterbi decoder 28, a read signal with few errors can be obtained from the Viterbi decoder 28. On the other hand, the output of the A / D converter 25 is also supplied to the gain / timing circuit 26. The gain control signal from the gain / timing circuit 26 is supplied to the variable gain amplifier 22, and clock recovery is performed from the timing signal from the gain / timing circuit 26. The recovered clock signal CLK from the voltage controlled oscillator 27 is supplied to the waveform equalizer 24 and the A / D converter 25. The variable gain amplifier 22, the low-pass filter, the waveform equalizer 24, the A / D converter 25, the gain / timing circuit 26, the voltage control oscillator 27, and the Viterbi decoder 28 that constitute the read channel of the HDD are printed on the HDD. It is formed on the printed circuit board HDD PCB.

  By adopting the above-described embodiment of the present invention, for example, the preamplifier having a small chip area shown in FIG. 4, for the HDD shown in FIGS. 18, 19, and 20, the HDD device can be further reduced in size and weight. . Further, since no external component capacitor is used as a coupling capacitor, the number of solder connections can be reduced, and the probability of solder breakage due to vibration of the reproducing head or the like can be reduced.

  In the above description, the hard disk drive (HDD) based on the invention made mainly by the present inventor has been described. However, the present invention is not limited to this, and a perpendicular magnetic recording system used for mainframe computers, servers, etc. It can also be applied to storage tape drives. The present invention can also be applied to preamplifiers for amplifying analog signals such as audio signals and video signals.

  In addition to the preamplifier shown in FIG. 4, the preamplifiers shown in FIGS. 3, 7, 10, and 17 can be used as the preamplifier used in the HDD shown in FIGS.

FIG. 1 is a block diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention including a preamplifier having a basic configuration for amplifying a weak signal of a magnetoresistive head of a perpendicular magnetic recording type hard disk drive. FIG. 2 is a diagram showing the frequency dependence characteristics of the transmission amount of each circuit in the preamplifier shown in FIG. FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to a second preferred embodiment of the present invention including a preamplifier having a specific configuration for amplifying a weak signal of a magnetoresistive head of a perpendicular magnetic recording type hard disk drive. FIG. 4 is a circuit diagram showing a semiconductor integrated circuit according to a third preferred embodiment of the present invention including two preamplifiers for amplifying weak signals of two magnetoresistive heads of a perpendicular magnetic recording type hard disk drive. is there. FIG. 5 is a block diagram showing a semiconductor integrated circuit according to a fourth embodiment of the present invention including a preamplifier having another basic configuration for amplifying a weak signal of a magnetoresistive head of a perpendicular magnetic recording type hard disk drive. FIG. 6 is a diagram showing the frequency dependence characteristics of the transmission amount of each circuit in the preamplifier shown in FIG. FIG. 7 is a circuit diagram showing a semiconductor integrated circuit according to a preferred embodiment of the present invention including a preamplifier having a specific configuration for amplifying a weak signal of a magnetoresistive head of a perpendicular magnetic recording type hard disk drive. FIG. 8 is a block diagram showing a semiconductor integrated circuit according to the fourth embodiment of the present invention including a preamplifier having another basic configuration for amplifying a weak signal of a magnetoresistive head of a perpendicular magnetic recording type hard disk drive. FIG. 9 is a diagram showing the frequency dependence characteristics of the transmission amount of each circuit in the preamplifier shown in FIG. FIG. 10 is a circuit diagram showing a semiconductor integrated circuit according to a preferred embodiment of the present invention including a preamplifier having a specific configuration for amplifying a weak signal of a magnetoresistive head of a perpendicular magnetic recording type hard disk drive. FIG. 11 is a circuit diagram showing the configuration of the loop amplifier of the preamplifier having the specific configuration shown in FIG. FIG. 12 is a circuit diagram showing a configuration of a preamplifier loop amplifier having the specific configuration shown in FIG. FIG. 13 is a diagram showing frequency characteristics of voltage gain of the preamplifier shown in FIG. FIG. 14 is a diagram showing the frequency characteristics of the input conversion noise of the preamplifier shown in FIG. FIG. 15 is a diagram for explaining an on / off control operation by the switch controller of the plurality of switches S of the preamplifier shown in FIG. FIG. 16 is a diagram for explaining the on / off control operation by the switch controller of the plurality of switches of the preamplifier corresponding to the selection operation of the two magnetoresistive heads shown in FIG. FIG. 17 is a circuit diagram showing a semiconductor integrated circuit according to another preferred embodiment of the present invention including a preamplifier having a specific configuration for amplifying a weak signal of a magnetoresistive head of a hard disk drive of a perpendicular magnetic recording system. FIG. 18 is a diagram showing a chip-on-suspension in which the preamplifier according to the embodiment of the present invention is mounted on an arm (suspension) of a hard disk drive. FIG. 19 is a diagram showing a configuration of a head including a recording head and a reproducing head mounted on the arm shown in FIG. FIG. 20 shows a read of a hard disk drive using PRML detection that processes an output signal of a preamplifier that amplifies a weak signal of high recording density by the perpendicular magnetic recording method detected by the giant magnetoresistive head shown in FIGS. It is a figure which shows a channel.

Explanation of symbols

RMR magnetoresistive head 5 Bias circuit 5_1, 5_2 Constant current source Main_Amp1, Main_Amp2 Main amplifiers Loop_Amp1, Loop_Amp2 Loop amplifiers Zin1, Zin2 Input impedance Zout1, Zout2 Output impedance C1 Capacitor DC & SLf_NFF 1 Signal 2 1 cutoff frequency fc2 2nd cutoff frequency fc3 Low frequency cutoff frequency

Claims (20)

A first differential amplifier; a second differential amplifier; a capacitor connected between an inverting input terminal of the first differential amplifier and an inverting input terminal of the second differential amplifier; and the first differential. A first negative feedback from the output of the first differential amplifier to the inverting input terminal of the first differential amplifier is connected between the output of the amplifier and the inverting input terminal of the first differential amplifier. A first negative feedback circuit for transmitting a signal; and an output of the second differential amplifier and an inverting input terminal of the second differential amplifier connected to the output of the second differential amplifier. A second negative feedback circuit for transmitting a second negative feedback signal to the inverting input terminal of the second differential amplifier on a semiconductor chip;
The first differential amplifier includes a first amplifying element and a second amplifying element that are differentially connected, and the second differential amplifier includes a third amplifying element and a fourth amplifying element that are differentially connected. Including
A non-inverting input signal and an inverting input signal of an AC differential input signal superimposed on a DC component are supplied to the non-inverting input terminal of the first differential amplifier and the non-inverting input terminal of the second differential amplifier, respectively.
A transmission amount of the first negative feedback signal to the inverting input terminal of the first differential amplifier and a transmission amount of the second negative feedback signal to the inverting input terminal of the second differential amplifier are a first cut. The first negative feedback circuit and the second negative feedback circuit have the first and second amplifiers of the first and second differential amplifiers so as to attenuate at a frequency higher than an off frequency. And having a first output impedance and a second output impedance of a predetermined resistance value having a resistance higher than the internal resistance of the third amplifying element and the fourth amplifying element,
A first input impedance between the non-inverting input terminal and the inverting input terminal of the first differential amplifier and a second input between the non-inverting input terminal and the inverting input terminal of the second differential amplifier. The resistance value of at least one of the input resistance of the impedance, the first output impedance of the first negative feedback circuit, and the output resistance of the second output impedance of the second negative feedback circuit, and the capacitance value of the capacitor A semiconductor integrated circuit in which a low-frequency cut-off frequency for amplification of the AC differential input signal of the first differential amplifier and the second differential amplifier is set by a product. A first differential amplifier, a second differential amplifier, and a first negative feedback circuit in which a non-inverting input terminal and an inverting input terminal are respectively connected to a non-inverting input terminal and an inverting input terminal of the first differential amplifier. A second negative feedback circuit in which a non-inverting input terminal and an inverting input terminal are connected to a non-inverting input terminal and an inverting input terminal of the second differential amplifier, respectively, and the inverting input of the first differential amplifier A capacitor connected between the terminal and the inverting input terminal of the second differential amplifier on a semiconductor chip;
The output of the first negative feedback circuit is connected to the inverting input terminal of the first differential amplifier and one end of the capacitor, and the output of the second negative feedback circuit is connected to the inverting input terminal of the second differential amplifier. Connected to the other end of the capacitor;
The first differential amplifier includes a first amplifying element and a second amplifying element that are differentially connected, and the second differential amplifier includes a third amplifying element and a fourth amplifying element that are differentially connected. Including
A non-inverting input signal and an inverting input signal of an AC differential input signal superimposed on a DC component are supplied to the non-inverting input terminal of the first differential amplifier and the non-inverting input terminal of the second differential amplifier, respectively. And
A transmission amount of the first negative feedback signal to the inverting input terminal of the first differential amplifier and a transmission amount of the second negative feedback signal to the inverting input terminal of the second differential amplifier are a first cut. The first negative feedback circuit and the second negative feedback circuit have the first and second amplifiers of the first and second differential amplifiers so as to attenuate at a frequency higher than an off frequency. And having a first output impedance and a second output impedance of a predetermined resistance value having a resistance higher than the internal resistance of the third amplifying element and the fourth amplifying element,
A first input impedance between the non-inverting input terminal and the inverting input terminal of the first differential amplifier and a second input between the non-inverting input terminal and the inverting input terminal of the second differential amplifier. The resistance value of at least one of the input resistance of the impedance, the first output impedance of the first negative feedback circuit, and the output resistance of the second output impedance of the second negative feedback circuit, and the capacitance value of the capacitor A semiconductor integrated circuit in which a low-frequency cut-off frequency for amplification of the AC differential input signal of the first differential amplifier and the second differential amplifier is set by a product.   One resistance value of the input resistance of the first input impedance and the second input impedance and the output resistance of the first output impedance and the second output impedance is the resistance value of the first input impedance and the second input impedance. An input resistance and a resistance value lower than or substantially equal to the other resistance value of the output resistance of the first output impedance and the second output impedance, and a resistance value of the low resistance or the substantially equal resistance The semiconductor integrated circuit according to claim 1, wherein the low-frequency cutoff frequency is set by a product of a resistance value of the capacitor and the capacitance value of the capacitor. The input resistance of the first input impedance between the non-inverting input terminal and the inverting input terminal of the first differential amplifier is the internal resistance and current amplification factor of the first amplifying element and the second amplifying element. The input resistance of the second input impedance between the non-inverting input terminal and the inverting input terminal of the second differential amplifier is proportional to the product of the third amplifying element and the fourth amplifier. It is proportional to the product of the internal resistance of the amplifying element and the current amplification factor,
The first input impedance of the first differential amplifier and the second differential amplifier that are proportional to the product of the internal resistance and the current gain and the input resistance of the second input impedance are the first negative feedback circuit and A resistance value lower than the output resistance of the first output impedance and the second output impedance of the second negative feedback circuit, and the first differential via the first input impedance of the first differential amplifier; From the non-inverting input terminal of the second differential amplifier to the inverting input terminal via the amount of transmission from the non-inverting input terminal of the amplifier to the inverting input terminal and the second input impedance of the second differential amplifier. Is attenuated at a frequency higher than the second cutoff frequency set to a frequency higher than the first cutoff frequency, and the second cutoff is The semiconductor integrated circuit according to claim 3, wherein the low cut-off frequency is set by the wave number. The first amplifying element and the second amplifying element of the first differential amplifier and the third amplifying element and the fourth amplifying element of the second differential amplifier are bipolar transistors,
The internal resistance of the first amplifying element, the second amplifying element, the third amplifying element, and the fourth amplifying element is an emitter nonlinear resistance, and the first amplifying element, the second amplifying element, and the third amplifying element are used. The current amplification factor of the element and the fourth amplification element is a grounded emitter current amplification factor,
A base current compensation circuit for compensating a base current of the bipolar transistor includes the non-inverting input terminal and the inverting input terminal of the first differential amplifier, and the non-inverting input terminal and the inverting input terminal of the second differential amplifier. The semiconductor integrated circuit according to claim 4, connected to. The first amplifying element, the second amplifying element, the third amplifying element, and the fourth amplifying element of the first differential amplifier and the second differential amplifier are each configured by a MOS current mirror,
The internal resistance of the first amplifying element, the second amplifying element, the third amplifying element, and the fourth amplifying element is a gate-source non-linear resistance, and the first amplifying element, the second amplifying element, and the The current amplification factors of the third amplification element and the fourth amplification element are mirror ratios of the MOS current mirror,
A current mirror input current compensation circuit for compensating an input current of the MOS current mirror includes the non-inverting input terminal and the inverting input terminal of the first differential amplifier and the non-inverting input terminal and the inverting of the second differential amplifier. The semiconductor integrated circuit according to claim 4 connected to an input terminal.   The first input impedance between the non-inverting input terminal and the inverting input terminal of the first differential amplifier and the first input impedance between the non-inverting input terminal and the inverting input terminal of the second differential amplifier. The first output impedance of the first negative feedback circuit and the second negative feedback circuit and the output resistance of the second output impedance have lower resistance values than the input resistance of two input impedances, and the first cutoff The semiconductor integrated circuit according to claim 3, wherein the low-frequency cutoff frequency is set according to a frequency. The first amplifying element, the second amplifying element, the third amplifying element, and the fourth amplifying element of the first differential amplifier and the second differential amplifier are MOS transistors, respectively.
The non-inverting input terminal and the inverting input of the first differential amplifier having higher resistance than the output resistance of the first output impedance and the second output impedance of the first negative feedback circuit and the second negative feedback circuit. The input resistance of the first input impedance between the terminal and the second input impedance between the non-inverting input terminal and the inverting input terminal of the second differential amplifier is determined by an insulated gate of the MOS transistor. 8. The semiconductor integrated circuit according to claim 7, which is realized. A first constant current source connected to the first differential amplifier; a second constant current source connected to the second differential amplifier; a third constant current source connected to the first negative feedback circuit; 2 The fourth constant current source is connected to the negative feedback circuit,
In a read mode in which the first differential amplifier and the second differential amplifier perform an amplification operation, the first constant current source, the second constant current source, the third constant current source, and the fourth constant current source Constant currents flowing through the first differential amplifier, the second differential amplifier, the first negative feedback circuit, and the second negative feedback circuit, respectively,
In an idle mode in which the first differential amplifier and the second differential amplifier stop the amplification operation, the first differential amplifier, the second differential amplifier, the first negative feedback circuit, and the second negative feedback circuit The semiconductor integrated circuit according to claim 1, wherein the constant currents flowing to the feedback circuit are cut off.   When the first differential amplifier and the second differential amplifier make a transition from the idle mode to the read mode, constant currents flowing through the third constant current source and the fourth constant current source are temporarily The semiconductor integrated circuit according to claim 9, wherein the semiconductor integrated circuit is increased.   In response to the transition from the idle mode to the read mode or from the read mode to the idle mode, the first constant current source, the second constant current source, the third constant current source, and the fourth constant current source. 11. The semiconductor integrated circuit according to claim 9, further comprising a controller that controls a current value of a current flowing through each of the current sources.   A first switch is connected between the non-inverting input terminal and the inverting input terminal of the first differential amplifier, and a first switch is connected between the non-inverting input terminal and the inverting input terminal of the second differential amplifier. Two switches are connected, and when the first differential amplifier and the second differential amplifier transition from the idle mode to the read mode, the first switch and the second switch are temporarily turned on. 12. The semiconductor integrated circuit according to claim 9, wherein the semiconductor integrated circuit is controlled to an off state after being controlled.   When the first differential amplifier and the second differential amplifier transition from the idle mode to the read mode, the controller switches the first switch in response to the transition from the idle mode to the read mode. The semiconductor integrated circuit according to claim 12, wherein the first switch and the second switch are controlled to be turned off after being temporarily turned on.   The semiconductor integrated circuit according to any one of claims 1 to 13, wherein the first negative feedback circuit and the second negative feedback circuit include an amplifier that generates the first output impedance and the second output impedance. A semiconductor integrated circuit according to any one of claims 1 to 14, wherein the magnetic recording medium is driven to perform perpendicular magnetic recording on the magnetic recording medium by a recording head of the head, and the head from the reproducing head of the head Processing a read signal of a magnetic recording medium by using the semiconductor integrated circuit,
A magnet formed by connecting both ends of the read head to the non-inverting input terminal of the first differential amplifier and the non-inverting input terminal of the second differential amplifier of the semiconductor integrated circuit without a coupling capacitor. Recording device.   The magnetic recording apparatus according to claim 15, wherein the reproducing head is a magnetoresistive head.   The magnetic recording apparatus according to claim 16, wherein a shield is formed between the recording head and the magnetoresistive head inside the head.   The magnetic recording apparatus according to claim 15, wherein the semiconductor integrated circuit is mounted on an arm on which the head is mounted.   The magnetic recording apparatus according to claim 15, wherein the magnetic recording medium is a magnetic disk.   The magnetic recording apparatus according to claim 15, wherein the magnetic recording medium is a magnetic tape.

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