JP2008052491A - Method for estimating waveform of consumption current and method for verifying semiconductor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for estimating the waveform of a consumption current, which can estimate the waveform of the consumption current without using circuit simulation. <P>SOLUTION: The method comprises a number-of-cells totalization step S1, a toggle probability calculation step S1, a number-of-operation-cells calculation step S1, and a consumption current waveform estimation step S2. The number-of-cells totalization step S1 totalizes the number of cells in each cell step. The toggle probability calculation step S1 calculates the average toggle probability of cells. The number-of-operation-cells calculation step S1 calculates the number of operation cells. The consumption current waveform estimation step S2 estimates the waveform of the consumption current by setting a value obtained by multiplying the number of cell steps by a previously set cell average delay value as time, multiplying the number of operation cells calculated by the number-of-operation-cells calculation step by previously set power supply voltage and a node average load capacity and setting a value obtained by dividing the multiplied result by the cell average delay value as a current consumption value. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for estimating a consumption current waveform and a method for verifying a semiconductor circuit.

  As the chip size and total power consumption of an LSI (Large Scale Integration), which is a semiconductor circuit, increase, the structure of wiring for supplying power is becoming more complex. Therefore, in the semiconductor circuit, a potential drop (IR drop) due to the resistance component of the wiring has been a problem. In order to verify this IR drop, a static IR drop verification tool or a dynamic IR drop verification tool has been used.

  In the static IR drop verification tool, verification is performed by setting an average current consumption value, and an average value of IR drop is obtained. However, although the static IR drop verification tool has a high execution speed, it cannot take into account the time variation of the current consumption, and thus cannot confirm the influence of components such as capacity on the IR drop. As a representative static IR drop verification tool, there is Astro-Rail manufactured by Synopsys.

  On the other hand, since the dynamic IR drop verification tool performs verification by setting a time change (consumption current waveform) of the current consumption, the time change of the IR drop can be obtained. A typical dynamic IR drop verification tool is HSIM-PWRA manufactured by Synopsys. A specific example of the dynamic IR drop verification tool is described in detail in Non-Patent Document 1.

H. Takata, R. Akiyama, T. Yamanaka, H. Ohkuma, Y. Suetsugu, T. Kanaoka, S. Kumaki, K. Ishihara, A. Hanami, T. Matsumura, T. Watanabe, Y. Ajioka, Y. Matsuda, and S. Iwade, "Physical design methodology for on-chip 64 Mb DRAM MPEG-2 encoding with a multimedia processor," IEICE Trans. Electronics, vol. E85-C, no. 2, pp. 368-374 (Feb 2002).

  The dynamic IR drop verification tool can take into account changes in current consumption over time and confirm the effects of components such as capacitance on IR drop. However, it is necessary to perform circuit simulation to collect the current consumption waveform. was there. Since the circuit simulation for collecting the consumption current waveform is performed, the execution speed of the dynamic IR drop verification tool becomes very slow. For this reason, it was necessary to perform dynamic IR drop verification at high speed. In addition, the dynamic IR drop verification has a large burden for performing the verification.

  Accordingly, the present invention provides a consumption current waveform estimation method capable of estimating a consumption current waveform without using circuit simulation, and a semiconductor circuit verification method using the consumption current waveform estimated by the method. With the goal.

  A solving means according to the present invention is a method for estimating a consumption current waveform of a data signal in a logic part of a semiconductor circuit, wherein all paths in the semiconductor circuit are determined based on a net list defining connection information of the semiconductor circuit. A comprehensive search and cell number counting step that counts the number of cells for each number of cell stages, and all cell types and the number of input terminals excluding the cells on the clock signal from the netlist are obtained. A toggle probability calculation step for calculating a cell average toggle probability based on the cell number for each cell stage calculated in the cell number aggregation step, an operation rate of a flip-flop or a latch circuit located at a preset path start point, and An operating cell that calculates the number of operating cells by multiplying the cell average toggle probability calculated in the toggle probability calculating step by a value that is a power of one less than the number of cell stages. The calculation step is calculated by multiplying the number of cell stages by a preset cell average delay value as the time, and by multiplying the number of operating cells calculated in the operating cell number calculation step by the preset power supply voltage and node average load capacity, the cell average A consumption current waveform estimation step for estimating a consumption current waveform using a value divided by the delay value as a consumption current value.

  The method for estimating a consumption current waveform according to the present invention includes a cell number counting step, a toggle probability calculation step, an operating cell number calculation step, and a consumption current waveform estimation step. There is an effect that the consumption current waveform can be estimated well.

(Embodiment 1)
As described in the background art, when dynamic IR drop verification is performed on a semiconductor circuit, a current consumption waveform is required. In this embodiment, a method for estimating a consumption current waveform of a data signal in the logic unit will be described below.

  First, FIG. 1 shows a flowchart of a method for estimating a consumption current waveform according to the present embodiment. In FIG. 1, a netlist 1 that defines semiconductor circuit connection information (cell type, connection relationship, number of input / output terminals, etc.) is input to step S1 of netlist analysis. In the netlist analysis of step S1, the operation rate 2 of the flip-flop or latch circuit located at the start point is input, and the cell number aggregation, toggle probability calculation, and operation cell number calculation described later are performed.

  Further, in FIG. 1, the output (number of operating cells) of step S1 is input to the consumption current waveform estimation step of step S2. In step S2, the consumption current waveform 4 is estimated and output based on the external input data 3 including the power supply voltage, the node average load capacity, and the cell average delay value, and the output of step S1.

  Next, the processing in the net list analysis in step S1 will be described in more detail. First, in the netlist analysis, a cell number aggregation process is performed. In this cell count totaling process, all paths in the semiconductor circuit are exhaustively searched from the input netlist, and the number of cells for each number of cell stages is counted. Specifically, description will be made using the semiconductor circuit shown in FIG. In FIG. 2, three stages including three flip-flops 5 are provided, and each stage is connected by a logic circuit 6. There are 18 (= 3 × 3 × 2) paths shown in FIG. 2, and all the paths are exhaustively searched to count the number of cells for each number of cell stages.

  Further, the path search and cell count conditions will be described in detail. All flip-flops or latch circuits in the semiconductor circuit are used as search starting points, all flip-flops or latch circuits, gated clock cells, and output terminals are searched. Is the end point of the search. In addition, the search is started from all starting points, a path is searched according to the net list, and the search ends when the path reaches the end point. When a plurality of paths reach the same cell, the cells are counted repeatedly.

  The above conditions will be described using a specific example. First, in FIG. 3A, the first stage is one cell (A), the second stage is two cells (B, C), and the third stage is three cells (D, E, F). Further, in FIG. 3B, the first stage includes two cells (A and B), and the second stage includes only the cell C. However, since the path from the cell A and the path from the cell B overlap, It becomes a cell (C, C). Similarly, in FIG. 3B, the third stage is four cells (D, D, E, E). In FIG. 3C, the first stage is one cell (A), the second stage is two cells (B, C), and the third stage is two cells (D, E). Further, in FIG. 3C, since there is a path from the cell D to the cell E, the fourth stage is one cell (E). In FIG. 3, the starting point cell is represented by a square, and the cells that are counted repeatedly are represented by hatching.

  Next, in the netlist analysis, a toggle probability calculation process is performed. In this toggle probability calculation process, the average value of the toggle probability of all cells excluding the cells on the clock signal from the net list is calculated. The cell toggle probability refers to the probability that when the input of a certain cell changes (for example, from Low to High), the output also changes (for example, from High to Low). Specifically, a method for calculating the average value of the toggle probability is shown below.

  First, there is a method in which the cell type (cell is NAND, NOR, etc.) and the number of input terminals are collected from the netlist, and the toggle probability of the cell is calculated from the cell type and the number of input terminals. As an example using this method, there is a first method in which the toggle probability is 100% for cells having one input terminal, and the toggle probability is uniformly 50% for cells having other input terminals. In addition, there is a second method for calculating a toggle probability by a calculation formula of toggle probability = 1 / (2 ^ (number of input terminals-1)). Further, there is a third method for combining the first method and the second method for each cell type. Specifically, in the third method, the second method is applied when the cell type is AND, NAND, OR, and NOR, and the first method is applied when the cell type is other. Furthermore, in the first method to the third method, there is a fourth method in which the toggle probability is set to 100% regardless of the number of input terminals or the like when the cell type is Exclusive-OR or Exclusive-NOR.

  In addition, when calculating the average value of the toggle probability, the cell type and the number of input terminals are investigated for all the cells in the semiconductor circuit to calculate the toggle probability, and the clock signal such as a flip-flop or latch circuit or a gated clock cell is calculated. The average value is obtained by excluding cells.

  Next, in the net list analysis, the operation cell number calculation process is performed. In this operation cell number calculation process, the number of operation cells per cell stage is based on the result obtained by the cell number aggregation process, the result obtained by the toggle probability calculation process, and the operation rate 2 of the flip-flop or latch circuit located at the start point. Calculate the distribution. Specifically, the number of operating cells = the number of cells in each cell stage × the operation rate of the flip-flop or latch circuit located at the starting point × the average toggle probability ^ (number of cell stages−1).

  Next, the process in the consumption current waveform estimation step in step S2 will be described in more detail. In this consumption current waveform estimation step, the consumption current waveform 4 is estimated based on the number of operating cells as a result of step S1, the power supply voltage, the node average load capacity, and the cell average delay value which are the external input data 3. Specifically, time = number of cell stages × cell average delay value and current consumption value = number of operating cells × node average load capacity × power supply voltage / cell average delay value can be obtained.

  If the time and the current consumption value obtained as described above are graphed with the horizontal axis representing time and the vertical axis representing the current consumption value, the result of consumption current waveform estimation in FIG. 4 is obtained. In FIG. 4, in order to compare with the consumption current waveform 4 obtained in the present embodiment, a circuit simulation result is also shown. The circuit simulation result is obtained by averaging a plurality of simulation patterns. In FIG. 4, the part slower than 0.0 ns shows the current consumption waveform of the data signal in the logic part.

  As described above, in this embodiment, it is possible to estimate the consumption current waveform of the data signal in the logic portion close to the consumption current waveform obtained by performing the circuit simulation without performing the circuit simulation. Further, in this embodiment, the consumption current waveform is obtained in a state where all the conditions such as the path operating in the semiconductor circuit, the cell toggle probability, the cell delay value, and the node load capacity are averaged. For this reason, the consumption current waveform of the semiconductor circuit varies depending on the simulation pattern, but when they are averaged, it becomes close to the consumption current waveform estimated in the present embodiment.

(Embodiment 2)
In the present embodiment, a method for estimating a consumption current waveform of a clock signal in the logic unit will be described below.

  First, FIG. 5 shows a flowchart of a method for estimating a consumption current waveform according to the present embodiment. In FIG. 5, a netlist 1 that defines semiconductor circuit connection information (cell type, connection relationship, number of input / output terminals, etc.) is input to step S1 of netlist analysis. In the netlist analysis in step S1, a toggle probability 10 of gated clock cells is input, and processing for counting the number of cells and calculating the number of operating cells, which will be described later, is performed.

  Further, in FIG. 5, the output (number of operating cells) of step S1 is input to the consumption current waveform estimation step of step S2. In the consumption current waveform estimation step of step S2, the consumption current waveform 4 is estimated and output based on the external input data 11 including the power supply voltage, the node average load capacitance, the clock node capacitance, and the cell average delay value, and the output of step S1. Is done.

  Next, the processing in the net list analysis in step S1 will be described in more detail. First, in the netlist analysis, a cell number aggregation process is performed. In this cell count totaling process, all clock trees in the semiconductor circuit are exhaustively searched from the input netlist, and the number of cells for each number of cell stages is counted.

  Specifically, all clock input terminals in the semiconductor circuit are set as starting points for searching, and all flip-flops or latch circuits are set as end points in searching. Then, the search is started from all the start points, and the clock tree path is searched according to the netlist 1 until the path reaches the end point. By this search, the number of cells for each cell stage can be totaled.

  Next, in the net list analysis, the operation cell number calculation process is performed. In this operation cell number calculation process, the number of operation cells for each cell stage is calculated by reflecting the toggle probability of each cell on the result of the cell number aggregation process.

  There are clock driver cells, flip-flops or latch circuits, and gated clock cells on the clock tree. The toggle probability of the clock driver cells and flip-flops or latch circuits is 100%, and the toggle probability of the gated clock cells is The value is set in advance (for example, 20%). For this reason, in the present embodiment, unlike the first embodiment, it is not necessary to perform the toggle probability calculation process.

  Further, when a gated clock cell exists on the clock tree, the cell operation rate at the later stage is corrected based on the toggle probability of the gated clock cell. More specifically, referring to FIG. 6, the clock driver cell 12 connected to the clock input terminal has a toggle probability of 100%, but the clock driver located at the subsequent stage of the gated clock cell 13 having a toggle probability of 20%. The toggle probability of the cell 14 is 20%. In other words, the cell operation rate at the subsequent stage of the gated clock cell 13 is a value obtained by multiplying the preceding cell operation rate of the gated clock cell 13 by the toggle probability of the gated clock cell 13.

  Next, the process in the consumption current waveform estimation step in step S2 will be described in more detail. In this consumption current waveform estimation step, the consumption current waveform is calculated based on the number of operating cells as a result of step S1 and the power supply voltage, node average load capacity, clock node capacity, and cell average delay value that are the external input data 11. estimate. Specifically, time = number of cell stages × cell average delay value, current consumption value other than final stage = number of operating cells × node average load capacity × power supply voltage / cell average delay value, and final stage current consumption value = operation It can be calculated as the number of cells × clock node capacity × power supply voltage / cell average delay value.

  Here, the clock node capacity is the clock node capacity in the flip-flop or the latch circuit, and is the sum of the capacitance values indicated by the arrows shown in FIG. Note that FIG. 7 is a circuit diagram of a certain flip-flop, and in order to simplify the drawing, wirings for portions to which the clock signals T0 and T1 are input are omitted. In FIG. 7, an arrow written on the gate of the transistor is a gate capacitance, and another arrow is a wiring capacitance or the like.

  FIG. 8 is a graph of the time and current consumption values obtained as described above, with the horizontal axis representing time and the vertical axis representing current consumption value. In FIG. 8, a circuit simulation result is also shown for comparison with the consumption current waveform obtained in the present embodiment. The circuit simulation result is obtained by averaging a plurality of simulation patterns. In FIG. 8, the portion earlier than 0.0 ns shows the current consumption waveform of the clock signal in the logic portion.

  Further, in the consumption current waveform estimation step of the present embodiment, the method for obtaining the difference between the final stage and the final stage is different. This is because the final stage of the clock tree is always a flip-flop or a latch circuit. In addition, since the value of the clock node capacity and the node average load capacity in the flip-flop or latch circuit are greatly different, in order to estimate the current consumption waveform with high accuracy, it is necessary to change the way of obtaining between the final stage and the final stage. is there.

  As described above, in this embodiment, the consumption current waveform of the clock signal in the logic unit can be estimated without applying the circuit simulation by applying the estimation method of the consumption current waveform of the first embodiment. it can. In this embodiment, since the cells constituting the clock tree are limited to clock driver cells, flip-flops or latch circuits, and gated clock cells, the calculation of the number of operating cells is a data signal in the logic unit. It can be simplified compared to

(Embodiment 3)
In the second embodiment, the current consumption waveform is estimated using the net list in which the clock tree is determined. However, in the present embodiment, the net list before the clock tree is determined is used. This is a method of estimating a consumption current waveform. Therefore, in the present embodiment, the method for calculating the number of operating cells for each cell stage in step S1 of netlist analysis is different from that in the second embodiment. Below, the estimation method of the consumption current waveform which concerns on this Embodiment is demonstrated.

  First, FIG. 9 shows a flowchart of a method for estimating a consumption current waveform according to the present embodiment. In FIG. 9, a netlist 1 that defines semiconductor circuit connection information (cell type, connection relationship, number of input / output terminals, etc.) is input to step S1 of netlist analysis. In the netlist analysis of step S1, the toggle probability 10 of the gated clock cell and the fanout number 20 are input, and the cell number estimation and operation cell number calculation described later are performed.

  Further, in FIG. 9, the output (number of operating cells) in step S1 is input to the consumption current waveform estimation step in step S2. In the consumption current waveform estimation step of step S2, the consumption current waveform 4 is estimated and output based on the external input data 11 including the power supply voltage, the node average load capacitance, the clock node capacitance, and the cell average delay value, and the output of step S1. Is done.

  Next, the processing in the net list analysis in step S1 will be described in more detail. Note that the consumption current waveform estimation step in step S2 is the same as that in the second embodiment, and thus detailed description thereof is omitted. First, in the net list analysis, cell number estimation processing is performed. In this cell number estimation process, unlike the second embodiment, since the clock tree is not fixed, the number of cells is estimated from the following conditions.

  The estimation condition is assumed that all flip-flops or latch circuits taken from the netlist 1 exist in the same cell stage. Then, for all the flip-flops or latch circuits, the number of drivers required in the preceding stage is estimated from the preset fan-out number 20. It should be noted that the same processing is performed for a plurality of stages until the number of drivers becomes 1. The fanout number 20 is an average value of the clock tree fanout numbers.

  The above process will be specifically described. First, in the cell number estimation process, information indicating that 1000 flip-flops or latch circuits exist from the netlist 1 is collected. If the preset fan-out number 20 is 5, the number of drivers in the previous stage of the flip-flop or latch circuit is 1000/5 = 200. When the same processing is repeated, the number of drivers in the second stage is 200/5 = 40, the number of drivers in the third stage is 40/5 = 8, the number of drivers in the fourth stage is 2, The number of drivers in the stage is one. The previous 4th stage and the previous 5th stage are not divisible by the fanout number 20, but the number of necessary drivers is described. From the above processing, it can be seen that the estimated number of cells is 125 and 1251 cells.

  Next, in the net list analysis, the operation cell number calculation process is performed. In this operation cell number calculation process, as in the second embodiment, the number of operation cells for each cell stage is calculated by reflecting the toggle probability of each cell on the result of the cell number estimation process. In this embodiment, the number of operating cells is calculated on the assumption that all gated clock cells are present one stage before the final stage (flip-flop or latch circuit). That is, with reference to FIG. 6, when the fourth stage (not shown) is the final stage, the positions of the gated clock cell 13 and the clock driver cell 14 are reversed. The upper path shown in FIG. 6 operates 100%, and the middle and lower paths operate 20% because the gated clock cell 13 exists immediately before the final stage.

  Based on the number of operating cells obtained as a result of the netlist analysis described above, the consumption current waveform estimation step described in the second embodiment can be performed to estimate the consumption current waveform as shown in FIG.

  As described above, in this embodiment, even before the clock tree design (before the clock tree is determined), if the number of flip-flops or latch circuits is determined, the current consumption of the clock signal in the logic unit The waveform can be estimated. In the present embodiment, the number of cells in each stage of the clock tree can be roughly estimated based on the information about the fanout number 20.

  The consumption current waveform of the data signal in the logic unit estimated by the method of the first embodiment and the consumption current waveform of the clock signal in the logic unit estimated by the method of the second or third embodiment are used. Perform dynamic IR drop verification. As a result, the execution speed of the dynamic IR drop verification tool becomes faster than when the circuit simulation result is used, and the burden for performing verification is reduced.

It is a flowchart of the estimation method of the consumption current waveform which concerns on Embodiment 1 of this invention. It is a figure explaining the path | pass of the semiconductor circuit which concerns on Embodiment 1 of this invention. It is a figure explaining the count of the number of cells which concerns on Embodiment 1 of this invention. It is a figure which shows the consumption current waveform which concerns on Embodiment 1 of this invention. It is a flowchart of the estimation method of the consumption current waveform which concerns on Embodiment 2 of this invention. It is a figure explaining the clock tree which concerns on Embodiment 2 of this invention. It is a figure explaining the clock node capacity | capacitance which concerns on Embodiment 2 of this invention. It is a figure which shows the consumption current waveform which concerns on Embodiment 2 of this invention. It is a flowchart of the estimation method of the consumption current waveform which concerns on Embodiment 3 of this invention.

Explanation of symbols

1 netlist, 2 operation rate, 3,11 external input data, 4 consumption current waveform, 5 flip-flop, 6 logic circuit, 10 toggle probability, 12,14 clock driver cell, 13 gated clock cell, 20 fanout number.

Claims (4)

A method of estimating a consumption current waveform of a data signal in a logic part of a semiconductor circuit,
Based on a net list defining the connection information of the semiconductor circuit, exhaustively search all the paths in the semiconductor circuit, and a cell number counting step of counting the number of cells for each number of cell stages,
A toggle probability calculation step of obtaining all cell types and input terminal numbers excluding cells on the clock signal from the netlist, and calculating a cell average toggle probability based on the cell types and the input terminal numbers;
The number of cells for each cell stage counted in the cell number counting step, the operation rate of the flip-flop or latch circuit located at the preset start point of the path, and the cell average toggle probability calculated in the toggle probability calculation step Is multiplied by a value that is a power of 1 less than the number of cell stages, and the number of operating cells is calculated.
A value obtained by multiplying the number of cell stages by a preset cell average delay value is time, and the number of operating cells calculated in the operating cell number calculation step is multiplied by a preset power supply voltage and a node average load capacity. A consumption current waveform estimation method comprising: a consumption current waveform estimation step for estimating a consumption current waveform using a value obtained by dividing a delay value as a consumption current value. A method for estimating a consumption current waveform of a clock signal in a logic part of a semiconductor circuit,
Based on a netlist defining the connection information of the semiconductor circuit, a clock tree in the semiconductor circuit is exhaustively searched, and a cell number counting step for counting the number of cells for each cell stage number;
Of the number of cells for each cell stage counted in the cell number counting step, the number of operating cells is calculated by applying a preset toggle probability to the gated clock cell. Steps,
A value obtained by multiplying the number of cell stages by a preset cell average delay value is time, and when the cell stage is other than the final stage, the power supply voltage and node average load capacity set in advance for the number of operating cells for each cell stage And the value obtained by dividing by the cell average delay value is a current consumption value, and when the cell stage is the final stage, the number of operating cells in the final stage is multiplied by a preset power supply voltage and clock node capacity, and the cell average A consumption current waveform estimation method comprising: a consumption current waveform estimation step for estimating a consumption current waveform using a value obtained by dividing a delay value as a consumption current value. A method for estimating a consumption current waveform of a clock signal in a logic part of a semiconductor circuit,
A cell number estimation step for estimating the number of cells for each cell stage based on a preset number of fan-outs, with respect to the total number of flip-flops or latch circuits collected from the net list defining the connection information of the semiconductor circuit,
By applying a toggle probability set in advance to a gated clock cell that is assumed to exist one stage before the last stage out of the number of cells for each cell stage estimated in the cell number estimation step, the cell stage An operation cell number calculating step for calculating the number of operation cells for each;
A value obtained by multiplying the number of cell stages by a preset cell average delay value is time, and when the cell stage is other than the final stage, the power supply voltage and node average load capacity set in advance for the number of operating cells for each cell stage And the value obtained by dividing by the cell average delay value is a current consumption value, and when the cell stage is the final stage, the number of operating cells in the final stage is multiplied by a preset power supply voltage and clock node capacity, and the cell average A consumption current waveform estimation method comprising: a consumption current waveform estimation step for estimating a consumption current waveform using a value obtained by dividing a delay value as a consumption current value. A first consumption current waveform estimation step for estimating a consumption current waveform of a data signal in the logic unit by the consumption current waveform estimation method according to claim 1;
A second consumption current waveform estimation step for estimating a consumption current waveform of a clock signal in the logic unit by the consumption current waveform estimation method according to claim 2 or 3,
A semiconductor circuit comprising: a verification step for performing dynamic IR drop verification using the consumption current waveform estimated in the first consumption current waveform estimation step and the consumption current waveform estimated in the second consumption current waveform estimation step Verification method.

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