JP2008047710A - Semiconductor substrate, semiconductor device, and manufacturing method thereof - Google Patents

Abstract

A coreless semiconductor substrate is obtained more easily without impairing reliability.
A multi-layer wiring capable of mounting a semiconductor chip on a base metal substrate is constructed in a plurality of regions, and a part of the metal substrate is selectively etched using a resist to mount each semiconductor chip. A stiffener 160 is formed so as to surround the electrode pad 25 in the region. Each region is cut by dicing or the like, and the semiconductor substrate 11 having the stiffener 160 is separated.
[Selection] Figure 6

Description

  The present invention relates to a semiconductor substrate and a semiconductor device. More specifically, the present invention relates to a coreless semiconductor substrate and a semiconductor device using the same.

  In recent years, as electronic devices such as computers, mobile phones, and PDAs (Personal Digital Assistance) have become smaller, more advanced, and faster, such ICs (integrated circuits) and LSIs (Large Scale Integrated Circuits) for such electronic devices have been developed. There is a demand for further downsizing, thinning, high speed and high density of a semiconductor device on which a semiconductor chip is mounted.

  As a technique for reducing the size and thickness of a semiconductor device, a technique of mounting a semiconductor chip on a so-called coreless substrate that does not have a base substrate is known. The coreless substrate can be obtained by building up a wiring substrate including a wiring layer on a base substrate made of metal foil or the like and then peeling the base substrate from the wiring substrate (see Patent Document 1).

Conventionally, after manufacturing a coreless substrate by removing a base substrate from a wiring substrate, a semiconductor device is manufactured by mounting electronic components such as a semiconductor chip on the coreless substrate.
JP 2005-236244 A

  Since the coreless substrate does not have a base substrate and is thin, the coreless substrate generally has poor rigidity. For this reason, a jig for supporting the coreless substrate may be required in the process of mounting an electronic component such as a semiconductor chip. In addition, since the coreless substrate has poor impact resistance and the like, there is a problem in that the handling property is poor, for example, the coreless substrate is damaged even if a small impact is applied to the end of the coreless substrate.

  The present invention has been made in view of these problems, and an object thereof is to provide a technique for more easily manufacturing a coreless semiconductor substrate without impairing reliability. Another object of the present invention is to provide a technique for more easily manufacturing a semiconductor device without impairing the reliability of the semiconductor device using a coreless substrate.

  One embodiment of the present invention is a semiconductor substrate. The semiconductor substrate includes a multilayer wiring layer composed of a plurality of interlayer insulating films and wiring layers, and a stiffener provided in a peripheral portion of the multilayer wiring layer, and the stiffener is used as a base for constructing the multilayer wiring layer. It is formed by selectively removing the metal substrate.

  According to this aspect, since rigidity is provided by the stiffener, handling of the semiconductor substrate is facilitated, and occurrence of damage to the semiconductor substrate can be suppressed. In addition, since a part of the metal substrate used as a base for constructing the multilayer wiring is used as a stiffener, the number of parts of the semiconductor substrate can be reduced.

  Another aspect of the present invention is a method for manufacturing a semiconductor substrate. The manufacturing method includes a step of constructing a multilayer wiring layer interconnected by at least one interlayer insulating film in a plurality of regions on the metal substrate, and a metal substrate so that the metal substrate remains in the peripheral portion of each region. The method includes a step of selectively removing the substrate and a step of dividing each multilayer wiring layer into individual pieces.

  According to this aspect, a semiconductor substrate is manufactured in which a part of the metal substrate that serves as a base for forming the coreless substrate is used as a stiffener. Since a part of the metal substrate used as a base in the manufacturing process is used as a stiffener, the semiconductor substrate does not require a stiffener member and can eliminate the step of attaching the stiffener. Manufacturing cost can be reduced.

  Yet another embodiment of the present invention is a semiconductor device. The semiconductor device includes a multilayer wiring layer including a plurality of interlayer insulating films and wiring layers, a stiffener provided in a peripheral portion of the multilayer wiring layer, and a semiconductor chip mounted on the multilayer wiring layer, and the stiffener is a multilayer It is characterized by being formed by selectively removing a metal substrate used as a base for constructing a wiring layer.

  According to this aspect, since the stiffness is provided by the stiffener, the handling of the semiconductor device is facilitated, and the occurrence of damage in the semiconductor device can be suppressed. Further, since a part of the metal substrate used as a base for constructing the multilayer wiring is used as the stiffener, the number of parts of the semiconductor device can be reduced.

  Yet another embodiment of the present invention is a method for manufacturing a semiconductor device. The method includes a step of constructing multi-layered wiring layers connected to each other by at least one interlayer insulating film in a plurality of regions on the metal substrate, and a metal substrate so that the metal substrate remains in a peripheral portion of each region. Are selectively removed to form a stiffener in each region, and a step of exposing the multilayer wiring layer in each portion surrounded by each stiffener, and a semiconductor chip is mounted on the surface of each exposed multilayer wiring layer A step, a step of sealing each multilayer wiring layer and each semiconductor chip with a sealing resin, a step of cutting the interlayer insulating film and the sealing resin between the regions, and separating each multilayer wiring layer into individual pieces. It is characterized by providing.

  According to this aspect, a semiconductor device is manufactured in which a part of the metal substrate that serves as a base for forming the coreless substrate is used as a stiffener. In the semiconductor device, since a part of the metal substrate used as a base in the manufacturing process is used as a stiffener, a member for the stiffener is not necessary, and the step of attaching the stiffener can be eliminated. Manufacturing cost can be reduced.

  According to the present invention, a coreless semiconductor substrate can be obtained more easily without impairing reliability.

  FIG. 1A is a diagram illustrating a structure of a semiconductor substrate 11 according to the embodiment. FIG. 1B is a plan view showing the structure of the lower surface side of the semiconductor substrate 11.

  The semiconductor substrate 11 has a multilayer wiring structure in which interlayer insulating films and wiring layers are alternately stacked. Specifically, in the semiconductor substrate 11, a plurality of wiring layers 22 are stacked via an interlayer insulating film 24. For example, copper is used for the wiring layer 22. The wiring layers 22 having different layers are electrically connected by via plugs 26 provided in the interlayer insulating film 24. A plurality of electrode pads 25 made of nickel, lead, gold, or alloys thereof formed by electrolytic plating are arranged in an array on the upper surface side of the semiconductor substrate 11 corresponding to the side on which the semiconductor chip is mounted. A C4 (Controlled Collapse Chip Connection) bump 27 made of tin, lead, or an alloy thereof is provided on the top. A stiffener 160 is formed on the upper surface side of the semiconductor substrate 11 so as to surround the C4 bump 27.

  On the other hand, a plurality of ball land portions 29 are arranged in an array on the lower surface side of the semiconductor substrate 11, and a solder ball 50 is joined to each ball land portion 29. Further, the surface of the interlayer insulating film 24 in the gap portion of the solder ball 50 is covered with a solder resist film 28.

  Since the semiconductor substrate 11 of the present embodiment is given rigidity by the stiffener 160, the semiconductor substrate can be easily handled and the occurrence of damage to the semiconductor substrate can be suppressed. The stiffener 160 is formed by using a part of a metal substrate that serves as a foundation for constructing a multilayer wiring structure. Thereby, the number of parts of the semiconductor substrate 11 can be reduced and the manufacturing cost can be reduced. The shape of the stiffener 160 is not limited to the form surrounding the C4 bump 27 as shown in FIG. For example, the C4 bumps 27 may be disposed in parallel with a pair of opposing sides with the group of C4 bumps 27 interposed therebetween.

(Semiconductor substrate manufacturing method)
2 to 6 are process diagrams showing a method for manufacturing a semiconductor device according to the embodiment.

  First, a multilayer wiring substrate is constructed on a metal substrate 100 such as copper serving as a base. Specifically, as shown in FIGS. 2A and 2B, a resist film 102 is applied on the metal substrate 100 and patterned into a shape having a predetermined opening by laser light irradiation. The metal substrate 100 has a size corresponding to the area of a plurality of semiconductor packages. The size of the metal substrate 100 is not particularly limited, but can be, for example, 500 mm square or 600 × 800 mm square. The resist film 102 formed on the metal substrate 100 has a predetermined pattern for each of a plurality of regions where a semiconductor device is formed.

  Next, as shown in FIG. 2C, an electrode pad 25 made of nickel, lead, gold, or an alloy thereof is formed on the metal substrate 100 by electrolytic plating using the resist film 102 as a mask.

  Next, after removing the resist film 102 as shown in FIG. 3A, an interlayer insulating film 24 is formed on the metal substrate 100 as shown in FIG.

  Next, as shown in FIG. 3C, a predetermined region of the interlayer insulating film 24 is removed by laser processing, drilling, or the like to form a via hole 112. By forming each via hole 112 by laser processing, the manufacturing cost can be reduced as compared with the case of drilling.

  Next, as shown in FIG. 4A, a seed layer 120 made of copper is formed on the surface of the interlayer insulating film 24 on the side walls and bottom of the via hole 112 by electroless plating. The seed layer 120 serves as a nucleus for copper growth during copper electroplating, which will be described later.

  Next, as shown in FIG. 4B, a resist film 122 is applied on the seed layer 120 and patterned into a shape having a predetermined opening by irradiation with laser light.

  Next, as shown in FIG. 4C, using the resist film 122 as a mask, the via hole 112 is filled with copper by electrolytic plating to form the via plug 26 and the wiring layer 22 is formed on the interlayer insulating film 24. . By the via plug 26, the wiring layers 22 between different layers are electrically connected.

  Next, as shown in FIG. 4D, after removing the resist film 122, the seed layer 120 existing under the resist film 122 is removed by etching, and the outermost surface of the wiring layer 22 is removed. The surface of the wiring layer 22 is purified.

  The multilayer wiring 20 as shown in FIG. 5A can be constructed on the metal substrate 100 by repeating the processes shown in FIGS. 2 to 4 described above. The multilayer wiring 20 has a multilayer wiring layer in which a semiconductor chip can be mounted in each of a plurality of regions. For example, when the interlayer insulating film has a six-layer structure, the thickness of the multilayer wiring 20 can be reduced to about 300 μm. Subsequently, as shown in FIG. 5B, using a resist film (not shown) as a mask, a solder resist film 28 is formed on the interlayer insulating film 24 so that the outermost wiring layer 22 is exposed. . Further, a ball land portion 29 is formed on the wiring layer 22.

  Next, as shown in FIG. 5C, solder balls 50 are joined to each ball land portion 29 by printing or the like.

  Next, as shown in FIG. 6A, a resist 150 is formed on the surface of the metal substrate 100 in each region where a semiconductor chip can be mounted. The pattern of the resist 150 is not particularly limited, but is preferably provided along the peripheral portion of each region where a semiconductor chip can be mounted.

Next, as shown in FIG. 6B, the metal substrate 100 is selectively removed by etching to expose the electrode pads 25 and the interlayer insulating film 24. Thereby, a part of the metal substrate 100 remains as the stiffener 160. Further, after soldering the C4 bumps 27 for flip chip mounting onto the electrode pads 25, the C4 bumps 27 are flattened by pressing or the like. Note that a solder resist (not shown) made of a resin material having excellent heat resistance may be applied between the C4 bumps 27. With the solder resist, when soldering to the semiconductor substrate 11, the uppermost interlayer insulating film 24 can be protected so that the solder does not adhere to other than necessary portions.
Next, as shown in FIG. 6C, each region where the semiconductor chip can be mounted is separated into pieces by dicing, and the semiconductor substrate 11 is manufactured.

  Through the above steps, the semiconductor substrate 11 is manufactured in which a part of the metal substrate serving as a base for forming the coreless substrate is used as a stiffener. Since part of the metal substrate used as the base or supporting base material in the manufacturing process is used as the stiffener, the semiconductor substrate 11 does not require a stiffener member and can eliminate the step of attaching the stiffener. The manufacturing cost of the semiconductor substrate can be reduced. In addition, since the semiconductor substrate 11 is provided with rigidity by a stiffener, it is easy to handle after singulation, and the occurrence of damage can be suppressed.

  FIG. 7 is a diagram showing a semiconductor device 10 in which a semiconductor chip 30 is packaged using the semiconductor substrate 11 described above. In FIG. 7, the structure of the semiconductor substrate 11 is simplified. The semiconductor chip 30 is flip-chip mounted on the semiconductor substrate 11 with the surface on which the external electrode terminals are provided facing down. More specifically, the solder bumps 32 provided on the external electrode terminals of the semiconductor chip 30 and the corresponding C4 bumps 27 on the upper surface of the semiconductor substrate 11 are soldered. An underfill 70 is filled in a gap between the semiconductor chip 30 and the semiconductor substrate 11. By providing the underfill 70 between the semiconductor chip 30 and the semiconductor substrate 11, it is possible to suppress the stress that the C4 bump 27 receives due to the gap fluctuation between the semiconductor substrate 11 and the semiconductor chip 30 due to thermal expansion during the temperature cycle. Can do. Further, a sealing resin layer 40 is molded on the semiconductor substrate 11 to protect the semiconductor substrate 11 and the semiconductor chip 30.

  On the other hand, on the lower surface of the semiconductor substrate 11, solder balls 50 are joined on each ball land portion 29 (see FIG. 1 and the like), and the ball land portions 29 are arranged in an array. A solder resist film 28 made of a resin material having excellent heat resistance is applied between the solder balls 50. The solder resist film 28 protects the lowermost interlayer insulating film 24 (see FIG. 1 and the like) so that solder does not adhere to areas other than necessary when soldering to the semiconductor substrate 11.

  A stiffener 160 is formed so as to surround the solder ball 50. Since the semiconductor device 10 of the present embodiment is given rigidity by the stiffener 160, the semiconductor device can be easily handled and the occurrence of damage in the semiconductor device can be suppressed. The stiffener 160 is formed by using a part of a metal substrate that serves as a foundation for constructing a multilayer wiring structure. Thereby, the number of parts of the semiconductor device 10 can be reduced and the manufacturing cost can be reduced.

  In the above-described embodiment, a method of mounting a semiconductor chip after forming a stiffener on a semiconductor substrate and separating it into individual pieces is illustrated. However, after the step shown in FIG. Each of the regions may be mounted with a semiconductor chip and further packaged with a sealing resin layer using a transfer molding method, and then separated into individual pieces as in FIG. 6C.

  In the above-described embodiment, the semiconductor chip 30 is flip-chip mounted on the semiconductor substrate 11 by reflow. However, the semiconductor chip 30 may be flip-chip mounted by the method described below.

  First, as shown in FIG. 8A, instead of the C4 bump 27 (see FIG. 5B), a soldered conductive paste 200 is applied to the upper surface of the semiconductor substrate 11. Here, the soldered conductive paste 200 is a paste in which an insulating resin such as epoxy and solder are kneaded.

  Next, as shown in FIG. 8B, after the semiconductor chip 30 is mounted in each region of the semiconductor substrate 11, heat treatment is performed at a temperature at which the solder melts. By the heat treatment, as shown in FIG. 8C, the electrode pad 25 and the solder bump 32 are joined by the solder 210 included in the conductive paste 200. A joint portion by the solder 210 is covered with an insulating resin 212 included in the conductive paste 200.

  According to this, the joint portion by the solder 210 is protected by the insulating resin 212. For this reason, it is suppressed that the joint part by the solder 210 is broken or stressed due to handling during assembly, heat, washing water pressure, and the like. As a result, the multilayer wiring board can be made thinner and narrower.

  The present invention is not limited to the above-described embodiments, and various modifications such as design changes can be added based on the knowledge of those skilled in the art. The form can also be included in the scope of the present invention.

  For example, in the above-described embodiment, the semiconductor chip is flip-chip mounted, but the semiconductor chip may be wire-bonded on the multilayer wiring board.

It is a figure which shows the structure of the semiconductor substrate which concerns on embodiment. It is process drawing which shows the method of manufacturing the semiconductor substrate which concerns on embodiment. It is process drawing which shows the method of manufacturing the semiconductor substrate which concerns on embodiment. It is process drawing which shows the method of manufacturing the semiconductor substrate which concerns on embodiment. It is process drawing which shows the method of manufacturing the semiconductor substrate which concerns on embodiment. It is process drawing which shows the method of manufacturing the semiconductor substrate which concerns on embodiment. It is a figure which shows the structure of the semiconductor device using the semiconductor substrate which concerns on embodiment. It is process drawing which shows the mounting method of a semiconductor chip.

Explanation of symbols

  10 semiconductor device, 11 semiconductor substrate, 24 interlayer insulating film, 25 electrode pad, 26 via plug, 27 C4 bump, 100 metal substrate, 160 stiffener.

Claims (4)

A multilayer wiring layer comprising a plurality of interlayer insulating films and wiring layers;
A stiffener provided in a peripheral portion of the multilayer wiring layer;
With
A semiconductor substrate, wherein the stiffener is formed by selectively removing a metal substrate used as a base for constructing the multilayer wiring layer. A step of constructing each of a plurality of regions on a metal substrate with a multilayer wiring layer interconnected by at least one interlayer insulating film;
Selectively removing the metal substrate such that the metal substrate remains in the peripheral portion of each region;
Dividing each of the multilayer wiring layers into pieces,
A method for manufacturing a semiconductor substrate, comprising: A multilayer wiring layer comprising a plurality of interlayer insulating films and wiring layers;
A stiffener provided in a peripheral portion of the multilayer wiring layer;
A semiconductor chip mounted on the multilayer wiring layer;
With
The semiconductor device, wherein the stiffener is formed by selectively removing a metal substrate used as a base for constructing the multilayer wiring layer. A step of constructing each of a plurality of regions on a metal substrate with a multilayer wiring layer interconnected by at least one interlayer insulating film;
Selectively removing the metal substrate so that the metal substrate remains in a peripheral portion of each region, forming a stiffener in each region, and exposing a multilayer wiring layer in a portion surrounded by each stiffener When,
Mounting each semiconductor chip on the exposed surface of each multilayer wiring layer;
Sealing each multilayer wiring layer and each semiconductor chip with a sealing resin;
Cutting the interlayer insulating film between the regions and the sealing resin, and separating each multilayer wiring layer;
A method for manufacturing a semiconductor device, comprising:

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