JP2008041898A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for semiconductor devices wherein, even with the inferior flatness of a wafer on its outer peripheral side, its flatness is improved by its sucking method up to the extent of making its exposure processing possible to be able to support it horizontally when sucking it. <P>SOLUTION: In the manufacturing method for semiconductor devices, a wall 13 is provided annularly on a base table 11 of a wafer chuck 10. Further, on the front surface of the base table 11 which exists on the inner side than the wall 13, a plurality of supporting pins 14a are so provided as to support the rear surface of a wafer by such supporting pins 14a. Moreover, in addition to this, a negative pressure is applied to the rear surface of the wafer which exists on the inner side than the wall 13 to suck the wafer. Furthermore, in such a suction of the wafer, underside-warp suppressing pins 15a are provided on the front surface of the base table 11 outer than the wall 13 to prevent the underside-warp of the wafer which generates on its outer peripheral side, and to make its exposure processing possible on its outer peripheral side. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor technology, and in particular, is a technology effective when applied to a case where it is necessary to horizontally support a wafer surface in exposure processing or the like.

  The technology described below has been studied by the present inventors in completing the present invention, and the outline thereof is as follows.

  In the manufacture of a semiconductor device, there are many processes for processing while the wafer surface is supported horizontally. Among such processing steps, the horizontal support of the wafer surface is particularly severe in the exposure step. This is because with the miniaturization of the semiconductor chip, the exposure wavelength is shortened and the numerical aperture of the projection lens of the optical system exposure apparatus is increased, and the depth of focus at the time of exposure is reduced accordingly. .

  In Patent Document 1, for the purpose of preventing the wafer outer peripheral side from warping upward, a continuous vertical wall is provided on the outer peripheral edge of the suction stage, and a plurality of protrusions having a small outer diameter are formed on the upper surface of the inner stage of the vertical wall. The structure which provided the processus | protrusion with a large outer diameter so that it may surround was disclosed.

Further, in Patent Document 2, the substrate holding chuck itself is not warped by performing double-sided processing so that the wafer held by the pin contact type substrate holding chuck is not caused by warpage of the single-sided substrate holding chuck. Techniques for doing so are disclosed.
JP-A-6-132387 JP 2000-286330 A

  However, the present inventor has found that the substrate holding technology such as the wafer has the following problems.

  In the exposure step, the reticle pattern is reduced and exposed on the wafer surface in units of a plurality of shots. However, if the flatness on the outer peripheral side of the product wafer is poor, even if it is attracted to the wafer chuck of the conventional exposure apparatus, the levelness is not improved at all. For this reason, a sufficient depth of focus cannot be ensured on the outer peripheral side of the wafer, the focus is out of focus, and the exposure process in that region cannot be performed properly.

  For example, in the range from the wafer outer periphery side to the inside of about 7.5 mm, the wafer level is poor, so that accurate exposure processing cannot be performed, and in general, product acquisition cannot be performed in this range.

  As described above, as described above, the semiconductor chip is required to be miniaturized, the exposure wavelength is shortened, and the numerical aperture of the projection lens of the optical system exposure apparatus is increased. As a result, the depth of focus during exposure becomes shallower. This is a problem that has become apparent.

  The problem caused by the flatness on the outer peripheral side of the product wafer is essentially to improve the flatness of the crystal of the product wafer itself, but the improvement of the product wafer is This raises another quality concern.

  That is, unlike the case where the current product wafer is used as it is, since the flatness of the crystal itself is improved, there is no risk that the quality of the wafer will change and some quality degradation will occur. In addition, there is a risk of increasing the cost of the product wafer. In this way, measures for improving the product wafer itself are not easily accepted because there is a possibility that an unexpected situation may occur in quality or the like.

  Therefore, the present inventor has wondered whether it is possible to cope with the wafer adsorption process without improving the product wafer itself.

  An object of the present invention is to improve the flatness of a wafer with poor flatness on the outer peripheral side by an adsorption method to such an extent that exposure processing is possible, and to enable horizontal support during adsorption.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, in the wafer suction, the outer peripheral side of the wafer is strongly suctioned while preventing downward warping from the horizontal position.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the present invention, the level of the wafer outer peripheral side can be improved to the extent that exposure processing is possible by adsorbing the outer peripheral side of the wafer while preventing downward warping from the horizontal position.

  In the present invention, even when the wafer outer peripheral side is warped, the level of the wafer outer peripheral side can be improved to such an extent that the wafer outer peripheral side can be subjected to exposure processing, so that the number of products acquired in such an area can be improved. It becomes possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof may be omitted.

  The present invention is a technique that can be effectively applied in, for example, exposure processing or the like, in which processing is performed by maintaining the wafer surface horizontal when manufacturing a semiconductor device. The wafer outer peripheral side may not have a good flatness. Even wafers with such low flatness can be processed even during exposure processing that requires strict leveling in relation to the depth of focus by holding the wafer with care so that the wafer outer periphery does not warp. The flatness on the wafer outer peripheral side can be corrected to such an extent.

(Embodiment 1)
FIG. 1 is a plan view schematically showing a configuration of a main part of a wafer chuck to which the present invention is applied. 2A is a cross-sectional view schematically showing a state cut along the line AA in FIG. 1, and FIG. 2B is a cross-sectional view schematically showing a state of the support pin.

  As shown in FIG. 1, the wafer chuck 10 has a circular base 11. As shown in FIG. 2, the base 11 is provided with a suction hole 12 connected to a vacuum pump (not shown) as an adsorbing member. Further, as shown in FIGS. 1 and 2, a circular negative pressure forming wall 13 is provided on the base 11 in a ring shape.

  Inside the wall 13, a plurality of support pins 14a are provided as support members 14 for supporting the wafer so as not to bend from the back surface. For example, the support pins 14a may be provided in a matrix at predetermined intervals.

  The plurality of support pins 14a provided in such a matrix and arranged vertically and horizontally are formed in a truncated cone shape, for example, and are configured so that the wafer back surface can be supported by a small area wafer support surface 14b on the top surface of the trapezoid. ing. As described above, by supporting the back surface of the wafer with the plurality of support pins 14a, it is possible to prevent the wafer support from being uneven due to intervening particles or the like, compared to the case where the entire back surface of the wafer is supported in a large area. be able to.

  In FIG. 1, the support pins 14a are shown only in one row in the diameter direction for the sake of simplicity, and the others are omitted.

  Further, on the base 11, a downward warping suppressing member 15 is provided outside the ring-shaped wall 13 so that the outer peripheral side of the wafer does not warp downward. For example, the downward warpage suppressing member 15 may be configured as a truncated cone-shaped downward warping suppressing pin 15a in the same manner as the support pin 14a.

  A guard member 16 that protects the lower warpage suppression pin 15a is provided on the outer peripheral side of the lower warpage suppression pin 15a. The guard member 16 may have any shape as long as it can protect the lower warp suppressing pin 15a from being broken. In the case shown in FIG. 1, the case where it was formed in the ring shape, for example was shown.

  In this configuration, the wall 13, the support pin 14 a, the downward warping suppression pin 15 a, and the gart member 16 are provided by etching the surface side of the base 11 when forming the base 11. For example, the base 11, the wall 13, the support pin 14a, the downward warping suppressing pin 15a, the gart member 16 and the like are made of alumina ceramic, and the surface of the alumina ceramic is etched and coated with TiN. Good.

  In the wafer chuck 10 configured as described above, most of the portion on the back side of the wafer is supported by the support pins 14 a provided inside the wall 13. In this state, by suctioning and exhausting with a vacuum pump (not shown) from a suction hole 12 as an adsorbing member provided in the base 11, a negative pressure is applied to the back side of the wafer surrounded by the wall 13 and supported by the support pins 14a. The back surface of the wafer is sucked and supported.

  At the time of such suction, the position of the wall 13 is made as close to the outer peripheral side as possible so that the above-mentioned suction support affects the outer peripheral side of the wafer. In this way, the wafer is attracted so that the outer peripheral side of the wafer does not warp at least above the horizontal position.

  However, in the above method, the wafer outer peripheral side can be adsorbed so that it does not warp upward, but if the wafer outer peripheral side is in a downward warped state from the beginning, the tendency of the downward warping may be further promoted. Get up.

  Therefore, in the present invention, the downward warpage suppressing member 15 is provided on the outer peripheral side of the wall 13 to suppress the promotion of the downward warping tendency. For example, the downward warping suppressing member 15 is configured as the downward warping suppressing pin 15a having the same configuration as that of the support pin 14a, thereby suppressing the downward warping tendency of the wafer outer peripheral side and achieving horizontal support on the wafer outer peripheral side.

  Although it is a very simple structure, the effect is remarkably large. For example, even if a wafer with the wafer outer peripheral side warped downward from the beginning is used, the wafer outer peripheral side can be sucked and supported at a horizontal position so that the entire wafer can be secured to the extent that exposure processing is possible. .

  FIG. 3 shows a state in which the wafer W is horizontally sucked and supported by the wafer chuck 10 having such a configuration. In the case shown in FIG. 3, the case where the wall 13 is formed in a ring shape with a passing length of 146.6 mm and the wafer W has a diameter of 150 mm is shown. A plurality of support pins 14a are provided inside the wall 13 at equal intervals of 2.0 mm.

  The downward warping suppression pin 15a is also provided on the outer side of the wall 13 with a distance of 2.0 mm from the outermost support pin 14a. Further, the portion of the lower warp suppression pin 15 a that contacts the back surface of the wafer is provided at a distance of about 0.8 mm from the wall 13.

  As shown in FIG. 3, basically, the lower warpage suppressing pin 15 a may be provided so that the support surface on the back surface of the wafer comes between the outside of the wall 13 and the outer peripheral side of the wafer. In the case shown in FIG. 3, the case where the wafer support surface is provided at the position of about 0.8 mm, which is the substantially central position of such a range, is shown.

  Thus, by using the wafer chuck 10 having the above-described configuration, for example, the wafer outer peripheral side that tends to warp from the beginning can be supported without promoting the tendency to warp downward. This state is shown in FIGS. 4 (a) and 5 (a).

  In FIG. 4A, as shown in FIG. 4B, the level of the suction support is examined in the radial direction AB that does not cover the orientation flat of the wafer W while the wafer W is sucked and supported on the base 11. It is a result. When the lower warpage suppressing pin 15a is provided, the warpage to the lower side of the wafer W is suppressed to about 0.5 μm in the downward direction on both the A end side and the B end side with reference to 0. I understand that

  However, it was confirmed that in the absence of the downward warp suppressing pin 15a, the warp is about 1 μm at the A end side and the warp is about 3 μm downward at the B end side. Thus, when there is no downward warp suppression pin 15a, the outer peripheral side of the wafer W is greatly warped downward, and in this region, the exposure process cannot be performed properly.

  Similarly, in FIG. 5A, the level of the suction support is set in the radial direction CD applied to the orientation flat of the wafer W as shown in FIG. It is the result of investigation. It can be seen that when the downward warp suppressing pin 15a is provided, the downward warping of the wafer W is suppressed to about 1.5 μm on the C end side and about 0.5 μm on the D end side.

  However, it was confirmed that in the absence of the downward warp suppressing pin 15a, the warp was warped downward by about 4 μm at the C end side and by about 1 μm at the D end side.

  Even in such a case, it can be seen that, on the C-end side, when there is no downward warp suppression pin 15a, the downward warping tendency is intense, and as in the case of the AB direction, appropriate exposure processing cannot be performed.

  In FIGS. 4 (a) and 5 (a), the warp conditions on the A-end side and B-end side and the warp conditions on the C-end side and D-end side are extremely different on the left and right end sides. This is an influence due to the deviation of the wafer suction position on the wafer chuck 10 during suction support. However, such a deviation of the wafer position is within a range that can actually occur, and therefore shows raw data as it is.

  As described above, in the wafer chuck 10 having the configuration of the present invention, by providing the downward warp suppressing pin 15a, the downward warping tendency of the outer peripheral side of the wafer W can be suppressed even if the wafer W tends to warp downward from the beginning. It was found that the flatness can be corrected appropriately.

  As described above, the level to the outer peripheral side of the wafer W can be corrected to such an extent that an appropriate exposure process can be performed, so that the number of products acquired in this region can be improved. The effect of the above configuration was verified from the viewpoint of the number of products acquired. For example, as schematically shown in FIG. 6A, it is assumed that shots during exposure are performed seven times in the radial direction not facing the orientation flat. When the conventional wafer chuck 10a is used, in the first and seventh shots, as shown in FIG. 6B, there is a strong tendency to warp on the outer peripheral side of the wafer W. Could not do.

  However, since it is possible to prevent a large downward warp on the outer peripheral side of the wafer W only by providing the downward warp suppressing pin 15a as described above, it is possible to obtain products up to the outer peripheral side of the wafer W. For example, as shown in FIG. 7A, in the conventional wafer W, in the four corner regions, product acquisition cannot be performed due to warpage on the outer peripheral side of the wafer W, and thus no shot is performed in the exposure process.

  However, by using the wafer chuck 10 having the configuration of the present invention, exposure can be appropriately performed up to the outer peripheral side of the wafer. For example, as shown in FIG. In the additional area, it is possible to add shots (indicated by crosses in the figure).

  Until now, it was thought that the exposure process could not be performed properly within the range of about 7.5 mm inside from the outer peripheral side of the wafer. However, as described above, by applying the present invention, appropriate exposure processing can be performed up to the wafer outer peripheral side, so that the number of products acquired can be improved.

  Incidentally, for example, when the chip size is 4 × 5 mm × 1 to 2 mm and the chip size is 4 × 5 mm × 1 to 2 mm, the number of products acquired is smaller than that of the conventional wafer chuck that does not include the downward warp suppression pin 15a. It was confirmed that the wafer per wafer was improved by 5%.

  As described above, the true value of the wafer chuck 10 having such a configuration is particularly remarkable in the exposure process of the photolithography process. Therefore, an example of photolithography process will be described below.

  First, a photoresist film is applied to a wafer to be subjected to photolithography. For example, a photoresist of a photosensitive resin is dropped on a wafer that is vacuum chucked on a rotating support base. The dropped photoresist is made into a thin photoresist film by rotating the wafer at high speed or the like.

  The photoresist film thus formed is transferred to an exposure process, and the reticle pattern is transferred. In this exposure processing step, for example, an exposure apparatus 20 as shown in FIG. 8 is used. The exposure apparatus 20 includes the wafer chuck 10 having the above-described configuration that horizontally supports a wafer W to be exposed.

  The wafer chuck 10 is configured to be freely movable in the horizontal direction by an XY stage 21. On the other hand, in order to transfer the pattern onto the wafer W, a lamp 22 configured as a mercury lamp or the like is provided facing the wafer W. The light emitted from the lamp 22 is configured to irradiate the reticle 24 via the condenser lens 23.

  By irradiating the reticle 24 with light transmitted through the condenser lens 23, the mask pattern drawn on the reticle 24 is reduced and exposed on the wafer W through the reduction lens 25.

  Using the exposure apparatus 20 having such a configuration, for example, an exposure process is performed in a process as shown in FIG. That is, as shown in step S110, a reticle 24 suitable for photolithography processing is prepared on the wafer W, and is transferred to the exposure apparatus 20 side. Thereafter, as shown in step S120, the reticle 24 is aligned, and the reticle 24 is set at an appropriate position.

  After the reticle 24 is set in the exposure apparatus 20, the wafer W is transferred to the exposure apparatus 20 as shown in step S130. In subsequent step S140, the wafer W is roughly aligned. After the rough alignment of the wafer W, the wafer W is set on the wafer chuck 10 in step S150. The wafer W is supported by the wafer chuck 10, and the wafer outer peripheral side is horizontally supported by the downward warpage suppressing pin 15 a so that the tendency of downward warping is suppressed and exposure is possible.

  In this manner, the pattern of the reticle 24 is detected as shown in step S160 in a state in which exposure to the outer peripheral side of the wafer W is performed and the horizontal accuracy is favorably supported.

  Thereafter, as shown in step S170, the wafer W is moved to the first first exposure point in the shot range that can be covered by one exposure process. After the movement, the focus is adjusted in step S180, and exposure processing is performed as shown in step S190. Thereafter, the exposure process is repeated a plurality of times as necessary by step & repeat, a required shot is performed, and the exposure process is terminated as shown in step S200.

  The wafer W for which the exposure process has been completed is unloaded as shown in step S210, and is transferred from the exposure apparatus 20 to the next development process, and the exposure process is completed.

  In the subsequent development processing step, the exposed or non-exposed portion is developed with a developer, and a reduced pattern of the reticle 24 is embodied to form a mask. After performing appropriate cleaning or the like, an etching process or the like may be performed using such a mask.

  Incidentally, as shown in FIGS. 10A and 10B, by using the wafer chuck 10 of the present invention, the width of the fine line pattern formed on the photoresist film is, for example, 0.3 μm wide. be able to. To the extent that such a line width can be formed with an accuracy of ± 0.04 μm, it is possible to horizontally support the outer peripheral side of the wafer.

  For example, as described above, the present invention can be effectively applied when performing an exposure process in the photolithography process in the method for manufacturing a semiconductor device. As a semiconductor device to which the present invention is applied, the present invention can be applied. Can be applied to any semiconductor device as long as the exposure process is included in the manufacturing stage. That is, it does not relate to the type of semiconductor device.

  Therefore, the semiconductor device 100 to which the manufacturing method of the present invention is applied will be described by taking as an example a case where the power MISFET is configured.

That is, as shown in FIG. 11, the power MISFET of the semiconductor device 100 has an impurity (for example, phosphorous) on the main surface side of the n ⁺ type single crystal silicon substrate 101A having the n type conductivity. ) Doped n ⁻ type single crystal silicon layer 101B is epitaxially grown and used as semiconductor substrate 101.

  The semiconductor substrate 101 includes an active cell area ACA in which active cells of the power MISFET are formed, an inactive cell area NCA in which inactive cells are formed, and a gate in which wiring that is electrically connected to the gate electrode of the power MISFET is formed. A wiring region GLA and a termination region FLR in which a field limiting ring is formed are provided.

The n ⁺ type single crystal silicon substrate 101A and the n ⁻ type single crystal silicon layer 101B serve as the drain region of the power MISFET.

A silicon oxide film 103 is formed on the main surface of the n ⁻ type single crystal silicon layer 101B by thermal oxidation. Further, the silicon oxide film 103 and the n ⁻ -type single crystal silicon layer 101B are etched by using the wafer chuck 10 described above as a mask by using the photoresist film patterned by reduction exposure of the reticle by photolithographic processing and development. To do. By this etching, a trench 104 is formed in the active cell region ACA and the inactive cell region NCA, and a trench 105 is formed in the gate wiring region GLA.

  Further, by subjecting the substrate to thermal oxidation treatment, a silicon oxide film 106 is formed on the sidewalls and bottom portions of the trenches 104 and 105 by thermal oxidation treatment of the semiconductor substrate 101, and becomes a gate insulating film of the power MISFET. Next, for example, a polycrystalline silicon film doped with phosphorus is deposited on the silicon oxide film 103 including the inside of the grooves 104 and 105, and the grooves 104 and 105 are filled with the polycrystalline silicon film.

  Subsequently, using the wafer chuck 10 described above, the polycrystalline silicon film is etched using the photoresist film patterned by reduction exposure of the reticle by photolithographic processing and development as a mask, and the polycrystalline silicon film is groove 104. , 105, and the gate electrode 107 of the power MISFET is formed in the trench 104. In addition, a gate extraction electrode 108 is formed in the trench 105.

Further, using the wafer chuck 10 described above as a mask, a photoresist film patterned by reduction exposure of a reticle by photolithographic processing and development is used as a mask.
By etching the silicon oxide film 103 and removing the unnecessary silicon oxide film 103, a field insulating film 103A is formed from the remaining silicon oxide film 103.

Thereafter, a silicon oxide film 109 is deposited on the surface of the n ⁻ type single crystal silicon layer 101B. Subsequently, using the wafer chuck 10 described above as a mask, the photoresist film patterned by reduction exposure of the reticle by photolithographic processing and development is used as a mask.
Impurity ions having p-type conductivity, such as B (boron), are introduced into the n ⁻ -type single crystal silicon layer 101B at a predetermined concentration (first impurity concentration), and the semiconductor substrate 101 is subjected to heat treatment to thereby remove the impurity ions. Spread.

In addition, a p ^- type field limiting ring 110 is formed in the termination region FLR using a photoresist film patterned by reduction exposure of the reticle by photolithographic processing and development using the wafer chuck 10 described above as a mask. To do. Further, a p ^- type semiconductor region (second semiconductor) is formed in the active cell region ACA by using, as another mask, a photoresist film patterned by reduction exposure of the reticle by photolithographic processing and development using the wafer chuck 10 described above. Layer) 111 is formed.

The p ⁻ type semiconductor region 111 becomes a channel layer of the power MISFET after the power MISFET is formed. Further, the p ⁻ type field limiting ring 110 is formed in a region surrounding the active cell region ACA and the inactive cell region NCA in a plurality of ring shapes in a plane.

The p ⁻ type field limiting ring 110 has an end that extends beyond the groove 105 in which the gate lead electrode 108 is formed and reaches a place where the p ⁻ type semiconductor region 111 is formed, and is formed deeper than the bottom of the groove 105. Has been. On the other hand, the p ⁻ type semiconductor region 111 is formed so that the end thereof reaches the side wall of the trench 105 in which the gate extraction electrode 108 is formed, and is formed to a depth that does not reach the bottom of the trenches 104 and 105.

  The field limiting ring is, for example, “Semiconductor Terminology Dictionary” edited by the Semiconductor Terminology Dictionary Editorial Committee, published by Nikkan Kogyo Shimbun Co., Ltd., March 20, 1999, p. As described in U.S. Pat. No. 938, the planar junction of the individual element or IC is surrounded by a ring-shaped junction, and the electric field at the corner portion of the planar junction is relaxed to realize a high breakdown voltage.

Subsequently, an n-type conductivity type impurity ion, for example, As (arsenic) is masked with a photoresist film patterned by reduced exposure of the reticle by photolithographic processing and development by using the wafer chuck 10 described above. As introduced into the semiconductor substrate 101. Thereafter, heat treatment is performed to diffuse the impurity ions, and an n ⁺ type semiconductor region 112 is formed in the p ⁻ type semiconductor region 111 of the active cell region ACA. In addition, an n ⁺ type guard ring region 113 is formed in the n ⁻ type single crystal silicon layer 101B in the termination region FLR.

The n ⁺ type guard ring region 113 is formed so as to surround the p ⁻ type field limiting ring 110 in a plane when the semiconductor substrate 101 is divided into individual semiconductor chips, and has a function of protecting the power MISFET element. .

In this manner, a power MISFET having the n ⁺ type single crystal silicon substrate 101A and the n ⁻ type single crystal silicon layer 101B as a drain region and the n ⁺ type semiconductor region 112 as a source region can be formed.

Thereafter, a PSG (Phospho Silicate Glass) film is deposited, an SOG (Spin On Glass) film is applied on the PSG film, and an insulating film 114 made of the PSG film and the SOG film is formed. Subsequently, using the wafer chuck 10 described above, the insulating film 114 and the n ⁻ -type single crystal silicon layer 101B are etched using the reduced-size exposure of the reticle by photolithography processing and the photoresist film patterned by development as a mask. The contact grooves 115, 116, 117, 118, and 119 are formed.

The contact trench 115 is formed between the adjacent gate electrodes 107 in the active cell region ACA, and is in contact with the n ⁺ type semiconductor region 112 serving as the source region of the power MISFET. Contact trench 116 is formed between adjacent gate electrode 107 and gate extraction electrode 108 in inactive cell region NCA, and is in contact with p ⁻ type semiconductor region 111.

Contact groove 117 is formed in termination region FLR and is in contact with p ⁻ -type field limiting ring 110. Contact groove 118 is formed in termination region FLR and is in contact with n ⁺ -type guard ring region 113. The contact trench 119 is formed in the gate wiring region GLA and reaches the gate lead electrode 108.

Next, impurity ions having p-type conductivity, such as BF ₂ (boron difluoride), are introduced into the bottoms of the contact trenches 115, 116, 117, and 118, and the impurity ions are diffused by subsequent heat treatment, and p ⁺ A type semiconductor region 120 is formed. The p ⁺ type semiconductor region 120 is used to make an ohmic contact with the p ⁻ type semiconductor region 111 or the p ⁻ type field limiting ring 110 at the bottom of the contact trench 115, 116, 117, 118 at the p ⁺ type semiconductor region 120. It is.

  Next, a TiW (titanium tungsten) film is thinly deposited as a barrier conductor film on the insulating film 114 including the inside of the contact trenches 115, 116, 117, 118, and 119 by, for example, sputtering, and then heat treatment is performed. Subsequently, an Al (aluminum) film is deposited on the TiW film by sputtering, for example. Such a barrier conductor film serves to prevent an undesired reaction layer from being formed by contact between Al and the substrate (Si). The Al film means a film containing Al as a main component and may contain other metals.

Subsequently, the TiW film and the Al film are etched by using the wafer chuck 10 described above as a mask by using the photoresist film patterned by reduction exposure of the reticle by photolithographic processing and development, thereby obtaining a gate lead electrode. A gate wiring 121 that is electrically connected to 108 and a source pad (source electrode) 122 that is electrically connected to an n ⁺ type semiconductor region 112 that becomes a source region of the power MISFET are formed.

In addition, p ^- -type field limiting rings 110 ^- type field and one electrically connected limiting rings 110, the source pad 122 electrically connected to the wiring 123, p wiring 123 are electrically connected Are a wiring 124 electrically connected to a different p ⁻ type field limiting ring 110, a wiring 125 electrically connected to the n ⁺ type guard ring region 113, and a gate pad (gate electrode) electrically connected to the gate wiring 121. ) Is also formed.

  As described above, the present invention is applied to, for example, the manufacture of a semiconductor device configured as a MISFET and the formation of a mask by the photolithography process.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above description, the case of the pin contact type has been described as an example, but the configuration in which the downward warp suppressing member is provided can be applied even to an adsorption configuration other than the pin contact type.

  In the above description, the downward warping suppressing means is a pin warping suppressing pin. However, for example, the downward warping suppressing means may be configured in a ring shape. Alternatively, it may be formed in an intermittent ring shape, for example, having an intermediate space, without being provided continuously in a ring shape.

  Also, in the above description, the case where one ring-shaped wall that contributes to the formation of negative pressure when adsorbing the back surface of the wafer has been described, but two or more walls are configured concentrically, and suction is performed corresponding to each of them. You may make it provide a hole. By adopting such a configuration, it is possible to appropriately adjust the suction state on the back surface of the wafer, and to ensure reliable back surface suction.

  In the description of the above embodiment, a case where a wafer whose wafer outer peripheral side tends to warp downward from the beginning has been described. However, even when the wafer outer peripheral side warps upward, the exposure processing can be performed horizontally in the same manner. It can be adsorbed while maintaining the degree.

  Although the present invention has been described as a method for manufacturing a semiconductor device in the appended claims, as described above, a semiconductor manufacturing device, an exposure device, a wafer suction support device, a wafer chuck, and a method for improving the number of product acquisitions, etc. Can be grasped as well.

  The present invention can be used for horizontally supporting a wafer, for example, in manufacturing a semiconductor device, in particular, in an exposure process.

It is a top view which shows typically one Example of the wafer chuck | zipper in one embodiment of this invention. (A) is sectional drawing which shows typically a mode that it cut | disconnected by the AA line of FIG. 1, (b) is a fragmentary sectional view which shows typically the mode of a support pin. It is sectional drawing which shows typically a mode that the wafer was adsorbed and supported. (A) is explanatory drawing which compared the effect in the presence or absence of a downward curvature suppression pin, (b) is the top view which showed the radial direction in the wafer which performed the comparison of (a). (A) is explanatory drawing which compared the effect in the presence or absence of a downward curvature suppression pin, (b) is the top view which showed the radial direction in the wafer which performed the comparison of (a). (A) is the plane explanatory view which showed typically the condition of the exposure shot in a wafer, (b) is sectional drawing which showed the mode of (a) typically. (A) is the top view which showed typically the shot range at the time of exposure in the conventional wafer, (b) is the top view which showed typically the shot range at the time of exposure by application of this invention. It is explanatory drawing which shows typically an example of the exposure apparatus used by this invention. It is the flowchart which showed an example of the procedure in an exposure process. (A) is a partial top view which shows an example which applied the present invention and formed the photoresist film by 0.3 micrometer width, (b) is a fragmentary sectional view. It is sectional drawing which showed typically an example of the structure of the semiconductor device to which this invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Wafer chuck 10a Wafer chuck 11 Base 12 Suction hole 13 Wall 14 Support member 14a Support pin 14b Wafer support surface 15 Bottom warp suppression member 15a Bottom warp suppression pin 20 Exposure device 21 XY stage 22 Lamp 23 Condenser lens 24 Reticle 100 Semiconductor device 101 Semiconductor substrate 101A n ⁺ type single crystal silicon substrate 101B n ⁻ type single crystal silicon layer 103 Silicon oxide film 103A Field insulating film 104 Groove 105 Groove 106 Silicon oxide film 107 Gate electrode 108 Gate extraction electrode 109 Silicon oxide film 110 p ⁻ type field limiting rings 111 p ^- -type semiconductor region 112 n ⁺ -type semiconductor regions 113 n ⁺ -type guard ring region 114 insulating film 115 contact grooves 116 contact trench 117 Ntakuto groove 118 contact grooves 119 contact grooves 120 p ⁺ -type semiconductor region 121 gate wirings 122 the source pad (source electrode)
123 wiring 124 wiring 125 wiring

Claims (5)

A method for manufacturing a semiconductor device comprising a step of horizontally supporting and processing a wafer,
The method for manufacturing a semiconductor device, wherein the horizontal support of the wafer is performed using means for suppressing the outer peripheral side of the wafer from warping below a horizontal position. A method for manufacturing a semiconductor device comprising a step of horizontally supporting and processing a wafer,
The method for manufacturing a semiconductor device, wherein the horizontal support of the wafer is performed by supporting the outer peripheral side of the wafer by a downward warping suppression pin that suppresses downward warping from the horizontal position of the wafer. A method of manufacturing a semiconductor device comprising a step of horizontally supporting a wafer and performing an exposure process,
In the exposure step, the outer peripheral side of the wafer is supported by a downward warping suppressing member that suppresses downward warping from a horizontal position. A method of manufacturing a semiconductor device comprising a step of horizontally supporting a wafer and performing an exposure process,
In the exposure step, the outer peripheral side of the wafer is supported by a downward warpage suppressing member that suppresses downward warping from a horizontal position,
The method of manufacturing a semiconductor device, wherein the lower warpage suppressing member is protected by a guard member provided on an outer edge side of the lower warping suppressing member. A method of manufacturing a semiconductor device comprising a step of horizontally supporting a wafer and performing an exposure process,
In the exposure step, the wafer is adsorbed by an adsorbing member while being supported by a plurality of supporting members,
A method of manufacturing a semiconductor device, wherein the outer peripheral side of the wafer is supported by a lower warpage suppressing member that is provided on the outer edge side of the adsorption member and suppresses the outer peripheral side of the wafer from warping downward from a horizontal position. .