JP2008041022A - I / O device, communication device, servo motor control device, control system and robot system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize a connector between control boards (save wiring) and increase the reliability of signals. <P>SOLUTION: A serial bus primary station board mounted with a CPU for device management and secondary station I/O and other boards each are provided with a parallel-serial conversion circuit. Saving of wiring and miniaturizing the connector are achieved by converting wiring between boards from a parallel bus to a serial bus. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a serial bus system, and more particularly to an I / O device, a communication device, a servo motor control device, and the like provided with the serial bus system.

A general control system can be divided into a system composed of one CPU (central processing unit) and a multi-CPU system composed of a plurality of CPUs.
In a system constituted by one CPU, an I / O device and a memory are accessed through a parallel bus composed of CPU address information, data information, and control signals. In the multi-CPU system, data is transmitted / received to / from each other via a shared RAM.
When configuring these control systems, in order to make the hardware common, consider developing a board for each function (I / O board, communication board, servo board, etc.) and using it for multiple control systems. Yes.

FIG. 11 is a diagram showing an I / O device composed of one CPU. In this figure, reference numeral 1 denotes a CPU board that controls the apparatus. Reference numeral 2 denotes an overall CPU that is mounted on the CPU board and performs control processing of the apparatus. Reference numeral 3 denotes a memory which is mounted on the CPU board and stores programs and data for the central CPU. Reference numeral 4 denotes a parallel bus for the general CPU to access an external device. Reference numeral 5 denotes an input / output (I / O) device, and reference numeral 6 denotes an I / O substrate on which the I / O device is mounted. Reference numeral 7 denotes a connector for connecting the CPU board and the I / O board. Through this connector, a parallel bus composed of the address information, data information, and control signals of the central CPU is connected to the I / O device. Control processing of the O device is performed.
FIG. 12 is a diagram showing a communication apparatus composed of two CPUs. In this figure, 8 is a communication CPU for processing communication data. Reference numeral 9 denotes an LSI for performing communication protocol processing. Reference numeral 10 denotes a shared memory for storing communication processing data. The shared memory is used to exchange data with a central CPU of a CPU board that controls the apparatus. Reference numeral 11 denotes a communication board on which a communication CPU, a communication LSI, and a shared memory are mounted. A parallel bus comprising address information, data information, and control signals of the shared memory of this communication board and the central CPU of the CPU board is connected via a connector, and the central CPU delivers data from the communication board as a communication device. Is being processed.
FIG. 13 is a diagram showing a servo motor control device composed of one CPU. In this figure, 12 is a motor power circuit, and 13 is a servo control circuit for outputting a torque command to the motor power circuit based on a command from the general CPU. Reference numeral 14 denotes a servo board on which a servo control circuit and a motor power circuit are mounted. Reference numeral 15 denotes a motor to which an output from the motor power circuit is connected, and reference numeral 16 denotes a position detection sensor installed in the motor. This position detection sensor signal is fed back to the servo control circuit on the servo board, and the parallel bus consisting of the servo control circuit and the central CPU's address information, data information, and control signal is connected via a connector. Servo control is performed.

Further, unlike the hardware configuration described above, there is a configuration in which a CPU board and an I / O board are connected by serial communication (for example, see Patent Document 1 and Patent Document 2).
FIG. 14 is a diagram illustrating an I / O device that is configured by one CPU and uses serial communication. In this figure, reference numeral 1 denotes a CPU board that controls the apparatus. Reference numeral 2 denotes an overall CPU that is mounted on the CPU board and performs control processing of the apparatus. Reference numeral 3 denotes a memory which is mounted on the CPU board and stores programs and data for the central CPU. A serial I / F circuit 15 converts parallel bus data of the central CPU into serial communication 17. Reference numeral 18 denotes an input / output (I / O) device having a serial I / F, and reference numeral 6 denotes an I / O board on which the I / O device is mounted. The CPU board and the plurality of I / O boards are multi-drop wired via a serial communication line, and the central CPU performs control processing of the I / O device.
Japanese Patent No. 3363603 (page 10, FIG. 1) Japanese Patent No. 2578773 (page 5, FIG. 1)

However, when a parallel bus composed of CPU address information, data information, and control signals is output to a connector and connected to an I / O board or the like, the interface specifications are not compatible in a system employing a different CPU, or the parallel bus is Since there are many signal lines, the size of the connector becomes large and problems such as difficulty in downsizing the system arise. In addition, since many parallel bus pattern wirings are required on the substrate, problems such as increased radiation noise and signal crosstalk occur.
Alternatively, in the case of a system using serial communication as shown in Patent Document 1, since a multi-drop wiring is provided between the CPU board and the I / O board, a plurality of I / O information is transmitted through the serial communication line. become. As a result, it takes a lot of time for serial communication, which causes a problem in performance degradation as a system.
The present invention has been made in view of such problems, and the miniaturization of a connector between a CPU board and an I / O board, a communication board, or a servo board realizes miniaturization as a system, The purpose is to improve communication performance.

In order to solve the above problem, the present invention is configured as follows.
The invention according to claim 1 is equipped with a primary station side parallel-serial conversion circuit that bidirectionally converts a parallel bus that handles address information, data information, and control signals of a CPU that controls the device into a serial bus, and A CPU board in which a serial bus output from a serial conversion circuit is wired to a connector, and a parallel bus that handles address information, data information, and control signals connected to the I / O device are converted into a serial bus bidirectionally 2 And an I / O board on which a serial bus output from the parallel serial conversion circuit is wired to a connector, and the serial bus of each of the CPU board and the I / O board Are connected to each other via a connector, and the CPU processes serial bus communication asynchronously. To have.
According to a second aspect of the present invention, the primary station parallel / serial conversion circuit includes a transmission memory for storing transmission data of a serial bus, and a parallel serial for converting parallel data in the transmission memory into a bit string of the serial bus. A converter, a serial-parallel converter that receives a serial bus bit string and converts it into parallel data, a reception memory that stores the received parallel data, and a frequency-divided clock that can change the setting of the serial bus transmission clock; A bit counter capable of changing the transmission data length of the serial bus, and the secondary station side parallel serial conversion circuit includes a transmission memory for storing transmission data of the serial bus, and a parallel in the transmission memory. A parallel-serial converter that converts data into a serial bus bit string and serial A serial / parallel converter that receives the bit string of the data and converts it into parallel data, a reception memory for storing the received parallel data, and a serial bus transmission clock transmitted from the primary station parallel / serial conversion circuit The transmission / reception circuit operates and includes a bit counter that enables setting and changing the transmission data length of the serial bus, and a switching circuit for switching the access direction of the parallel bus.
According to a third aspect of the present invention, there is provided a parallel serial conversion circuit on the primary station side for bidirectionally converting a parallel bus that handles address information, data information, and control signals of a CPU that controls the device into a serial bus, and the parallel The secondary station side that bi-directionally converts the serial bus output from the serial conversion circuit into a serial bus, and the parallel bus that handles the CPU address information, data information, and control signals of the CPU that performs communication processing with the CPU board A communication board equipped with a parallel-serial conversion circuit and a serial bus output from the parallel-serial conversion circuit wired to a connector, and the serial buses of the CPU board and the communication board are connected to each other via a connector The CPU processes the serial bus communication asynchronously.
According to a fourth aspect of the present invention, the primary station parallel / serial conversion circuit includes a transmission memory for storing transmission data of a serial bus, and a parallel serial for converting parallel data in the transmission memory into a bit string of the serial bus. A converter, a serial-parallel converter that receives a serial bus bit string and converts it into parallel data, a reception memory that stores the received parallel data, and a frequency-divided clock that can change the setting of the serial bus transmission clock; A bit counter capable of changing the transmission data length of the serial bus, and the secondary station side parallel serial conversion circuit includes a transmission memory for storing transmission data of the serial bus, and a parallel in the transmission memory. A parallel-serial converter that converts data into a serial bus bit string and serial A serial / parallel converter that receives the bit string of the data and converts it into parallel data, a reception memory for storing the received parallel data, and a serial bus transmission clock transmitted from the primary station parallel / serial conversion circuit A bit counter that enables the transmission / reception circuit to operate and change the transmission data length of the serial bus,
And a switching circuit for switching the access direction of the parallel bus.
According to a fifth aspect of the present invention, there is provided a parallel serial conversion circuit on the primary station side for bidirectionally converting a parallel bus that handles address information, data information, and control signals of a CPU that controls the device into a serial bus, and the parallel The serial board output from the serial conversion circuit is connected to the CPU board and the parallel serial bus that handles the address information, data information, and control signals of the servo control circuit to the serial bus. A servo board having a conversion circuit and a serial bus output from the parallel-serial conversion circuit wired to a connector; and connecting the serial buses of the CPU board and the servo board to each other via a connector; The CPU processes the serial bus communication asynchronously.
According to a sixth aspect of the present invention, the primary station parallel / serial conversion circuit includes a transmission memory for storing transmission data of the serial bus, and a parallel serial for converting parallel data in the transmission memory into a bit string of the serial bus. A converter, a serial-parallel converter that receives a serial bus bit string and converts it into parallel data, a reception memory that stores the received parallel data, and a frequency-divided clock that can change the setting of the serial bus transmission clock; A bit counter capable of changing the transmission data length of the serial bus, and the secondary station side parallel serial conversion circuit includes a transmission memory for storing transmission data of the serial bus, and a parallel in the transmission memory. A parallel-serial converter that converts data into a serial bus bit string and serial A serial / parallel converter that receives the bit string of the data and converts it into parallel data, a reception memory for storing the received parallel data, and a serial bus transmission clock transmitted from the primary station parallel / serial conversion circuit The transmission / reception circuit operates and includes a bit counter that enables setting and changing the transmission data length of the serial bus, and a switching circuit for switching the access direction of the parallel bus.
According to a seventh aspect of the present invention, a primary station side parallel serial conversion circuit for bidirectionally converting a parallel bus that handles address information, data information, and control signals of a CPU that controls the device into a serial bus is mounted. I / O device connected to each of a plurality of serial buses provided in the primary station side parallel serial conversion circuit in a control system including a CPU board in which a serial bus output from a serial conversion circuit is wired to a connector A communication device and a servo motor control device, wherein the transmission clock and transmission data length of the serial bus can be set and changed.
The invention described in claim 8 is characterized in that the I / O device described in claim 1 is provided.
The invention described in claim 9 is characterized by including the communication device according to claim 3.
According to a tenth aspect of the present invention, the servo motor control device according to the fifth aspect is provided.

According to the first and eighth aspects of the present invention, the pattern wiring design work of the board is achieved by reducing the signal wiring between the CPU board and the I / O board from the parallel bus to the serial bus as in the case of the I / O device. The interface connector for connecting the substrates can be miniaturized. In addition, when this configuration is realized by the conventional technology, a pattern wiring of a large number of parallel buses is necessary for the CPU board. Therefore, by using the present invention, the pattern wiring can be reduced to reduce radiation noise and signals. Problems such as crosstalk can be reduced. Furthermore, by using the serial bus, new processing such as serial bus communication interrupts is not added, and the CPU processing is asynchronous with reading / writing to the I / O device as before. it can.
According to the third and ninth aspects of the invention, the signal wiring between the CPU board having the general CPU constituting the multi-CPU system communication device and the communication board having the communication CPU is reduced from the parallel bus to the serial bus. Thus, the pattern wiring design work of the boards can be facilitated, and the interface connector for connecting the boards can be miniaturized. In addition, when this configuration is realized by the conventional technology, a pattern wiring of a large number of parallel buses is necessary for the CPU board. Therefore, by using the present invention, the pattern wiring can be reduced to reduce radiation noise and signals. Problems such as crosstalk can be reduced. In addition, by using the serial bus, new processing such as serial bus communication interruption is not added, and the processing of the CPU can be performed asynchronously like the I / O device as the processing of the CPU. it can.
According to the inventions as claimed in claims 5 and 10, the signal wiring between the CPU board and the servo board constituting the servo motor control device is reduced from the parallel bus to the serial bus. The interface connector for connecting the substrates can be reduced in size. In addition, when this configuration is realized by the conventional technology, a pattern wiring of a large number of parallel buses is necessary for the CPU board. Therefore, by using the present invention, the pattern wiring can be reduced to reduce radiation noise and signals. Problems such as crosstalk can be reduced. Furthermore, by using the serial bus, new processing such as serial bus communication interruption is not added, and the processing of the CPU can be performed asynchronously as in the case of the I / O device. it can.
According to the invention described in claims 2, 4 and 6, since the memory unit including the transmission memory and the reception memory is mounted in the parallel-serial conversion circuit installed in the primary station and the secondary station, the memory Is used as a shared memory, when a CPU is mounted in a functional block on the secondary station side, a multi-CPU system composed of a plurality of CPUs can be realized. In the parallel-serial conversion circuit on the secondary station side, by switching the direction of the parallel bus, a stand-alone hardware configuration in which no CPU is installed can be realized, and various systems can be supported. From these, by reducing the signal line wiring between the primary station side and the secondary station side of the system from the parallel bus to the serial bus, the pattern wiring design work of the board can be facilitated. The interface connector to be connected can be downsized. Further, since the transmission clock and transmission data length of the serial bus can be variably set, it can be applied to various systems from a system requiring high speed and a large amount of data to a system requiring low speed and a small amount of data. As a result, the use of the parallel-serial conversion circuit in any system can promote the common use of the interface circuit.
According to the seventh aspect of the present invention, since the primary station is provided with a plurality of serial bus interfaces, a system constituted by a single CPU such as an I / O device, a plurality of communication devices such as a communication device. It becomes possible to easily configure a system composed of CPUs.
In addition, since the interface connector for connecting the boards can be made common, it is possible to standardize the interface. Thereby, it becomes possible to improve the customizability of the system.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram of a serial bus system applied to the I / O device of the present invention. In FIG. 1, 1 is a CPU board, 2 is a CPU, 3 is a memory, 4 is a parallel bus of the CPU, 5 is an I / O device, 6 is an I / O board, 100 is a parallel / serial conversion circuit, 101 is a serial bus, A small connector 102 connects the CPU board and the I / O board by a serial bus.

  FIG. 5 shows a parallel-serial conversion circuit on the primary station (CPU board) side of the present invention. In FIG. 5, 200 is a transmission memory, 201 is a parallel-serial converter, 202 is a serial-parallel converter, 203 is a reception memory, 204 is a divided clock circuit for generating a serial bus transmission clock, and 205 is serial bus transmission data. Bit counter for determining length, 300 is serial bus transmission data, 301 is serial bus reception data, 302 is a serial bus transmission clock, 310 is a transmission clock frequency setting value, 311 is a transmission bit length setting value, 312 is a clock, 320 is an address bus, 321 is a data bus, 322 is a write signal WR, 323 is a read signal RD, and 324 is a selection signal CS.

  FIG. 6 shows a parallel-serial conversion circuit on the secondary station (I / O board) side of the present invention. In FIG. 6, 206 is a circuit for switching the direction of the parallel bus, and 325 is a stand-alone mode signal for switching the direction of the parallel bus.

FIG. 9 is a timing chart between the primary station and the secondary station of the present invention.
The difference between the present invention and the conventional parallel bus system is that a parallel-serial conversion circuit for bidirectionally converting the parallel bus into a serial bus is installed between the CPU board and the I / O board, and wiring between the boards is performed with the serial bus. In order to do so, a small connector was installed.
Further, the present invention is different from Patent Document 1 in that the CPU board and the I / O board, the communication board, and the servo board are connected one-to-one.
In addition, the serial bus transmission clock can be variably set by installing a divided clock circuit inside the parallel-serial conversion circuit, and the serial bus transmission bit length can be variably set by installing a bit counter. It is possible to switch the output direction so that the address bus, write signal, read signal, and select signal to the I / O device can be output to the secondary station side by installing a bus switching circuit. is there.

  The configuration shown in FIG. 1 is an I / O device including a CPU board and an I / O board. When writing data from the CPU on the CPU board to the I / O device on the I / O board, the CPU writes the parallel data to the transmission memory inside the parallel-serial conversion circuit. The parallel data is converted from the transmission memory to serial data via the parallel serial converter, output to the serial bus, and transmitted to the parallel serial conversion circuit on the I / O board. Before this serial bus transmission, it is necessary to set the transmission clock frequency and the transmission bit length according to the I / O device. The parallel / serial conversion circuit on the I / O board converts the serial data received from the CPU board into parallel data via the serial / parallel converter, and stores the data in the reception memory. The parallel data of the reception memory is output to the I / O device together with the address bus, the write signal, and the selection signal via the bus direction switching circuit set by the stand-alone mode signal, and the write process is performed.

  On the other hand, in reading data from the I / O board, the parallel data read from the I / O device is taken into the secondary station parallel serial conversion circuit and stored in the transmission memory. The parallel data is converted from the transmission memory to serial data via the parallel-serial converter, output to the serial bus, and transmitted to the parallel-serial conversion circuit on the CPU board. The parallel / serial conversion circuit on the CPU board converts the serial data received from the I / O board into parallel data via the serial / parallel converter, and stores the data in the reception memory. The CPU can read information on the I / O device from the reception memory.

  The timing chart of FIG. 9 will be described. First, it is assumed that the CPU of the CPU board performs control processing by accessing the I / O device asynchronously at the timing of the CPU itself. This indicates that serial bus communication is not transmitted at regular intervals, and that information is transmitted to and received from the I / O device at the access timing required by the CPU. That is, the CPU can access the I / O device asynchronously via the serial bus, just as the CPU accesses the I / O device asynchronously via the parallel bus.

  When transmitting / receiving I / O device information, the CPU writes transmission data to the primary station parallel / serial conversion circuit, and then reads data already received. The CPU starts control processing based on the read data. Next, in the transmission path of the serial bus output from the primary station parallel / serial conversion circuit, the data transmitted by the CPU is received by the secondary station parallel / serial conversion circuit, and the data is converted into parallel data for I / O. Written as device output data. When the CPU is transmitting data, the secondary station parallel-serial conversion circuit reads input data from the I / O device and transmits the data to be received data of the CPU. This data is read from the primary station parallel / serial conversion circuit in the next control process in the CPU.

  According to the above I / O device, the wiring between the CPU board and the I / O board can be made into a serial bus. Thereby, the pattern wiring design work of each board | substrate can be made easy and the interface connector for connecting between board | substrates can be reduced in size.

  FIG. 2 is a block diagram of a serial bus system applied to the communication apparatus of the present invention. In FIG. 2, 1 is a CPU board, 2 is a CPU, 3 is a memory, 4 is a parallel bus of the CPU, 8 is a communication CPU, 9 is a communication LSI, 11 is a communication board, 100 is a parallel-serial conversion circuit, and 101 is a serial. A bus 102 is a small connector for connecting the CPU board and the communication board via a serial bus.

  FIG. 5 shows a parallel-serial conversion circuit on the primary station (CPU board) side of the present invention. In FIG. 5, 200 is a transmission memory, 201 is a parallel-serial converter, 202 is a serial-parallel converter, 203 is a reception memory, 204 is a divided clock circuit for generating a serial bus transmission clock, and 205 is serial bus transmission data. Bit counter for determining length, 300 is serial bus transmission data, 301 is serial bus reception data, 302 is a serial bus transmission clock, 310 is a transmission clock frequency setting value, 311 is a transmission bit length setting value, 312 is a clock, 320 is an address bus, 321 is a data bus, 322 is a write signal WR, 323 is a read signal RD, and 324 is a selection signal CS.

FIG. 7 shows a parallel-serial conversion circuit on the secondary station (communication board) side of the present invention. In FIG. 7, 206 is a circuit for switching the direction of the parallel bus, and 326 is a host mode signal for switching the direction of the parallel bus.
FIG. 10 is a timing chart between the primary station and the secondary station of the present invention.

The difference between the present invention and the conventional parallel bus system is that a parallel-serial conversion circuit for bidirectionally converting the parallel bus into a serial bus is installed between the CPU board and the communication board, and the boards are wired with the serial bus. Is a small connector.
Further, the present invention is different from Patent Document 1 in that the CPU board and the I / O board, the communication board, and the servo board are connected one-to-one.
In addition, the serial bus transmission clock can be variably set by installing a divided clock circuit inside the parallel-serial conversion circuit, and the serial bus transmission bit length can be variably set by installing a bit counter. It is possible to switch the output direction so that an address bus, a write signal, a read signal, and a selection signal can be input from a CPU installed on the secondary station side by installing a bus switching circuit. .

  The configuration shown in FIG. 2 is a communication device including a CPU board and a communication board. When data is transmitted from the CPU of the CPU board to the communication board, the CPU writes the parallel data to the transmission memory inside the parallel-serial conversion circuit. The parallel data is converted from the transmission memory to serial data via the parallel-serial converter, output to the serial bus, and transmitted to the parallel-serial conversion circuit on the communication board. Prior to this serial bus transmission, it is necessary to set the transmission clock frequency and the transmission bit length according to the data transmission / reception speed and data amount with the communication board. The parallel / serial conversion circuit of the communication board converts the serial data received from the CPU board into parallel data via the serial / parallel converter, and stores the data in the reception memory. The parallel data in the reception memory is read by inputting the address bus, write signal, and selection signal from the communication CPU via the bus direction switching circuit set by the host mode signal. The data is written into the communication LSI and communication processing is performed outside the substrate.

  On the other hand, in the data reading from the communication board, the parallel data read from the communication LSI by the communication CPU is taken into the secondary station side parallel serial conversion circuit and stored in the transmission memory. The parallel data is converted from the transmission memory to serial data via the parallel-serial converter, output to the serial bus, and transmitted to the parallel-serial conversion circuit on the CPU board. The parallel / serial conversion circuit on the CPU board converts the serial data received from the communication board into parallel data via the serial / parallel converter, and stores the data in the reception memory. The CPU can read information from the communication board from the reception memory.

  The timing chart of FIG. 10 will be described. First, it is assumed that the CPU of the CPU board performs control processing by accessing the communication CPU side asynchronously at the timing of the CPU itself. This indicates that the serial bus communication is not transmitted at regular intervals, and that information is transmitted to and received from the communication CPU side at the access timing required by the CPU. That is, it is possible to access the communication CPU side asynchronously via the serial bus, just as the CPU accesses the communication CPU side asynchronously via the parallel bus.

  When transmitting / receiving information on the communication CPU side, the CPU writes transmission data to the primary station parallel / serial conversion circuit, and then reads data already received. The CPU starts control processing based on the read data. Next, in the serial bus transmission line output from the primary station parallel serial conversion circuit, the data transmitted by the CPU is received by the secondary station parallel serial conversion circuit, and the data is converted into parallel data and transmitted to the communication CPU. It is read and processed for communication. The data received by the communication CPU from the external communication is written in the secondary station parallel / serial conversion circuit, and the data is transmitted so as to become the received data of the CPU. This data is read from the primary station parallel / serial conversion circuit in the next control process in the CPU.

  According to the above communication device, the wiring between the CPU board and the communication board can be made into a serial bus. Thereby, the pattern wiring design work of each board | substrate can be made easy and the interface connector for connecting between board | substrates can be reduced in size.

  FIG. 3 is a block diagram of a serial bus system applied to the servo motor control apparatus of the present invention. In FIG. 3, 1 is a CPU board, 2 is a CPU, 3 is a memory, 4 is a parallel bus, 12 is a motor power circuit, 13 is a servo control circuit, 14 is a servo board, 15 is a motor, 16 is a position detection sensor, 100 Is a parallel-serial conversion circuit, 101 is a serial bus, and 102 is a small connector for connecting the CPU board and the communication board via the serial bus.

  FIG. 5 shows a parallel-serial conversion circuit on the primary station (CPU board) side of the present invention. In FIG. 5, 200 is a transmission memory, 201 is a parallel-serial converter, 202 is a serial-parallel converter, 203 is a reception memory, 204 is a divided clock circuit for generating a serial bus transmission clock, and 205 is serial bus transmission data. Bit counter for determining length, 300 is serial bus transmission data, 301 is serial bus reception data, 302 is a serial bus transmission clock, 310 is a transmission clock frequency setting value, 311 is a transmission bit length setting value, 312 is a clock, 320 is an address bus, 321 is a data bus, 322 is a write signal WR, 323 is a read signal RD, and 324 is a selection signal CS.

FIG. 6 shows a parallel-serial conversion circuit on the secondary station (servo substrate) side of the present invention. In FIG. 6, 206 is a circuit for switching the direction of the parallel bus, and 325 is a stand-alone mode signal for switching the direction of the parallel bus.
The difference between the present invention and the conventional parallel bus system is that a parallel / serial conversion circuit for bidirectionally converting the parallel bus into a serial bus is installed between the CPU board and the servo board, and wiring between the boards is performed by the serial bus. Is a small connector.

Further, the present invention is different from Patent Document 1 in that the CPU board and the I / O board, the communication board, and the servo board are connected one-to-one.
In addition, the serial bus transmission clock can be variably set by installing a divided clock circuit inside the parallel-serial conversion circuit, and the serial bus transmission bit length can be variably set by installing a bit counter. It is possible to switch the output direction so that the secondary station can output the address bus, write signal, read signal, and select signal to the servo control circuit by installing a bus switching circuit. is there.

  The configuration shown in FIG. 3 is a servo motor control device including a CPU substrate and a servo substrate. When data is transmitted from the CPU of the CPU board to the servo board, the CPU writes the parallel data to the transmission memory inside the parallel-serial conversion circuit. The parallel data is converted from the transmission memory to serial data via the parallel-serial converter, output to the serial bus, and transmitted to the parallel-serial conversion circuit on the servo board. Prior to the serial bus transmission, it is necessary to set the transmission clock frequency and the transmission bit length in accordance with the data transmission / reception speed and data amount with the servo board. The parallel / serial conversion circuit of the servo board converts serial data received from the CPU board into parallel data via a serial / parallel converter, and stores the data in the reception memory. Parallel data in the reception memory is written by outputting the address bus, write signal, and selection signal to the servo control circuit via the bus direction switching circuit set by the stand-alone mode signal, and the servo control processing is performed. Done. The torque command output from the servo control circuit is input to the motor power circuit for power conversion, and then output to the motor. The position detection sensor information installed in the motor is fed back to the servo control circuit to control the servo motor.

  On the other hand, in the data reading from the servo board, the parallel data read from the servo control circuit is taken into the secondary station side parallel serial conversion circuit and stored in the transmission memory. The parallel data is converted from the transmission memory to serial data via the parallel-serial converter, output to the serial bus, and transmitted to the parallel-serial conversion circuit on the CPU board. The parallel / serial conversion circuit on the CPU board converts the serial data received from the servo board into parallel data via the serial / parallel converter, and stores the data in the reception memory. The CPU can read information from the servo board from the reception memory. These write and read processing timings are performed at the same timing as that of the I / O device of FIG.

It can be performed asynchronously at a timing required by the CPU.
According to the servo motor control device, the wiring between the CPU board and the servo board can be converted into a serial bus. Thereby, the pattern wiring design work of each board | substrate can be made easy and the interface connector for connecting between board | substrates can be reduced in size.

  FIG. 4 is a diagram showing the configuration of the fourth embodiment. In the fourth embodiment, a configuration in which the first to third embodiments are combined is shown. FIG. 8 shows a circuit in which a plurality of parallel-serial conversion circuits used on the primary station side are combined, and is a circuit used in the primary station of FIG.

The configuration shown in FIG. 4 is a control system in which an I / O board, a communication board, and a servo board are connected to one CPU board. When this configuration is performed by the prior art, a large number of parallel bus pattern wirings are required on the CPU substrate, which causes an increase in design man-hours and problems such as radiation noise and signal crosstalk. However, by installing a parallel-serial conversion circuit and converting the wiring of each board from a parallel bus to a serial bus, the pattern wiring on the CPU board can be greatly reduced, making the pattern wiring design work easier The interface connector for connecting the substrates can be miniaturized.
In addition, the CPU of the CPU board asynchronously accesses each board via the parallel-serial conversion circuit at a timing when command data is transmitted to each board or when response data is obtained from each board. This asynchronous access avoids interrupt processing from a plurality of boards to the CPU, reduces an increase in processing load on the CPU, and can improve system performance.

  According to the present invention, an ultra-small robot system can be realized by configuring a system including a plurality of control boards with a serial bus.

The block diagram of the serial bus system which shows 1st Example of this invention Configuration diagram of a serial bus system showing a second embodiment of the present invention The block diagram of the serial bus system which shows 3rd Example of this invention The block diagram of the serial bus system which shows 4th Example of this invention The block diagram which shows the primary station side parallel serial conversion circuit of this invention The block diagram which shows the parallel serial conversion circuit at the time of the secondary station side of this invention in stand-alone mode The block diagram which shows the parallel serial conversion circuit at the time of the secondary station side of this invention in host mode The block diagram which shows the parallel serial conversion circuit in case the primary station side of this invention is comprised from the some parallel serial conversion circuit Timing chart of serial bus system showing first embodiment of the present invention Timing chart of serial bus system showing second embodiment of the present invention Configuration diagram of I / O device showing first conventional example Configuration diagram of communication apparatus showing second conventional example Configuration diagram of servo motor control apparatus showing third conventional example Configuration diagram of I / O device showing conventional fourth embodiment

Explanation of symbols

1 CPU board 2 CPU
3 Memory 4 Parallel bus 5 I / O device 6 I / O board 7 Connector 8 Communication CPU
9 Communication LSI
DESCRIPTION OF SYMBOLS 10 Shared memory 11 Communication board 12 Motor power circuit 13 Servo control circuit 14 Servo board 15 Motor 16 Position detection sensor 17 Serial communication 18 Serial IF circuit 100, 100a, 100b, 100c Parallel serial conversion circuit 101 Serial bus 102 Small connector 200 Transmission memory 201 Parallel Serial Converter 202 Serial Parallel Converter 203 Reception Memory 204 Divided Clock 205 Bit Counter 206 Bus Direction Switching Circuit 300 Serial Bus Transmission Data 301 Serial Bus Reception Data 302 Serial Bus Transmission Clock 310 Transmission Clock Setting Value 311 Transmission Bit Length Setting Value 312 Clock 320 Address bus 321 Data bus 322 Write signal WR
323 Read signal RD
324 Selection signal CS
325 Stand-alone mode signal 326 Host mode signal

Claims (10)

A serial bus that is equipped with a primary station side parallel serial conversion circuit that bidirectionally converts a parallel bus that handles address information, data information, and control signals of a CPU that controls the device into a serial bus, and is output from the parallel serial conversion circuit A CPU board wired to the connector;
Equipped with a secondary station side parallel serial conversion circuit that converts the parallel bus that handles address information, data information, and control signals connected to the I / O device into a serial bus bidirectionally, and is output from the parallel serial conversion circuit An I / O board with a serial bus wired to the connector,
An I / O device characterized in that serial buses of the CPU board and the I / O board are connected to each other via a connector, and the CPU processes serial bus communication asynchronously. The primary station parallel-serial conversion circuit includes a transmission memory for storing transmission data of a serial bus,
A parallel-serial converter that converts parallel data in the transmission memory into a bit string of a serial bus; and
A serial-parallel converter that receives a serial bus bit string and converts it into parallel data;
A reception memory for storing the received parallel data;
A frequency-divided clock that allows the serial bus transmission clock to be changed, and
A bit counter capable of changing the transmission data length of the serial bus, and
The secondary station side parallel-serial conversion circuit includes a transmission memory for storing transmission data of a serial bus,
A parallel-serial converter that converts parallel data in the transmission memory into a bit string of a serial bus; and
A serial-parallel converter that receives a serial bus bit string and converts it into parallel data;
A reception memory for storing the received parallel data;
A bit counter that allows a transmission / reception circuit to operate with a serial bus transmission clock transmitted from the primary station side parallel serial conversion circuit, and to change the transmission data length of the serial bus;
The I / O device according to claim 1, further comprising: a switching circuit for switching an access direction of the parallel bus. Equipped with a primary station side parallel serial conversion circuit that bi-directionally converts a parallel bus that handles the address information, data information, and control signals of the CPU that controls the device into a serial bus, and is output from the parallel serial conversion circuit A CPU board to which the connector is wired;
Equipped with a secondary station side parallel serial conversion circuit that bi-directionally converts the parallel bus that handles communication processing CPU address information, data information, and control signals into a serial bus, and the serial bus output from the parallel serial conversion circuit A communication board wired to the connector,
A serial communication device, wherein serial buses of the CPU board and the communication board are connected to each other via a connector, and the CPU processes serial bus communication asynchronously. The primary station parallel-serial conversion circuit includes a transmission memory for storing transmission data of a serial bus,
A parallel-serial converter that converts parallel data in the transmission memory into a bit string of a serial bus; and
A serial-parallel converter that receives a serial bus bit string and converts it into parallel data;
A reception memory for storing the received parallel data;
A frequency-divided clock that allows the serial bus transmission clock to be changed, and
A bit counter capable of changing the transmission data length of the serial bus, and
The secondary station side parallel-serial conversion circuit includes a transmission memory for storing transmission data of a serial bus,
A parallel-serial converter that converts parallel data in the transmission memory into a bit string of a serial bus; and
A serial-parallel converter that receives a serial bus bit string and converts it into parallel data;
A reception memory for storing the received parallel data;
A bit counter that allows a transmission / reception circuit to operate with a serial bus transmission clock transmitted from the primary station side parallel serial conversion circuit, and to change the transmission data length of the serial bus;
The communication apparatus according to claim 3, further comprising a switching circuit for switching an access direction of the parallel bus. Equipped with a primary station side parallel serial conversion circuit that bi-directionally converts a parallel bus that handles the address information, data information, and control signals of the CPU that controls the device into a serial bus, and is output from the parallel serial conversion circuit A CPU board wired to the connector;
Equipped with a secondary station side parallel serial conversion circuit that converts the parallel bus handling address information, data information, and control signals of the servo control circuit into a serial bus bidirectionally, and the serial bus output from the parallel serial conversion circuit is a connector And a servo board wired to
A servo motor control apparatus, wherein serial buses of the CPU board and the servo board are connected to each other via a connector, and the CPU processes serial bus communication asynchronously. The primary station parallel-serial conversion circuit includes a transmission memory for storing transmission data of a serial bus,
A parallel-serial converter that converts parallel data in the transmission memory into a bit string of a serial bus; and
A serial-parallel converter that receives a serial bus bit string and converts it into parallel data;
A reception memory for storing the received parallel data;
A frequency-divided clock that allows the serial bus transmission clock to be changed, and
A bit counter capable of changing the transmission data length of the serial bus, and
The secondary station side parallel-serial conversion circuit includes a transmission memory for storing transmission data of a serial bus,
A parallel-serial converter that converts parallel data in the transmission memory into a bit string of a serial bus; and
A serial-parallel converter that receives a serial bus bit string and converts it into parallel data;
A reception memory for storing the received parallel data;
A bit counter that allows a transmission / reception circuit to operate with a serial bus transmission clock transmitted from the primary station side parallel serial conversion circuit, and to change the transmission data length of the serial bus;
6. The servo motor control device according to claim 5, further comprising a switching circuit for switching the access direction of the parallel bus. Equipped with a primary station side parallel serial conversion circuit that bi-directionally converts a parallel bus that handles the address information, data information, and control signals of the CPU that controls the device into a serial bus, and is output from the parallel serial conversion circuit In a control system comprising a CPU board wired to a connector,
An I / O device connected to a plurality of serial buses provided in the primary station side parallel serial conversion circuit, a communication device, and a servo motor control device;
A control system, wherein the transmission clock and transmission data length of the serial bus can be changed. A robot system comprising the I / O device according to claim 1. A robot system comprising the communication device according to claim 3. A robot system comprising the servo motor control device according to claim 5.

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