JP2008040691A - Clock duty automatic correction circuit and clock duty automatic correction method using the same - Google Patents

Abstract

To accurately measure and automatically correct the duty of a clock signal without using an external signal.
A semiconductor device includes a clock duty automatic correction circuit and a PLL circuit. The clock duty automatic correction circuit 1 includes a clock measurement unit 11, a clock duty specifying unit 12, and a clock generation unit 13, and receives a pre-correction clock signal CLKA output from the PLL circuit 2 and having a changed duty ratio. The duty of the clock signal CLKA before correction is measured by the clock measuring unit 11 and the duty is specified by the clock duty specifying unit 12. Based on the clock switching signal S _CLKS2 and the delay selection signal S _DS2 output from the clock duty specifying unit 12, the clock generation unit 13 automatically corrects the duty ratio of the pre-correction clock signal CLKA without using an external signal. Is called.
[Selection] Figure 1

Description

  The present invention relates to a technique for measuring and correcting a duty of a clock signal.

  In a semiconductor device such as a digital LSI or SoC (System On a Chip), various clock supply circuits are used, and a PLL (Phase Locked Loop) circuit (also called a frequency multiplier circuit) or a DLL (Delay locked Loop) circuit is used. It is used a lot. In recent years, with the progress of miniaturization and higher integration of semiconductor elements, the frequency of clock signals output from clock supply circuits has increased, and the frequency and duty of clock signals have been increased due to changes in circuit thresholds due to manufacturing variations. Variations may occur. For this reason, it is important to measure and correct the frequency and duty of the clock signal with high accuracy. As the duty measurement, a highly accurate measurement of the duty is performed using an external sampling clock signal having a frequency several times larger than that of the clock signal (see, for example, Patent Document 1).

In the duty measurement of a clock signal described in Patent Document 1 or the like, there is a problem that the duty cannot be measured only by a signal generated inside the semiconductor device. In the case of a state-of-the-art digital LSI or SoC, there is a problem that a higher-speed external sampling clock signal is required because the clock signal has a higher frequency. And there is a problem that the duty cannot be corrected. In addition, the circuit configuration becomes complicated in order to perform highly accurate duty measurement and correction. If these circuits are provided in a semiconductor device, the cost of the semiconductor device increases, while these circuits are provided outside the semiconductor device. However, there is a problem that the evaluation cost increases.
JP 2001-124813 A (Page 13, FIG. 1 and Page 14, FIG. 2)

  The present invention provides a clock duty automatic correction circuit capable of accurately measuring and automatically correcting the duty of a clock signal without using an external signal, and a clock duty automatic correction method using the clock duty automatic correction circuit.

  In order to achieve the above object, an automatic clock duty correction circuit according to one embodiment of the present invention includes a second clock signal having a high level period or a low level period shorter than the first clock signal having a duty ratio of 50% and 50%. And a plurality of first delay means having different delay times for delaying the second clock signal, and selected from the plurality of first delay means immediately after the output signal changes. A clock measuring unit that uses the first delay time of the delay means as the duty of the second clock signal, and the duty of the second clock signal is specified based on the output signal output from the clock measuring unit. A clock duty specifying unit that generates a delay selection signal and a delay time for inputting the second clock signal and delaying the second clock signal are different. The first delay time is subtracted from the time of the duty ratio of 50% of the first clock signal based on the delay selection signal output from the clock duty specifying unit. A delay unit having a second delay time corresponding to the determined value is selected from the plurality of second delay units, and the duty of the second clock signal is automatically corrected using the second delay time. And a clock generation unit.

  Furthermore, in order to achieve the above object, a clock duty automatic correction method using a clock duty automatic correction circuit according to one aspect of the present invention includes a clock duty measurement unit, a clock duty specifying unit, and a clock generation unit. A clock duty automatic correction method using a circuit, wherein a second clock signal having a High level period or a Low level period shorter than a first clock signal having a duty ratio of 50% and 50% is used as the clock measuring unit and the clock. A step of inputting to the measuring unit; selecting one of a plurality of first delay circuits provided in the clock measuring unit; delaying the second clock signal by the selected delay circuit; and Immediately after the output signal of the measurement unit changes from Low level to High level, The first delay time of the delay circuit selected from among the delay circuits is set as the duty of the second clock signal, and the output signal output from the clock measuring unit is input to the clock duty specifying unit. Generating a delay selection signal for specifying a duty of the second clock signal based on the output signal; inputting the second clock signal and the delay selection signal to the clock generation unit; and A time with a duty ratio of 50% of the first clock signal based on the delay selection signal from among a plurality of second delay circuits having different delay times for delaying the second clock signal provided in the generation unit. A delay circuit having a second delay time corresponding to a value obtained by subtracting the first delay time from the first delay time is selected, and the second delay time is used to select the first delay circuit. Characterized by the including the step of automatically correcting the duty of the clock signal.

  According to the present invention, it is possible to accurately measure and automatically correct the duty of a clock signal without using an external signal.

  Embodiments of the present invention will be described below with reference to the drawings.

  A clock duty automatic correction circuit and a clock duty automatic correction method using the same according to Embodiment 1 of the present invention will be described with reference to the drawings. 1 is a block diagram showing a configuration of a semiconductor device, FIG. 2 is a block diagram showing a clock measurement unit, FIG. 3 is a block diagram showing a clock duty specifying unit, and FIG. 4 is a block diagram showing a clock generation unit. In this embodiment, an automatic clock duty correction circuit is provided in a semiconductor device as a SoC (System On a Chip).

  As shown in FIG. 1, the semiconductor device 30 is provided with a clock duty automatic correction circuit 1 and a PLL circuit 2, and based on the corrected clock signal CLKC output from the clock duty automatic correction circuit 1, Internal circuit operates.

  The clock duty automatic correction circuit 1 includes a clock measurement unit 11, a clock duty specifying unit 12, and a clock generation unit 13. The clock duty automatic correction circuit 1 is output from the PLL circuit 2 and has a duty ratio of 50% due to, for example, circuit threshold change due to manufacturing variations. The pre-correction clock signal CLKA having a changed duty ratio is input to the ideal clock signal CLK of 50%. Then, the clock duty automatic correction circuit 1 measures the pre-correction clock signal CLKA and outputs the post-correction clock signal CLKC automatically corrected to the duty ratio of 50% and 50%. Here, the frequency of the pre-correction clock signal CLKA output from the PLL circuit 2 is a high-speed signal, for example, 800 MHz.

  As shown in FIG. 2, the clock measurement unit 11 includes a delay circuit DA0, a delay circuit DA1,... A delay circuit DAn, an XOR circuit EX1, flip-flops FF1 to FF3, an inverter INV1, an inverter INV2, a selector SEL1, and a selector SEL2. It is composed of

The inverter INV2 receives the pre-correction clock signal CLKA and outputs the inverted signal to the selector SEL2. The selector SEL2 receives the pre-correction clock signal CLKA and its inverted signal, selects any signal based on the clock switching signal S _CLKS1 output from the clock duty specifying unit 12, and outputs it as the pre-correction clock signal CLKB. .

The flip-flop FF1 with a reset function is provided between the selector SEL2 and the delay circuit DA0, the delay circuit DA1,... Delay circuit DAn, and inputs the pre-correction clock signal CLKB as a clock, and the output signal is output from the inverter INV1. The inverted signal is input again as data. The flip-flop FF1 latches data when the pre-correction clock signal CLKB rises. The flip-flop FF1 with a reset function receives a reset signal and outputs a signal A according to the signal level of the reset signal. Here, the signal A is output to the clock duty specifying unit 12 as a control clock signal S _SCLK signal.

  Delay circuit DA0, delay circuit DA1,... Delay circuit DAn are n delay circuits DA provided in parallel between reset function flip-flop FF1 and selector SEL1, and having different delay times. It serves to delay the signal A output from the FF1 for a predetermined period. Here, the delay circuit DA0, the delay circuit DA1,... Delay circuit DAn are first delay means.

  Here, for the delay circuits DA0 to DAn, for example, an inverter chain having an inverter as a minimum delay unit is preferably used. The number of inverters constituting the inverter chain is preferably set to an even number. The delay time of the delay circuits DA0 to DAn is calculated using, for example, SPICE (Simulation Program with Integrated Circuit Emphasis) which is a circuit simulator from device data or data obtained from TEG (Test Element Group) evaluation. May be used. Note that the delay times of the XOR circuit EX1, the flip-flops FF1 to FF3, the inverter INV1, the inverter INV2, the selector SEL1, and the selector SEL2 provided in the clock measurement unit 11 are sufficiently shorter than the delay times of the delay circuits DA0 to DAn. It is preferable to set.

The selector SEL1 is provided between the delay circuit DA0 through DAn and the flip-flop FF3, enter the delay selection signal _{S DS1} outputted from the clock duty specifying unit 12, a delay circuit DA0 to on the basis of the delay selection signal _{S DS1} One of DAn is selected, and a signal AD delayed by a predetermined time from the signal A is output.

  The flip-flop FF2 is provided between the flip-flop FF1 and the XOR circuit EX1, inputs the uncorrected clock signal CLKB as a clock, latches the signal A data when the uncorrected clock signal CLKB falls, and outputs the signal B To do.

  The flip-flop FF3 is provided between the selector SEL1 and the XOR circuit EX1, inputs the uncorrected clock signal CLKB as a clock, latches the signal AD data when the uncorrected clock signal CLKB falls, and outputs the signal C .

XOR circuit EX1 receives the signal C outputted from the signal B and the flip-flop FF3 is outputted from the flip-flop FF2, and outputs a measurement result output signal S _SK which logical operation to the clock duty specifying unit 12. This measurement result output signal _SSK is used for duty measurement.

  Here, when the signal level of the signal B of the flip-flop FF2 and the signal level of the signal C of the flip-flop FF3 are different, the XOR circuit EX1 outputs a “High” level signal and the signal B of the signal of the flip-flop FF2 When the level and the signal level of the signal B of the flip-flop FF3 are the same, a “Low” level signal is output. Note that the XOR circuit is also referred to as an Exclusive-OR circuit, an EX-OR circuit, or an Ex-OR.

  As shown in FIG. 3, the clock duty specifying unit 12 is provided with a rising cycle detecting unit 21, a synchronous counter DCN, and a loaded flip-flop LFF1.

  The rising cycle detection unit 21 is provided with a flip-flop FF4 and a two-input AND circuit AND1.

The flip-flop FF4 receives the control clock signal S _SCLK output from the clock measurement unit 11 as a clock, and outputs a measurement result output from the XOR circuit EX1 of the clock measurement unit 11 when the control clock signal S _SCLK falls. The data of the signal _SSK is latched.

2-input AND circuit AND1 is provided between the flip-flops FF4 and loaded with flip-flop LFF1, inputs a signal obtained by inverting the signal output from the flip-flop FF4 and the measurement result output signal S _SK, in the logical operation signal and it outputs a certain rise cycle detection signal _{S TAC} loaded with flip-flop LFF1. Here, the rising cycle detection signal S _TAC is a signal for detecting a rising cycle when the measurement result output signal S _SK becomes the “High” level.

The synchronous counter DCN receives the control clock signal S _SCLK output from the clock measuring unit 11 as a clock, and outputs a signal that has been up-counted in synchronization with the counter control signal S _CNS . Among the plurality of signals output from the synchronous counter DCN, signal topmost Bit is used as a clock switching signal _{S CLKS1,} the remaining signal is used as a delay selection signal _{S DS1.} The clock switching signal S _CLKS1 and the delay selection signal S _DS1 are output to the clock measuring unit 11.

The load flip-flop LFF1 receives the control clock signal S _SCLK output from the clock measuring unit 11 as a clock, and the signal level of the rising cycle detection signal S _TAC changes from “Low” level to “High” level (enable signal). When the control clock signal S _SCLK rises, the data of the signal output from the synchronous counter DCN is latched. Among the plurality of signals output from the load with the flip-flop LFF1, signal topmost Bit is used as a clock switching signal _{S CLKS2,} the remaining signal is used as a delay selection signal _{S DS2.} The clock switching signal S _CLKS2 and the delay selection signal S _DS2 are input to the clock generation unit 13.

  As shown in FIG. 4, the clock generator 13 includes a delay circuit DB0, a delay circuit DB1,... Delay circuit DBn, a 2-input AND circuit AND2, a 2-input OR circuit OR1, a selector SEL3, and a selector SEL4. N delay circuits DA having different delay times are provided.

  The delay circuit DB0, the delay circuit DB1,... Delay circuit DBn (second delay means) each receive the pre-correction clock signal CLKA and delay the pre-correction clock signal CLKA for a predetermined time. The delay circuit DB0, delay circuit DB1,... Delay circuit DBn are second delay means.

  Here, for example, an inverter chain having an inverter as a minimum delay unit is preferably used for the delay circuit DB0, the delay circuit DB1,. The number of inverters constituting the inverter chain is preferably set to an even number. The delay circuit DB0, delay circuit DB1,... Delay time calculation method of the delay circuit DBn is, for example, calculated from device data using SPICE, which is a circuit simulator, or using data obtained from TEG evaluation. May be. Note that the delay times of the two-input AND circuit AND2, the two-input OR circuit OR1, the selector SEL3, and the selector SEL4 provided in the clock generation unit 13 should be set sufficiently shorter than the delay times of the delay circuits DB0 to DBn. preferable.

The selector SEL3, the delay circuits DB0 to provided between DBn and 2-input OR circuit OR1 and two-input AND circuit AND2, enter the delay selection signal _{S DS2,} the delay circuit DA0 through DAn based on the delay selection signal _{S DS2} And outputs a signal D delayed by a predetermined time from the pre-correction clock signal CLKA.

  The 2-input OR circuit OR1 is provided between the selectors SEL3 and SEL4, receives the pre-correction clock signal CLKA and the signal D, and outputs a logically calculated signal E. Here, the signal E becomes “Low” level when the pre-correction clock signal CLKA and the signal D are “Low” level, and otherwise becomes “High” level.

  The 2-input AND circuit AND2 inputs the pre-correction clock signal CLKA and the signal D, and outputs a signal F obtained by logical operation. Here, the signal F becomes “High” level when the pre-correction clock signal CLKA and the signal D are “High” level, and becomes “Low” level otherwise.

  The selector SEL4 receives the clock switching signal SCLKS2, selects either the signal E or the signal F based on the clock switching signal SCLKS2, and receives the corrected clock signal CLKC automatically corrected to a duty ratio of 50% and 50%. Output.

  Next, the operation of the clock duty automatic correction circuit will be described with reference to FIGS. 5 to 9. FIG. 5 is a diagram showing the relationship between the duty of the clock signal and the delay time of the delay circuit, and FIG. 6 is the delay time of the delay circuit. FIG. 7 is a diagram showing switching between the “High” level period and the “Low” level period of the clock signal in the duty measurement / correction, and FIG. 7A shows the correction of the “High” level period. FIG. 7B is a diagram illustrating correction of the “Low” level period, FIG. 8 is a timing chart illustrating the operation of the clock duty automatic correction circuit using the “High” level period of the clock signal, and FIG. 6 is a timing chart showing the operation of the clock duty automatic correction circuit using the “Low” level period of FIG.

As shown in FIG. 5, the ideal clock signal CLK has a duty of 50% for the “High” level period TH, a duty of 50% for the “Low” level period TL, and TH = TL. For the known clock signal CLK, the sum of the delay time T _DA of the delay circuit _DA and the delay time T _DB of the delay circuit DB is
TL, TH (50%) = T _DA + T _DB ... (1)
And set. Here, the sum is the “Low” level period TL.

As shown in FIG. 6, in the delay circuit DA, the delay time T _DAn of the delay circuit DAn is maximized, the delay time is gradually decreased, and the delay time T _DA0 of the delay circuit DA0 is set to the minimum. On the other hand, the maximum delay time _{T DA0} of the delay circuit DB at delay circuit DB0, gradually decreasing the delay time is set to a minimum delay time _{T DAn} of the delay circuit DAn. The delay circuit DA is selected by the delay selection signal _SDS1 , and the delay circuit DB is selected by the delay selection signal _SDS2 , for example, the delay circuit DA1 and the delay circuit DB1 are selected. The delay time interval for each delay circuit is
T _{DAm + 1} −T _DAm = T _DBm −T _{DBm + 1} Expression (2)
It is preferable to set the same. Here, the value of m is 0 to (n−1).

  As shown in FIG. 7A, when the “High” level period of the pre-correction clock signal CLKA is shorter than the “High” level period TH (50%) of the clock signal, the delay circuit is selected to be “High”. The level period is corrected to approach the “High” level period TH (50%) of the clock signal.

On the other hand, as shown in FIG. 7B, when the “Low” level period of the pre-correction clock signal CLKA is shorter than the “Low” level period TL (50%) of the clock signal CLK, the delay circuit is selected. The “Low” level period is corrected to approach the “Low” level period TL (50%) of the clock signal CLK. The selection of the correction for the “High” level period and the correction for the “Low” level period is performed based on the clock switching signal S _CLKS1 , the clock switching signal S _CLKS2 , the delay selection signal S _DS1 , and the delay selection signal S _DS2. .

As shown in FIG. 8, for example, in the operation of the automatic clock duty correction circuit 1 when the “High” level period of the pre-correction clock signal CLKA is shorter than the ideal clock signal CLK, first, it is output from the flip-flop FF1. A control clock signal S _{SCLK as the} signal A is input to the synchronous counter DCN, and a signal up-counted by the counter control signal S _CN is output from the synchronous counter DCN.

Next, the “Low” level clock switching signal S _CLKS1 output from the synchronous counter DCN is input to the selector SEL2, and the uncorrected clock signal CLKB has the same signal level as the uncorrected clock signal CLKA. Maintained. A delay selection signal S _SD1 (indicated as “0” in FIG. 8) for selecting the delay circuit DA0 output from the synchronous counter DCN is input to the selector SEL1, the delay circuit DA0 is selected, and the signal delayed by the delay circuit DA0 AD is output from the selector SEL1. Here, since the delay time of the delay circuit DA0 is set to zero, the signal AD has the same signal level as the signal A. When the pre-correction clock signal CLKB (pre-correction clock signal CLKA) falls, the flip-flop FF2 latches the “High” level data of the signal A, outputs the “High” level signal B, and the flip-flop FF3 outputs the signal. The AD “High” level data is latched and a “High” level signal C is output. In this case the measurement result output signal _{S SK} outputted from the XOR circuit EX1 is maintained at "Low" level.

Subsequently, a delay selection signal S _SD1 (indicated as “1” in FIG. 8) for selecting the delay circuit DA1 output from the synchronous counter DCN is input to the selector SEL1, the delay circuit DA1 is selected, and the delay circuit DA1 performs the delay. A signal AD delayed by time _TDA1 is output from the selector SEL1. When the pre-correction clock signal CLKB (pre-correction clock signal CLKA) falls, the flip-flop FF2 latches the “High” level data of the signal A, outputs the “High” level signal B, and the flip-flop FF3 outputs the signal. The AD “High” level data is latched and a “High” level signal C is output. In this case the measurement result output signal _{S SK} outputted from the XOR circuit EX1 is maintained at "Low" level.

Then, a delay selection signal S _SD1 (indicated as “2” in FIG. 8) for selecting the delay circuit DA2 output from the synchronous counter DCN is input to the selector SEL1, the delay circuit DA2 is selected, and the delay time is delayed by the delay circuit DA2. T _DA2 minutes delayed signal AD is outputted from the selector SEL1. When the pre-correction clock signal CLKB (pre-correction clock signal CLKA) falls, the flip-flop FF2 latches the “High” level data of the signal A, outputs the “High” level signal B, and the flip-flop FF3 outputs the signal. The AD “Low” level data is latched, and the “Low” level signal C is output. At this time, the measurement result output signal S _SK output from the XOR circuit EX1 becomes “High” level. Here, since the measurement result output signal S _SK changes from the “Low” level to the “High” level, the “High” period of the PLL output is specified. Delay time _{T DA2} of the delay circuit DA2 is determined that the closest to the "High" level period of the pre-correction clock signal CLK.

Next, the “High” level measurement result output signal S _SK is input to the rising cycle detection unit 21, and the rising cycle detection signal S _TAC output from the cycle detection unit 21 changes from the “Low” level to the “High” level (enable). Signal). In response to this “High” level (enable signal) signal, the loaded flip-flop LFF1 starts to operate, and the “Low” level clock switching signal S _CLKS2 which is the most significant bit is paired with the delay time T _DA2 of the delay circuit DA2. delay selection signal _{S DS2} for selecting the delay time _{T DB2} eggplant delay circuit DB2 is output to the clock generator 13. Here, the relationship between the delay time T _DA2 , the delay time T _DB2 , and the “High” level period TH (50%) of the ideal clock signal CLK is T _DA2 + T _DB2 = TH as in the equation (1). (50%).

Subsequently, a delay selection signal S _DS2 for selecting the delay time T _DB2 is input to the selector 3 of the clock generation unit 13, and a signal D obtained by delaying the pre-correction clock signal CLKA by the delay time T _DB2 is output from the selector 3. . Uncorrected clock signal CLKA and the signal D obtained by delaying _DB2 minute delay time _T before the correction clock signal CLKA is input to two-input OR circuit OR1 and two-input AND circuit AND2, the logical operation signal at the 2-input OR circuit OR1 A signal F logically operated by E and the 2-input AND circuit AND2 is output to the selector SEL4. The “Low” level clock switching signal S _CLKS2 is input to the selector _SEL4 , and the signal E is selected based on this signal. The selected signal E is a signal obtained by adding the delay time T _DB2 to the “High” level period of the pre-correction clock signal CLKA and subtracting the delay time T _DB2 to the “Low” level period of the pre-correction clock signal CLKA. Thus, the automatically corrected corrected clock signal CLKC having the “High” level period TH (50%) and the “Low” level period TL (50%) is output from the selector SEL4 to the internal circuit of the semiconductor device 30.

As shown in FIG. 9, in the operation of the automatic clock duty correction circuit 1 when the “High” level period of the pre-correction clock signal CLKA is longer than the ideal clock signal CLK, first, a signal output from the flip-flop FF1 A control clock signal S _SCLK which is A is input to the synchronous counter DCN, and a signal up-counted by the counter control signal S _CN is executed from the synchronous counter DCN until the up-counting is completed. Here, even when the delay time T _DAn of the delay circuit DAn having the longest delay time is selected from the delay selection signal S _DS1 and the clock switching signal S _CLKS1 is at the “Low” level, the measurement result output signal S _SK is “Low”. The level does not change to the “High” level.

Next, the synchronous counter DCN is reset by a reset signal. After reset, the synchronous counter DCN outputs a new signal based on the counter control signal S _CNS . The clock switching signal S _CLKS1 that is the most significant bit signal output from the synchronous counter DCN is changed to the “High” level.

Subsequently, the “High” level clock switching signal S _CLKS1 is input to the selector SEL2, and the pre-correction clock signal CLKB is a signal having a phase opposite to that of the pre-correction clock signal CLK. A delay selection signal S _SD0 (shown as “0” in FIG. 9) for selecting the delay circuit DA0 output from the synchronous counter DCN is input to the selector SEL1, the delay circuit DA0 is selected, and the signal delayed by the delay circuit DA0 AD is output from the selector SEL1. Here, since the delay time of the delay circuit DA0 is set to zero, the signal AD has the same signal level as the signal A. When the pre-correction clock signal CLKB falls (when the pre-correction clock signal CLKA rises), the flip-flop FF2 latches the “High” level data of the signal A, outputs the “High” level signal B, and the flip-flop The FF 3 latches the “High” level data of the signal AD, and outputs the signal C of the “High” level. In this case the measurement result output signal _{S SK} outputted from the XOR circuit EX1 is maintained at "Low" level.

A delay selection signal S _SD1 (shown as “1” in FIG. 9) for selecting the delay circuit DA1 output from the synchronous counter DCN is input to the selector SEL1, the delay circuit DA1 is selected, and the delay time is delayed by the delay circuit DA1. T _DA1 minutes delayed signal AD is outputted from the selector SEL1. When the pre-correction clock signal CLKB falls (when the pre-correction clock signal CLKA rises), the flip-flop FF2 latches the “High” level data of the signal A, outputs the “High” level signal B, and the flip-flop The FF 3 latches the “Low” level data of the signal AD and outputs the “Low” level signal C. At this time, the measurement result output signal S _SK output from the XOR circuit EX1 becomes “High” level. Here, since the measurement result output signal S _SK changes from the “Low” level to the “High” level, the “Low” period of the PLL output is specified. Delay time _{T DA1} of the delay circuit DA1 is determined that the closest to the "Low" level period of the pre-correction clock signal CLK.

Next, the “High” level measurement result output signal S _SK is input to the rising cycle detection unit 21, and the rising cycle detection signal S _TAC output from the cycle detection unit 21 changes from the “Low” level to the “High” level (enable). Signal). The "High" level (enable signal) signal, flip-flop LFF1 starts operating with load, "High" level of the clock switching signal _{S CLKS2} the delay circuit DB1 forming the delay time _{T DA1} and the pair of delay circuit DA1 A delay selection signal S _DS1 for selecting the delay time T _DB1 is output to the clock generation unit 13. Here, the relationship between the delay time T _DA1 , the delay time T _DB1 , and the ideal “Low” level period TL (50%) of the clock signal CLK is T _DA1 + T _DB1 = TL as in the equation (1). (50%).

Subsequently, a delay selection signal S _DS1 for selecting the delay time T _DB1 is input to the selector 3 of the clock generation unit 13, and a signal D obtained by delaying the uncorrected clock signal CLKA by the delay time T _DB1 is output from the selector 3. . Uncorrected clock signal CLKA and the signal D obtained by delaying the delay time _{T DB1} minutes before the correction clock signal CLKA is input to two-input OR circuit OR1 and two-input AND circuit AND2, the logical operation signal at the 2-input OR circuit OR1 A signal F logically operated by E and the 2-input AND circuit AND2 is output to the selector SEL4. The “High” level clock switching signal S _CLKS2 is input to the selector _SEL4 , and the signal F is selected based on this signal. The selected signal F is a signal obtained by adding the delay time T _DB1 to the “Low” level period of the pre-correction clock signal CLKA and subtracting the delay time T _DB1 to the “High” level period of the pre-correction clock signal CLKA. Thus, the automatically corrected corrected clock signal CLKC having the “High” level period TH (50%) and the “Low” level period TL (50%) is output from the selector SEL4 to the internal circuit of the semiconductor device 30.

Note that, in the operation of the automatic clock duty correction circuit 1 when the “High” level period of the pre-correction clock signal CLKA is longer than the ideal clock signal CLK, the most significant bit clock signal S _CLKS1 output from the synchronous counter DCN. Is initially set to the “Low” level, but this setting may be set to the “High” level. In this case, it is not necessary to reset the synchronous counter DCN, and the steps of measuring the clock signal CLKA before correction and automatically correcting it can be simplified.

As described above, in the clock duty automatic correction circuit and the clock duty automatic correction method of this embodiment, the clock duty automatic correction circuit 1 and the PLL circuit 2 are provided in the semiconductor device 30. The clock duty automatic correction circuit 1 includes a clock measurement unit 11, a clock duty specifying unit 12, and a clock generation unit 13. The pre-correction clock signal CLKA output from the PLL circuit 2 and having a changed duty ratio is input to the clock measurement unit 11 and the clock generation unit 13. The duty of the clock signal CLKA before correction is measured by the clock measuring unit 11 and the duty is specified by the clock duty specifying unit 12. The clock switching signal S _CLKS2 and the delay selection signal S _DS2 output from the clock duty specifying unit 12 are input to the clock generation unit 13, and the clock generation unit 13 uses an external signal for automatic correction of the duty ratio of the pre-correction clock signal CLKA. Done without.

  Therefore, the duty measurement of the clock signal CLKA before correction is performed using only the signal in the semiconductor device without using an external sampling clock signal having a frequency several times larger than the internal clock signal of the semiconductor device 30 as in the prior art. In addition, automatic correction can be performed with high accuracy. In addition, the circuit configuration is relatively simpler than before, duty measurement and automatic correction can be simplified, and there is no need to use an expensive measuring device.

  In this embodiment, an inverter chain is used for the delay circuit, but a buffer, a resistor, an RC delay circuit, or the like composed of a MOS transistor may be used. Further, although one of the plurality of delay circuits is selected using the selector and the clock signal is delayed, a plurality of selection means for selecting one of the plurality of delay circuits using the selector may be provided. . In this case, the number of delay circuits can be reduced as compared with the case of the one-stage configuration by increasing the delay time of the first-stage delay circuit and decreasing the delay time of the second-stage and subsequent delay circuits. It becomes possible. Further, the automatic clock duty correction circuit receives the pre-correction clock signal directly from the PLL circuit, but may input the pre-correction clock signal indirectly through the circuit.

  Next, an automatic clock duty correction circuit according to a second embodiment of the present invention will be described with reference to the drawings. 10 is a block diagram showing the configuration of the semiconductor device, FIG. 11 is a diagram showing the degree of delay time of the delay circuit, and FIG. 12 is a diagram showing a combination table of delay circuits stored in the combination table section. In this embodiment, k types of clock signals are input to the automatic clock duty correction circuit.

  As shown in FIG. 10, the semiconductor device 30a is provided with an automatic clock duty correction circuit 1a, and the internal circuit of the semiconductor device 30a operates based on the corrected clock signal CLKCa output from the automatic clock duty correction circuit 1a. To do.

Here, Example 1, as shown in FIG. 11 the relationship between the delay time T _DB of the delay circuit DB provided in the delay time T _DA and clock generator 13 of the delay circuit DA provided to the clock measuring unit 11 It has a different configuration. That is, the delay time T _DAn of the delay circuit DAn provided in the clock measuring unit 11 is maximized, the delay time is gradually decreased, and the delay time T _DA0 of the delay circuit DA0 is set to the minimum. Similarly, the delay time T _DBn of the delay circuit DBn provided in the clock generation unit 13 is maximized, the delay time is gradually decreased, and the delay time T _DB0 of the delay circuit DB0 is set to the minimum. The delay time for each delay circuit is
T _DAm = T _DBm・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (3)
It is preferable to set the same. Here, the value of m is 0 to n. The delay time interval for each delay circuit is preferably changed to be the same.

  The clock duty automatic correction circuit 1a includes a clock measurement unit 11, a clock duty specifying unit 12, a clock generation unit 13, a combination table unit 14, and a selector SEL5, and is output from a plurality of PLL circuits (not shown). The pre-correction clock signal CLKAa,..., The pre-correction clock signal CLKAk with the duty ratio changed is input to an ideal clock signal having a duty ratio of 50% or 50% due to a change in circuit threshold due to variations. Then, one clock duty automatic correction circuit 1a selects any one of the pre-correction clock signal CLKAa,..., The pre-correction clock signal CLKAk, measures the selected pre-correction clock signal, and has a duty ratio of 50%, 50 Outputs the corrected clock signal automatically corrected to%.

The selector SEL (frequency selection means) 5 receives k types of pre-correction clock signals CLKAa,..., And pre-correction clock signals CLKAk output from a plurality of PLL circuits and having different duty ratios. One of them is selectively output as the pre-correction clock signal CLKA based on the setting signal S _SHS . Here, the pre-correction clock signal CLKAa is selected. The pre-correction clock signal CLKAa,..., And the pre-correction clock signal CLKAk are signals output from the PLL circuit directly or through the circuit, respectively.

The clock measuring unit 11 is provided between the selector SEL5 and the clock duty specifying unit 12, and receives the pre-correction clock signal CLKAa selected by the selector SEL5, and outputs the measurement result output signal S _SKa and the control clock signal S _CLKa to the clock duty. Output to the identification unit 12. Note that the operation of the clock measurement unit 11 is the same as that of the first embodiment, and thus the description thereof is omitted.

The clock duty specifying unit 12 is provided between the clock measurement unit 11, the clock generation unit 13, and the combination table unit 14, and receives the measurement result output signal S _SKa and the control clock signal S _CLKa output from the clock measurement unit 11. The clock switching signal S _CLKS1a and the delay selection signal S _DS1a are output to the clock measurement unit 11, the delay selection signal S _DS2a is output to the combination table unit 14, and the clock switching signal S _CLKS2a is output to the clock generation unit 13. Since the circuit operation of the clock duty specifying unit 12 is the same as that of the first embodiment, description of the circuit operation is omitted. The delay selection signal S _DS2a output from the clock duty specifying unit 12 is output to the combination table unit 14, and the delay selection signal S _DS2a output from the clock duty specifying unit 12 determines the delay time T _DA of the delay circuit DA. The selected signal is different from the first embodiment.

Combination table unit 14 includes, for example, a register for storing a plurality of combination table is provided between the clock duty specifying unit 12 and the clock generator 13, the delay selection signal S _Ds2a output from the clock duty determiner 12 And the frequency setting signal S _SHS are input, and a combination table corresponding to the frequency setting signal S _SHS is selected. Then, the combination table unit 14 selects the delay time T _DB of the delay circuit DB that is paired with the delay selection signal S _DS2a that is a signal that selects the delay time T _DA of the delay circuit DA, and generates the clock of the delay selection signal S _DS2b. To the unit 13.

  As shown in FIG. 12, the combination table includes a delay circuit DA and a delay circuit DB for each frequency. Here, a case where the number k of the clock signals CLKA before correction is 3 is shown. For example, the frequency (f) is set to 800 MHz, the frequency (f / 2) is set to 400 MHz, and the frequency (f / 4) is set to 200 MHz, for example.

In the combination table at the frequency (f), as shown in FIG. 12A, (1/4) n delay circuits (DA0 to DA ((1/4) n)) are provided as the delay circuit DA. N delay circuits (DB0 to DB ((1/4) n)) are provided as the delay circuit DB, where the delay circuit DA ((1/4) n) is 1 of the delay time _TDAn . A delay circuit having a delay time of / 4, and the delay circuit DB ((1/4) n) is a delay circuit having a delay time of 1/4 of the delay time T _DBn , and a pair of delays The sum of the time is maintained at a constant value T1, for example, the delay selection signal S for selecting the frequency (f) by the frequency setting signal S _SHS and selecting the delay circuit DA0 having the delay time T _DA0 by the clock duty unit 12. _{If DS2a} is selected, it has a delay time _{T DB ((1/4) n)} , Delay selection signal _{S Ds2b} for selecting the delay circuit DB paired with delay circuit DA0 ((1/4) n) is output to the clock generator 13.

In the combination table at the frequency (f / 2), as shown in FIG. 12B, (1/2) n delay circuits (DA0 to DA ((1/2) n) are provided as the delay circuit DA. N delay circuits (DB0 to DB ((1/2) n)) are provided as the delay circuit DB, where the delay circuit DA ((1/2) n) is the delay time T _DAn. The delay circuit DB ((1/2) n) is a delay circuit having a delay time that is 1/2 of the delay time T _DBn . The sum of the delay times is maintained at a constant value 2 × T1, for example, the frequency (f / 2) is selected by the frequency setting signal S _SHS , and the clock duty unit 12 sets the delay circuit DA0 having the delay time T _DA0. When the delay selection signal S _{DS2a to} be selected is selected, the delay time T _{DB ((1/2) n)} have a delay selection signal _{S Ds2b} for selecting the delay circuit DB paired with delay circuit DA0 ((1/2) n) is output to the clock generator 13.

In the combination table at the frequency (f / 4), as shown in FIG. 12C, n delay circuits (DA0 to DAn) are provided as the delay circuit DA, and n delay circuits (DA) are provided as the delay circuit DB. DB0 to DBn) are provided. Here, the sum of the paired delay times is kept at a constant value of 4 × T1. For example, when the frequency (f / 4) is selected by the frequency setting signal S _SHS and the delay selection signal S _DS2a for selecting the delay circuit DA0 having the delay time T _DA0 is selected by the clock duty unit 12, the delay time T _DBn is set. a delay selection signal _{S Ds2b} for selecting the delay circuit DBn paired with delay circuit DA0 is outputted to the clock generator 13.

  Here, when the frequency of the pre-correction clock signal CLKA is (f / 2), the number of delay circuits is set twice and the sum of delay times is set to twice that when the frequency is (f). . Further, when the frequency of the pre-correction clock signal CLKA is (f / 4), the number of delay circuits is set to 4 times and the sum of delay times is set to 4 times that when the frequency is (f). That is, when the gear ratio is changed, for example, when the frequency of the pre-correction clock signal CLKA is (f / k), the number of delay circuits is multiplied by k and the sum of the delay times is k compared to when the frequency is (f). What is necessary is just to set to double.

As described above, the clock duty automatic correction circuit according to the present embodiment includes the clock measuring unit 11, the clock duty specifying unit 12, the clock generating unit 13, the combination table unit 14, and the selector SEL5. The selector SEL5 receives the pre-correction clock signal CLKAa,..., And the pre-correction clock signal CLKAk, which are output from a plurality of PLL circuits and have different duty ratios at different frequencies, and is selected based on the frequency setting signal S _SHS One is selectively output as a pre-correction clock signal. The pre-correction clock signal selected by the selector SEL5 is input to the clock measurement unit 11 and the clock generation unit 13. The clock measurement unit 11 measures the duty of the selected pre-correction clock signal, and the clock duty specifying unit 12 specifies the duty. Delay select signal delay from the selection signal S _Ds2a and frequency setting signal S _SHS output from the clock duty determiner 12 selects the delay circuit DB that forms a delay circuit DA and a pair of clock measuring unit 11 corresponding to the specified frequency The _{SDS 2b} is output from the combination table unit 14. The delay selection signal _SDS2b output from the combination table unit 14 and the clock switching signal _SCLKS2a output from the clock duty specifying unit 12 are input to the clock generation unit 13, and the clock signal before correction selected by the clock generation unit 13 The duty ratio is automatically corrected without using an external signal.

  Therefore, it is stored in the combination table unit 14 using only the signal in the semiconductor device without using an external sampling clock signal having a frequency several times larger than the internal clock signal of the semiconductor device 30 as in the prior art. Duty measurement and automatic correction of different types of pre-correction clock signals can be performed with high accuracy from the combination table of the delay circuit DA and the delay circuit DB. In addition, the circuit configuration is relatively simpler than before, duty measurement and automatic correction can be simplified, and there is no need to use an expensive measuring device.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in this embodiment, the duty ratio of the clock signal output from the PLL circuit is automatically corrected by using an automatic clock duty correction circuit, but a DLL (Delay locked Loop) circuit or an SMD (Synchronous Mirror Delay) circuit is used. It is possible to automatically correct the duty ratio of the clock signal output from the above. In the embodiment, one of a plurality of delay circuits is selected using a selector and the clock signal is delayed. However, a selection unit that selects one of the plurality of delay circuits using a selector is provided in a plurality of stages. It may be provided. In this case, the number of delay circuits can be reduced as compared with the case of the one-stage configuration by increasing the delay time of the first-stage delay circuit and decreasing the delay time of the second-stage and subsequent delay circuits. It becomes possible.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A second clock signal having a high level period or a low level period shorter than that of the first clock signal having a duty ratio of 50% and 50% is input, and the delay time for delaying the second clock signal is different. A plurality of first delay circuits each including an inverter chain, and immediately after an output signal changes, a first delay time of a delay circuit selected from the plurality of first delay circuits is set to the first delay time; A clock measuring unit that sets the duty of the second clock signal, and a clock duty specifying unit that generates a delay selection signal that specifies the duty of the second clock signal based on the output signal output from the clock measuring unit, The second clock signal is input, and the second clock signal is delayed to delay the second clock signal. The first delay time is subtracted from the time of the duty ratio of 50% of the first clock signal based on the delay selection signal output from the clock duty specifying unit. A delay circuit having a second delay time corresponding to the selected value is selected from the plurality of second delay circuits, and the duty of the second clock signal is automatically corrected using the second delay time. An automatic clock duty correction circuit comprising a clock generation unit.

(Supplementary note 2) A selector that inputs a plurality of clock signals having different frequencies in a high level period or a low level period and selects one of the plurality of clock signals based on a frequency setting signal, and is selected by the selector A plurality of first delay circuits configured by inverter chains having different delay times for inputting the first clock signal and delaying the first clock signal, and the plurality of first delay circuits immediately after the output signal changes A clock measuring unit that uses a first delay time of the delay circuit selected from the first delay circuit as a duty of the first clock signal, and the output signal output from the clock measuring unit. A clock duty specifying unit for generating a first delay selection signal for specifying a duty of the first clock signal; and the frequency setting And the first delay selection signal output from the clock duty specifying unit, a plurality of combination tables, and a combination table corresponding to the first clock signal from the plurality of combination tables. A register for selecting a second delay selection signal corresponding to a duty of the first clock signal from the selected combination table; and the first clock signal is input. A plurality of second delay circuits composed of inverter chains having different delay times, and based on the second delay selection signal output from the combination table unit, the first clock signal A delay circuit having a second delay time corresponding to a value obtained by subtracting the first delay time from a half cycle time; A clock duty automatic correction circuit comprising: a clock generator that selects from a plurality of second delay circuits and automatically corrects the duty of the first clock signal using the second delay time.

(Supplementary Note 3) In a plurality of combination tables corresponding to the clock frequency input to the register, a first combination table corresponding to the clock frequency (f) and a second combination table corresponding to the clock frequency (f / k). The number of the first and second delay circuits in the second combination table is set to be k times greater than that of the first and second delay circuits in the first combination table. The sum of the delay time of the first delay circuit and the delay time of the second delay circuit corresponding to each other in the combination table is the delay time of the first delay circuit and the second delay corresponding to each other in the first combination table. The automatic clock duty correction circuit according to Supplementary Note 2, wherein the clock duty correction circuit is set to be k times larger than the sum of the delay times of the circuit.

1 is a block diagram showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. 1 is a block diagram illustrating a clock measurement unit according to Embodiment 1 of the present invention. The block diagram which shows the clock duty specific | specification part which concerns on Example 1 of this invention. 1 is a block diagram showing a clock generation unit according to Embodiment 1 of the present invention. The figure which shows the relationship between the duty of the clock signal which concerns on Example 1 of this invention, and the delay time of a delay circuit. FIG. 3 is a diagram illustrating the degree of delay time of the delay circuit according to the first embodiment of the invention. FIG. 6 is a diagram showing switching between a “High” level period and a “Low” level period of a clock signal in duty measurement / correction according to the first embodiment of the present invention. 6 is a timing chart showing the operation of the automatic duty correction circuit using the “High” level period of the clock signal according to the first embodiment of the present invention. 4 is a timing chart showing the operation of the automatic duty correction circuit using the “Low” level period of the clock signal according to the first embodiment of the present invention. FIG. 6 is a block diagram showing a configuration of a semiconductor device according to Embodiment 2 of the present invention. The figure which shows the grade of the delay time of the delay circuit which concerns on Example 2 of this invention. The figure which shows the combination table of the delay circuit stored in the combination table part which concerns on Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1a Clock duty automatic correction circuit 2 PLL circuit 11 Clock measurement part 12 Clock duty specific | specification part 13 Clock generation part 14 Combination table part 21 Rising cycle detection part 30, 30a Semiconductor device AND1, 2-input AND circuit CLK Clock signal CLKA, CLKB, CLKAa, CLKAk Clock signal before correction CLKC, CLKCa Clock signal after correction DA0, DA1, DAn, DB0, DB1, DBn Delay circuit DCN Synchronization counter EX1 XOR circuit FF1-4 Flip flop INV1, INV2 Inverter LFF1 Flip flop OR1 with load 2-input OR circuit S _CNS counter control signals S _CLKS1 , S _CLKS2 , S _CLKS1a , S _CLKS2a Clock switching signals S _DS1 , S _DS2 , S _DS1a , S _DS2a , S _DS2b delay selection signals SEL1 to 4 selector S _SK , S _SKa measurement result output signal S _SCLK , S _SCLKa control clock signal S _SHS frequency setting signal S _TAC rising cycle detection signal T _DA delay circuit DA Delay time T _DB Delay time _{DB of DB} delay circuit TH “High” level period TL “Low” level period

Claims (5)

A second clock signal having a high level period or a low level period shorter than that of the first clock signal having a duty ratio of 50% and 50% is input, and the first clock signals having different delay times for delaying the second clock signal are input. Clock measurement using the first delay time of the delay means selected from the plurality of first delay means immediately after the output signal is changed as the duty of the second clock signal. And
A clock duty specifying unit for generating a delay selection signal for specifying a duty of the second clock signal based on the output signal output from the clock measuring unit;
Based on the delay selection signal output from the clock duty specifying unit, having a plurality of second delay means having different delay times for inputting the second clock signal and delaying the second clock signal. The delay means having a second delay time corresponding to a value obtained by subtracting the first delay time from the time of the duty ratio of 50% of the first clock signal is selected from the plurality of second delay means. A clock generator that automatically corrects the duty of the second clock signal using the second delay time;
An automatic clock duty correction circuit comprising: A second clock signal having a high level period or a low level period shorter than that of the first clock signal having a duty ratio of 50% and 50% is input, and the first clock signals having different delay times for delaying the second clock signal are input. Immediately after the output signal changes from the low level to the high level, the first delay time of the delay circuit selected from the plurality of first delay circuits is set to the second clock signal. A clock measurement unit for duty;
Generate a clock switching signal for selecting duty measurement during the High level period or Low level period of the second clock signal, and output the clock switching signal to the clock measurement unit to measure the duty of the second clock signal A clock duty specification for determining a high-level period or a low-level period and generating a delay selection signal for specifying a duty of the second clock signal based on the output signal output from the clock measurement unit And
The delay selection signal and the clock that are input from the second clock signal and have a plurality of second delay circuits having different delay times for delaying the second clock signal, and output from the clock duty specifying unit Based on the switching signal, a delay circuit having a second delay time corresponding to a value obtained by subtracting the first delay time from a time with a duty ratio of 50% of the first clock signal is set to the plurality of second delays. A clock generation unit that automatically selects a high level period or a low level period duty of the second clock signal using the second delay time,
An automatic clock duty correction circuit comprising: A frequency selection means for inputting a plurality of clock signals having different frequencies of a high level period or a low level period and selecting one of the plurality of clock signals based on a frequency setting signal;
Immediately after the first clock signal selected by the frequency selection means is input, and a plurality of first delay means having different delay times for delaying the first clock signal, the output signal changes. A clock measurement unit having a first delay time of a delay unit selected from a plurality of first delay units as a duty of the first clock signal;
A clock duty specifying unit for generating a first delay selection signal for specifying a duty of the first clock signal based on the output signal output from the clock measuring unit;
The frequency setting signal and the first delay selection signal output from the clock duty specifying unit are input, and have a plurality of combination tables, and correspond to the first clock signal from the plurality of combination tables. A combination table unit that selects a combination table and selects a second delay selection signal corresponding to the duty of the first clock signal from the selected combination table;
The second delay selection signal output from the combination table unit includes a plurality of second delay units having different delay times for inputting the first clock signal and delaying the first clock signal. Based on the second delay means, a delay means having a second delay time corresponding to a value obtained by subtracting the first delay time from a half cycle time of the first clock signal is provided. A clock generator that selects and automatically corrects the duty of the first clock signal using the second delay time;
An automatic clock duty correction circuit comprising: A frequency selection means for inputting a plurality of clock signals having different frequencies of a high level period or a low level period and selecting one of the plurality of clock signals based on a frequency setting signal;
The first clock signal selected by the frequency selection means is input, and a plurality of first delay circuits having different delay times for delaying the first clock signal are provided, and the output signal changes from low level to high level. Immediately after, a clock measurement unit having a first delay time of a delay circuit selected from the plurality of first delay circuits as a duty of the first clock signal;
A duty of the first clock signal measured by generating a clock switching signal for selecting duty measurement of the high level period or the low level period of the first clock signal and outputting the clock switching signal to the clock measuring unit. Either a high level period or a low level period is determined, and a first delay selection signal for specifying a duty of the first clock signal is generated based on the output signal output from the clock measurement unit. A clock duty specifying unit;
The frequency setting signal and the first delay selection signal output from the clock duty specifying unit are input, and have a plurality of combination tables, and correspond to the first clock signal from the plurality of combination tables. A combination table unit that selects a combination table and selects a second delay selection signal corresponding to the duty of the first clock signal from the selected combination table;
A plurality of second delay circuits having different delay times for inputting the first clock signal and delaying the first clock signal, the second delay selection signal output from the combination table unit; A delay circuit having a second delay time corresponding to a value obtained by subtracting the first delay time from a ½ cycle time of the first clock signal based on the clock switching signal. A clock generation unit that selects from among delay circuits and automatically corrects the duty of the high level period or the low level period of the first clock signal using the second delay time;
An automatic clock duty correction circuit comprising: A clock duty automatic correction method using a clock duty automatic correction circuit having a clock measurement unit, a clock duty specifying unit, and a clock generation unit,
Inputting a second clock signal having a high level period or a low level period shorter than the first clock signal having a duty ratio of 50% and 50% to the clock measurement unit and the clock measurement unit;
One of a plurality of first delay circuits provided in the clock measuring unit is selected, the second clock signal is delayed by the selected delay circuit, and the output signal of the clock measuring unit is at a low level. Immediately after changing from high level to high level, setting the first delay time of the delay circuit selected from the plurality of first delay circuits as the duty of the second clock signal;
Inputting the output signal output from the clock measuring unit to a clock duty specifying unit, and generating a delay selection signal for specifying the duty of the second clock signal based on the output signal;
The second clock signal and the delay selection signal are input to the clock generation unit, and a plurality of second delay circuits having different delay times for delaying the second clock signal provided in the clock generation unit are provided. A delay circuit having a second delay time corresponding to a value obtained by subtracting the first delay time from a time of a duty ratio of 50% of the first clock signal based on the delay selection signal; Automatically correcting the duty of the second clock signal using a second delay time;
An automatic clock duty correction method using an automatic clock duty correction circuit.

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