JP2007329234A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a rate of crack of semiconductor elements in the steps of manufacturing thinner semiconductor elements. <P>SOLUTION: A dicing tape 21 as a foaming tape is laminated to the front surface of a semiconductor wafer on which an element structure is formed to the front and rear surfaces thereof, and the dicing process is conducted under this condition. Next, each position of individual chip 22 formed by the dicing process is irradiated with a laser beam, and thereby an adhesive force of the dicing tape 21 is lowered. Thereafter, the chip 22 at the position irradiated with the laser beam is peeled from the dicing tape 21 with vacuum attraction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor element that requires processing of the back surface of a wafer, and in particular, a power semiconductor element such as an insulated gate bipolar transistor (hereinafter referred to as IGBT), a bidirectional device having bidirectional withstand voltage, or The present invention relates to a method for manufacturing a reverse blocking device.

  2. Description of the Related Art Conventionally, an integrated circuit (IC) in which a large number of transistors, resistors, and the like are connected to form an electric circuit and integrated on a single chip is often used as a main part of a computer or a communication device. Among such ICs, those including power semiconductor elements are called power ICs, and IGBTs are one of the power semiconductor elements.

  The IGBT is a power element in which a MOSFET (insulated gate field effect transistor) having high-speed switching characteristics and voltage driving characteristics and a bipolar transistor having low on-voltage characteristics are configured on a single chip. The range of applications has expanded from industrial fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS), or switching power supplies to consumer equipment fields such as microwave ovens, rice cookers, and strobes. Further, IGBTs having a lower on-voltage using a new chip structure have been developed, and reductions in the loss and efficiency of application devices using the IGBT have been achieved.

  The IGBT has a punch-through (hereinafter referred to as PT) type, non-punch-through (hereinafter referred to as NPT) type, and field stop (hereinafter referred to as FS) type, and an n-channel vertical double type. A diffusion structure is the mainstream. Accordingly, in this specification, an n-channel IGBT is described as an example, but the same applies to a p-channel IGBT.

The PT-type IGBT is formed using an epitaxial wafer obtained by epitaxially growing an n ⁺ buffer layer and an n ⁻ active layer on a p ⁺ semiconductor substrate. Therefore, for example, in a device with a withstand voltage of 600 V, the thickness of the active layer is about 70 μm, but the total thickness including the p ⁺ semiconductor substrate is about 200 to 300 μm. In the PT type IGBT, the depletion layer in the n ⁻ active layer reaches the n ⁺ buffer layer.

FIG. 12 is a cross-sectional view showing the configuration of a half cell of an NPT type IGBT having a shallow p ⁺ collector layer with a low dose. As shown in FIG. 12, for example, an n ⁻ semiconductor substrate made of an FZ wafer (hereinafter referred to as “wafer”) 1 is used as an active layer, and ap ⁺ base region 2 is selectively formed on the surface side. An n ⁺ emitter region 3 is selectively formed on the surface layer of the base region 2. A gate electrode 5 is formed on the substrate surface via a gate oxide film 4.

The emitter electrode 6 is in contact with the emitter region 3 and the base region 2 and is insulated from the gate electrode 5 by the interlayer insulating film 7. The back surface of the substrate, p ⁺ collector layer 8 and the collector electrode 9 is formed. In the case of the NPT type, the thickness of the wafer 1 is thicker than that of the PT type, but the entire device is significantly thinner than the PT type device. Moreover, since the FZ substrate is used without using the epitaxial substrate, the cost is low.

FIG. 13 is a cross-sectional view showing the configuration of a half cell of the FS type IGBT. As shown in FIG. 13, the element structure on the substrate surface side is the same as the NPT type element shown in FIG. The back surface of the substrate, n ^- between the wafer 1 and the p ⁺ collector layer 8 is a layer, n ⁺ buffer layer 10 is provided. In the case of the FS type, the thickness of the wafer 1 is about 70 μm (withstand voltage 600V system), which is the same as the PT type, and the thickness of the entire element is about 100 to 200 μm.

FIG. 14 is a cross-sectional view showing the configuration of 1/2 cell of a reverse blocking IGBT. As shown in FIG. 14, the reverse blocking IGBT has the same structure as the NPT type element shown in FIG. 12 except that the isolation layer 11 is formed in contact with the p ⁺ collector layer 8. The reverse blocking IGBT has a reverse breakdown voltage in addition to the basic performance of the conventional IGBT, and is used for a semiconductor switch of a matrix converter that performs AC-AC exchange without passing through DC.

  Unlike a conventional converter, the matrix converter does not require a capacitor, and power supply harmonics are reduced. On the other hand, since the input of the matrix converter is an alternating current, the semiconductor switch is required to have reverse breakdown voltage. For this reason, in the case of a semiconductor switch using a conventional IGBT, it is necessary to connect reverse blocking diodes in series. On the other hand, according to the semiconductor switch using the reverse blocking IGBT, since it is not necessary to connect the diodes in series, the conduction loss can be halved and the conversion efficiency of the matrix converter can be greatly improved. For manufacturing a reverse blocking IGBT, a technology for forming a deep junction having a thickness of 100 μm or more from the substrate surface and a technology for producing an ultrathin wafer having a thickness of 100 μm or less are indispensable.

  Recently, in order to further reduce the total loss, an attempt has been made to make the device as thin as possible by shaving the wafer thinly. For example, in the case of an element having a withstand voltage of 600 V, the thickness of the FS type IGBT is assumed to be about 70 μm. When the breakdown voltage class is lowered, the thickness of the element is further reduced. As a manufacturing method of the FS type IGBT having such a thickness or a device similar thereto, a method of polishing an FZ wafer is known as described below.

15 to 19 are diagrams showing a manufacturing process of an FS type IGBT using a conventional FZ wafer. As shown in FIG. 15, the active layer the n ^- surface side of the wafer 1, the base region, an emitter region, a gate oxide film made of SiO _2, a gate electrode, made of BPSG interlayer insulating film, Al- A surface side element structure portion 12 having an emitter electrode made of Si film or the like and an insulating protective film made of polyimide film or the like is formed (FIG. 15).

  Next, the back surface of the wafer 1 is ground by means such as back grinding or etching, so that the wafer 1 has a desired thickness, for example, 70 μm (FIG. 16). In the case of etching, although it is not strictly grinding, in this specification, since means for thinning the wafer 1 is not limited, grinding including etching is performed.

  Next, from the back surface of the wafer 1, for example, ion implantation of phosphorus (P) as an n-type impurity and boron (B) as a p-type impurity is performed, and a heat treatment (annealing) at 350 to 500 ° C. is performed in an electric furnace. A buffer layer 10 and a collector layer 8 are formed (FIG. 17). Next, a plurality of metals such as aluminum (Al), titanium (Ti), nickel (Ni), and gold (Au) are vapor-deposited on the back surface of the wafer 1, that is, the surface of the collector layer 8 to form the collector electrode 9 ( FIG. 18).

  Finally, dicing is performed by attaching a dicing tape 13 to the collector electrode 9 side, and the wafer 1 is cut into a plurality of chips 14 (FIG. 19). Then, the collector electrode 9 of each chip 14 is soldered to a fixing member, and an aluminum wire electrode is fixed to the electrode of the surface side element structure portion 12 by a wire bonding apparatus.

  However, if an attempt is made to produce a thin element having a thickness of, for example, about 70 μm by the conventional method described above, the thickness of the wafer after back grinding or back grinding by etching (see FIG. 16) is thin. The wafer is likely to crack or warp during electrode deposition.

  In order to prevent such cracking and warping of the wafer, a method in which a support member is attached to the surface of the wafer on which the surface side element structure is formed, and after performing the back side process in that state, the wafer is peeled off from the support member Has been proposed (see, for example, Patent Document 1 below). In addition, a wafer peeling apparatus that peels a wafer from a support member by adhering the support member and the wafer to each other in a direction opposite to each other and heating the wafer after the manufacturing process is performed is known. (For example, refer to Patent Document 2 below).

  Also, in order to prevent the wafer from warping, a dicing line is inserted from the back side of the wafer (first dicing) to the wafer on which the surface protecting tape is attached, and after the back side process is performed, the second dicing is performed. There has been proposed a method of forming a semiconductor chip by performing (see, for example, Patent Document 3 below).

  In addition, a method has been proposed in which only the outer peripheral portion of a diced wafer attached to a support sheet and defective chips are removed from the support sheet by spot irradiation with UV light (for example, see Patent Document 4 below).

Japanese Patent Laying-Open No. 2005-005672 (see FIGS. 1 and 2) Japanese Patent Laid-Open No. 06-268051 (see paragraph 0030) JP 2002-134441 A (see paragraph 0016) Japanese Patent Laying-Open No. 2005-322683 (see paragraph numbers 0048 and 0049)

  However, according to the above-described prior art, since the wafer after the back surface process is thin, there is a problem that when the individual chips after dicing are peeled from the dicing tape, the chips are likely to be cracked. Moreover, the same problem occurs when the thin wafer after back grinding is peeled off from the support member.

  For example, when a UV tape whose adhesive strength is weakened by irradiation with UV light is used as the dicing tape, even when UV light is applied to weaken the adhesive strength of the tape, pressure is applied to the chips when picking up individual chips with tweezers. This may cause the chip to break. In addition, when a foam tape whose adhesive strength is weakened by heating and foaming is used as the dicing tape, even if the adhesive strength of the tape is weakened by heating the foam tape, the adhesive strength becomes strong again over time. Therefore, it is necessary to peel off all the chips within a short time after heating, which is difficult.

  Further, when peeling with a peeling tape is performed, the chip may be broken by the adhesive force of the dicing tape when the peeling tape is pulled up from the dicing tape. Furthermore, if tweezers are used when picking up a chip adhered to the peeling tape, pressure may be applied to the chip, which may cause the chip to break.

  Further, for example, even if the wafer is peeled from the support member using the method as in Patent Document 1 or the apparatus as in Patent Document 2, the chip is cracked when the chip is peeled off from the dicing tape after dicing. There is a problem that. Moreover, since the apparatus of patent document 2 is for peeling a wafer, it is not suitable for peeling each chip | tip. The method of Patent Document 3 also has a problem in that the wafer is cracked when the surface protecting sheet is peeled off from the wafer and when the second dicing is performed.

  Further, the method of Patent Document 4 has a problem that a mask is required to irradiate UV light for each chip. Further, when a UV laser is used for spot irradiation with UV light, since the wavelength is as short as about 300 nm, there is a problem that it takes a long time to peel off all the chips on the wafer. For example, in the case of a 10 mm square chip, only about 5 chips can be peeled per day, resulting in a reduction in production efficiency.

  In order to eliminate the above-described problems caused by the prior art, the present invention manufactures a semiconductor device capable of reducing the cracking rate of a chip at the time of peeling from a dicing tape or a support member or a wafer that can be separated into chips. It aims to provide a method.

  In order to solve the above-described problems and achieve the object, a method for manufacturing a semiconductor device according to claim 1 includes a forming step of forming an element structure portion on a semiconductor wafer, and a semiconductor wafer on which the element structure portion is formed. A bonding step of bonding a support member that can be peeled off by heating to the surface of the substrate, a separation step of bringing the semiconductor wafer into a substantially separable state in a state where the support member is bonded, and the support A heating step of individually heating a portion corresponding to each chip of the member; and a chip bonded to the portion of the support member heated in the heating step is adsorbed to remove the chip from the support member And a peeling step for peeling.

  According to the first aspect of the present invention, portions of the support member corresponding to the individual chips are individually heated, and the chips bonded to the heated portions are adsorbed and separated from the support member. Thereby, only the desired chip on the semiconductor wafer can be peeled from the support member. Moreover, since it peels from a support member by adsorb | sucking a chip | tip, an excessive pressure is not applied to a chip | tip and it can prevent that a chip | tip cracks at the time of peeling from a support member.

  According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect, wherein the support member is a surface protective sheet having an adhesive layer that can be peeled off by heating. .

  According to the second aspect of the present invention, the semiconductor wafer can be made substantially separable into chips while the surface of the semiconductor wafer is protected by the surface protection sheet. Moreover, when peeling each chip | tip from the sheet | seat for surface protection, a chip | tip can be prevented from cracking.

  According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor element according to the second aspect of the present invention, wherein the separating step includes dicing the semiconductor wafer by dicing the surface protection sheet. Is divided into individual chips.

  According to the third aspect of the present invention, it is possible to prevent the chips from breaking when the chips are separated from the surface protection sheet after the semiconductor wafer is cut (diced) to form the chips.

  According to a fourth aspect of the present invention, there is provided a semiconductor element manufacturing method according to the first aspect, wherein the support member is a glass substrate that is bonded to the semiconductor wafer via an adhesive layer that can be peeled off by heating. It is characterized by being.

  According to the fourth aspect of the present invention, the semiconductor wafer can be made substantially separable into chips in a state where the glass substrate is bonded to the surface of the semiconductor wafer via the adhesive layer. Moreover, when each chip | tip is peeled from a glass substrate, it can prevent that a chip | tip cracks.

  According to a fifth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the fourth aspect of the present invention, wherein in the separation step, the separation groove is formed from the back surface of the semiconductor wafer in a state where the support member is bonded. The semiconductor wafer is substantially separated into individual chips by forming the wafer so as to substantially reach the surface of the wafer.

  According to the fifth aspect of the present invention, after the separation groove is formed in the semiconductor wafer bonded to the support member to make it substantially separable into chips, the chip is broken when the chips are peeled off from the support member. Can be prevented.

  According to a sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to any one of the second to fifth aspects, wherein the adhesive layer is an adhesive sheet that can be peeled off by heat foaming. And

  According to the invention of claim 6, by heating the foam sheet, the adhesive force with the semiconductor wafer is weakened, and each chip can be easily peeled off.

  According to a seventh aspect of the present invention, in the semiconductor element manufacturing method according to the first aspect of the present invention, the forming step includes a step of grinding the back surface of the semiconductor wafer. Features.

  According to the seventh aspect of the present invention, the chip can be prevented from cracking when the back surface of the semiconductor wafer is ground and the chip having a reduced thickness is peeled off from the adhesive layer.

  A method for manufacturing a semiconductor element according to an invention of claim 8 is the invention according to any one of claims 2 to 7, wherein the heating step is bonded to any chip of the adhesive layer. The exposed portion is irradiated with laser light and heated, and the peeling step peels off the chip bonded to the portion irradiated with the laser light.

  According to the invention of claim 8, only an arbitrary chip on the semiconductor wafer can be peeled from the adhesive layer.

  According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eighth aspect, the heating step irradiates a laser beam in an irradiation range substantially equal to a size of the chip. And

  According to the invention of claim 9, only an arbitrary chip on the semiconductor wafer can be peeled off from the adhesive layer.

  According to the semiconductor element manufacturing method of the present invention, there is an effect that it is possible to reduce the chip and the crack rate of the wafer that can be separated into chips when peeling from the dicing tape or the support member.

  Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment 1)
In the first embodiment, a case where a dicing cut chip is picked up from a dicing tape and separated into individual chips in the manufacturing process of the FS type IGBT will be described. In the first and second embodiments described below, the case where the present invention is applied to the manufacture of an FS type IGBT will be described. However, even when manufacturing an NPT type IGBT, reverse blocking IGBT, MOS-FET, diode, or the like. Can be applied as well.

  1 and 2 are diagrams illustrating a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 1 shows a state in which a wafer bonded to a dicing tape 21 is diced into a plurality of chips 22. These chips 22 are formed by the same manufacturing process as the conventional FS type IGBT as described in the background art. That is, first, a surface side element structure portion is formed on the surface side of a wafer to be an active layer (see FIG. 15). Next, the back surface of the wafer is ground by means such as back grinding or etching, so that the wafer has a desired thickness (see FIG. 16).

  Subsequently, ion implantation and annealing are performed to form a buffer layer and a collector layer (see FIG. 17), and then a plurality of metals are deposited on the back surface of the wafer to form a collector electrode (see FIG. 18). Then, dicing tape 21 is attached to the collector electrode side to perform dicing, and the wafer is cut into a plurality of chips 22 (see FIG. 1). At this time, the dicing tape 21 is a foam tape that can be peeled off by foaming by heating. The chip 22 is formed by the above process.

Next, each chip 22 is peeled from the dicing tape 21. Specifically, as shown in FIG. 2, YAG laser (wavelength: 1064 nm) or CO ₂ laser (wavelength: 10.64 μm) is irradiated in accordance with the position of the chip 22 to be peeled off. The irradiation energy of laser should just be the grade which reaches the peeling temperature of the foaming tape which is the dicing tape 21. FIG. For example, in the case of model 3198M manufactured by Nitto Denko Corporation, the peeling temperature of the foam tape is 120 ° C. When irradiating with YAG laser, the irradiation energy may be about 500 mJ / cm ² .

  The laser spot size is adjusted according to the size of the chip 22 to be peeled off. For example, when the size of the chip 22 is 10 mm square, the laser spot size is preferably 10 mm square. This is because it is desirable that only the range of the foam tape that is bonded to the chip 22 reaches the peeling temperature by one laser irradiation. Note that the spot diameter pulse irradiation may be performed a plurality of times per chip so that the range of the foamed tape bonded to the chip 22 reaches the peeling temperature.

  Then, the chip 22 whose bonding strength with the foam tape is weakened by laser irradiation is vacuum-sucked and picked up from the dicing tape 21. The above processing is performed on all the chips 22 on the wafer, and all the chips 22 are peeled off from the dicing tape 21.

  FIG. 3 is an explanatory diagram showing the relationship between the chip cracking rate and the chip thickness at the time of chip peeling. When the manufacturing process proceeds as in the first embodiment, the relationship between the chip cracking rate and the chip thickness when the individual chips are peeled from the dicing tape is shown by a black triangle plot in FIG. 3 (Example) 1).

  For comparison, when a UV tape is used as a dicing tape and the chip is picked up with tweezers after the UV tape is irradiated with the UV light, the relationship between the chip cracking ratio and the chip thickness is shown by a black square plot in FIG. This is shown (conventional example 1). Also, the relationship between the chip cracking rate and the chip thickness when a foam tape is used as the dicing tape and the chip is picked up with tweezers after the foam tape is heated is shown by a white triangle plot in FIG. 3 (conventional example 2). . Further, the relationship between the chip cracking rate and the chip thickness when the chip is pulled up from the dicing tape by peeling with a peeling tape and then picked up with the tweezers is shown in FIG. (Conventional example 3).

  As shown in FIG. 3, when the manufacturing process is advanced as in the first embodiment, even if the thickness of the chip is reduced to 50 μm, the cracking rate of the chip when peeled from the dicing tape is almost zero. Very small. On the other hand, in Conventional Example 1, when the thickness of the chip is 80 μm or less, the cracking rate exceeds 60%. Similarly, when the chip thickness is 80 μm or less, the crack rates of Conventional Example 2 and Conventional Example 3 exceed 50% and 70%, respectively.

  As described above, according to the manufacturing method according to the first embodiment, the foamed tape is used as the dicing tape, the laser beam is irradiated to each chip after dicing, the adhesive strength of the dicing tape is weakened, and vacuum adsorption is performed. To peel the chip from the dicing tape. Thereby, since it can peel from a dicing tape, without applying excessive pressure like the time of pinching with a tweezers, a chip can be prevented from cracking at the time of peeling from a dicing tape.

  Moreover, since the adhesive force of only a part of the foam tape can be weakened by irradiating the laser beam in accordance with the position of an arbitrary chip, only an arbitrary chip can be peeled from the dicing tape.

(Embodiment 2)
In the second embodiment, a case will be described in which, in the manufacturing process of the FS type IGBT, separation grooves are formed around the chips by alkali etching, and individual chips are picked up from the support members along the separation grooves.

  4-11 is a figure which shows a part of manufacturing process of the manufacturing method of the semiconductor element concerning Embodiment 2. FIGS. First, a surface-side element structure such as the surface electrode 32 is formed on the surface side of the wafer 31 (FIG. 4). Next, the back surface of the wafer 31 is ground by means such as back grinding or etching, so that the wafer 31 has a desired thickness (FIG. 5).

  Next, the wafer 31 is inverted and an etching mask 33 is formed on the back side of the wafer 31. Further, the support member 40 is bonded to the front surface side of the wafer 31 (FIG. 6). For example, a glass substrate is used as the support member 40.

  The wafer 31 and the support member 40 are bonded together with an adhesive tape 45 as shown in FIG. 7, for example. The adhesive tape 45 has a foam tape 42 bonded to one side of a PET film 41 serving as a base material, and a UV tape 43 bonded to the other side. A foam tape 42 is bonded to the wafer 31, and a UV tape 43 is bonded to the support member 40. The thickness of the PET film 41 is, for example, 100 μm, the thickness of the foam tape 42 is, for example, 50 μm, and the thickness of the UV tape 43 is, for example, 40 μm. With such an adhesive tape 45, for example, the support member 40 having a thickness of 625 μm and the wafer 31 are bonded together.

  Next, using the etching mask 33, a separation groove 34 having a V-shaped cross section on the back surface of the wafer 31 is formed, for example, by wet anisotropic etching using an alkaline solution (FIG. 8). Specifically, for example, potassium hydroxide, hydrazine, ammonia, tetramethylammonium hydroxide (TMAH), ethylenediamine, or the like can be used as the alkaline solution. The separation groove 34 is formed so that the deepest part of the separation groove 34 reaches the vicinity of the surface side of the wafer 31. Thus, since the deepest part of the separation groove 34 reaches the vicinity of the surface of the semiconductor wafer, it is possible to separate the individual chips 37 along the separation groove 34 without performing dicing.

  Next, the etching mask 33 is removed, and boron (B) is ion-implanted from the back surface of the wafer 31 as a P-type impurity. Thereafter, the back surface of the wafer 31 is irradiated with laser and annealed to form the collector layer 35 (FIG. 9). And gold | metal | money is vapor-deposited on the back surface of the wafer 31, and the back surface electrode 36 is formed (FIG. 10).

Subsequently, the individual chips 37 are peeled from the support member 40 along the separation grooves 34 (FIG. 11). Specifically, as shown in FIG. 11, the YAG laser (wavelength is selected from the support member 40 side in accordance with the position of the chip 37 to be peeled off and focused on the foam tape 42 of the adhesive tape 45 (see FIG. 7). : 1064 nm) or CO ₂ laser (wavelength: 10.64 μm). In addition, since the wavelength transmission band of the glass substrate which is the support member 40 is 0.3 μm to 2.4 μm, a YAG3ω laser (YAG laser third harmonic), a YAG2ω laser (YAG laser second harmonic), A semiconductor laser (wavelength: about 800 nm) may be used. When a CO ₂ laser is used, since the wavelength is long, for example, the laser beam may be reflected by light to be guided to a portion to be irradiated and irradiated without contact.

  Similarly to the case of the first embodiment, the laser irradiation energy only needs to reach the peeling temperature of the foam tape 42 (see FIG. 7) of the adhesive tape 45. Further, similarly to the first embodiment, the laser spot size is preferably adjusted according to the size of the chip 37 to be peeled off, so that the peeling temperature is reached by one laser irradiation. Alternatively, the spot diameter pulse irradiation may be performed a plurality of times per chip so that the range of the foam tape 42 bonded to the chip 47 reaches the peeling temperature.

  Then, the chip 37 whose bonding force with the foam tape 42 is weakened by laser irradiation is vacuum-sucked and picked up from the support member 40. The above processing is performed on all the chips 37 on the wafer, and all the chips 37 are peeled off from the support member 40.

  When the manufacturing process proceeds as in the second embodiment, the relationship between the chip cracking rate and the chip thickness when the individual chips are peeled off from the support member is shown by a white circle in FIG. 3 (Example) 2). As shown in FIG. 3, when the manufacturing process is advanced as in the second embodiment, the chip when peeled off from the support member, even if the thickness of the chip is reduced to 50 μm, as in the first embodiment. The cracking rate is extremely small, almost zero.

  As described above, according to the manufacturing method according to the second embodiment, foaming tape is used to bond the support member and the wafer, and foaming is performed by irradiating laser light to each chip after forming the separation groove. The adhesive strength of the tape is weakened, and the chip is peeled from the support member by vacuum suction. Thereby, like Embodiment 1, since a chip | tip can be peeled from a supporting member, without applying excessive pressure like the time of pinching with tweezers, it can prevent that a chip | tip breaks. Moreover, only an arbitrary chip can be peeled from the support member.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a semiconductor device having a thin device thickness. In particular, a general-purpose inverter, AC servo, uninterruptible power supply (UPS), switching power supply, etc. It is suitable for manufacturing power semiconductor elements such as IGBTs used in industrial fields and consumer equipment fields such as microwave ovens, rice cookers or strobes.

FIG. 6 is a diagram showing a part of the manufacturing process of the semiconductor element manufacturing method according to the first exemplary embodiment; FIG. 6 is a diagram showing a part of the manufacturing process of the semiconductor element manufacturing method according to the first exemplary embodiment; It is explanatory drawing which shows the relationship between the crack rate of the chip | tip at the time of chip | tip peeling, and the thickness of a chip | tip. FIG. 10 is a diagram showing a part of the manufacturing process of the semiconductor element manufacturing method according to the second exemplary embodiment; FIG. 10 is a diagram showing a part of the manufacturing process of the semiconductor element manufacturing method according to the second exemplary embodiment; FIG. 10 is a diagram showing a part of the manufacturing process of the semiconductor element manufacturing method according to the second exemplary embodiment; FIG. 10 is a diagram showing a part of the manufacturing process of the semiconductor element manufacturing method according to the second exemplary embodiment; FIG. 10 is a diagram showing a part of the manufacturing process of the semiconductor element manufacturing method according to the second exemplary embodiment; FIG. 10 is a diagram showing a part of the manufacturing process of the semiconductor element manufacturing method according to the second exemplary embodiment; FIG. 10 is a diagram showing a part of the manufacturing process of the semiconductor element manufacturing method according to the second exemplary embodiment; FIG. 10 is a diagram showing a part of the manufacturing process of the semiconductor element manufacturing method according to the second exemplary embodiment; It is sectional drawing which shows the structure for 1/2 cell of NPT type IGBT which has a shallow p <+> collector layer of a low dose amount. It is sectional drawing which shows the structure for 1/2 cell of FS type IGBT. It is sectional drawing which shows the structure for 1/2 cell of reverse blocking IGBT. It is a figure which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is a figure which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is a figure which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is a figure which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is a figure which shows the manufacturing process of FS type IGBT using the conventional FZ wafer.

Explanation of symbols

21 Dicing tape 22 Chip 31 Wafer 32 Surface electrode 33 Etching mask 34 Separation groove 35 Collector layer 36 Back surface electrode 37 Chip 40 Support member 41 PET film 42 Foam tape 43 UV tape 45 Adhesive tape

Claims (9)

Forming a device structure on a semiconductor wafer;
A bonding step of bonding a support member that can be peeled off by heating to the surface of the semiconductor wafer on which the element structure is formed,
A separation step of bringing the semiconductor wafer into a substantially separable state in a state where the support member is bonded;
A heating step of individually heating portions corresponding to the individual chips of the support member;
A separation step of adsorbing the chip bonded to the portion heated in the heating step of the support member and peeling the chip from the support member;
The manufacturing method of the semiconductor element characterized by the above-mentioned.   The method for manufacturing a semiconductor element according to claim 1, wherein the support member is a surface protective sheet having an adhesive layer that can be peeled off by heating.   3. The method of manufacturing a semiconductor element according to claim 2, wherein in the separating step, the semiconductor wafer is separated into individual chips by dicing in a state where the surface protection sheet is bonded.   The method for manufacturing a semiconductor element according to claim 1, wherein the support member is a glass substrate that is bonded to the semiconductor wafer through an adhesive layer that can be peeled off by heating.   In the separation step, the semiconductor wafer is substantially separated into individual chips by forming a separation groove from the back surface of the semiconductor wafer so as to substantially reach the surface of the semiconductor wafer with the support member bonded. The method of manufacturing a semiconductor device according to claim 4.   The method for manufacturing a semiconductor element according to claim 2, wherein the adhesive layer is an adhesive sheet that can be peeled off by heating and foaming.   The said formation process includes the process of grinding the back surface of the said semiconductor wafer, The manufacturing method of the semiconductor element as described in any one of Claims 1-6 characterized by the above-mentioned. In the heating step, the portion of the adhesive layer that is bonded to the arbitrary chip is irradiated with a laser beam and heated,
The method of manufacturing a semiconductor element according to claim 2, wherein in the peeling step, the chip bonded to the portion irradiated with the laser beam is peeled off. 9. The method of manufacturing a semiconductor element according to claim 8, wherein the heating step irradiates a laser beam in an irradiation range that substantially matches a size of the chip.

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