JP2007318290A - Semiconductor integrated circuit for communication - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the circuit scale of a compensation circuit for reducing the phase noise of a PLL circuit and simplifies control for the compensation circuit, while alleviating non-linear effect resulting from mismatch between a source current injection transistor and a sink current discharge transistor at a charge pump circuit CPC of the PLL circuit, wherein the PLL circuit is a fractional N PLL circuit included in a semiconductor integrated circuit for RF communication as a frequency synthesizer in use for transmitting/receiving operation. <P>SOLUTION: A closed loop band of a fractional N PLL circuit is set to narrow bands of dozens of kHz order, as a frequency synthesizer Frct_Synth in use for transmitting/receiving operation. Alleviation of non-linear effect resulting from mismatch between two transistors at a charge pump circuit CPC can be actualized by a simplest method, injecting dc current Ioffset into a loop filter LFC by offset circuits MN2 and MN3 or discharging Ioffset from the LFC. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit for RF communication including a fractional N PLL (Phase Locked Loop) circuit in which a frequency division ratio N includes not only an integer but also a fraction (decimal number), and particularly used for a reception operation and a transmission operation. In a semiconductor integrated circuit for RF communication equipped with a fractional N PLL circuit as a frequency synthesizer, the influence of nonlinearity due to mismatch between the source current injection transistor and the sink current emission transistor of the charge pump circuit CPC of the fractional N PLL circuit is reduced. On the other hand, the present invention relates to a technique useful for reducing the circuit scale of the compensation circuit for reducing the phase noise of the fractional N PLL circuit and simplifying the control of the compensation circuit.

In a general PLL circuit with only an integer division ratio, the frequency resolution of the locked loop is the reference frequency f _REF , so that a small reference frequency f _REF is required when precise frequency resolution is required, and thus a small (narrow) ) Loop frequency band. A narrow loop frequency band is not desirable because it takes a long switching time to determine the lock frequency of the PLL circuit, and the phase noise of the voltage controlled oscillator (VCO) of the PLL circuit is not sufficiently suppressed, and the influence of noise from outside the PLL circuit is Easy to receive.

The fractional synthesizer was developed to have a finer frequency resolution than the reference frequency f _REF . In the fractional N divider, the division ratio is periodically changed from N to N + 1, and as a result, the average division ratio is greater than N. Also increases by the duty ratio of (N + 1) division. The overflow from the accumulator is used to modulate the instantaneous division ratio.

  Thus, in the fractional PLL circuit, the frequency division ratio N of the frequency divider in the negative feedback loop of the PLL circuit is a rational number including not only an integer but also a fraction (decimal number). This fractional N division allows a wide loop bandwidth for a given channel spacing to allow for fast settling times and lower phase noise requirements for voltage controlled oscillators. Non-Patent Document 1 below discloses a dual coefficient divider having a division ratio of n / n + 1 related to a cumulative adder (accumulator) of a primary ΔΣ modulator (also referred to as a ΣΔ modulator). ) Is described. The cumulative adder overflow condition is used to shift to n + 1 division. Further, Non-Patent Document 2 below reports that the spurious output frequency in the fractional N frequency synthesis is also reduced by the high order noise shaving technique using the high order ΔΣ modulation for the fractional N division.

  Further, Non-Patent Document 3 below reports a fractional N frequency synthesizer using MASH (Multistage Noise Shaping Technique) in which a plurality of primary ΣΔ modulators are multistage.

Non-Patent Document 4 below describes a fractional N frequency in a 700 KHz frequency band employing spurious noise compensation and linearization technology for use in an RF semiconductor integrated circuit for WCDMA (Wide Band Channel-Division Multiple Access) applications. A synthesizer is described. This RF semiconductor integrated circuit employs a direct modulation transmission system in a wide band. Further, the closed loop bandwidth of the fractional PLL circuit is 700 KHz, which is an extremely wide bandwidth. Further, the phase comparator of this fractional N frequency synthesizer includes an up flip-flop in which the power supply voltage V _DD is supplied to the data input terminal and the reference frequency signal is supplied to the clock input terminal, and the power supply voltage V There are two down flip-flops to which _DD is supplied and the frequency division output signal from the frequency divider is supplied to the clock input terminal, the output signal of the up flip-flop and the output signal of the down flip-flop. An AND circuit supplied to the input terminal and a delay circuit supplied with an output signal of the AND circuit are included. The output signal of the delay circuit is supplied to the reset input terminal of the up flip-flop and the reset input terminal of the down flip-flop. The gate input terminal of the P-channel MOS transistor of the charge pump circuit that supplies the source current to the low-pass filter that generates the phase control voltage for controlling the oscillation frequency of the voltage-controlled oscillator is driven by the output signal of the flip-flop for up-pass. The gate input terminal of the N-channel MOS transistor for passing a sink current from the filter is driven by the output signal of the down flip-flop. This Non-Patent Document 4 describes that the nonlinearity in the PLL building block is mainly the input / output characteristics of the phase comparator and the charge pump circuit, and in particular, increases the in-band spurious noise of the fractional PLL circuit. Non-Patent Document 4 describes that typical nonlinearity between the phase comparator and the charge pump circuit is caused by a mismatch between the P-MOS and the N-MOS of the charge pump circuit. Further, Non-Patent Document 4 describes that other nonlinearity is indicated by the phase difference ΔΦ versus the injected charge Q especially when the phase difference is small. Non-Patent Document 4 describes that in order to completely avoid the influence of this non-linearity, the phase comparator and the charge pump circuit are operated in their more linear portions. Furthermore, Non-Patent Document 4 describes that the simplest way to achieve this is to inject a dc direct current into the loop filter, but has the disadvantage of enhancing the reference spurious noise. Further, Non-Patent Document 4 discloses that a better solution is a periodic current synchronized with the comparison edge of the phase comparator input with a long pulse width so that the phase comparator and the charge pump circuit operate outside the nonlinear portion. It is described that the pulse is injected into the loop filter.

  Further, the following Non-Patent Document 5 describes a charge pump linearization technique in which an additional pulse source current and an additional pulse sink current that are similar to the injection of the periodic current pulse into the loop filter described in Non-Patent Document 4 are passed through the loop filter. And phase noise cancellation technology is introduced. As a result, in a local oscillator for a CMOS ΔΣ fractional-N PLL configured as a Bluetooth-compliant wireless LAN (Local Area Network) transmitter and a direct-conversion Bluetooth-compliant receiver, a required 1-Mb / s transfer signal is transmitted. It reports that it has achieved the required specifications for phase noise and spurious characteristics with a sufficiently wide 460 KHz bandwidth that allows modulation within the loop.

Brian Miller and Robert J.M. Conley “A Multiple Modulator Fractional Divider”, IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 40. NO. 3. JUNE 1991. PP. 578-583. Tom A. D. Riley et al “Delta-Sigma Modulation in Fractional-N Frequency Synthesis”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28. NO. 5. MAY 1993. PP. 553-559. A. E. Hussein and M.M. I. Elmasry "A FRACTIONIONAL-N FREQUENCY SYNTHESIZER FOR WIRELESS COMMUNICATIONS", 2002 IEEE International Symposium Circuits and Systems, PP. IV-513-IV-516. Enrico Temporiti et al, “A 700-kHz Bandwidth ΣΔ Fractional Synthesizer With Spur Compensation and Linearization Technologies for WCDMA Applications I WID 39. NO. 9. SEPTEMBER 2004. PP. 1446-1454. Sudhakar Parmarti et al, “A Wideband 2.4-GHz Delta-Sigma Fractional-N PLL With 1-Mb / s In-Loop Modulation,” IEEE JOUNAL OF SOLIT SOLITOLS 39. NO. 1. JANUARY 2004. PP. 49-62.

  Prior to the present invention, the inventors engaged in the development of an RF IC corresponding to GSM communication.

  The GSM system (Global System for Mobile Communication) is a communication system that performs GMSK (Gaussian minimum Shift Keying) modulation using only phase modulation as one of TDMA systems. TDMA is an abbreviation for Time-Division Multiple Access. In the TDMA system, each time slot of the plurality of time slots of the mobile phone terminal device can be set to any of an idle state, a reception operation from the base station, and a transmission operation to the base station. A method for improving a communication data transfer rate as compared with the GSM method is also known. As an improvement method, an EDGE (Enhanced Data for GSM Evolution) method that uses amplitude modulation as well as phase modulation has recently been attracting attention. GPRS is an abbreviation for General Packet Radio Service.

This RF IC fractional PLL circuit is based on a reference oscillation frequency f _REF of a reference frequency oscillator DCXO that generates a stable and accurate reference signal by a crystal oscillator and an automatic frequency control (AFC) signal from a baseband LSI. An oscillation frequency f _TXVCO of the transmission voltage controlled oscillator _TXVCO is generated. An RF IC corresponding to a recent GSM communication system is configured to correspond to four frequency bands of GSM850 MHz, GSM900 MHz, DCS1800 MHz, and PCS1900 MHz. Therefore, the oscillation frequency f _{TXVCO of} the RF transmission voltage controlled oscillator TXVCO must also correspond to these four frequency bands. The reference oscillation frequency f _REF of the RF IC reference frequency oscillator DCXO is on the order of several tens of MHz, whereas the oscillation frequency f _TXVCO of the RF transmission voltage controlled oscillator TXVCO corresponding to a plurality of frequency bands is several GHz. The frequency of the order. That is, compared with the reference oscillation frequency f _REF of the reference frequency oscillator DCXO, the oscillation frequency f TXVCO from the RF transmission voltage control oscillator _TXVCO is a much higher frequency. As described above, the RF IC fractional PLL circuit performs a frequency multiplication by multiplying the reference oscillation frequency f _REF in the order of several tens of MHz of the reference frequency oscillator DCXO by a frequency multiplication ratio that is a reciprocal of the fractional N division ratio. A reference oscillation frequency f _TXVCO of the RF transmission voltage controlled oscillator TXVCO of the order of GHz is generated.

  FIG. 1 is a diagram showing a configuration of a fractional synthesizer Frct_Synth formed on a chip of a communication semiconductor integrated circuit RF IC examined by the present inventors prior to the present invention.

As shown in the figure, the fractional synthesizer Frct_Synth is a reference frequency set to a stable and accurate reference oscillation frequency f _REF by a crystal resonator Xtal and an automatic frequency control (AFC) signal from a baseband LSI not shown. An oscillator DCXO is included. The reference oscillation frequency f _REF is set to a frequency of 26 MHz, for example. The reference frequency signal of the reference oscillation frequency f _REF from the reference frequency oscillator DCXO is supplied to one input terminal of the phase comparator PDC of the fractional PLL circuit. The output of the phase comparator PDC is supplied to the RF voltage controlled oscillator RFVCO via the charge pump circuit CPC and the low pass filter LFC. The output of the RF voltage controlled oscillator RFVCO is supplied to the input of the frequency divider DIV, and the frequency division output signal of the frequency divider DIV is supplied to the other input terminal of the phase comparator PDC. A control input terminal for controlling the frequency division ratio of the frequency divider DIV is connected to a frequency division ratio setting logic DRSL. The frequency division ratio setting logic DRSL has channel selection information for RF communication from a baseband LSI (not shown). Channel_inf is supplied. The frequency divider DIV is composed of a counter, and is set, for example, as a control input terminal for controlling the frequency division ratio by counting up the change from low level to high level of the output of the RF voltage controlled oscillator RFVCO from zero. The frequency division output signal of the frequency divider DIV is changed from the low level to the high level at a frequency of a value obtained by subtracting 1 from the value. When the frequency-divided output signal of the frequency divider DIV becomes high level, the count value of the counter is set to zero by the change of the output of the next RF voltage controlled oscillator RFVCO from low level to high level, and the frequency of the frequency divider DIV is divided. The frequency output signal is returned to the low level, and the next frequency division operation is executed. The frequency division ratio setting logic DRSL includes a frequency division ratio calculator DRALU, a ΣΔ modulator ΣΔMod, and an adder ADD. First, the integer unit Int and the fractional unit Fra of the frequency division ratio calculator DRALU calculate integer value information I and fractional value information F based on the input channel selection information Channel_inf. The integer value information I from the integer unit Int of the division ratio calculator DRALU is supplied to one input terminal of the adder ADD, and the fractional value information F from the fraction unit Fra of the division ratio calculator DRALU is supplied to the ΣΔ modulator ΣΔMod. It is supplied to the reference frequency signal from the reference frequency oscillator DCXO the ΣΔ modulator ΣΔMod is further supplied as f _REF is the operating clock signal. On the other hand, the ΣΔ modulator ΣΔMod holds denominator information G for setting a frequency division ratio as internal information. As an example, the denominator information G is set to 1625. The ΣΔ modulator ΣΔMod generates an output signal F / G having fractional value information F / denominator information G, for example, 403/1625 fraction information from fractional value information F and denominator information G, The other input terminal of the adder ADD is supplied. The adder ADD sets the output information of the integer value information I (for example, I = 137) and the output signal F / G to I + F / G, for example, 137+ (403/1625) = 137.248 as the average division ratio N. Supply to frequency divider DIV. As a result, the average frequency division ratio of the frequency divider DIV is set to a value including 137.248, an integer and a fraction (decimal number). Thus, the fractional examination constellation Frct_Synth the RF oscillation output signal of the oscillation frequency _{f RFVCO} of 3568.448MHz that the 26MHz reference oscillation frequency _{f REF} by multiplying the average frequency division ratio N (137.248) from the reference frequency oscillator DCXO Generate. Further, the average frequency division ratio N will be described in detail. The frequency according to the integer value information I (I = 137) from the integer unit Int of the frequency division ratio calculator DRALU and the output signal F / G from the ΣΔ modulator ΣΔMod. In response to the overflow and 1-bit output generated at (403/1625), the frequency division ratio n of the frequency divider DIV is changed from n (= I = 137) to n + 1 (= I + 1 = 138). Therefore, the frequency at which the frequency division ratio of the frequency divider DIV is n (= I = 137) is 1222/1652 = 75.2%, and the frequency division ratio of the frequency divider DIV is n + 1 (= I + 1 = 138). The frequency is 403/1625 = 24.8%. Therefore, the average frequency division ratio N is 137 × 0.752 + 138 × 0.248 = 137.248.

  FIG. 2 is a diagram showing a configuration of the ΣΔ modulator ΣΔMod of the fractional synthesizer Frct_Synth shown in FIG.

  As shown in the figure, the fractional value information F from the fractional unit Fra of the frequency division ratio calculator DRALU is supplied as an input signal (A) to one input terminal of the first adder Sum1, while the first adder An output signal (C) of a second adder Sum2 described later is supplied to the other input terminal of Sum1. The output signal of the first adder Sum1 is supplied to a delay circuit as an integrator Ingtgrtr, and the output signal (B) of the integrator Ingtgrtr is supplied to the input of a quantizer qntzr having a 1-bit output. The output signal (D) of the quantizer qnttzr is supplied to the input of a feedback circuit fbc having a predetermined gain 1 / G. The reciprocal G of the gain 1 / G corresponds to denominator information G (for example, G = 1625) in which the ΣΔ modulator ΣΔMod sets a division ratio as internal information. Therefore, in the non-overflow state where the 1-bit output signal (D) of the quantizer qnttzr is “0”, the output of the feedback circuit fbc is zero, and the 1-bit output signal (D) of the quantizer qntzr is “1”. In the state, the output of the feedback circuit fbc is 1625. Therefore, the feedback circuit fbc operates as a 1-bit D / A converter. Accordingly, when an overflow state occurs in which the 1-bit output signal (D) of the quantizer qntzr is “1”, the second adder Sum2 outputs the output 1625 of the feedback circuit fbc from the cumulative addition of the output signal (B) of the integrator Ingtgrtr. Subtraction is performed. Further, the output signal (C) of the second adder Sum2 is supplied to the other input terminal of the first adder Sum1. The 1-bit output signal (D) of the quantizer qntzr indicating the non-overflow state / overflow state is supplied to the adder ADD as the output signal F / G of the ΣΔ modulator ΣΔMod.

  FIG. 3 is a diagram showing an operation of the ΣΔ modulator ΣΔMod of the fractional synthesizer Frct_Synth shown in FIG. The labels (A) to (D) in FIG. 3 correspond to the signals (A) to (D) in FIG.

As shown in FIG. 1, the ΣΔ modulator ΣΔMod is supplied with a reference frequency signal having a reference frequency f _REF from the reference frequency oscillator DCXO as an operation clock signal. Further, as shown in FIG. 3A, fractional value information F is steadily supplied as an input signal (A) to one input terminal of the first adder Sum1 of the ΣΔ modulator ΣΔMod. Therefore, one cumulative addition result is obtained from the output of the integrator Ingtgrtr in one cycle of the operation clock signal. As shown in FIG. 3B, the fifth cumulative addition result is obtained from the output signal (B) of the integrator Intgrtr in the fifth cycle of the operation clock signal. Further, as shown in FIG. 3D, an overflow state of “1” appears in the 1-bit output signal (D) of the quantizer qntzr in the fifth cycle of the operation clock signal. Then, as shown in FIG. 3C, in the second adder Sum2, the output 1625 of the feedback circuit fbc is subtracted from the cumulative addition of the output of the integrator Intgrtr to generate the output signal (C). . The quantizer qnttzr outputs a 1-bit output signal in a non-overflow state of “0” when the input signal is 0 to 1624, while “0” when the input signal is 1625 or larger. A 1-bit output signal in an overflow state of 1 ″ is output. The above operation is repeated in response to the operation clock signal f _REF, and the 1-bit output signal in the overflow state of “1” is quantized at the frequency of the fraction information F / G (403/1625) from the ΣΔ modulator ΣΔMod. Generated from the generator qntzr.

  The output signal (D) of the quantizer qntzr shown in FIG. 2, that is, the 1-bit output signal F / G of the ΣΔ modulator ΣΔMod is supplied to the adder ADD of the frequency division ratio setting logic DRSL of FIG. Is added to the integer value information I supplied from the integer unit Int of the division ratio calculator DRALU. In the non-overflow state where the 1-bit output signal of the ΣΔ modulator ΣΔMod is “0”, the frequency division ratio n of the frequency divider DIV of the fractional synthesizer Frct_Synth is set to integer value information I (I = 137), and the ΣΔ modulator ΣΔMod In the overflow state of the 1-bit output signal of “1”, the frequency division ratio of the frequency divider DIV of the fractional synthesizer Frct_Synth is set to (n + 1) (= (I + 1) = 138), and as a result, the average frequency division ratio N is 137.248.

  FIG. 4 is a diagram showing a MASH type ΣΔ modulator ΣΔMod configured by MASH (Multistage Noise Shaping Technique) used in the fractional synthesizer Frct_Synth of FIG. The MASH type ΣΔ modulator is a multi-stage connection of a first-order ΣΔ modulator, and an n-order ΣΔ modulation noise / shaving characteristic is obtained.

  As shown in the figure, the ΣΔ modulator in the first stage is similar to the ΣΔ modulator ΣΔMod shown in FIG. 2, an adder Sum11, a delay circuit as an integrator Ingtgrtr11, a 1-bit output quantizer qntzr1, a gain A feedback circuit fbc1 having 1 / G and an adder Sum12 are included, and the output of the quantizer qntzr1 is transmitted to the adder Sum13 of the output F / G via the integrator Ingtgrtr12. The output of the adder Sum12 of the first stage ΣΔ modulator is transmitted to the second stage ΣΔ modulator. Similar to the first-stage ΣΔ modulator, the second-stage ΣΔ modulator includes an adder Sum21, a delay circuit as an integrator Ingtgrtr21, a 1-bit output quantizer qntzr2, and a feedback circuit fbc2 having a gain 1 / G. , An adder Sum22, an integrator Intgrtr22, and an adder Sum23, and a digital differentiator dif11 connected between the output of the adder Sum23 and the input of the adder Sum13. The output of the adder Sum22 of the second stage ΣΔ modulator is transmitted to the third stage ΣΔ modulator. The third-stage ΣΔ modulator includes an adder Sum31, a delay circuit as an integrator Ingtgrtr31, a 1-bit output quantizer qnttzr3, a feedback circuit fbc3 having a gain 1 / G, and an adder Sum32, and includes a quantizer qntzr3 Is transmitted to the adder Sum23 via the digital differentiator dif21.

  The ΣΔ modulator ΣΔMod shown in FIG. 4 is a third-order ΣΔ modulator, which is in principle the same as the higher-order ΣΔ modulator ΣΔMod reported in Non-Patent Document 3 above, The shaving characteristics can be improved. This high-order ΣΔ modulator ΣΔMod is not limited to a third-order ΣΔ modulator, and a third-order to fifth-order ΣΔ modulator can be used.

  As shown in FIG. 4, another adder Sum0 is connected between the input terminal to which the fractional value information F is supplied and the input of the adder Sum11 of the first-stage ΣΔ modulator. The fractional value information F is supplied to one input terminal of the adding unit Sum0, and the pseudo random noise from the output of the dither dither is supplied to the other input terminal of the adding unit Sum0 by the digital differentiator diff31 and the gain (1) 1) is transmitted.

FIG. 5 is a diagram showing a circuit configuration of the dither dither shown in FIG. As shown in the figure, the dither dither includes five stages of delay circuits D1 to D5, exclusive OR circuit EXOR1, three stages of delay circuits D6 to D8, exclusive OR circuit EXOR2, and four stages of delay circuits D9 to D12. The exclusive OR circuit EXOR3 comprises two delay circuits D13 and D14. By inputting the initial value to the first-stage delay circuit D1, the output of the last-stage delay circuit D14 is fed back to the input of the first-stage delay circuit D1. The output of this dither dither is pseudo-random noise of a 1-bit stream of “0” and “1” having 2 ¹⁵ −1 combinations. As a result, the output of the digital differentiator diff31 connected to the output of the dither dither is either +1, 0, or -1, but +1 is not output continuously and -1 is not output continuously. In the high-order ΣΔ modulator ΣΔMod (for example, the third-order ΣΔ modulator) shown in FIG. A spurious signal is generated due to a periodic change in the frequency division ratio of the circuit of the device ΣΔMod. In order to reduce this spurious signal, the dither amplitude from the dither dither connected to the other input terminal of the adding unit Sum0 in FIG. 4 is set to an appropriate value. As a result, the pseudo random noise disturbs the noise (fractional noise) caused by the periodic division ratio change in the circuit of the higher-order ΣΔ modulator ΣΔMod, and further frequency-converts the spurious signal that is frequency-converted during dithering. . As a result, it is possible to reduce the level of the spurious signal in the 400 KHz frequency band which is strict with the transmission modulation spectrum standard defined by the GMSK (Gaussian minimum Shift Keying) standard.

  FIG. 6 is a diagram illustrating a circuit configuration of the phase comparator PDC, the charge pump circuit CPC, and the low-pass filter LFC of the fractional synthesizer Frct_Synth of FIG. When the control output voltage VCNT from the low pass filter LFC increases, the frequency of the output signal of the RF voltage controlled oscillator RFVCO increases.

As shown in the figure, the phase comparator PDC includes an up flip-flop FF_Up in which the power supply voltage V _DD is supplied to the data input terminal and the reference frequency signal V _REF from the reference frequency oscillator DCXO is supplied to the clock input terminal. And the output of the down flip-flop FF_Dn whose power input voltage V _DD is supplied to the data input terminal and the divided output signal V _DIV from the frequency divider DIV is supplied to the clock input terminal, and the output of the up flip-flop FF_Up It includes a NAND circuit in which the signal Q and the output signal Q of the down flip-flop FF_Dn are supplied to two input terminals, and a delay circuit Dly_Cir to which the output signal of the NAND circuit is supplied. The output signal VR of the delay circuit Dly_Cir is supplied to the reset input terminal / _R of the up flip-flop FF_Up and the reset input terminal / R of the down flip-flop FF_Dn. Voltage controlled oscillator RFVCO oscillation frequency gate input terminal of the charge supplying a source current Isource to the low pass filter LFC for generating a phase control voltage for controlling the _{f RFVCO} pump circuit CPC of P-channel MOS transistor MP1 of the flip-flop FF_Up for up The gate input terminal of an N-channel MOS transistor MN1 that is controlled by a switch driven by an output signal Q (V _QREF ) and flows a sink current I sink from a low-pass filter LFC is an output signal Q (V _QDIV ) of a down flip-flop FF_Dn. Controlled by a driven switch. The low-pass filter LFC is composed of a high-order (third-order) loop filter including a plurality of resistors R1 and R2 and a plurality of capacitors C1, C2, and C3. The source current Isource and the sink current I sink of the charge pump circuit CPC drive one end of the capacitor C1, one end of the resistor R1, and one end of the resistor R2. Control output voltage VCNT for controlling the oscillation frequency _{f RFVCO} of the voltage controlled oscillator RFVCO from one end of the connection node between the other end and the capacitor C3 of the resistor R2 is generated.

FIG. 7 shows an ideal state in which the current value of the source current Isource of the P-channel MOS transistor MP1 of the charge pump circuit CPC is equal to the current value of the sink current Isink of the N-channel MOS transistor MN1 in the fractional synthesizer Frct_Synth of FIG. The phase comparator PDC and the charge pump circuit CPC in the unlocked state when the phase of the divided output signal V _DIV from the frequency divider DIV is ahead of the phase of the reference frequency signal V _REF from the reference frequency oscillator DCXO It is a figure which shows the waveform of each part. In the fractional synthesizer Frct_Synth of FIG. 1, it is assumed that a fixed value is supplied to the control input terminal that controls the frequency division ratio of the frequency divider DIV.

As shown in FIG. 7, the output signal V _qdiv flip flop FF_Dn for down substantially in synchronism from the divided output signal V _DIV of low level to rise to a high level is changed from a low level to a high level, up Flip-flop FF_Up is controlled to the set state. Substantially synchronous with the flip-flop FF_Dn the set state for the down output signal V _QREF of flip-flop FF_Up is changed from a low level to a high level for up to rise from the low level of the subsequent reference frequency signal V _REF to a high level To be controlled. After the lapse of the delay time T_Dly of the delay circuit Dly_Cir the output signal _{V qdiv} the output signal _{V QREF} is turned both high level, the reset signal _{V R} of low level is generated from the delay circuit Dly_Cir. Then, the reset signal _{V R} of low level, and the flip-flop FF_Dn for flip flop FF_Up and down for up is controlled in the reset state. During the set state of the up flip-flop FF_Up, the switch SW connected to the P-channel MOS transistor MP1 of the charge pump circuit CPC is turned off, and the source current Isource from the P-channel MOS transistor MP1 is supplied to the low-pass filter LFC. Flowing. During the period when the down flip-flop FF_Dn is set, the switch SW connected to the N-channel MOS transistor MN1 of the charge pump circuit CPC is turned off, and the sink current Isink is supplied from the low-pass filter LFC to the N-channel MOS transistor MN1. Flowing. When the phase of the divided output signal V _DIV is ahead of the phase of the reference frequency signal V _REF, the period in which the sink current I sink flows is longer than the period in which the source current I source flows, and the total charge pump current I _CP Becomes a negative current due to the sink current I sink of the N-channel MOS transistor MN1. Therefore, decreases the oscillation frequency _{f RFVCO} of the voltage controlled oscillator RFVCO level of the control output voltage VCNT generated from the low-pass filter LFC is reduced, the phase of the divided output signal _{V DIV} starts late. Eventually, the phase of the _divided output signal V _DIV matches the phase of the reference frequency signal V _REF , and the state is shifted to the locked state.

FIG. 8 shows an ideal state in which the current value of the source current Isource of the P-channel MOS transistor MP1 of the charge pump circuit CPC is equal to the current value of the sink current I sink of the N-channel MOS transistor MN1 in the fractional synthesizer Frct_Synth of FIG. The phase comparator PDC and the charge pump circuit CPC in the locked state in which the phase of the reference frequency signal V _REF from the reference frequency oscillator DCXO and the phase of the divided output signal V _DIV from the divider DIV match. It is a figure which shows the waveform of each part. In this case as well, in the fractional synthesizer Frct_Synth of FIG. 1, it is assumed that a fixed value is supplied to the control input terminal for controlling the frequency division ratio of the frequency divider DIV.

As shown in FIG. 8, the period during which the source current Isource flows is equal to the period during which the sink current I sink flows, and the total charge pump current I _CP becomes zero. Accordingly, the level of the control output voltage VCNT generated from the low pass filter LFC is maintained. Eventually, the state in which the phase of the reference frequency signal V _REF matches the phase of the _divided output signal V _DIV is maintained.

FIG. 9 shows a realistic state where the current value of the sink current I sink of the N-channel MOS transistor MN1 is smaller than the current value of the source current I source of the P-channel MOS transistor MP1 of the charge pump circuit CPC in the fractional synthesizer Frct_Synth of FIG. The phase comparator PDC and the charge pump in the locked state with a phase difference offset in which the phase of the frequency-divided output signal V _DIV from the frequency divider DIV is ahead of the phase of the reference frequency signal V _REF from the reference frequency oscillator DCXO It is a figure which shows the waveform of each part of the circuit CPC. In this case as well, in the fractional synthesizer Frct_Synth of FIG. 1, it is assumed that a fixed value is supplied to the control input terminal for controlling the frequency division ratio of the frequency divider DIV. In the RF IC, the drain-source voltage V _DS -drain current _ID of the P-channel MOS transistor is higher than the constant-current characteristic of the drain-source voltage V _DS -drain current _ID of the N-channel MOS transistor. The constant current characteristics are inferior. That is, in the N-channel MOS transistors, whereas the Δ variation _{I D} of the drain current _{I D} is smaller relative variation [Delta] V _DS of the drain-source voltage _{V DS,} the P-channel MOS transistors, the variation of the drain-source voltage _{V DS} [Delta] V Δ variation _{I D} of a drain current _{I D} with respect to _DS is large. As a result, the current value of the source current Isource of the P channel MOS transistor MP1 becomes larger than the current value of the sink current I sink of the N channel MOS transistor MN1.

As shown in FIG. 9, as compared with the locked state of FIG. 8, since the sink current I sink of the N-channel MOS transistor MN1 is small, the period in which the sink current I sink flows is longer than the period in which the source current I source flows. In FIG. 9, the area of the shortage A from the ideal current value of the sink current I sink is equal to the area B of the extension of the period during which the sink current I sink flows. Therefore, the time integration value of the source current Isource and the time integration value of the sink current I sink are equal, and the total charge pump current I _CP becomes zero. Accordingly, the level of the control output voltage VCNT generated from the low pass filter LFC is maintained. Eventually, the locked state with the phase difference offset in which the phase of the peripheral output signal V _DIV is advanced from the phase of the reference frequency signal V _REF is maintained.

FIG. 10 shows a realistic state in which the current value of the sink current I sink of the N channel MOS transistor MN1 is smaller than the current value of the source current I source of the P channel MOS transistor MP1 of the charge pump circuit CPC in the fractional synthesizer Frct_Synth of FIG. FIG. 10 is a diagram illustrating waveforms of respective parts of the phase comparator PDC and the charge pump circuit CPC when the frequency division ratio of the frequency divider DIV is changed from a high frequency division ratio to a low frequency division ratio. When the high-order MASH type ΣΔ modulator as shown in FIG. 4 is used for the fractional PLL, not only high-order ΣΔ modulation noise shaping characteristics can be obtained, but also the amount transmitted from the quantizers qntzr1, qntzr2, and qntzr3. The ratio change value is also high. That is, if the order of the MASH type ΣΔ modulator as shown in FIG. 4 is N, the division ratio change value is ^2N . If N = 3, the frequency division ratio change value is a large value of 8. Assume that the division ratio of the fractional frequency divider DIV is changed from a high division ratio N + 8 to a low division ratio N. In the fractional PLL, as will be described below, an average desired fraction is obtained by always performing control to increase or decrease the frequency of the oscillation output signal of the voltage controlled oscillator RFVCO from the locked state with phase difference offset. A division ratio including (decimal number) and an oscillation period are obtained.

As shown in FIG. 10, since the frequency division ratio is changed to a low frequency division ratio N, the timing of finishing the count-up of the frequency divider DIV in the fractional synthesizer Frct_Synth of FIG. by comparison, the timing of the divided output signal V _DIV from the frequency divider DIV changes from low level to high level is accelerated by [Delta] T. 10, since a flip-flop FF_Dn for flip flop FF_Up and down for up generates timing of the reset signal _{V R} of low level controlled by the reset condition is determined by the delay time T_Dly by the delay circuit Dly_Cir, FIG it is identical to the generation timing of the low-level reset signal V _R at the 9. Therefore, the period in which the sink current I sink flows is longer than the period in which the source current I source flows, and the total charge pump current I _CP becomes a negative current due to the sink current I sink of the N-channel MOS transistor MN1. Therefore, decreases the oscillation frequency _{f RFVCO} of the voltage controlled oscillator RFVCO level of the control output voltage VCNT generated from the low-pass filter LFC is reduced, controlled so that the oscillation period of the oscillation output signal of the voltage controlled oscillator RFVCO longer Is done.

FIG. 11 shows a realistic state in which the current value of the sink current I sink of the N channel MOS transistor MN1 is smaller than the current value of the source current I source of the P channel MOS transistor MP1 of the charge pump circuit CPC in the fractional synthesizer Frct_Synth of FIG. FIG. 10 is a diagram illustrating waveforms of respective parts of the phase comparator PDC and the charge pump circuit CPC when the frequency division ratio of the frequency divider DIV is changed from a low frequency division ratio to a relatively high frequency division ratio. As a result, the phase of the _divided output signal V _DIV coincides with the phase of the reference frequency signal V _REF by chance, and the extended period ΔT shown in FIG. 10 disappears in FIG. 11 corresponding to the shortening of the divided period. is doing. Incidentally, the locked state of FIG. 11 is different from the charge pump current I _CP retardation locked with offsets of zero total shown in FIG. 9, the total of the charge pump current I _CP is the charge pump circuit CPC P-channel A positive current is generated by the source current Isource of the MOS transistor MP1. Therefore, the control and increases the oscillation frequency _{f RFVCO} of the voltage controlled oscillator RFVCO level of the control output voltage VCNT generated from the low-pass filter LFC rises, so that the oscillation period of the oscillation output signal of the voltage controlled oscillator RFVCO shorter Is done.

  FIG. 12 shows a realistic state in which the current value of the sink current I sink of the N channel MOS transistor MN1 is smaller than the current value of the source current I source of the P channel MOS transistor MP1 of the charge pump circuit CPC in the fractional synthesizer Frct_Synth of FIG. FIG. 10 is a diagram illustrating waveforms of respective parts of the phase comparator PDC and the charge pump circuit CPC when the frequency division ratio of the frequency divider DIV is changed from a low frequency division ratio N to a considerably high frequency division ratio N + 8.

As the frequency division ratio is changed to a considerably high frequency division ratio N + 8, the end timing of the count-up of the frequency divider DIV in the fractional synthesizer Frct_Synth of FIG. 1 tends to be considerably delayed. However, the timing of the divided output signal _{V DIV} from the frequency divider DIV changes from low level to high level, can not enter the delay time T_Dly by the delay circuit Dly_Cir. A flip-flop FF_Dn for flip flop FF_Up and down for up are both controlled to the set state, after a lapse of the delay time of the delay circuit Dly_Cir T_Dly, the reset signal _{V R} of low level is generated from the delay circuit Dly_Cir In this case, the delay time T_Dly by the delay circuit Dly_Cir must be secured.

Therefore, as shown in FIG. 12, as compared with FIG. 9, the timing at which the divided output signal V _DIV from the frequency divider DIV changes from low level to high level is delayed, and the up flip-flop FF_Up and a flip-flop FF_Dn for down are both controlled to the set state, the delay time of the delay circuit Dly_Cir the reset signal _{V R} of low level is generated is extended to T_Dly 'from T_Dly. Thus, shortening of the division period of time 2ΔT the divided output signal V _DIV reset signal V _R for dividing the output signal V _DIV delay and the low level of the timing changing from low level to high level is generated This is achieved by delaying generation timing. Therefore, a longer period through which the source current Isource than period flows Suinku current Isink, the charge pump current _{I CP} total becomes a positive current by the source current Isource of P-channel MOS transistor MP1. Thus, elevated levels of the control output voltage VCNT generated from the low-pass filter LFC, and the oscillation frequency _{f RFVCO} of the voltage controlled oscillator RFVCO rises, so that the oscillation period of the oscillation output signal of the voltage controlled oscillator RFVCO shorter Be controlled.

Incidentally, the present inventors have shown in FIG. 10 in a realistic state that the current value of the sink current I sink of the N channel MOS transistor MN1 is smaller than the current value of the source current I source of the P channel MOS transistor MP1 of the charge pump circuit CPC. As shown, when the frequency division ratio is changed from a high frequency division ratio to a low frequency division ratio N, the voltage controlled oscillator RFVCO is driven by the total negative charge pump current I _CP generated by the sink current I sink of the N channel MOS transistor MN1. When the division ratio is changed from a low division ratio to a considerably high division ratio N as shown in FIG. 12 as determined by the control output voltage VCNT of the low-pass filter LFC, the voltage controlled oscillator RFVCO is a P-channel MOS transistor. MP1 source current Isource Found to be determined by the low pass filter LFC control output voltage VCNT by positive the charge pump current I _CP of Taru. In particular, when a high-order MASH ΣΔ modulator as shown in FIG. 4 is used in the fractional PLL, the division ratio of the fractional divider DIV is changed from a high division ratio N + 8 to a low division ratio N and vice versa. It is frequently changed from a low frequency division ratio N to a high frequency division ratio N + 8 with a large change width. Each time such a large change width division ratio change, the oscillation operation of the voltage controlled oscillator RFVCO depends on the state determined by the total positive charge pump current I _CP by the source current I source of the P channel MOS transistor MP1 and the N channel. Switching is made between the state determined by the total negative charge pump current I _CP by the sink current I sink of the MOS transistor MN1.

Further, the present inventors have shown in FIG. 11 in a realistic state that the current value of the sink current I sink of the N channel MOS transistor MN1 is smaller than the current value of the source current I source of the P channel MOS transistor MP1 of the charge pump circuit CPC. the reference frequency signal V _REF of the reference frequency signal V _REF, as shown in FIGS. 9 and 10 the state of phase meets the divided output signal V _DIV as a boundary with respect to the phase the phase as shown The phase of the _divided output signal V _DIV is advanced and the charge pump current I _CP changes from negative to positive, and the phase of the _divided output signal V _DIV with respect to the phase of the reference frequency signal V _REF as shown in FIG. exist with changing conditions only positive never becomes delayed and the charge pump current I _CP is negative, this second extremes Also found that different larger operation of the charge pump circuit CPC in the state.

In particular, prior to the present invention, the present inventors differed in the current value of the charge pump current I _{CP in} the two states due to a mismatch in characteristics between the source current injection transistor and the sink current emission transistor of the charge pump circuit CPC. Thus, it has been found that the phase noise characteristics of the fractional PLL circuit are greatly affected.

  FIG. 13 shows that the characteristics of the source current injection transistor and the sink current emission transistor of the charge pump circuit CPC match, and the sink current I sink of the N channel MOS transistor MN1 of the charge pump circuit CPC and the source current Isource of the P channel MOS transistor MP1. It is a figure which shows the phase noise characteristic of a fractional PLL circuit when the electric current value of is equal.

  In FIG. 13, the vertical axis represents the phase noise level, and the horizontal axis represents the offset frequency from the center frequency. When the current values of the sink current I sink and the source current I source are equal, the maximum phase noise is suppressed to about −78 dBc / Hz or less.

  FIG. 14 shows that the characteristics of the source current injection transistor and the sink current emission transistor of the charge pump circuit CPC are mismatched, and the P channel MOS transistor MP1 is larger than the current value of the sink current I sink of the N channel MOS transistor MN1 of the charge pump circuit CPC. It is a figure which shows the phase noise characteristic of the fractional PLL circuit when the electric current value of source current Isource of is large. When the current value of the source current Isource is larger than the sink current I sink, the maximum phase noise increases to about −75 dBc / Hz.

  The result of FIG. 14 is consistent with the description in Non-Patent Document 4 in which the increase in the in-band spurious noise of the fractional PLL circuit is caused by the mismatch between the P-MOS and the N-MOS of the charge pump circuit.

  In Non-Patent Document 4, the closed loop bandwidth of the fractional PLL circuit is 700 KHz, which is an extremely wide band. The RF IC transmission method employs a direct modulation transmission method in a wide band of 700 KHz. The direct modulation transmission method refers to a baseband transmission signal formed by vector synthesis of a transmission baseband signal I and a transmission baseband signal Q from a baseband signal processing unit such as a baseband LSI, from the baseband frequency band. This is a method of directly modulating to the RF transmission frequency band. In the RF IC of such an architecture, the non-patent document 4 discloses that the simplest method for completely avoiding the influence of nonlinearity is to inject a dc direct current into the loop filter. It describes that there is a drawback of enhancing noise.

  However, a long pulse width described as a better solution in Non-Patent Document 4 and a method of injecting a periodic current pulse synchronized with a comparison edge of a phase comparator input into a loop filter or described in Non-Patent Document 5 The method of flowing the additional pulse source current and the additional pulse sink current to the loop filter has a problem that not only the circuit scale is large due to the study by the present inventors, but also the timing control of the periodic current pulse and the additional pulse is complicated. It was revealed to have.

  Therefore, the present invention has been made on the basis of the results of the study by the present inventors as described above. Accordingly, an object of the present invention is to provide a source current of a charge pump circuit CPC of a fractional N PLL circuit in an RF communication semiconductor integrated circuit having a fractional N PLL circuit as a frequency synthesizer used for reception and transmission operations. While reducing the influence of nonlinearity due to mismatch between the injection transistor and the sink current emission transistor, the compensation circuit for reducing the phase noise of the fractional N PLL circuit is reduced and the compensation circuit is also easily controlled. It is to become.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The basic technical idea of the present invention for solving the above-mentioned object is that a fractional N PLL circuit as a frequency synthesizer used for reception and transmission operations has a closed loop bandwidth of a few tens of KHz. Reduction of non-linearity caused by mismatch between source current injection transistor and sink current emission transistor of charge pump circuit CPC of N PLL circuit is realized by injection of dc direct current to loop filter which is the purest method It is to be. Injecting the dc direct current into the loop filter, which was denied for the reason of emphasizing the reference spurious noise in Non-Patent Document 4, in the present invention, the closed loop band of the fractional N PLL circuit is a narrow band of the order of several tens of KHz. By setting to, generation of large spurious noise and phase noise can be avoided.

  A more specific technical idea of the present invention that realizes the basic technical idea of the present invention is to realize the transmission operation of the semiconductor integrated circuit for RF communication with an offset PLL circuit.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

That is, a communication semiconductor integrated circuit according to one aspect of the present invention includes a reference frequency oscillator (DCXO) that generates a reference frequency signal having a reference oscillation frequency (f _REF ) and the reference frequency oscillator (DCXO). A phase comparator (PDC) to which a reference frequency signal is supplied to one input terminal; a charge pump circuit (CPC) responsive to an up output signal and a down output signal of the phase comparator (PDC); and the charge pump A low pass filter (LFC) responsive to a charge pump current (I _CP ) of a circuit (CPC), an RF voltage controlled oscillator (RFVCO) responsive to a control output voltage (VCNT) of the low pass filter (LFC), and the RF voltage Connected between the output terminal of the controlled oscillator (RFVCO) and the other input terminal of the phase comparator (PDC) A frequency synthesizer (Frct_Synth) by including a frequency divider (DIV) and an RF oscillation output signal (f _RFVCO ) of the output terminal of the RF voltage controlled oscillator of the PLL circuit. And an RF transmission voltage controlled oscillator (TXVCO) for generating an RF transmission frequency signal for an RF transmission signal of RF communication. The PLL circuit constituting the frequency synthesizer (Frct_Synth) is a fractional PLL circuit whose average frequency division ratio includes an integer and a fraction by changing the frequency division ratio of the frequency divider (DIV). The loop band is set to a narrow band on the order of several tens of KHz (see FIG. 15).

The charge pump circuit (CPC) injects a source current (Isource) into the low-pass filter (LFC) in response to the up output signal (V _QREF ) of the phase comparator (PDC). ), A sink current emission transistor (MN1) that emits a sink current (Isink) from the low-pass filter (LFC) in response to the down output signal (V _QDIV ) of the phase comparator (PDC), and the low-pass filter And an offset current circuit (MN2, MN3, Roffset) for discharging a dc direct current from (LFC) or injecting a dc direct current into the low-pass filter (LFC) (see FIGS. 16 and 17).

  The offset current circuit (MN2, MN3, Roffset) includes devices (MN2, MN3, Roffset) set to intentional device sizes so as to set the dc direct current to a predetermined value (Ioffset) (FIG. 18, see FIG.

  According to the means of the one aspect of the present invention, the original object can be solved by the mechanism described in the basic technical idea of the present invention.

  According to the means of the more specific form of the present invention, it is possible to reduce the level of the spurious signal in the frequency band near 400 KHz of the transmission modulation spectrum defined by the GMSK (Gaussian minimum Shift Keying) standard.

In the semiconductor integrated circuit according to a more specific embodiment of the present invention, the PLL circuit constituting the frequency synthesizer (Frct_Synth), the RF voltage-controlled oscillator the RF oscillation output signal generated from (RFVCO) a _{(f RFVCO)} An intermediate frequency divider (IF DIV) that generates an intermediate frequency signal (f _{IF DIV} ) by dividing is included. The semiconductor integrated circuit includes a transmission mixer that forms an intermediate frequency transmission signal from the intermediate frequency signal (f _{IF DIV} ) generated from the intermediate frequency divider ( _{IF DIV} ) and a transmission baseband signal (TxABI, TXABQ) (TX-MIX_I, TX-MIX_Q ) and, a transmission system offset PLL circuit (TX_Offset_PLL), the RF voltage controlled oscillator (RFVCO) dividing the RF oscillation output signal generated to _{(f RFVCO)} by dividing the And an RF divider (RF DIV) for generating an RF frequency signal. The transmission system offset PLL circuit (TX_Offset_PLL) includes a phase comparison circuit (PC) in which the intermediate frequency transmission signal generated from the transmission mixer (TX-MIX_I, TX-MIX_Q) is supplied to one input terminal; The RF transmission voltage controlled oscillator (TXVCO) responsive to the output of the phase comparison circuit (PC) and the RF transmission frequency signal (f _TXVCO ) generated from the RF transmission voltage controlled oscillator ( _TXVCO ) are one input. A frequency control mixer for frequency control feedback (DWN_MIX_PM), which is supplied to the terminal and generated by the RF divider (RF DIV) and supplied to the other input terminal. The output signal of the phase control feedback frequency downmixer (DWN_MIX_PM) is supplied to the other input terminal of the phase comparison circuit (PC) (see FIG. 15).

A semiconductor integrated circuit according to a more specific form of the present invention includes an RF reception signal analog signal processing circuit (RX SPU). The RF reception signal analog signal processing circuit (RX SPU) is supplied with a low noise amplifier (LNA1 to LNA4) for amplifying the RF reception signal and an RF amplification reception output signal generated by the low noise amplifier (LNA1 to LNA4). Reception mixers (RX-MIX_I, RX-MIX_Q) for generating reception baseband signals (RxABI, RxABQ). The PLL circuit constituting the frequency synthesizer (Frct_Synth), the RF voltage-controlled oscillator wherein the receiving mixer by the RF oscillation output signal dividing (RX of the oscillation frequency generated from _{(RFVCO) (f} RFVCO) -MIX_I, RX-MIX_Q) A first frequency divider (DIV1) that forms an RF carrier signal to be supplied to the first frequency divider (DIV1) and a second frequency divider (DIV4) that divides the output signal of the first frequency divider (DIV1) Including.

  When the semiconductor integrated circuit receives the RF reception signal in the GSM850 MHz frequency band or GSM900 MHz frequency band, the frequency-divided output signal generated from the first frequency divider (DIV1) is used as the RF carrier signal. By being transmitted to the reception mixer (RX-MIX_I, RX-MIX_Q), the RF reception signal in the frequency band of the GSM850 MHz or the frequency band of the GSM900 MHz is transmitted from the reception mixer (RX-MIX_I, RX-MIX_Q). Frequency-converted received baseband signals (RxABI, RxABQ) are generated.

When the semiconductor integrated circuit receives the RF reception signal in the frequency band of DCS 1800 MHz or the frequency band of PCS 1900 MHz, the RF oscillation output of the oscillation frequency (f _RFVCO ) generated from the RF voltage controlled oscillator (RFVCO) A signal is transmitted to the reception mixer (RX-MIX_I, RX-MIX_Q) as the RF carrier signal, so that reception is frequency-converted from the RF reception signal in the frequency band of the DCS 1800 MHz or the frequency band of the PCS 1900 MHz. Baseband signals (RxABI, RxABQ) are generated.

When the semiconductor integrated circuit forms the RF transmission frequency signal in the GSM850 MHz frequency band or GSM900 MHz frequency band, the intermediate frequency signal and the transmission baseband signal (TX-MIX_I, TX-MIX_Q) are transmitted by the transmission mixer (TX-MIX_I, TX-MIX_Q). The intermediate frequency transmission signal is formed from TxABI, TxABQ), and the first frequency divider (DIV1) and the second frequency divider (DIV4) operate as the RF frequency divider (RF DIV). The frequency-divided output signal of the second frequency divider (DIV4) is supplied to the other input terminal of the frequency control mixer (DWN_MIX_PM) for phase control feedback of the transmission system offset PLL circuit (TX_Offset_PLL). As the transmission system offset PLL circuit ( TX_Offset_PLL) converts the intermediate frequency transmission signal into the RF transmission frequency signal (f _TXVCO ) in the GSM850 MHz frequency band or the GSM900 MHz frequency band.

When the semiconductor integrated circuit forms the RF transmission frequency signal in the frequency band of DCS 1800 MHz or the frequency band of PCS 1900 MHz, the intermediate frequency signal and the transmission baseband signal (TX-MIX_I, TX-MIX_Q) are transmitted by the transmission mixer (TX-MIX_I, TX-MIX_Q). The intermediate frequency transmission signal is formed from TxABI, TxABQ), and the first frequency divider (DIV1) operates as the RF frequency divider (RF DIV), so that the first frequency divider (DIV1) A frequency-divided output signal is transmitted as the frequency-divided RF frequency signal to the other input terminal of the phase control feedback frequency downmixer (DWN_MIX_PM) of the transmission system offset PLL circuit (TX_Offset_PLL), and the transmission system offset PLL circuit ( TX_Offset_PLL ), The intermediate frequency transmission signal is frequency-converted to the RF transmission frequency signal (f _TXVCO ) in the frequency band of the DCS 1800 MHz or the frequency band of the PCS 1900 MHz (see FIG. 24).

  According to the means of the more specific form of the present invention, reception / transmission of four frequency bands of GSM850 MHz, GSM900 MHz, DCS1800 MHz, and PCS1900 MHz becomes possible.

  A semiconductor integrated circuit according to a more specific form of the present invention is configured in a polar loop system to support an EDGE (Enhanced Data for GSM Evolution; Enhanced Data for GPRS) system, and the transmission system offset PLL circuit (TX_Offset_PLL) is A phase loop (PM LP) for phase modulation of the polar loop system and an amplitude loop (AM LP) of the polar loop system, the phase comparison circuit (PC) of the transmission system offset PLL circuit (TX_Offset_PLL); The RF transmission voltage controlled oscillator (TXVCO) and the phase control feedback frequency downmixer (DWN_MIX_PM) constitute the phase loop (PM LP) (see FIG. 25).

  According to the means of the more specific form of the present invention, it is possible to cope with the EDGE system with a high communication data transfer rate that uses amplitude modulation for both phase modulation.

  A semiconductor integrated circuit according to a more specific form of the present invention is configured by a polar modulator system to support the EDGE system, and the transmission system offset PLL circuit (TX_Offset_PLL) is a phase loop for phase modulation of the polar modulator system. (PM LP) and the polar modulator type amplitude loop (AM LP), the phase comparison circuit (PC) of the transmission system offset PLL circuit (TX_Offset_PLL), the RF transmission voltage controlled oscillator (TXVCO), and the The phase control feedback frequency downmixer (DWN_MIX_PM) constitutes the phase loop (PM LP) (see FIG. 26).

  According to the means of the more specific form of the present invention, it is possible to cope with the EDGE system with a high communication data transfer rate that uses amplitude modulation for both phase modulation.

  In a semiconductor integrated circuit according to a more specific form of the present invention, the fractional PLL circuit includes a ΣΔ modulator (ΣΔMod) for calculating the decimal of the average division ratio, and the ΣΔ modulator (ΣΔMod) is 1 This is a MASH type in which a plurality of next ΣΔ modulators are provided (see FIG. 4).

  In the semiconductor integrated circuit according to a more specific form of the present invention, the MASH type ΣΔ modulator (ΣΔMod) is supplied with pseudo-random noise from a dither circuit (dither) via a digital differentiator (diff31). (See FIG. 4).

  A communication semiconductor integrated circuit according to another embodiment of the present invention includes an RF reception signal analog signal processing circuit (RX SPU), an RF transmission signal analog signal processing circuit (TX SPU), and a frequency synthesizer (Frct_Synth). . The RF reception signal analog signal processing circuit (RX SPU) includes a low noise amplifier (LNA1 to LNA4) that amplifies the RF reception signal, an RF amplification reception output signal generated by the low noise amplifier (LNA1 to LNA4), and the frequency synthesizer. Reception mixers (RX-MIX_I, RX-MIX_Q) that generate reception baseband signals (RxABI, RxABQ) by being supplied with the reception carrier signal generated by (Frct_Synth). The RF transmission signal analog signal processing circuit (TX SPU) includes transmission mixers (TX-MIX_I, TX-MIX_Q) to which transmission baseband signals (TxABI, TxABQ) are supplied from a baseband signal processing unit (BB_LSI), When the RF transmission signal analog signal processing circuit (TX SPU) is supplied with the transmission carrier signal generated by the frequency synthesizer (Frct_Synth), the RF transmission signal analog signal processing circuit (TX SPU) (Tx_GSM850, Tx_GSM900, Tx_DCS1800, Tx_PCS1900) are generated (see FIG. 24).

The frequency synthesizer (Frct_Synth) has a reference frequency oscillator (DCXO) that generates a reference frequency signal of a reference oscillation frequency (f _REF ), and the reference frequency signal formed from the reference frequency oscillator (DCXO) is one input terminal. A phase comparator (PDC) supplied to a charge pump circuit (CPC) responsive to an up output signal and a down output signal of the phase comparator (PDC), and a charge pump current of the charge pump circuit (CPC) A low pass filter (LFC) responsive to (I _CP ), an RF voltage controlled oscillator (RFVCO) responsive to a control output voltage (VCNT) of the low pass filter (LFC), and an output terminal of the RF voltage controlled oscillator (RFVCO) And a frequency divider connected between the other input terminal of the phase comparator (PDC) And a PLL circuit including a device (DIV). The PLL circuit constituting the frequency synthesizer (Frct_Synth) is a fractional PLL circuit whose average frequency division ratio includes an integer and a fraction by changing the frequency division ratio of the frequency divider (DIV). The loop band is set to a narrow band on the order of several tens of KHz (see FIG. 15).

The charge pump circuit (CPC) injects a source current (Isource) into the low-pass filter (LFC) in response to the up output signal (V _QREF ) of the phase comparator (PDC). ), A sink current emission transistor (MN1) that emits a sink current (Isink) from the low-pass filter (LFC) in response to the down output signal (V _QDIV ) of the phase comparator (PDC), and the low-pass filter And an offset current circuit (MN2, MN3, Roffset) for discharging a dc direct current from (LFC) or injecting a dc direct current into the low-pass filter (LFC) (see FIGS. 16 and 17).

  The offset current circuit (MN2, MN3, Roffset) includes devices (MN2, MN3, Roffset) set to intentional device sizes so as to set the dc direct current to a predetermined value (Ioffset) (FIG. 18, see FIG.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, in a communication semiconductor integrated circuit having a fractional N PLL circuit as a frequency synthesizer used for a reception operation and a transmission operation, the P-MOS and N- of the charge pump circuit CPC of the fractional N PLL circuit are used. It is possible to reduce the influence of non-linearity due to the mismatch with the MOS, to reduce the circuit scale of the compensation circuit for reducing the phase noise of the fractional N PLL circuit, and to simplify the control of the compensation circuit.

≪Configuration of Fractional Synthesizer Frct_Synth≫
FIG. 15 is a diagram showing a configuration of a fractional synthesizer Frct_Synth formed on a chip of a communication semiconductor integrated circuit RF IC according to one embodiment of the present invention.

In this embodiment, a frequency control of a transmission system signal processing subunit of a communication semiconductor integrated circuit RF IC is performed using a fractional synthesizer Frct_Synth including a reference frequency oscillator DCXO. Further, the ΣΔ modulator ΣΔMod of the fractional synthesizer Frct_Synth includes the third-order MASH type ΣΔ modulator shown in FIG. 4 and includes the dither circuit shown in FIG. Further, the closed loop bandwidth of the fractional N PLL circuit constituting the fractional synthesizer Frct_Synth is set to the order of several tens of KHz which is much lower than 100 KHz. A specific example of this closed loop band is 30 KHz. This transmission system signal processing subunit includes a transmission system offset PLL circuit TX_Offset_PLL. By being supplied to the fractional examination constellation Frct_Synth intermediate frequency divider IF DIV which RF oscillation output signal is set to the division ratio 26 which is the output of the RF voltage controlled oscillator RFVCO oscillation frequency _f RFVCO (3568.448MHz) A doubled intermediate frequency signal (137.248 MHz) is formed from the output of the intermediate frequency divider IF DIV. The double intermediate frequency signal (137.248 MHz) is supplied to the input of the 90 ° phase shifter 90degShift to form two intermediate frequency signals (68.624 MHz) having different 90 ° phases. The transmission mixers TX-MIX_I, TX-MIX_Q are supplied with the baseband transmission signals TxABI, TxABQ and two intermediate frequency signals (68.624 MHz) that are 90 ° out of phase, so that the transmission mixers TX-MIX_I, TX- An intermediate frequency transmission signal (68.624 MHz) obtained by vector synthesis is formed at the output of the adder connected to the output of MIX_Q. This intermediate frequency transmission signal (68.624 MHz) is supplied to one input terminal of the phase comparator PC. The output of the phase comparator PC is supplied to the RF transmission voltage controlled oscillator TXVCO via the low pass filter LF1, so that the frequency of the RF transmission voltage controlled oscillator TXVCO is controlled to about 1715.6 MHz. The oscillation output signal of the RF transmission voltage controlled oscillator TXVCO is supplied to one input terminal of the phase control feedback frequency downmixer DWN_MIX_PM via the buffer amplifier BF, and is supplied to the other input terminal of the phase control feedback frequency downmixer DWN_MIX_PM. An RF signal for a downmixer (1784.2224 MHz) is supplied from an RF frequency divider RF DIV set to a frequency division ratio of 2. In the phase control feedback frequency downmixer DWN_MIX_PM, the oscillation signal (approximately 1715.6 MHz) from the RF transmission voltage controlled oscillator TXVCO and the downmixer RF signal (1784.224 MHz) from the RF divider RF DIV are mixed. Is called. Therefore, a feedback signal having a difference frequency of 1784.2224 MHz−1715.6 MHz = 68.624 MHz is formed from the output of the phase control feedback frequency down mixer DWN_MIX_PM and supplied to the other input terminal of the phase comparator PC. The The transmission system offset PLL circuit TX_Offset_PLL performs negative feedback control so that the phase and frequency of the two input signals of the phase comparator PC coincide with each other. As a result, an accurate 1715.6 MHz from the RF transmission voltage control oscillator TXVCO is obtained. A signal having an RF transmission frequency f _TXVCO can be obtained. Further, an intermediate frequency transmission signal f _IF (68.624 MHz) obtained by vector synthesis at the output of the adder connected to the outputs of the transmission mixers TX-MIX_I and TX-MIX_Q is input to one input terminal of the phase comparator PC. Have been supplied. Furthermore, to the other input terminal of the phase comparator PC, RF voltage-controlled oscillator RFVCO oscillation frequency _{f RFVCO} the dividing ratio 2 by dividing the dividing RF oscillation frequency _{f RFVCO} / 2 RF transmission voltage controlled oscillator from TXVCO difference frequency signal obtained by subtracting the frequency _{f TXVCO} of the RF transmission frequency signal _{(f RFVCO / 2-f TXVCO} ) is supplied. By the negative feedback control of the transmission system offset PLL circuit TX_Offset_PLL, the reference frequency of one input terminal of the phase comparator PC matches the negative feedback frequency of the other input terminal of the phase comparator PC, and therefore the following relationship is established. .

_{f IF = f RFVCO / 2-} f TXVCO ... (1 type)
When the above equation is modified, the following equation is obtained.

_{f TXVCO = f RFVCO / 2-} f IF ... (2 type)
= (356.448 MHz / 2)-68.624 MHz
= 1784.224 MHz-68.624 MHz
= 1715.6MHz
Therefore, the RF transmission frequency f _TXVCO generated from the RF transmission voltage controlled oscillator TXVCO inside the transmission system offset PLL circuit TX_Offset_PLL is the oscillation frequency f of the RF oscillation output signal generated from the RF voltage controlled oscillator RFVCO inside the fractional synthesizer Frct_Synth. is set correctly in response to an intermediate frequency transmission signal f _IF output of _RFVCO the connected adders to the output of the transmission mixer. The intermediate frequency transmission signal f _IF is also accurately set by the RF transmission frequency f _TXVCO generated from the RF transmission voltage controlled oscillator TXVCO inside the transmission system offset PLL circuit TX_Offset_PLL. If the high-order MASH type ΣΔ modulator shown in FIG. 4 is used for the fractional PLL, the change value of the division ratio becomes a large value of 8, and the change value of the division ratio is a simple repetition such as 1. Spurious noise can be reduced more than the pattern.

  On the other hand, the RF transmission signal generated from the RF transmission voltage controlled oscillator TXVCO inside the transmission system offset PLL circuit TX_Offset_PLL is transmitted from the antenna to the base station via the RF power amplifier and the antenna switch. The phase noise component and the spurious noise component included in the RF transmission signal are obtained by narrowing the closed loop band of the fractional PLL circuit of the fractional synthesizer Frct_Synth to the order of several tens of KHz by injecting dc direct current into the loop filter LFC described below. By setting the bandwidth, it can be reduced to a sufficiently low level.

≪Configuration of phase comparator PDC and charge pump circuit CPC≫
16 shows a phase comparator PDC constituting a fractional N PLL circuit of a fractional synthesizer Frct_Synth formed on a chip of a communication semiconductor integrated circuit RF IC according to one embodiment of the present invention shown in FIG. It is a circuit diagram which shows the structure of the charge pump circuit CPC.

  FIG. 16 basically differs from the charge pump circuit studied by the present inventors during the development of the RF IC prior to the present invention shown in FIG. 6 in that the dc direct current Ioffset is emitted from the low-pass filter LFC. The offset current circuits MN2 and MN3 are added. A P-channel MOS transistor (hereinafter abbreviated as P-MOS) MP1 and P-MOS MP0 that supply source current Isource to the low-pass filter LFC constitute a current mirror. A constant current Io_Up set to 100 μA is supplied to the diode-connected P-MOS MP0. An N-channel MOS transistor (hereinafter abbreviated as N-MOS) MN1 and N-MOS MN0 that flow a sink current Isink from the low-pass filter LFC also constitute a current mirror. The constant current Io_Dn set to 100 μA is also supplied to the diode-connected N-MOS MN0. Further, the N-MOS MN3 and the N-MOS MN2 that flow the dc direct current Ioffset from the low-pass filter LFC also constitute a current mirror. The constant current Io_Dn set to 100 μA is also supplied to the diode-connected N-MOS MN2. The N-MOS MN2 and N-MOS MN3 constituting the current mirror are set to intentional device sizes so as to set the dc DC current Ioffset to a predetermined value.

  FIG. 18 is a diagram showing device sizes of the P-MOS MP0, MP1, N-MOS MN0, MN1, MN2, and MN3 of the charge pump circuit CPC shown in FIG.

  In the figure, S, G, D, Lg, and Wg indicate the source, gate, drain, gate length, and gate width of the MOS transistor, respectively. The gate lengths Lg of the six MOS transistors are all set equal. However, the gate width WgMP0 of the P-MOS MP0 and the gate width WgMP1 of the P-MOS MP1 are set at a ratio of 5: 1. As a result, a source current Isource of 20 μA, which is one fifth of 100 μA of the constant current Io_Up, is supplied from the drain of the P-MOS MP1 to the low-pass filter LFC. The gate width WgMN0 of the N-MOS MN0 and the gate width WgMN1 of the N-MOS MN1 are set at a ratio of 5: 1. As a result, a sink current I sink of 20 μA, which is one fifth of 100 μA of the constant current Io_Dn, flows from the low-pass filter LFC to the drain of the N-MOS MN1. Further, the gate width WgMN2 of the N-MOS MN2 and the gate width WgMN3 of the N-MOS MN3 are set at a ratio of 5 to 0.15. A dc direct current Ioffset of 3 μA, which is 0.15 / 5 of 100 μA of the constant current Io_Dn, flows from the low-pass filter LFC to the drain of the N-MOS MN3.

  Further, the offset circuit that causes the dc direct current Ioffset to flow from the low-pass filter LFC to the ground potential GND is not limited to an N-MOS current mirror. FIG. 17 is a diagram illustrating that an offset circuit that causes the dc DC current Ioffset to flow from the low-pass filter LFC to the ground potential GND is configured by a resistor Roffset. In order to flow the dc direct current Ioffset from the low-pass filter LFC to the ground potential GND by the resistor Roffset, the resistance value of the resistor Roffset is designed as follows.

In FIG. 17, the power supply voltage V _DD is 2.8 volts. When the source current Isource flowing from the drain of the P-MOS MP1 and the sink current I sink flowing to the drain of the N-MOS MN1 are both equal to 20 μA, the resistance Roffset has about half of the power supply voltage V _DD 2.8 volts. A certain 1.4 volts is applied. Therefore, the resistance value of the resistor Roffset is obtained as follows.

Roffset = V _DD /(2×Ioffset)=466.7 KΩ
As shown in FIG. 19, the resistor Roffset that constitutes the offset circuit for flowing the dc DC current Ioffset from the low-pass filter LFC of FIG. 17 is also set to an intentional device size so as to have a predetermined resistance value. As shown in the figure, the resistor Roffset has a meandering plane shape, and is electrically connected to the low resistance wiring layer at the square portions at both ends. If the resistor Roffset is composed of a high-resistance polysilicon resistor or a diffused resistor, the resistance value of the resistor Roffset is obtained from the sheet resistance ρs, the resistance width Wr, and the total meandering distance Lr of the resistor as follows. It is done.

Roffset = ρs · (Lr / Wr)
<< Operation of Phase Comparator PDC and Charge Pump Circuit CPC >>
FIG. 20 shows the configuration of the phase comparator PDC and the charge pump circuit CPC constituting the fractional N PLL circuit of the fractional synthesizer Frct_Synth according to one embodiment of the present invention shown in FIG. FIG. 6 is a diagram showing waveforms of respective parts of the phase comparator PDC and the charge pump circuit CPC when an offset circuit for flowing a dc direct current Ioffset is removed. Also in this case, the current value of the sink current I sink of the N channel MOS transistor MN1 is smaller than the current value of the source current I source of the P channel MOS transistor MP1 of the charge pump circuit CPC. FIG. 20 shows the phase comparator PDC and the charge pump in the locked state in which the phase of the reference frequency signal V _REF from the reference frequency oscillator DCXO and the phase of the divided output signal V _DIV from the divider DIV match. It is a figure which shows the waveform of each part of the circuit CPC. Again, in the fractional synthesizer Frct_Synth of FIG. 15, it is assumed that a fixed value is supplied to the control input terminal that controls the frequency division ratio of the frequency divider DIV.

As shown in the figure, the period in which the source current Isource flows is equal to the period in which the sink current I sink flows, but the total charge pump current I _CP becomes positive due to the difference in the sink current I sink <the source current I source. Accordingly, the level of the control output voltage VCNT generated from the low-pass filter LFC increases, and the phase of the divided output signal V _DIV from the frequency divider DIV starts to advance. Eventually, the advance of the phase of the frequency- _divided output signal V _DIV with respect to the phase of the reference frequency signal V _REF is controlled, and the phase shifts to the locked state with phase difference offset.

FIG. 21 shows the grounding from the low-pass filter LFC as shown in the configuration of the phase comparator PDC and the charge pump circuit CPC constituting the fractional N PLL circuit of the fractional synthesizer Frct_Synth according to one embodiment of the present invention shown in FIG. It is a figure which shows the waveform of each part of the phase comparator PDC and charge pump circuit CPC at the time of adding the offset circuit which flows dc direct current Ioffset to the electric potential GND. Again, in the fractional synthesizer Frct_Synth of FIG. 15, it is assumed that a fixed value is supplied to the control input terminal that controls the frequency division ratio of the frequency divider DIV. In this case, the current value of the sink current I sink of the N channel MOS transistor MN1 is smaller than the current value of the source current I source of the P channel MOS transistor MP1 of the charge pump circuit CPC. The charge pump circuit CPC 16, the negative charge pump current _{I CP} by the Suinku current Isink and dc direct current Ioffset to the ground potential GND from the low-pass filter LFC is flowed due to source current Isource from the power supply voltage Vdd to the low pass filter LFC A positive charge pump current I _CP is passed. Since the PLL circuit operates so that the time integration amount of the negative charge pump current I _CP (−Ioffset) and the time integration amount of the positive charge pump current I _CP (Isource− (Ioffset + Isink)) are equal to each other, FIG. As shown in FIG. 5, there is a period in which the charge pump current I _CP becomes a total positive I source − (I offset + I sink) before the period in which the charge pump current I _CP becomes the negative dc DC current −Ioffset. This means that the phase of the divided output signal V _DIV inevitably lags behind the phase of the reference frequency signal V _REF due to the negative dc DC current −Ioffset by the offset circuits MN2 and MN3. As a result, as shown in FIG. 12, the phase of the frequency- _divided output signal V _DIV is delayed with respect to the phase of the reference frequency signal V _REF , and the charge pump current I _CP does not become negative and changes only in the positive state. Occurrence can be avoided.

FIG. 22 shows the configuration of the phase comparator PDC and the charge pump circuit CPC constituting the fractional N PLL circuit of the fractional synthesizer Frct_Synth according to one embodiment of the present invention shown in FIG. FIG. 6 is a diagram showing phase noise characteristics of a fractional PLL circuit when an offset circuit for passing a dc direct current Ioffset is removed. The phase noise characteristics indicated by the four lines L1, L2, L3, and L4 in FIG. 22 depend on the current value of the charge pump current _ICP . The current value of the charge pump current I _{CP is} the current value of the sink current I sink and the source current I source. The maximum phase noise when the charge pump current I _CP is 20 μA increases to about −76 dBc / Hz. The characteristic of the maximum phase noise of about −76 dBc / Hz of the line L1 is in good agreement with the phase noise characteristic of FIG.

FIG. 23 shows the grounding from the low-pass filter LFC as shown in the configuration of the phase comparator PDC and the charge pump circuit CPC constituting the fractional N PLL circuit of the fractional synthesizer Frct_Synth according to one embodiment of the present invention of FIG. It is a figure which shows the phase noise characteristic of the fractional PLL circuit at the time of adding the offset circuit which flows dc direct current Ioffset to the electric potential GND. Similarly, the phase noise characteristics shown in the four lines L1, L2, L3, and L4 in FIG. 23 depend on the current value of the charge pump current _ICP . The maximum phase noise when the charge pump current I _CP is 20 μA is suppressed to about −80 dBc / Hz or less. The characteristic of the maximum phase noise of about −80 dBc / Hz of the line L1 is very similar to the phase noise characteristic of FIG. Note that the closed-loop band that is 3 dBc lower than the maximum phase noise of about −80 dBc / Hz is about 30 KHz as already described.

Further, from the four lines L1, L2, L3, and L4 in FIG. 23, the closed loop band of the fractional N PLL circuit can be narrowed by reducing the charge pump current I _CP to 120 μA, 80 μA, 40 μA, and 20 μA. Understood.

  As a result, the linearity of the charge pump circuit CPC shown in FIG. 16 can be improved, and the fractional N PLL circuit constituting the fractional synthesizer Frct_Synth shown in FIG. In synergy with the effect of (a specific example is 30 KHz), it becomes possible to reduce the phase noise and spurious noise of the fractional N PLL circuit. Further, the fractional N PLL circuit of the fractional synthesizer Frct_Synth of FIG. 15 also has a synergistic effect of noise reduction using the third-order MASH type ΣΔ modulator shown in FIG. 4 and the dither circuit shown in FIG. . Thus, the present invention contributes to the improvement of the frequency spectrum characteristics of the RF transmission signal of the RF communication semiconductor integrated circuit.

The leakage spurious signal component outside the frequency spectrum of the normal RF transmission signal is finally amplified by an RF power amplifier connected to the output of the transmission system signal processing subunit of the RF IC, and then the mobile phone terminal It is transmitted as an adjacent disturbance signal from the antenna of the device. The leakage spurious signal component of ± 400 KHz in the vicinity of the RF transmission frequency f _TXVCO of 1715.6 MHz, which is the output signal of the RF transmission voltage controlled oscillator TXVCO, falls below a predetermined value (−60 dBm) according to the standard of GMSK (Gaussian minimum Shift Keying). It is strictly defined. FIG. 27 shows a frequency spectrum of an RF transmission signal of a mobile phone terminal device defined by the GMSK standard, and a thick solid line PSD is a level defined by the GMSK standard. The attenuation amount in the vicinity of the center frequency (RF transmission frequency) ± 200 KHz is set to −30 dBm or less, and the attenuation amount in the vicinity of the center frequency (RF transmission frequency) ± 400 KHz is set to −60 dBm or less. The thin solid line shows an example that satisfies this standard.

As a modified embodiment of the present invention, as the offset circuit, a current mirror of the offset circuit may be configured by a P-MOS so as to inject the dc direct current + Ioffset from the power supply voltage V _DD to the low-pass filter LFC. In this case, on the contrary, there is necessarily a period in which the charge pump current I _CP becomes negative −I sink + (I offset + source) before the period in which the charge pump current I _CP becomes positive dc direct current + Ioffset. To do. This means that the phase of the divided output signal V _DIV inevitably advances from the phase of the reference frequency signal V _REF due to the positive dc direct current + Ioffset by the offset circuit formed of a P-MOS current mirror. Needless to say.

<< More Specific Embodiment of the Present Invention >>
FIG. 24 is a diagram showing a configuration of a communication semiconductor integrated circuit RF IC according to a more specific embodiment of the present invention. The RF IC shown in FIG. 24 is configured to correspond to four bands of quad bands of GSM850 MHz, GSM900 MHz, DCS1800 MHz, and PCS1900 MHz in both the reception operation from the base station and the transmission operation to the base station. DCS is an abbreviation for Digital Cellular System, and PCS is an abbreviation for Personal Communication System. In FIG. 24, Frct_Synth is an RF carrier synchronization subunit configured by the fractional PLL circuit or the fractional synthesizer described with reference to FIG.

  The RF IC corresponding to the quad-band band includes the fractional synthesizer Frct_Synth described with reference to FIG. 15, the RF reception signal analog signal processing subunit RX SPU, and the RF transmission signal analog signal processing subunit TX SPU. Has been. The RF reception signal received by the antenna ANT of the mobile phone terminal device is supplied to the RF reception signal analog signal processing unit RX SPU via the antenna switch ANTSW and the surface acoustic wave filter SAW. The RF reception signal analog signal processing subunit RX SPU demodulates the input RF reception signal to generate reception baseband signals RxABI and RxABQ, and supplies the reception baseband signals RxABI and RxABQ to the baseband LSI (BB_LSI). To do. Transmission baseband signals TxABI and TxABQ are supplied from the baseband LSI (BB_LSI) to the RF transmission signal analog signal processing subunit TX SPU. The RF transmission signal analog signal processing subunit TX SPU modulates the input transmission baseband signal to form an RF transmission signal, and the RF power amplifiers RF_PA1, RD_PA2 and the antenna switch ANTSW Supply to antenna ANT.

  First, the reception operation of the RF reception signal analog signal processing subunit RX SPU will be described. An RF reception signal received by an antenna of a mobile phone terminal device is supplied to four low noise amplifiers via an antenna switch ANTSW and a surface acoustic wave filter SAW. The frequency band of the RF reception signal Rx_GSM850 in the GSM850 MHz band is 869 MHz to 894 MHz, and is amplified by the first low noise amplifier LNA1. The frequency band of the RF reception signal Rx_GSM900 in the GSM 900 MHz band is 925 MHz to 960 MHz, and is amplified by the second low noise amplifier LNA2. The frequency band of the RF reception signal Rx_DCS1800 in the band of DCS 1800 MHz is 1805 MHz to 1880 MHz, and is amplified by the third low noise amplifier LNA3. The frequency band of the RF reception signal Rx_PCS1900 in the band of PCS1900 MHz is 1930 MHz to 1990 MHz, and is amplified by the fourth low noise amplifier LNA4. The RF amplified reception output signals of the four low noise amplifiers LNA1 to LNA4 are supplied to one input terminal of two mixing circuits RX-MIX_I and RX-MIX_Q constituting the reception mixer. Two RF carrier signals having a 90 ° phase formed by a 90 ° phase shifter 90 deg Shift (1/2) are supplied to the other input terminals of the two mixing circuits RX-MIX_I and RX-MIX_Q. In the reception mode of GSM850 MHz or GSM900 MHz, the output of the RF voltage controlled oscillator RFVCO is supplied to the 90 ° phase shifter 90degShift (1/2) via the 1/2 frequency divider DIV1 with a frequency division ratio of 2. In the reception mode of DCS 1800 MHz or PCS 1900 MHz, the output of the RF voltage controlled oscillator RFVCO is directly supplied to the 90 ° phase shifter 90 deg Shift (1/2). A reception baseband signal RxABI and a reception baseband signal RxABQ are generated from the output of the mixing circuit RX-MIX_I and the output of the mixing circuit RX-MIX_Q, respectively. The reception baseband signal RxABI and the reception baseband signal RxABQ are respectively variable gain amplifiers PGI1, PGI2, PGAI3, filter circuits FCI1, FCI2, FCI3 buffer amplifiers BAI and variable gain amplifiers PGAQ1, PGAQ2, PGAQ3, filter circuits FCQ1, FCQ2, The signal is supplied to the baseband LSI (BB_LSI) via the FCQ3 buffer amplifier BAQ.

To accommodate operation of receiving 869MHz~894MHz band frequency band of the RF reception signal Rx_GSM850 of the GSM 850 MHz, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO is set to 3476MHz～3576MHz. The oscillation frequency f _RFVCO of the RF voltage controlled oscillator RFVCO is divided by a quarter by a frequency divider DIV1 (1/2) set to a frequency division ratio of 2 and a 90 ° phase shifter 90 degShift (1/2). The RF frequency-divided frequency signal divided by 869 MHz to 894 MHz is supplied to two mixing circuits RX-MIX_I and RX-MIX_Q constituting the receiving mixer. Therefore, analog baseband reception signals RxABI and RXABQ are formed from the outputs of the two mixing circuits RX-MIX_I and RX-MIX_Q by receiving the RF reception signal Rx_GSM850 in the GSM850 MHz band. To accommodate operation of receiving 925MHz~960MHz band frequency band of the RF reception signal Rx_GSM900 of GSM 900 MHz, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO is set to 3700MHz～3840MHz. The oscillation frequency f _RFVCO of the RF voltage controlled oscillator RFVCO is divided by a quarter by a frequency divider DIV1 (1/2) set to a frequency division ratio of 2 and a 90 ° phase shifter 90 degShift (1/2). The RF frequency-divided frequency signal frequency-divided by ¼ to 925 MHz to 960 MHz is supplied to two mixing circuits RX-MIX_I and RX-MIX_Q constituting the receiving mixer. Accordingly, analog baseband reception signals RxABI and RXABQ are formed from the outputs of the two mixing circuits RX-MIX_I and RX-MIX_Q by receiving the RF reception signal Rx_GSM900 in the GSM 900 MHz band. Frequency band of the RF reception signal Rx_DCS1800 of DCS1800MHz is to correspond to the reception operation of 1805MHz～1880MHz, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO is set to 3610MHz～3760MHz. The oscillation frequency _{f RFVCO} of the RF voltage-controlled oscillator RFVCO is 1/2 frequency division by 90 ° phase shifter 90degShift (1/2), RF division frequency signal received mixer is 1/2 frequency-divided into 1805MHz~1880MHz Are supplied to two mixing circuits RX-MIX_I and RX-MIX_Q. Accordingly, analog baseband reception signals RxABI and RXABQ are formed from the outputs of the two mixing circuits RX-MIX_I and RX-MIX_Q by receiving the RF reception signal Rx_DCS1800 in the band of DCS1800 MHz. Frequency band of the RF reception signal Rx_PCS1900 of PCS1900MHz is to correspond to the reception operation of 1930MHz～1990MHz, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO is set to 3860MHz～3980MHz. The oscillation frequency _{f RFVCO} of the RF voltage-controlled oscillator RFVCO is 1/2 frequency division by 90 ° phase shifter 90degShift (1/2), RF division frequency signal received mixer is 1/2 frequency-divided into 1930MHz~1990MHz Are supplied to two mixing circuits RX-MIX_I and RX-MIX_Q. Accordingly, analog baseband reception signals RxABI and RXABQ are formed from the outputs of the two mixing circuits RX-MIX_I and RX-MIX_Q by receiving the RF reception signal Rx_PCS1900 in the band of PCS1900 MHz.

Next, the transmission operation of the RF transmission signal analog signal processing subunit TX SPU will be described. By supplying the RF oscillation output signal of the output of the RF voltage controlled oscillator RFVCO of the fractional synthesizer Frct_Synth to the intermediate frequency divider DIV2 (1 / N _IF ) set to a predetermined division ratio, the intermediate frequency division is performed. A double intermediate frequency signal is formed from the output of the device DIV2 (1 / N _IF ). The double intermediate frequency signal is supplied to the input of the 90 ° phase shifter 90degShift, thereby forming two intermediate frequency signals of 68.624 MHz having different 90 ° phases. The transmission mixers TX-MIX_I and TX-MIX_Q are supplied with the baseband transmission signals TxABI and TxABQ from the baseband LSI (BB_LSI) and two intermediate frequency signals of 68.624 MHz that are 90 ° out of phase. A vector synthesized 68.624 MHz intermediate frequency transmission signal is formed at the output of the adder connected to the outputs of the mixers TX-MIX_I and TX-MIX_Q. The intermediate frequency transmission signal of 68.624 MHz is supplied to one input terminal of the phase comparator PC. The output of the phase comparator PC is supplied to the RF transmission voltage controlled oscillator TXVCO via the low pass filter LPF1, so that the oscillation frequency of the RF transmission voltage controlled oscillator TXVCO is controlled to about 3431.2 MHz. The frequency transmission band of the GSM850 MHz RF transmission signal Tx_GSM850 is 824 MHz to 849 MHz, and the two frequency dividers DIV5 (1 / 2) is supplied to the input of the first RF power amplifier RF_PA1 via the frequency divider DIV3 (1/2). The frequency band of the RF transmission signal Tx_GSM900 in the band of GSM 900 MHz is 880 MHz to 915 MHz, and the two frequency dividers DIV5 (1 / 2) is supplied to the input of the first RF power amplifier RF_PA1 via the frequency divider DIV3 (1/2). The frequency band of the RF transmission signal Tx_DCS1800 in the band of DCS 1800 MHz is 1710 MHz to 1785 MHz, and one frequency divider DIV5 (1 / 2) to the input of the second RF power amplifier RF_PA2. The frequency band of the RF transmission signal Tx_PCS1900 in the PCS 1900 MHz band is 1850 MHz to 1910 MHz, and one frequency divider DIV5 (1 / 2) to the input of the second RF power amplifier RF_PA2.

To accommodate transmission operation of the 880MHz~915MHz the frequency band of the RF transmit signal Tx_GSM900 frequency band 824MHz~848MHz and GSM900MHz band band of the RF transmission signal Tx_GSM850 of the GSM 850 MHz, the RF voltage-controlled oscillator RFVCO oscillation frequency _{f RFVCO} Is one input of the frequency control mixer DWN_MIX_PM for phase control feedback of the transmission system offset PLL circuit TX_Offset_PLL via two frequency dividers DIV1 (1/2) and DIV4 (1/2) set to a frequency division ratio of 2 Supplied to the terminal. Further, an intermediate frequency divider DIV2 connected to a 90 ° phase shifter 90degShift (1/2) connected to two mixing circuits TX-MIX_I and TX-MIX_Q that constitute a transmission mixer of the transmission system offset PLL circuit TX_Offset_PLL ( The frequency division ratio N _IF of 1 / N _IF is set to 26. Accordingly, two frequency dividers DIV5 (1/2) and frequency divider DIV3 (1/2) in which the oscillation output signal of the oscillation frequency f _TXVCO of the RF transmission voltage controlled oscillator TXVCO is set to the frequency division ratio 2 are Is supplied to one input terminal of the phase control feedback frequency downmixer DWN_MIX_PM, and the other input terminal of the phase control feedback frequency downmixer DWN_MIX_PM is _divided by ¼ of the oscillation frequency f _RFVCO of the RF voltage controlled oscillator RFVCO. The signal is supplied through two frequency dividers DIV1 (1/2) and DIV4 (1/2). In the phase control feedback frequency downmixer DWN_MIX_PM, the 1/4 frequency signal of the oscillation frequency f _RFVCO is mixed with the 1/4 frequency signal of the oscillation frequency signal _fTXVCO of the RF transmission voltage control oscillator TXVCO. Is called. Therefore, a feedback signal having a frequency difference of (1/4) × f _RFVCO− (1/4) f _TXVCO is formed from the output of the phase control feedback frequency downmixer DWN_MIX_PM, and the phase of the transmission system offset PLL circuit TX_Offset_PLL It is supplied to the other input terminal of the comparator PC. Further, one input terminal of the phase comparator PC is supplied with an intermediate frequency transmission signal f _IF that is vector-synthesized at the output of the adder connected to the outputs of the transmission mixers TX-MIX_I and TX-MIX_Q. . This intermediate frequency transmission signal f _IF is divided into f _RFVCO / 52 by a 1/2 frequency division function with 26 which is a frequency division ratio N _IF of the intermediate frequency divider DIV2 (1 / N _IF ) and a 90 ° phase shifter 90 degShift. It becomes. By the negative feedback control of the transmission system offset PLL circuit TX_Offset_PLL, the reference frequency of one input terminal of the phase comparator PC matches the negative feedback frequency of the other input terminal of the phase comparator PC, and therefore the following relationship is established. .

_{f RFVCO / 52 = (1/4)} × f RFVCO - (1/4) × f TXVCO
_{(1/4) × f TXVCO = (} 1/4) × f RFVCO -f RFVCO / 52
= ((13-1) / 52) * f _RFVCO
= (12/52) × _{f RFVCO
∴f RFVCO = 4.33333 × (1/4)} × f TXVCO
Therefore, the oscillation frequency of the RF voltage controlled oscillator RFVCO corresponds to the transmission operation of 824 MHz to 848 MHz in the frequency band of the GSM850 MHz band RF transmission signal Tx_GSM850 and 880 MHz to 915 MHz in the frequency band of the GSM900 MHz band RF transmission signal Tx_GSM900. the f _RFVCO may be set to 4.33333 times the 1/4 frequency signal of the oscillation frequency _{f TXVCO} of the RF transmission voltage-controlled oscillator _{TXVCO ((1/4) × f TXVCO} ). Therefore, in response to 824MHz~849MHz the frequency band of the RF transmit signal Tx_GSM850 band the GSM 850 MHz, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO may be set to 3570.6639MHz～3678.9971MHz, band GSM900MHz in response to 880MHz~915MHz the frequency band of the RF transmit signal Tx_GSM900, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO may be set to 3813.3304MHz～3974.997MHz.

In order to support the transmission operation of the RF transmission signal Tx_DCS1800 in the frequency band of DCS 1800 MHz from 1710 MHz to 1785 MHz in the frequency band of the RF transmission signal Tx_PCS1900 in the band of PCS1900 MHz, the oscillation frequency f RFVCO of the RF voltage controlled oscillator _RFVCO Is supplied to one input terminal of the frequency control mixer DWN_MIX_PM for phase control feedback of the transmission system offset PLL circuit TX_Offset_PLL via one frequency divider DIV1 (1/2) set to the frequency division ratio 2. Further, an intermediate frequency divider DIV2 connected to a 90 ° phase shifter 90degShift (1/2) connected to two mixing circuits TX-MIX_I and TX-MIX_Q that constitute a transmission mixer of the transmission system offset PLL circuit TX_Offset_PLL ( The frequency division ratio N _IF of 1 / N _IF is set to 26. Therefore, the frequency control mixer DWN_MIX_PM for phase control feedback passes through one frequency divider DIV5 (1/2) in which the oscillation output signal of the oscillation frequency f _TXVCO of the RF transmission voltage controlled oscillator TXVCO is set to the frequency division ratio 2. Of the phase control feedback frequency down mixer DWN_MIX_PM is supplied with a divide-by-one signal DIV1 (a half-frequency- _divided signal of the oscillation frequency f _RFVCO of the RF voltage controlled oscillator RFVCO). 1/2). Mixing is carried out in 1/2 divided signal of the oscillation output signal of the oscillation frequency _{f TXVCO} of 1/2 frequency division signal and the RF transmission voltage-controlled oscillator TXVCO of the phase control feedback frequency down mixer DWN_MIX_PM the oscillation frequency _{f RFVCO} . Therefore, a feedback signal having a frequency difference of (1/2) × f _RFVCO− (1/2) × f _TXVCO is formed from the output of the phase control feedback frequency down mixer DWN_MIX_PM, and the transmission system offset PLL circuit TX_Offset_PLL It is supplied to the other input terminal of the phase comparator PC. Further, one input terminal of the phase comparator PC is supplied with an intermediate frequency transmission signal f _{IF that} is vector-synthesized with the output of an adder connected to the outputs of the transmission mixers TX-MIX_I and TX-MIX_Q. This intermediate frequency transmission signal f _IF is divided into f _RFVCO / 52 by a 1/2 frequency division function with 26 which is a frequency division ratio N _IF of the intermediate frequency divider DIV2 (1 / N _IF ) and a 90 ° phase shifter 90 degShift. It becomes. By the negative feedback control of the transmission system offset PLL circuit TX_Offset_PLL, the reference frequency of one input terminal of the phase comparator PC matches the negative feedback frequency of the other input terminal of the phase comparator PC, and therefore the following relationship is established. .

_{f RFVCO / 52 = (1/2)} × f RFVCO - (1/2) × f TXVCO
_{(1/2) × f TXVCO = (} 1/2) × f RFVCO -f RFVCO / 52
= ((26-1) / 52) × f RFVCO = (25/52) × f RFVCO
_{∴f RFVCO = 2.08 × (1/2)} × f TXVCO
Accordingly, the oscillation frequency of the RF voltage controlled oscillator RFVCO corresponds to the transmission operation of 1710 MHz to 1785 MHz in the frequency band of the RF transmission signal Tx_DCS1800 in the band of DCS1800 MHz and 1850 MHz to 1910 MHz in the frequency band of the RF transmission signal Tx_PCS1900 in the band of PCS1900 MHz. the f _RFVCO may be set to 2.08 times the 1/2 frequency division signal of the oscillation frequency _{f TXVCO} of the RF transmission voltage-controlled oscillator _{TXVCO ((1/2) × f TXVCO} ). Therefore, in response to 1710MHz~1785MHz the frequency band of the RF transmit signal Tx_DCS1800 band DCS1800 MHz, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO it may be set to 3556.8MHz～3712.8MHz, band PCS1900MHz in response to 1850MHz~1910MHz the frequency band of the RF transmit signal Tx_PCS1900, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO may be set to 3848MHz～3972.8MHz.

  FIG. 25 is a diagram showing a configuration of a communication semiconductor integrated circuit RF IC according to a more specific embodiment of the present invention.

  This RF IC employs a polar-loop transmission method for supporting the EDGE method in which communication between a base station and a communication terminal device uses amplitude modulation for both phase modulation.

  One semiconductor chip of the RF IC includes three subunits Frct_Synth, RX SPU, and TX SPU. In addition to the RF IC, FIG. 25 also shows an antenna ANT for transmission / reception of a mobile phone terminal device and a front-end module FEM. The front end module FEM includes an antenna switch ANT_SW, a transmission RF power amplifier RF_PA, and a power coupler CPL for detecting transmission power from the transmission RF power amplifier RF_PA.

In FIG. 25, Frct_Synth is an RF carrier synchronization subunit configured by the fractional PLL circuit or the fractional synthesizer described with reference to FIG. In the RF carrier synchronization subunit Frct_Synth, the fractional frequency synthesizer to which the system reference clock signal from the system reference clock oscillator DCXO in which the oscillation frequency frequency f _REF is stably maintained by the crystal resonator Xtal outside the integrated circuit RF IC is applied. The RF oscillation frequency f RFVCO of the RF oscillator _RFVCO is also maintained stably. The RF output of the RF oscillator RFVCO is supplied to the frequency divider DIV1 (DIV4) (1/2 or 1/4), so that RF from the output of the frequency divider DIV1 (DIV4) (1/2 or 1/4) A signal ΦRF is obtained. The RF signal ΦRF is supplied to the RF reception signal analog signal processing subunit RX SPU and the RF transmission signal analog signal processing subunit TX SPU in the communication RF analog signal processing integrated circuit RF IC. That is, the RF transmission signal analog signal processing subunit 302TX SPU is configured in a polar loop system to support the EDGE system.

  In the time slot set to the reception state, the antenna switch ANT_SW of the front end module FEM is connected to the upper side. Therefore, the RF reception signal received by the antenna ANT is supplied to the input of the low noise amplifier LNA of the RF reception signal analog signal processing subunit RX SPU via the reception filter SAW configured by, for example, a surface acoustic wave device. The RF amplified output signal of the low noise amplifier LNA is supplied to one input of two mixing circuits RX-MIX_I and RX-MIX_Q constituting the receiving mixer. The other input of the two mixing circuits RX-MIX_I and RX-MIX_Q has a 90 ° phase shifter 90degShift (1/1 based on the RF signal ΦRF from the frequency divider DIV1 (DIV4) (1/2 or 1/4). Two RF carrier signals having a 90 ° phase formed in 2) are supplied. As a result, in the mixer circuits RX-MIX_I and RX-MIX_Q of the reception mixer, direct down frequency conversion from the RF reception signal frequency to the baseband signal frequency is performed, and reception analog baseband signals RxABI and RxABQ are obtained from the output. The received analog baseband signals RxABI and RxABQ are amplified by variable gain amplifiers PGA1, PGA1, PGA3, PGAQ1, PGAQ2, and PGAQ3 whose gains are adjusted according to the reception time slot setting, and then A / D conversion in the chip of the RF IC Is converted into a digital signal. This digital received signal is supplied to a baseband signal processing LSI (not shown).

In the time slot set to the transmission state, a digital transmission baseband signal is supplied to the RF IC from a baseband signal processing LSI (not shown). As a result, the analog baseband transmission signals TxABI and TxABQ are converted from the output of the D / A converter (not shown) inside the RF IC into two mixing circuits TX-MIX_I of the transmission mixer of the RF transmission signal analog signal processing subunit TX SPU. , TX-MIX_Q. By RF oscillation frequency _{f RFVCO} of RF oscillator RFVCO it is divided by an intermediate frequency divider DIV2 (1 _{/ N IF),} intermediate frequency _{f IF} of the signal ΦIF is obtained. Two IF transmission carrier signals having a 90 ° phase formed by a 90 ° phase shifter 90degShift based on the IF signal ΦIF are supplied to the other inputs of the two mixing circuits TX-MIX_I and TX-MIX_Q. As a result, in the mixer circuits TX-MIX_I and TX-MIX_Q of the transmission mixer, frequency up-conversion from the frequency of the analog baseband transmission signal to the IF transmission signal is executed, and one IF transmission modulation vector-synthesized from the adder A signal is obtained. The IF transmission modulation signal from the adder is supplied to one input of the phase comparator PC constituting the PM loop circuit PM LP for transmission of the phase modulation component of the RF transmission signal analog signal processing subunit TX SPU. In the PM loop circuit PM LP, the output of the phase comparator PC is transmitted to the control input of the transmission oscillator TXVCO via the charge pump CP and the low pass filter LF1.

  The operating voltage from the voltage regulator Vreg is supplied to the buffer amplifier BF whose input is connected to the output of the transmission oscillator TXVCO. The output of the transmission voltage controlled oscillator TXVCO is supplied to the input of the PM loop frequency downmixer DWN_MIX_PM to which the RF signal ΦRF is supplied from the frequency divider DIV1 (DIV4) (1/2 or 1/4), so that DWN_MIX_PM The first IF transmission feedback signal is obtained from the output of. For the phase modulation information when the transmission time slot is GSM, the first IF transmission feedback signal is supplied to the other input of the phase comparator PC constituting the PM loop circuit PM LP via the switch SW_1. As a result, the transmission signal that is the output of the transmission RF power amplifier RF_PA includes accurate phase modulation information of the GSM system. Further, transmission power information (amplification gain of the RF power amplifier RF_PA for transmission) when the transmission time slot is the GSM system is specified by the lamp output voltage Vramp of the ramp signal D / A converter Ramp DAC in the RF IC. This lamp output voltage Vramp is supplied to the 10 MHz filter (10 MHz Filter) via the switch SW2. The lamp output voltage Vramp from this filter and the transmission power detection signal Vdet from the power coupler CPL for detecting the transmission power of the transmission RF power amplifier RF_PA and the power detection circuit PDET are supplied to the error amplifier Err_Amp. By the power supply voltage control or bias voltage control by the automatic power control voltage Vapc from the output of the error amplifier Err_Amp, the amplification gain of the transmission RF power amplifier RF_PA is set in proportion to the distance between the base station and the portable communication terminal device. The digital ramp input signal supplied from the baseband signal processing unit such as the baseband LSI to the ramp signal D / A converter Ramp DAC is a transmission power level indicating signal indicating the level of transmission power. The transmission power level is controlled to be high in proportion to the distance from the communication terminal device. An analog ramp output voltage Vramp is generated from the output of the ramp signal D / A converter Ramp DAC.

  On the other hand, when the transmission time slot is the EDGE system, the IF transmission modulation signal from the adder includes not only phase modulation information but also amplitude modulation information. Therefore, the IF transmission modulation signal from the adder is not only supplied to one input of the phase comparator PC constituting the PM loop circuit PM LP but also one input of the amplitude comparator AC constituting the AM loop circuit AM LP. To be supplied. At this time, the output of the transmission oscillator TXVCO is not supplied to the other input of the phase comparator PC via the PM loop frequency downmixer DWN_MIX_PM. Rather, the information related to the transmission power of the RF power amplifier RF_PA for transmission (RF transmission power level RFPLV) is transmitted through the power coupler CPL, the variable gain circuit MVGA, and the frequency down mixer DWN_MIX_AM for the AM loop to the other of the phase comparator PC. Will be supplied to the input. Further, the information (RF transmission power level RFPLV) related to the transmission power of the transmission RF power amplifier RF_PA is also supplied to the other input of the amplitude comparator AC that constitutes the AM loop circuit AM LP, the power coupler CPL, and the variable gain circuit MVGA. , And AM loop frequency down mixer DWN_MIX_AM. In the AM loop circuit AM LP, the output of the amplitude comparator AC is supplied to the 10 MHz filter (10 MHz Filter) via the low pass filter LF2, the variable gain circuit IVGA, the voltage / current converter V / I, the charge pump CP, and the switch WS2. . As a result, the transmission power signal output from the transmission RF power amplifier RF_PA that amplifies the RF oscillation output signal of the transmission oscillator TXVCO is first included in the PM loop circuit PM LP including accurate EDGE phase modulation information. Further, the AM loop circuit AM LP causes the transmission power signal output from the transmission RF power amplifier RF_PA to include accurate amplitude modulation information of the EDGE system.

  As the power coupler CPL that detects the transmission power of the transmission RF power amplifier RF_PA, a coupler that detects the transmission power of the RF power amplifier RF_PA electromagnetically or capacitively can be used. As this power coupler CPL, a current sense type coupler can also be employed. In this current sense type coupler, a small detection DC / AC operation current proportional to the DC / AC operation current of the final stage power amplification element of the RF power amplifier RF_PA is caused to flow to the detection amplification element.

  In the RF IC of FIG. 25, the control circuit CNTL is set so that the gains of the two variable gain circuits MVGA and IVGA of the AM loop circuit AM LP responding to the ramp voltage Vramp of the ramp signal D / A converter Ramp DAC are reversed. Generates two 8-bit control signals in response to the 10-bit digital ramp signal. That is, when the gain of the variable gain circuit MVGA decreases in response to the ramp voltage Vramp, the sum of the gains of the two variable gain circuits MVGA and IVGA becomes substantially constant by increasing the gain of the variable gain circuit IVGA. As a result, the phase margin of the open loop frequency characteristic of the AM loop circuit AM LP is significantly reduced in response to the ramp voltage Vramp.

  FIG. 26 shows an RF IC that is different from the RF IC that employs the polar-loop transmission method shown in FIG. 23 because the communication with the base station corresponds to the EDGE method that uses amplitude modulation for both phase modulation. That is, the RF IC shown in FIG. 24 employs a polar modulator transmission method in order to support the EDGE method in which amplitude modulation is used for both phase modulation and communication with the base station. The processing subunit TX SPU is configured in a polar modulator system for supporting the EDGE system.

  That is, the amplitude modulation loop control circuit AM_LP for controlling the amplitude of the RF transmission output signal from the transmission RF power amplifier RF_PA based on the transmission intermediate frequency signal formed by the transmission modulation circuits TX_MIX_I and TX_MIX_Q is as follows: It is configured.

  In this AM loop circuit AM LP, the output of the amplitude comparator AC is the low-pass filter LF2, the variable gain circuit IVGA, the voltage / current converter V / I, the output of the buffer amplifier BF via the charge pump CP, and the transmission voltage controlled oscillator. The signal is supplied to an amplitude modulation variable gain amplifier VGA inserted between the TXVCO input and the TXVCO input. A transmission intermediate frequency signal formed by the transmission modulation circuit (TX_MIX_I, TX_MIX_Q) is supplied to one input terminal of the phase comparator AC of the AM loop circuit AM LP. At the other input terminal of the phase comparator AC, information (RF transmission power level RFPLV) related to the transmission power of the transmission RF power amplifier RF_PA is the power coupler CPL, variable gain circuit MVGA, AM loop frequency down mixer DWN_MIX_AM Is supplied through. As a result, it is inserted between the output of the buffer amplifier BF and the input of the transmission voltage controlled oscillator TXVCO so that the IF signal amplitude of the other input terminal matches the IF signal amplitude of one input terminal of the amplitude comparator AC. The gain of the amplitude modulation variable gain amplifier VGA is controlled by the output of the amplitude comparator AC via the low-pass filter LF2, the variable gain circuit IVGA, the voltage / current converter V / I, and the charge pump CP. As a result, the transmission power of the transmission RF power amplifier RF_PA includes accurate amplitude modulation information of the EDGE method.

  In both the GSM system and the EDGE system, the ramp output voltage Vramp of the ramp signal D / A converter Ramp DAC, the power coupler CPL that detects the transmission power of the transmission RF power amplifier 203, and the power detection circuit PDET The transmission power detection signal Vdet from is supplied to the error amplifier Err_Amp. By the power supply voltage control or bias voltage control using the automatic power control voltage Vapc from the output of the error amplifier Err_Amp, the amplification gain of the RF power amplifier RF_PA for transmission is set in proportion to the distance between the base station and the portable communication terminal device. Control is performed.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the charge pump circuit CPC shown in FIGS. 16 and 17, the N-channel MOS transistor and the P-channel MOS transistor constituting the current mirror can be replaced with an NPN bipolar transistor and a PNP bipolar transistor, respectively.

FIG. 1 is a diagram showing a configuration of a fractional synthesizer formed on a chip of a communication semiconductor integrated circuit RF IC examined by the present inventors prior to the present invention. FIG. 2 is a diagram showing a configuration of the ΣΔ modulator of the fractional synthesizer shown in FIG. FIG. 3 is a diagram showing the operation of the ΣΔ modulator of the fractional synthesizer shown in FIG. FIG. 4 is a diagram showing a MASH type ΣΔ modulator used in the fractional synthesizer of FIG. FIG. 5 is a diagram showing a circuit configuration of the dither shown in FIG. FIG. 6 is a diagram showing a circuit configuration of the phase comparator, charge pump circuit, and low-pass filter of the fractional synthesizer of FIG. FIG. 7 shows an ideal state where the current value of the source current of the P-channel MOS transistor of the charge pump circuit and the current value of the sink current of the N-channel MOS transistor in the fractional synthesizer of FIG. It is a figure which shows the waveform of each part of a phase comparator and a charge pump circuit in an unlocked state when the phase of the frequency-divided output signal from the frequency divider is ahead of the phase of the reference frequency signal. FIG. 8 shows an ideal state in which the current value of the source current of the P-channel MOS transistor of the charge pump circuit and the current value of the sink current of the N-channel MOS transistor in the fractional synthesizer of FIG. It is a figure which shows the waveform of each part of the phase comparator PDC and the charge pump circuit CPC in the locked state in which the phase of the reference frequency signal and the phase of the divided output signal from the divider match. FIG. 9 shows a realistic state where the current value of the sink current of the N channel MOS transistor is smaller than the current value of the source current of the P channel MOS transistor of the charge pump circuit in the fractional synthesizer of FIG. It is a figure which shows the waveform of each part of the phase comparator PDC and the charge pump circuit CPC in the locked state with a phase difference offset in which the phase of the frequency-divided output signal from the frequency divider is ahead of the phase of the reference frequency signal. FIG. 10 shows a realistic state where the current value of the sink current of the N-channel MOS transistor is smaller than the current value of the source current of the P-channel MOS transistor of the charge pump circuit in the fractional synthesizer of FIG. It is a figure which shows the waveform of each part of a phase comparator and a charge pump circuit at the time of changing a frequency ratio from a high frequency division ratio to a low frequency division ratio. FIG. 11 shows a practical state where the current value of the sink current of the N-channel MOS transistor is smaller than the current value of the source current of the P-channel MOS transistor of the charge pump circuit in the fractional synthesizer of FIG. It is a figure which shows the waveform of each part of a phase comparator and a charge pump circuit at the time of changing from a low frequency division ratio to a comparatively high frequency division ratio. FIG. 12 shows a realistic state where the current value of the sink current of the N-channel MOS transistor is smaller than the current value of the source current of the P-channel MOS transistor of the charge pump circuit in the fractional synthesizer of FIG. It is a figure which shows the waveform of each part of a phase comparator and a charge pump circuit at the time of changing a frequency ratio from a low frequency division ratio to a considerably high frequency division ratio. FIG. 13 is a diagram showing the phase noise characteristics of the fractional PLL circuit when the current values of the sink current I sink and the source current I source of the charge pump circuit of FIG. 6 are equal. FIG. 14 is a diagram showing the phase noise characteristics of the fractional PLL circuit when the current value of the source current Isource is larger than the current value of the sink current I sink of the charge pump circuit of FIG. FIG. 15 is a diagram showing a configuration of a fractional synthesizer formed on a chip of a communication semiconductor integrated circuit according to one embodiment of the present invention. 16 shows a phase comparator and a charge pump circuit constituting a fractional N PLL circuit of a fractional synthesizer formed on a chip of a communication semiconductor integrated circuit according to one embodiment of the present invention shown in FIG. It is a circuit diagram which shows a structure. FIG. 17 is a diagram showing that an offset circuit for flowing a dc direct current from the low-pass filter to the ground potential is configured by a resistor Roffset. FIG. 18 is a diagram showing the device size of the MOS transistor of the charge pump circuit CPC shown in FIG. FIG. 19 is a diagram showing a device size of the resistor Roffset shown in FIG. FIG. 20 is a circuit diagram showing the structure of the phase comparator and charge pump circuit of the fractional N PLL circuit of the fractional synthesizer according to the embodiment of the present invention shown in FIG. It is a figure which shows the waveform of each part of a phase comparator and a charge pump circuit at the time of removing the offset circuit to flow. FIG. 21 shows a dc direct current from the low pass filter to the ground potential as shown in the configuration of the phase comparator and the charge pump circuit constituting the fractional N PLL circuit of the fractional synthesizer according to one embodiment of the present invention of FIG. It is a figure which shows the waveform of each part of a phase comparator and a charge pump circuit at the time of adding the offset circuit which sends an electric current. FIG. 22 is a circuit diagram showing the structure of the phase comparator and charge pump circuit of the fractional N PLL circuit of the fractional synthesizer according to one embodiment of the present invention shown in FIG. It is a figure which shows the phase noise characteristic of a fractional PLL circuit at the time of removing the flowing offset circuit. FIG. 23 shows a dc direct current from the low pass filter to the ground potential as shown in the configuration of the phase comparator and the charge pump circuit constituting the fractional N PLL circuit of the fractional synthesizer according to one embodiment of the present invention of FIG. It is a figure which shows the phase noise characteristic of the fractional PLL circuit at the time of adding the offset circuit which sends an electric current. FIG. 24 is a diagram showing a configuration of a communication semiconductor integrated circuit RF IC according to a more specific embodiment of the present invention. FIG. 25 is a diagram showing a configuration of a semiconductor integrated circuit for communication according to a more specific embodiment of the present invention. FIG. 26 is a diagram showing a configuration of a communication semiconductor integrated circuit according to a more specific embodiment of the present invention. FIG. 27 is a diagram illustrating a frequency spectrum of an RF transmission signal of a mobile phone terminal device defined by the GMSK standard.

Explanation of symbols

RF IC communication semiconductor integrated circuit DCXO reference frequency oscillator PDC phase comparator CPC charge pump circuit MP1 source current injection transistor MN1 sink current emission transistor Isource source current I sink sink current MN2, MN3 offset circuit Ioffset offset current LFC loop filter

Claims (14)

A reference frequency oscillator for generating a reference frequency signal of a reference oscillation frequency, a phase comparator in which the reference frequency signal formed from the reference frequency oscillator is supplied to one input terminal, and an up output signal of the phase comparator; A charge pump circuit responsive to a down output signal, a low pass filter responsive to a charge pump current of the charge pump circuit, an RF voltage controlled oscillator responsive to a control output voltage of the low pass filter, and an output of the RF voltage controlled oscillator A PLL circuit constituting a frequency synthesizer by including a frequency divider connected between the terminal and the other input terminal of the phase comparator;
An RF transmission voltage controlled oscillator that generates an RF transmission frequency signal for an RF transmission signal of RF communication using an RF oscillation output signal of the output terminal of the RF voltage controlled oscillator of the PLL circuit. ,
The PLL circuit constituting the frequency synthesizer is a fractional PLL circuit in which an average frequency division ratio includes an integer and a fraction by changing a frequency division ratio of the frequency divider, and a closed loop bandwidth thereof is several tens of KHz. Set to a narrow band of the order of
The charge pump circuit includes a source current supply transistor that injects a source current into the low pass filter in response to the up output signal of the phase comparator, and the low pass filter in response to the down output signal of the phase comparator. A sink current discharge transistor for discharging a sink current from the low-pass filter; and an offset current circuit for discharging a dc direct-current from the low-pass filter or injecting a dc direct-current into the low-pass filter;
The offset current circuit includes a device set to an intentional device size so as to set the dc direct current to a predetermined value. The PLL circuit constituting the frequency synthesizer includes an intermediate frequency divider that generates an intermediate frequency signal by dividing the RF oscillation output signal generated from the RF voltage controlled oscillator,
The semiconductor integrated circuit includes: a transmission mixer that forms an intermediate frequency transmission signal from the intermediate frequency signal generated from the intermediate frequency divider and a transmission baseband signal; a transmission system offset PLL circuit; and the RF voltage controlled oscillator An RF divider that generates a divided RF frequency signal by dividing the RF oscillation output signal generated from
The transmission system offset PLL circuit includes a phase comparison circuit to which the intermediate frequency transmission signal generated from the transmission mixer is supplied to one input terminal, and the RF transmission voltage controlled oscillator that responds to an output of the phase comparison circuit The RF transmission frequency signal generated from the RF transmission voltage-controlled oscillator is supplied to one input terminal, and the divided RF frequency signal generated from the RF divider is supplied to the other input terminal. The communication semiconductor integrated circuit according to claim 1, further comprising: a phase control feedback frequency downmixer, wherein an output signal of the phase control feedback frequency downmixer is supplied to the other input terminal of the phase comparison circuit. Including an RF reception signal analog signal processing circuit,
The RF reception signal analog signal processing circuit includes a low noise amplifier that amplifies the RF reception signal, and a reception mixer that generates a reception baseband signal by being supplied with the RF amplified reception output signal generated by the low noise amplifier. ,
The PLL circuit constituting the frequency synthesizer divides the RF oscillation output signal of the oscillation frequency generated from the RF voltage controlled oscillator to form an RF carrier signal to be supplied to the reception mixer. A frequency divider, and a second frequency divider that divides the output signal of the first frequency divider,
When the semiconductor integrated circuit receives the RF reception signal in the GSM850 MHz frequency band or GSM900 MHz frequency band, the divided output signal generated from the first frequency divider is supplied to the reception mixer as the RF carrier signal. By being transmitted, a reception baseband signal frequency-converted from the RF reception signal in the frequency band of the GSM850 MHz or the frequency band of the GSM900 MHz is generated from the reception mixer,
When the semiconductor integrated circuit receives the RF reception signal in the frequency band of DCS 1800 MHz or the frequency band of PCS 1900 MHz, the RF oscillation output signal of the oscillation frequency generated from the RF voltage controlled oscillator is used as the RF carrier signal. By being transmitted to the reception mixer, a frequency-converted reception baseband signal is generated from the RF reception signal in the frequency band of the DCS 1800 MHz or the frequency band of the PCS 1900 MHz,
When the semiconductor integrated circuit forms the RF transmission frequency signal in the GSM850 MHz frequency band or GSM900 MHz frequency band, the intermediate frequency transmission signal is formed from the intermediate frequency signal and the transmission baseband signal by the transmission mixer. When the first frequency divider and the second frequency divider operate as the RF frequency divider, the frequency division output signal of the second frequency divider becomes the phase control feedback of the transmission system offset PLL circuit. Is transmitted to the other input terminal of the frequency downmixer as the divided RF frequency signal, and the intermediate frequency transmission signal is transmitted in the frequency band of the GSM850 MHz or the frequency band of the GSM900 MHz in the transmission system offset PLL circuit. Frequency converted to RF transmission frequency signal,
When the semiconductor integrated circuit forms the RF transmission frequency signal in the frequency band of DCS 1800 MHz or the frequency band of PCS 1900 MHz, the intermediate frequency transmission signal is formed from the intermediate frequency signal and the transmission baseband signal by the transmission mixer. When the first frequency divider operates as the RF frequency divider, the frequency-divided output signal of the first frequency divider becomes the other frequency control mixer for the phase control feedback of the transmission system offset PLL circuit. The divided frequency signal is transmitted to the input terminal as the divided RF frequency signal, and the intermediate frequency transmission signal is frequency-converted to the RF transmission frequency signal in the frequency band of DCS1800 MHz or the frequency band of PCS1900 MHz by the transmission system offset PLL circuit. The communication semiconductor according to claim 2. Product circuit.   The communication semiconductor integrated circuit is configured by a polar loop system to support the EDGE system, and the transmission system offset PLL circuit includes a phase loop for polar loop system phase modulation, an amplitude loop of the polar loop system, 3. The communication semiconductor integrated circuit according to claim 2, wherein the phase comparator of the transmission system offset PLL circuit, the RF transmission voltage control oscillator, and the phase control feedback frequency down mixer constitute the phase loop. .   The semiconductor integrated circuit for communication is configured by a polar modulator system to support the EDGE system, and the transmission system offset PLL circuit includes a phase loop for phase modulation of the polar modulator system and an amplitude loop of the polar modulator system. 3. The communication semiconductor integrated circuit according to claim 2, wherein the phase comparator of the transmission system offset PLL circuit, the RF transmission voltage control oscillator, and the phase control feedback frequency down mixer constitute the phase loop. .   6. The fractional PLL circuit includes a ΣΔ modulator for calculating the fraction of the average division ratio, and the ΣΔ modulator is a MASH type having a plurality of first-order ΣΔ modulators. A semiconductor integrated circuit for communication according to any one of the above.   The communication semiconductor integrated circuit according to claim 6, wherein the MASH type ΣΔ modulator is supplied with pseudo-random noise from a dither circuit via a digital differentiator. An RF reception signal analog signal processing circuit, an RF transmission signal analog signal processing circuit, and a frequency synthesizer;
The RF reception signal analog signal processing circuit is supplied with a low noise amplifier that amplifies the RF reception signal, an RF amplification reception output signal generated by the low noise amplifier, and a reception carrier signal generated by the frequency synthesizer. A receiving mixer for generating a receiving baseband signal,
The RF transmission signal analog signal processing circuit includes a transmission mixer to which a transmission baseband signal is supplied from a baseband signal processing unit, and the RF transmission signal analog signal processing circuit is supplied with a transmission carrier signal generated by the frequency synthesizer Thus, the RF transmission signal analog signal processing circuit generates an RF transmission signal,
The frequency synthesizer includes a reference frequency oscillator that generates a reference frequency signal of a reference oscillation frequency, a phase comparator in which the reference frequency signal formed from the reference frequency oscillator is supplied to one input terminal, and the phase comparator A charge pump circuit responsive to an up output signal and a down output signal, a low pass filter responsive to a charge pump current of the charge pump circuit, an RF voltage controlled oscillator responsive to a control output voltage of the low pass filter, and the RF A PLL circuit including a frequency divider connected between the output terminal of the voltage controlled oscillator and the other input terminal of the phase comparator;
The PLL circuit constituting the frequency synthesizer is a fractional PLL circuit in which an average frequency division ratio includes an integer and a fraction by changing a frequency division ratio of the frequency divider, and a closed loop bandwidth thereof is several tens of KHz. Set to a narrow band of the order of
The charge pump circuit includes a source current supply transistor that injects a source current into the low pass filter in response to the up output signal of the phase comparator, and the low pass filter in response to the down output signal of the phase comparator. A sink current discharge transistor for discharging a sink current from the low-pass filter; and an offset current circuit for discharging a dc direct-current from the low-pass filter or injecting a dc direct-current into the low-pass filter;
The offset current circuit includes a device set to an intentional device size so as to set the dc direct current to a predetermined value. The PLL circuit constituting the frequency synthesizer includes an intermediate frequency divider that generates an intermediate frequency signal by dividing the RF oscillation output signal generated from the RF voltage controlled oscillator,
The RF transmission signal analog signal processing circuit of the semiconductor integrated circuit includes the transmission mixer that forms an intermediate frequency transmission signal from the intermediate frequency signal generated from the intermediate frequency divider and a transmission baseband signal, and a transmission system An offset PLL circuit, and an RF divider that generates a divided RF frequency signal by dividing the RF oscillation output signal generated from the RF voltage controlled oscillator,
The transmission system offset PLL circuit includes a phase comparison circuit to which the intermediate frequency transmission signal generated from the transmission mixer is supplied to one input terminal, and the RF transmission voltage controlled oscillator that responds to an output of the phase comparison circuit The RF transmission frequency signal generated from the RF transmission voltage controlled oscillator is supplied to one input terminal, and the divided RF frequency signal generated from the RF divider is supplied to the other input terminal. 9. The communication semiconductor integrated circuit according to claim 8, further comprising: a phase control feedback frequency downmixer, wherein an output signal of the phase control feedback frequency downmixer is supplied to the other input terminal of the phase comparison circuit. The PLL circuit constituting the frequency synthesizer divides the RF oscillation output signal of the oscillation frequency generated from the RF voltage controlled oscillator to form an RF carrier signal to be supplied to the reception mixer. A frequency divider, and a second frequency divider that divides the output signal of the first frequency divider,
When the semiconductor integrated circuit receives the RF reception signal in the GSM850 MHz frequency band or GSM900 MHz frequency band, the divided output signal generated from the first frequency divider is supplied to the reception mixer as the RF carrier signal. By being transmitted, a reception baseband signal frequency-converted from the RF reception signal in the frequency band of the GSM850 MHz or the frequency band of the GSM900 MHz is generated from the reception mixer,
When the semiconductor integrated circuit receives the RF reception signal in the frequency band of DCS 1800 MHz or the frequency band of PCS 1900 MHz, the RF oscillation output signal of the oscillation frequency generated from the RF voltage controlled oscillator is used as the RF carrier signal. By being transmitted to the reception mixer, a frequency-converted reception baseband signal is generated from the RF reception signal in the frequency band of the DCS 1800 MHz or the frequency band of the PCS 1900 MHz,
When the semiconductor integrated circuit forms the RF transmission frequency signal in the GSM850 MHz frequency band or GSM900 MHz frequency band, the intermediate frequency transmission signal is formed from the intermediate frequency signal and the transmission baseband signal by the transmission mixer. When the first frequency divider and the second frequency divider operate as the RF frequency divider, the frequency division output signal of the second frequency divider becomes the phase control feedback of the transmission system offset PLL circuit. Is transmitted to the other input terminal of the frequency downmixer as the divided RF frequency signal, and the intermediate frequency transmission signal is transmitted in the frequency band of the GSM850 MHz or the frequency band of the GSM900 MHz in the transmission system offset PLL circuit. Frequency converted to RF transmission frequency signal,
When the semiconductor integrated circuit forms the RF transmission frequency signal in the frequency band of DCS 1800 MHz or the frequency band of PCS 1900 MHz, the intermediate frequency transmission signal is formed from the intermediate frequency signal and the transmission baseband signal by the transmission mixer. When the first frequency divider operates as the RF frequency divider, the frequency-divided output signal of the first frequency divider becomes the other frequency control mixer for the phase control feedback of the transmission system offset PLL circuit. The divided frequency signal is transmitted to the input terminal as the divided RF frequency signal, and the intermediate frequency transmission signal is frequency-converted to the RF transmission frequency signal in the frequency band of DCS1800 MHz or the frequency band of PCS1900 MHz by the transmission system offset PLL circuit. The communication semiconductor according to claim 9. Product circuit.   The communication semiconductor integrated circuit is configured by a polar loop system to support the EDGE system, and the transmission system offset PLL circuit includes a phase loop for polar loop system phase modulation, an amplitude loop of the polar loop system, The communication semiconductor integrated circuit according to claim 9, wherein the phase comparator, the RF transmission voltage-controlled oscillator, and the phase-controlled feedback frequency downmixer of the transmission system offset PLL circuit constitute the phase loop. .   The semiconductor integrated circuit for communication is configured by a polar modulator system to support the EDGE system, and the transmission system offset PLL circuit includes a phase loop for phase modulation of the polar modulator system and an amplitude loop of the polar modulator system. The communication semiconductor integrated circuit according to claim 9, wherein the phase comparator, the RF transmission voltage-controlled oscillator, and the phase-controlled feedback frequency downmixer of the transmission system offset PLL circuit constitute the phase loop. .   13. The fractional PLL circuit includes a ΣΔ modulator for calculating the fraction of the average division ratio, and the ΣΔ modulator is a MASH type having a plurality of first-order ΣΔ modulators. A semiconductor integrated circuit for communication according to any one of the above.   14. The semiconductor integrated circuit for communication according to claim 13, wherein pseudo random noise from a dither circuit is supplied to the MASH type ΣΔ modulator via a digital differentiator.

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