JP2007311650A - Semiconductor device manufacturing method using coating diffusion method and diode structure - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor element using a coating diffusion method for manufacturing a semiconductor element such as a diode or a capacitor formed on an integrated circuit or an interposer substrate using a silicon substrate represented by the semiconductor field by a coating diffusion method, and The present invention relates to a diode structure.

When forming a high withstand voltage planar type diode, it is necessary to adjust the amount of impurity implantation. Therefore, the ion implantation method is used which allows easy concentration control. Alternatively, it can be realized by using a mesa structure that can increase the breakdown voltage structurally instead of the planar type.
For example, Patent Document 1 discloses a conventional technique using an ion implantation method. As shown in FIG. 2, the silicon oxide film 12 formed on the silicon substrate 11 is patterned to form a mask 13, and ion implantation is performed using the mask 13 to introduce impurities 14 into the silicon substrate 11. . Although not shown, an element isolation diffusion layer is formed by forming a silicon oxide film in a portion where the upper layer of the silicon substrate is removed, and introducing impurities into the silicon substrate therethrough. Also, an impurity is introduced from only the silicon oxide film to form a low-concentration diffusion layer on the silicon substrate by an ion implantation method using an antioxidant film and a silicon oxide film formed on the silicon substrate as a mask, thereby preventing oxidation. Impurities are introduced into the silicon substrate from only the film to form a high concentration diffusion layer. This improves the reliability of the ion implantation process.

For example, as shown in FIG. 3, a planar type diode using a coating diffusion method is manufactured by injecting an n ⁺ layer 22 into a p ⁺ silicon substrate 21 and injecting a p ⁺⁺ layer 23 into the n ⁺ layer 22. The p ⁺⁺ n ⁺ layer is used as a diode.
JP-A-7-273186

However, when the ion implantation method is used as in Patent Document 1, it is difficult to manufacture a diode at a low cost because expensive equipment investment such as an ion implantation apparatus is required.
Also, a planar planar diode using the coating diffusion method as shown in FIG. 3 is difficult to manufacture because the impurity concentration cannot be controlled. However, the mesa diode is like a planar type because of its trapezoidal structure. Since there is no concentration difference at the depth direction joint 24 indicated by a broken line frame in FIG. 3 and no curved angle joint R at the depth direction joint 24, high breakdown voltage can be easily obtained. However, the mesa structure is structurally difficult to apply as an element built in a silicon circuit substrate.

Therefore, a planar type diode is preferable as the diode formed in the silicon circuit substrate. Incidentally, in order to form a high-breakdown-voltage planar diode in a silicon circuit substrate at a low cost, a manufacturing process using a coating diffusion method is essential.
However, in the conventional coating diffusion method, impurities are implanted and diffused into the substrate only by thermal diffusion as shown in FIG. 3, so that the diffusion concentration has a concentration gradient in the junction depth direction. On the basis of this manufacturing principle, the depth direction junction 24 becomes high in concentration, and the leakage current increases. In other words, a bonding surface having a low breakdown voltage is formed on the high concentration side (substrate surface side). Further, in the planar type, a curved corner joint R that causes a decrease in breakdown voltage is formed in the diffusion layer.

For these reasons, the conventional coating diffusion method has a problem that a high-breakdown-voltage diode cannot be formed in a silicon circuit substrate at a low cost.
The present invention has been made in view of such a problem, and provides a semiconductor element manufacturing method and a diode structure using a coating diffusion method capable of forming a high breakdown voltage diode in a semiconductor substrate at a low cost. The purpose is to do.

In order to achieve the above object, a method of manufacturing a semiconductor device using a coating diffusion method according to claim 1 of the present invention includes at least one impurity atom of phosphorus, arsenic, antimony, and boron on a semiconductor substrate. After the thermal oxide film is applied, baking is performed to form a diffusion source, and impurities supplied by heating from the diffusion source are diffused into the semiconductor substrate by a certain amount, and then the supply of the impurities is stopped by removing the diffusion source. In this case, an implantation control layer having a fixed number of impurities is formed at n, and an n layer is formed by reheating so that this layer has a target junction depth and concentration, and the n layer is formed in this n layer. In a method of manufacturing a semiconductor device using a coating diffusion method in which a p layer is formed by a method, and a pn structure portion having a polarity of p ⁺⁺ n ⁺ or n ⁺⁺ p ⁺ n ⁻ is formed as a diode in this formation, High concentration portion and low concentration portion of impurities in the pn structure portion Junction in the depth direction as well, characterized in that the bending angle joint and the high density portion and a low density portion joined to the bending angle shape is removed by etching.

  According to this method, in the pn structure portion formed by the coating diffusion method, the breakdown voltage is lowered at the junction in the depth direction between the high-concentration portion and the low-concentration portion of the impurity. Since the electric field concentration is likely to occur at the curved corner joint where the portion and the low-concentration portion are joined in a curved corner shape, the withstand voltage is likely to decrease, but the curved corner joint portion and the joint portion in the depth direction are removed. Since the diode is manufactured, a high breakdown voltage diode can be formed in the semiconductor substrate at a low cost.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device using a coating diffusion method according to the first aspect, wherein the n layer is independently formed in the semiconductor substrate when the n layer is formed in the semiconductor substrate. It is formed and used as a lower electrode of a capacitor.
According to this method, since the capacitor can be manufactured in the same manufacturing process as the diode, it can be manufactured efficiently and the number of manufacturing steps can be reduced.

According to a third aspect of the present invention, there is provided a diode structure in which a pn structure portion having a polarity of p ⁺⁺ n ⁺ or n ⁺⁺ p ⁺ n ⁻ is formed in a semiconductor substrate. The junction in the depth direction between the high-concentration portion and the low-concentration portion of the impurity and the curved corner joint where the high-concentration portion and the low-concentration portion are joined in a curved corner shape are removed. To do.

  According to this structure, in the diode structure having the pn structure portion, the breakdown voltage is lowered at the junction in the depth direction between the high concentration portion and the low concentration portion of the impurity, and the high concentration portion and the low concentration portion are reduced. Since the electric field concentration is likely to occur at the curved corner junction where the portion is joined to the curved corner, the breakdown voltage tends to decrease, but the curved corner junction and the junction in the depth direction are removed to form a diode. Therefore, the diode can have a high breakdown voltage. In addition, since the diode can be formed by a coating diffusion method, a high breakdown voltage diode can be formed in the semiconductor substrate at a low cost.

  As described above, according to the method for manufacturing a semiconductor element using the coating diffusion method of the present invention, there is an effect that a high breakdown voltage diode can be formed in a semiconductor substrate at a low cost.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, parts corresponding to each other in all the drawings in this specification are denoted by the same reference numerals, and description of the overlapping parts will be omitted as appropriate.
FIG. 1 is a process diagram for explaining a diode manufacturing method using a coating diffusion method according to an embodiment of the present invention.
A problem in manufacturing a high-breakdown-voltage diode without using an expensive ion implantation method is the control of impurity concentration and the establishment of an insulation isolation technique. In the present embodiment, in order to achieve the target impurity concentration, a step of stopping impurities supplied from the diffusion source is added, thereby forming a target pn structure. Further, the curved corner joint R, which is a cause of low breakdown voltage and leakage, formed at the bottom of the diffusion layer is structurally separated by using a dry etching method or a wet etching method. With these two points, a high breakdown voltage diode is formed in the silicon (Si) circuit board.

As shown in FIG. 1A, a thermal oxide film (SiO 2) 32 used as a coating diffusion mask is formed on a p ⁻ -Si wafer 31, and the thermal oxide film 32 is patterned by photolithography. A diffusion portion 33 is formed. As a result, a coating diffusion mask is formed.
Next, as shown in (b), in order to form an n ⁺ layer on the Si wafer 31 shown in (c), phosphorus (P) is used as an impurity atom on the upper surface of the wafer after the step (a). To spread the coating. The diffusing agent other P, if n ⁺ layer arsenic (As), antimony (Sb), boron (B) is used if n ⁺⁺ layer. That is, a diffusing agent in which an oxide containing these impurity atoms is dissolved in an organic solvent is uniformly applied to the diffusion portion 33 on the Si wafer 31 and the upper surface of the thermal oxide film 32 by the SOG (Spin on Glass) method. To do. And in order to evaporate the organic solvent contained in the coating layer, baking is performed at 150 to 200 ° C. with a hot plate. Thereby, the diffusion source 35 is formed.

Next, as shown in (c), in order to inject and diffuse impurities from the diffusion source 35 into the Si wafer 31, heating is performed at a temperature of 200 to 1000 ° C. in a nitrogen atmosphere. At this time, a certain amount of impurities are diffused in the Si wafer 31 by appropriately adjusting the temperature and time. Then, once the heating is stopped and the temperature is lowered to room temperature, only the diffusion source 35 is removed by HF (hydrofluoric acid) treatment. As a result, an n ⁺ layer (implantation control layer) 36 having a fixed number of impurities is formed.

After formation of the n ⁺ layer 36, again, subjected to heat, bonding this time, by optimizing the thermal history conditions of the heating temperature and time, to (d), the target n ⁺ layer 36a Control to depth and concentration.
Next, as shown in (e), a p ⁺⁺ layer 37a is formed in the n ⁺ layer 36a in the same manner as in the steps (a) to (d).
Thus, the p ⁺⁺ n ⁺ structure portion formed in the p ⁻ -Si wafer 31 has been conventionally used as a diode. However, the polarity may be an n ⁺⁺ p ⁺ n ⁻ structure.

In the present embodiment, after the above processing, the depth direction junction 24, which is the junction in the depth direction of the high concentration portion of p ^{++ and} the high concentration portion of n ⁺ , where the breakdown voltage is lowered, The curved corner joint R, which is likely to occur, is removed.
For this reason, first, a thermal oxide film used as an etching mask is formed on the upper surface of the wafer after the step (e) with a thickness of about 0.5 to 2 μm. However, the material of the thermal oxide film may be a Si oxide film or a metal film as long as it can serve as an etching mask. Then, as shown in (f), a thermal oxide film is formed on the mask 38 having a removal shape.

Next, as indicated by reference numeral 40 in (g), dry etching using an etching gas such as CF4 or SF6, or wet etching using an alkali solution such as KOH or TMAH, or an acid solution such as a SECCO etching solution. The depth direction joint portion 24 and the bending angle joint portion R are removed. As a result, a diode having the p ⁺⁺ n ⁺ structure portion formed in the p ⁻ -Si wafer 31 and having the depth direction junction 24 and the curved angle junction R in the structure removed is formed.

As described above, according to the present embodiment, the p ⁺⁺ n ⁺ structure portions 36a and 37a are formed in the p ⁻ −Si wafer 31 by using the coating diffusion method, and breaks are generated in the structure portions 36a and 37a. Since the diode is manufactured by removing the depth direction junction 24 where the down voltage is lowered and the curved corner junction R where electric field concentration is likely to occur, a high breakdown voltage diode is formed in the Si wafer 31 at low cost. be able to.

Further, as shown in FIG. 1H, when the n ⁺ layer 36a is formed in the p ⁻ -Si wafer 31 by the above (a) to (d), the n ⁺ layer 36b is independently formed. By using this as the lower electrode of the capacitor, the capacitor can be formed in the same process as the diode. That is, since the capacitor can be manufactured in parallel, it can be manufactured efficiently, and the manufacturing man-hour can be reduced.

It is process drawing for demonstrating the manufacturing method of the diode using the application | coating diffusion method which concerns on embodiment of this invention. It is an ion implantation process figure of patent documents 1. It is a block diagram of the diode manufactured by the conventional application | coating diffusion method.

Explanation of symbols

24 Depth direction junction 31 p ⁻ −Si wafer 32, 38 Thermal oxide film (SiO 2)
33 Diffusion part 35 Diffusion source 36, 36an ⁺ layer (injection control layer)
36b n ⁺ layer for capacitor 37a p ⁺⁺ layer 40 removed portion R curved corner joint

Claims (3)

A diffusion source is formed by applying a thermal oxide film containing at least one impurity atom of phosphorus, arsenic, antimony, and boron on a semiconductor substrate, followed by baking, and the impurities supplied by heating from the diffusion source After diffusing a certain amount in the semiconductor substrate, an implantation control layer having a fixed number of impurities is formed by stopping the supply of the impurities by removing the diffusion source so that this layer has a target junction depth and concentration. An n layer is formed by reheating, and a p layer is formed in the same manner as the n layer is formed on the n layer. In this formation, the polarity is p ⁺⁺ n ⁺ or n ⁺⁺ p ⁺ n ^−. In a manufacturing method of a semiconductor element using a coating diffusion method in which a pn structure portion to be a diode is used,
Etching was performed to remove the junction in the depth direction between the high-concentration portion and the low-concentration portion of the impurity in the pn structure portion, and the curved corner junction where the high-concentration portion and the low-concentration portion are joined in a curved corner shape A method of manufacturing a semiconductor device using a coating diffusion method characterized by the above.   2. The coating diffusion method according to claim 1, wherein when the n layer is formed in the semiconductor substrate, the n layer is independently formed in the semiconductor substrate and used as the lower electrode of the capacitor. A method for manufacturing a semiconductor device. In a diode structure formed by forming a pn structure portion having a polarity of p ⁺⁺ n ⁺ or n ⁺⁺ p ⁺ n ⁻ in a semiconductor substrate,
The junction in the depth direction between the high-concentration portion and the low-concentration portion of the impurity of the pn structure portion, and the curved corner junction where the high-concentration portion and the low-concentration portion are joined in a curved corner shape are removed. Diode structure characterized by

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