JP2007235280A - Gate drive device - Google Patents

Abstract

Provided is a gate driving device capable of suppressing power loss due to dv / dt through current and overcurrent which has been generated conventionally.
A shut-off circuit for shutting off a first power MOS transistor includes two shut-off circuits having different currents for discharging a gate charge. The first power MOS transistor is shut off and the second power MOS transistor is The first power MOS transistor 1 is completely cut off by the cut-off circuit having a large current for discharging the gate charge at the same time as the cut-off and the conduction state.
[Selection] Figure 1

Description

  The present invention relates to a gate driving device for driving a power MOS transistor for controlling power supply to a motor load.

  Conventionally, motor driving devices used in various fields include power saving as one of the desired features, and a PWM driving method is generally used to realize this. The PWM drive system is a system in which the power applied to the motor winding is controlled by turning on and off the upper and lower power MOS transistors connected to the motor winding, and changing the duty ratio of the conduction and cutoff. It is.

  When such a PWM drive system is employed, the power MOS transistor is repeatedly turned on or off by the gate drive device. When the switching speed of conduction or cutoff at the time of PWM driving is slowed down, the power loss of the power MOS transistor becomes large and heat is generated, and there is a case where it is destroyed, so the switching speed must be increased to some extent.

  However, when the switching speed is increased, there is an adverse effect of through current (described in detail below) generated due to parasitic capacitance between the drain and gate and between the gate and source of the power MOS transistor.

The conventional gate driving apparatus as described above will be described below with reference to the drawings.
FIG. 7 is a circuit block diagram showing an example of the configuration of a conventional gate driving device. In the gate drive device 13 of FIG. 7, the first power MOS transistor 1 and the second power MOS transistor 2 are connected in series between the power supplies, and the gate 3 of the first power MOS transistor 1 is controlled by the first drive signal C1. The first gate drive circuit 4 is connected, and the gate 5 of the second power MOS transistor 2 is connected to the second gate drive circuit 6 controlled by the second drive signal C2. The motor driving load 7 is connected to a connection point 8 between the first power MOS transistor 1 and the second power MOS transistor 2. Here, the first drive signal C1 and the second drive signal C2 are signals that repeat a high level (hereinafter referred to as H) and a low level (hereinafter referred to as L), respectively.

  The first gate drive circuit 4 includes a Pch MOS transistor 9 and a resistor 10. The Pch MOS transistor 9 drives the gate by the inverted signal of the first drive signal C1, and the drain and source are between the power supply VPUMP (12) whose voltage is higher than the power supply VCC (11) and the gate of the first power MOS transistor 1, respectively. It is connected to the. The resistor 10 is connected between the gate and source of the first power MOS transistor 1.

The operation of the gate driving device 13 configured as described above will be described below.
First, conduction and cutoff control of the first power MOS transistor 1 will be described.
When the first power MOS transistor 1 is switched from the cutoff state to the conductive state, the first drive signal C1 is changed from L to H. L, which is an inverted signal of the first drive signal C1, is input to the gate of the Pch MOS transistor 9, and the Pch MOS transistor 9 is turned on, so that the gate of the first power MOS transistor 1 is short-circuited to the power supply VPUMP (12). 1 Power MOS transistor 1 is turned on.

  On the other hand, when the first power MOS transistor 1 is cut off from the conduction state, the first drive signal C1 is changed from H to L. The H voltage, which is an inverted signal of the first drive signal C1, is input to the gate voltage of the Pch MOS transistor 9, and the Pch MOS transistor 9 is turned off. At this time, the first power MOS transistor 1 is in a cut-off state by drawing out gate / source charges by the resistor 10.

  Next, when the second power MOS transistor 2 is to be cut off from the conduction state, the gate voltage of the second power MOS transistor 2 is lowered by the second gate drive circuit 6 by changing the second drive signal C2 from H to L. Shut off. In the case of switching from the cutoff state to the conductive state, the second drive signal C2 is changed from L to H so that the gate voltage of the second power MOS transistor 2 is raised by the second gate drive circuit 6 to make it conductive.

  In the above circuit configuration, the first power MOS transistor 1 and the second power MOS transistor 2 are cut off and the regenerative current flows in the direction A in FIG. 7 will be described with reference to FIG. 8 when the drive current flows in the B direction.

  FIG. 8 is a timing chart showing the operation of the conventional gate driving apparatus. When a regenerative current is passed in the direction A in FIG. 7, the first drive signal C1 and the second drive signal C2 are set to L, and the first power MOS transistor 1 and the second power MOS transistor 2 are turned off. At this time, the potential of the connection point 8 rises to the power supply VCC (11) + the conduction voltage VD1 of the diode D1 (time T1).

  Next, when the second drive signal C2 is changed from L to H (time T2), and the second power MOS transistor 2 is turned off from the cutoff state by the second gate drive circuit 6 (time T3), the second power MOS transistor 2 is eventually turned on. The drain voltage, that is, the voltage at the connection point 8 starts to drop toward the ground GND (14), and at the same time, a drive current flows in the direction B in FIG.

  At that time, the gate-source potential of the first power MOS transistor 1 rises due to the drain-gate parasitic capacitance 15, the gate-source resistance 10 and the parasitic capacitance 16 (time T 4), and the first power MOS transistor 1 When the gate-source voltage of the first power MOS transistor becomes equal to or higher than the threshold value Vt, the first power MOS transistor 1 becomes conductive. At this time, the second power MOS transistor 2 is also conductive, so that a through current (hereinafter referred to as dv / dt through) is generated. However, there has been a problem that malfunction occurs due to noise caused by destruction of the power MOS transistor or through current.

As a gate drive device for preventing this problem, a gate drive device 17 shown in FIG. 9 (see, for example, Patent Document 1) is known.
The above gate drive device will be described below with reference to the drawings.

  FIG. 9 is a circuit block diagram showing another configuration example of the conventional gate driving device. From the circuit of the above-described conventional example, as shown in the gate driving device 17 of FIG. 9, the first power driving circuit 18 is connected to the cutoff circuit 19 controlled by the second driving signal C2, and the first power is supplied. A point in which a diode D3 is connected between the gate and source of the MOS transistor 1 is added.

  Specifically, the diode D3 is connected between the gate and source of the first power MOS transistor 1, the cathode side of the diode D3 is connected to the gate 3 of the first power MOS transistor 1, and the gate and source of the first power MOS transistor 1 are connected. The breakdown voltage between sources is prevented. The cutoff circuit 19 is constituted by an Nch MOS transistor 20, the gate is connected to the second drive signal C2, and the drain and source are connected between the gate 3 of the first power MOS transistor 1 and the ground GND (14), respectively. ing.

  Although the operation of the gate driving device 17 configured as described above will be described, the conduction and blocking of the second power MOS transistor 2 and the conduction of the first power MOS transistor 1 are the same as in the above-described conventional example, and thus will be omitted.

  Regarding the cutoff of the first power MOS transistor 1, the first drive signal C1 is set to L. At this time, if the second drive signal C2 is H, the Nch MOS transistor 20 of the cutoff circuit 19 is turned on. 1 gate 3 is shorted to ground. If the first drive signal C1 is set to L and the second drive signal C2 is L at this time, the Nch MOS transistor 20 of the cutoff circuit 19 is off. The source charge is pulled out and blocked.

  In the configuration as described above, from the state in which the first power MOS transistor 1 and the second power MOS transistor 2 in which the dv / dt penetration state has occurred in the conventional example is in the cut-off state, the regenerative current flows in the direction A in FIG. A case will be described in which the second power MOS transistor 2 is switched from the cutoff state to the conductive state and the drive current flows in the direction B in FIG.

  The case where the regenerative current flows in the direction A in FIG. 9 is the same as in the conventional example described above, and the first power MOS transistor 1 and the second power MOS transistor 2 are cut off. At this time, the potential of the connection point 8 rises to the power supply VCC (11) + the conduction voltage VD1 of the diode D1.

  Next, by changing the second drive signal C2 from L to H, when the second power MOS transistor 2 is turned on from the cutoff state by the second gate drive circuit 6, the drive current starts to flow in the direction B in FIG. At this time, as the second power MOS transistor 2 becomes conductive, the voltage at the node 8 starts to drop to the ground GND (14).

At this time, in the conventional example, dv / dt penetration occurs due to the rise of the gate-source voltage of the first power MOS transistor 1, but in this configuration, when the second drive signal C2 changes from L to H, the cutoff circuit 19 The Nch MOS transistor 20 is turned on, and the gate 3 of the first power MOS transistor 1 is short-circuited to the ground GND (14), thereby discharging the gate charge of the first power MOS transistor 1 and increasing the gate-source voltage. This prevents the occurrence of dv / dt penetration.
Japanese Patent Laid-Open No. 3-11996

  However, in the conventional gate driving device 17 as described above, the second drive signal C2 is changed from L to H, the timing at which the second power MOS transistor 2 is actually turned on from the cutoff state, and the Nch MOS transistor 20 of the cutoff circuit 19 The timing relationship is not the same as the timing when the signal is turned on, but the timing relationship varies.

  For example, as shown in FIG. 10, a case will be described in which the timing at which the Nch MOS transistor 20 of the cutoff circuit 19 is turned on is earlier than the timing at which the second power MOS transistor 2 is turned on from the cutoff state. When the Nch MOS transistor 20 of the cutoff circuit 19 is switched from OFF to ON (time T5), the second power MOS transistor 2 is still in the cutoff state, so that the regenerative current continues to flow in the direction A in FIG. The power supply VCC (11) + diode D1 conduction voltage VD1 is maintained.

  At that time, since the gate of the first power MOS transistor 1 is short-circuited to the ground by the Nch MOS transistor 20 of the cutoff circuit 19, a large current flows from the connection point 8 through the diode D3 to the ground GND (14). (Current corresponding to the current capability of the Nch MOS transistor 20) flows, and this large current causes the second power MOS transistor 2 to be in a conducting state (time T6), the potential at the connection point 8 is lowered, and the conducting voltage of the diode D3 It continues to flow until reaching VD3 (time T7), and there is a problem that a large power loss is caused by this large current.

  On the other hand, as shown in FIG. 11, a case will be described in which the timing at which the Nch MOS transistor 20 of the cutoff circuit 19 is turned on is later than the timing at which the second power MOS transistor 2 is turned on from the cutoff state. When the second power MOS transistor 2 changes from the cutoff state to the conductive state (time T8), since the cutoff circuit 19 is still off, when the voltage at the node 8 drops due to the conduction of the second power MOS transistor 2, Similarly, the gate potential of the first power MOS transistor 1 rises due to the drain-gate parasitic capacitance 15, the gate-source resistance 10 and the parasitic capacitance 16 (time T9), and the first power MOS transistor 1 has a dv / Dt penetration occurs, and there is a problem that power loss is caused by the penetration current.

  The present invention solves the above-described conventional problems, and provides a gate driving device capable of suppressing power loss due to a dv / dt through current and an overcurrent that have been generated conventionally.

  In order to solve the above problems, the first invention is a gate drive for driving the gates of the first power MOS transistor and the second power MOS transistor connected in series between the power supplies in order to control the power supply to the load. In the device, a first gate drive circuit connected to the gate of the first power MOS transistor to turn on or off the first power MOS transistor based on a first drive signal, and connected to the gate of the second power MOS transistor A second gate driving circuit for conducting or blocking the second power MOS transistor based on the second driving signal, and a blocking of the first power MOS transistor by the first gate driving circuit based on the second driving signal. And a first gate drive circuit for controlling the first drive signal. Based on the first power MOS transistor, a first cutoff circuit and a second cutoff circuit, and a selector circuit for switching the selection of the first cutoff circuit and the second cutoff circuit. And a cutoff circuit that shuts off the first power MOS transistor based on the first power MOS transistor, and the cutoff control circuit is configured so that the first power MOS transistor is in a cutoff state and the second power MOS transistor is shut off based on the first drive signal. The first cutoff circuit is selected by the selector circuit based on the second drive signal during an arbitrary period before and after conducting from the cutoff, and the selector circuit is selected based on the second drive signal except during the optional period. A second cutoff circuit is selected, and the first power MOS transistor is shut off by one of the selected cutoff circuits. , Characterized by being configured to control.

  According to a second aspect of the present invention, in the first aspect of the present invention, the selection of the cutoff control circuit for the first cutoff circuit and the second cutoff circuit by the selector circuit is based on the second drive signal. It is characterized in that it is controlled according to the state of the gate potential of the transistor.

  According to a third aspect of the present invention, in the first aspect, the first power MOS based on the second drive signal is selected based on the second drive signal by selecting the cutoff control circuit for the first cutoff circuit and the second cutoff circuit by the selector circuit. Control is performed according to the state of the potential of the connection point between the transistor and the second power MOS transistor.

According to a fourth invention, in any one of the first to third inventions, the first cutoff circuit and the second cutoff circuit are configured by a current source.
According to a fifth invention, in any one of the first to fourth inventions, the discharge current of the gate charge is larger in the first cutoff circuit than in the second cutoff circuit.

  As described above, according to the present invention, when the power supply to the motor load is controlled by the conduction and interruption of the first power MOS transistor and the second power MOS transistor connected between the power supplies, the first power MOS transistor When the second power MOS transistor is switched from the cutoff to the conductive state in the cutoff state, the first power MOS transistor can be completely cut off at the same time.

  Therefore, it is possible to prevent generation of a through current when the first power MOS transistor is in a cut-off state and the second power MOS transistor is turned off to a conductive state with low power consumption. In addition, power loss due to overcurrent can be suppressed.

Hereinafter, a gate drive device showing an embodiment of the present invention will be specifically described with reference to the drawings.
(Embodiment 1)
A gate driving apparatus according to Embodiment 1 of the present invention will be described.

  FIG. 1 is a circuit block diagram showing a configuration example of the gate driving apparatus according to the first embodiment. 1, the first power MOS transistor 1 and the second power MOS transistor 2 are connected in series between the power supplies, and the gate 3 of the first power MOS transistor 1 is controlled by the first drive signal C1. The first gate drive circuit 22 is connected, and the gate 5 of the second power MOS transistor 2 is connected to the second gate drive circuit 6 controlled by the second drive signal C2. The motor driving load 7 is connected to a connection point 8 between the first power MOS transistor 1 and the second power MOS transistor 2. Here, the first drive signal C1 and the second drive signal C2 are signals that repeat a high level (hereinafter referred to as H) and a low level (hereinafter referred to as L), respectively.

  Next, the second gate drive circuit 6 is the same as the conventional example, and by setting the second drive signal C2 to L, the gate voltage of the second power MOS transistor 2 is lowered and cut off. Further, by setting the second drive signal C2 to H, the gate voltage of the second power MOS transistor 2 is raised to make it conductive. The first gate drive circuit 22 is constituted by a conduction circuit 23 for conducting the first power MOS transistor 1 and a cutoff circuit 24 for cutting off. The outputs of the conduction circuit 23 and the cutoff circuit 24 are common, and the first power MOS transistor 1 Connected to the gate 3.

  When the first drive signal C1 is H, the conduction circuit 23 and the cutoff circuit 24 operate to make the first power MOS transistor 1 conductive, and when the first drive signal C1 is L, the cutoff circuit 24 operates. Then, the first power MOS transistor 1 is shut off. The cutoff circuit 24 includes a first current source 25, a second current source 26, and a selector circuit 27. The first current source 25 and the second current source 26 are connected to the input of the selector circuit 27, and either the first current source 25 or the second current source 26 is connected to the first power MOS transistor 1 during the operation of the cutoff circuit 24. By connecting to the gate 3, the gate charge is discharged and the first power MOS transistor 1 is shut off. Here, it is assumed that the first current source 25 has a larger current for discharging the gate charge than the second current source 26.

  The switching between the first current source 25 and the second current source 26 by the selector circuit 27 is controlled by the output 29 of the cutoff control circuit 28. When the output 29 is H, the first current source 25 is selected and the output 29 is L In this case, the second current source 26 is selected. The shut-off control circuit 28 includes a timing generation circuit 30, the reference clock CLK and the second drive signal C 2 are connected to the input, and the output 29 is connected to the selector circuit 27. The timing generation circuit 30 outputs an H pulse when the second drive signal C2 switches from L to H.

  Specifically, the second drive signal C2 is switched from L to H, and the output 29 of the timing generation circuit 30 is switched from L to H after time t1, and the output 29 is set to L again after the H pulse time t2. Although not shown, the time t1 and the time t2 are determined by a counter, a shift register, or the like, and can be determined by an arbitrary number of clocks times the reference clock CLK.

  Next, in the gate drive device 21 according to the first embodiment configured as described above, the first power MOS transistor 1 and the second power that have generated power loss due to dv / dt penetration and overcurrent in the conventional example. The operation in the case where the MOS transistor 2 is in the cut-off state and the regenerative current flows in the direction A in FIG. 1 and the second power MOS transistor 2 is switched from the cut-off to the conductive state and the drive current flows in the direction B in FIG. Will be described.

  FIG. 2 is a timing chart showing the operation of the gate driving apparatus according to the first embodiment. In the case where the regenerative current flows in the direction A in FIG. 1, as in the conventional example, both the first drive signal C1 and the second drive signal C2 are set to L, and the first power MOS transistor 1 and the second power MOS transistor 2 are cut off. At this time, the potential of the connection point 8 rises to the power supply voltage VCC (11) + the conduction voltage VD1 of the diode D1. At this time, since the second drive signal C2 is L, the output 29 becomes L. Therefore, the selector circuit 27 selects the second current source 26 and puts the first power MOS transistor 1 into a cut-off state.

  Next, when the second drive signal C2 is changed from L to H (time T10), the output 29 of the timing generation circuit 30 becomes H (time T11) after time t1, so that the selector circuit 27 changes the current source to the second current source. 26 to the first current source 25. Here, when the setting of the time t1 is the time from when the second drive signal is switched from L to H until the second power MOS transistor 2 is turned off to the conductive state, the second power MOS transistor 2 is turned off to the conductive state. At the same time, the output of the cutoff circuit 24 can be switched from the second current source 26 to the first current source 25.

  Further, when the second power MOS transistor 2 becomes conductive, the source voltage of the first power MOS transistor 1, that is, the voltage at the connection point 8, starts to rapidly drop toward the ground GND (14), and at the same time in the direction B in FIG. Drive current begins to flow. Here, the time t2 is set so that the drain voltage (connection point 8) of the second power MOS transistor 2 becomes the ground GND (14) from the timing when the second power MOS transistor 2 is turned on from the cut-off state (time T12). Time until. As a result, the first power MOS transistor 1 can be shut off by the first current source 25 having a large discharge current during the period in which the voltage at the connection point 8 is rapidly decreasing.

  In the conventional example, the operation timing of the cutoff circuit that prevents the dv / dt penetration corresponding to the first current source 25 is before and after the timing at which the second power MOS transistor 2 becomes conductive from the cutoff. The power loss was caused by the overcurrent caused by the / dt penetration or the cutoff circuit.

On the other hand, according to the present embodiment, the timing at which the second power MOS transistor 2 is switched from the cutoff state to the conductive state and the timing at which the cutoff circuit 24 is switched from the second current source 26 to the first current source 25 are generated. The first power MOS transistor 1 is completely shut off by the first current source 25 having a large discharge current during the period when the voltage at the connection point 8 is sharply lowered by the circuit 30, which has occurred in the past. It is possible to prevent power loss due to dv / dt penetration and overcurrent.
(Embodiment 2)
A gate drive device according to a second embodiment of the present invention will be described.

  FIG. 3 is a circuit block diagram showing a configuration example of the gate driving apparatus according to the second embodiment. In the first embodiment, the cutoff control circuit 28 is configured by the timing generation circuit 30, and the first current source 25 and the second current source 26 are switched by the selector circuit 27 based on the output 29 from the timing generation circuit 30. However, as shown in FIG. 3, in the gate drive device 31 of the second embodiment, the cutoff control circuit 32 is configured by a comparator 33 that detects the gate voltage of the second power MOS transistor 2.

  Although a detailed configuration will be described below, the second gate drive circuit 6 and the first gate drive circuit 22 are the same as those in the first embodiment, and thus the description thereof will be omitted. Only the comparator 33 that controls the selector circuit 27 will be described. .

  In the comparator 33, the voltage V1 slightly lower than the threshold voltage of the second power MOS transistor 2 is connected to the “−” input, and the gate 5 of the second power MOS transistor 2 is connected to the “+” input. The output 34 of the comparator 33 is connected to the selector circuit 27. When the output 34 is H, the selector circuit 27 selects the first current source 25, and when the output 34 is L, the second current source 26 is selected. Here, the output 34 of the comparator 33 outputs H when the “+” input voltage is higher than the “−” input.

  Next, in the gate drive device 30 according to the second embodiment configured as described above, the first power MOS transistor 1 and the second power that have caused power loss due to dv / dt penetration and overcurrent in the conventional example. The operation when the MOS transistor 2 is in the cut-off state and the regenerative current flows in the direction A in FIG. 3 and the second power MOS transistor 2 is switched from the cut-off to the conductive state and the drive current flows in the direction B in FIG. Will be described.

  FIG. 4 is a timing chart showing the operation of the gate driving apparatus according to the second embodiment. The case where the regenerative current flows in the direction A in FIG. 3 is the same as the conventional example, and both the first drive signal C1 and the second drive signal C2 are set to L, and the first power MOS transistor 1 and the second power MOS transistor 2 are turned on. By setting the cut-off state, the potential of the connection point 8 rises to the power supply VCC (11) + the conduction voltage VD1 of the diode D1. Here, the comparator 33 outputs L because the second power MOS transistor 2 is cut off and the gate voltage is lower than the voltage V1. Therefore, since the second drive signal C2 is L and the output 34 of the comparator 33 is L, the cutoff circuit 24 puts the first power MOS transistor 1 into the cutoff state by the second current source 26.

  Next, by changing the second drive signal C2 from L to H (time T13), the gate voltage of the second power MOS transistor 2 is increased by the second gate drive circuit 6, and when the voltage V1 is reached, the output 34 of the comparator 33 is reached. Switches to H (time T14). At this time, since the output 34 of the comparator 33 becomes H, the selector circuit 27 switches the output of the cutoff circuit 24 from the second current source 26 to the first current source 25 having a large discharge current.

  After that, although the gate voltage further increases, the voltage V1 is set to a value slightly lower than the threshold voltage of the second power MOS transistor 2, so that immediately after the output 34 of the comparator 33 is switched from L to H, 2 The power MOS transistor 2 becomes conductive (time T14), and the source voltage of the first power MOS transistor 1, that is, the voltage at the connection point 8, starts to rapidly drop toward the ground GND (14), and the direction B in FIG. Drive current begins to flow.

  Here, in the conventional example, the operation timing of the shut-off circuit 19 corresponding to the first current source 25 changes before and after the timing when the second power MOS transistor 2 is turned on, and thus the dv / dt penetration. And the power loss was caused by the overcurrent by the interruption circuit.

On the other hand, according to the present embodiment, since the comparator 33 detects the timing at which the second power MOS transistor 2 is turned on from the cutoff, the cutoff circuit 24 is connected from the second current source 26 to the first current. The timing for switching to the source 25 and the timing when the second power MOS transistor 2 is turned on are not changed. Therefore, it is possible to suppress power loss due to dv / dt penetration and overcurrent, which has conventionally occurred.
(Embodiment 3)
A gate drive device according to a third embodiment of the present invention will be described.

  FIG. 5 is a circuit block diagram showing a configuration example of the gate driving apparatus according to the third embodiment. In the second embodiment, the comparator 33 of the cutoff control circuit 32 detects the gate voltage of the second power MOS transistor 2, but as shown in FIG. 5, in the gate drive device 35 of the third embodiment, the cutoff is performed. The control circuit 36 includes a comparator 37 that detects the voltage at the connection point 8.

  Although a detailed configuration will be described below, the second gate drive circuit 6 and the first gate drive circuit 22 are the same as those in the first embodiment, and thus the description thereof will be omitted. Only the comparator 37 that controls the selector circuit 27 will be described. .

  In the comparator 37, the connection point 8 is connected to the "-" input, and the voltage VCC (11) is connected to the "+" input. The output 38 of the comparator 37 is connected to the selector circuit 27. When the output 38 is H, the selector circuit 27 selects the first current source 25, and when the output 38 is L, the second current source 26 is selected. Here, as in the second embodiment, the output 38 of the comparator 37 outputs H when the “+” input voltage is higher than the “−” input.

  Next, in the gate driving device 35 according to the third embodiment configured as described above, the first power MOS transistor 1 and the second power that have caused power loss due to dv / dt penetration and overcurrent in the conventional example. The operation when the MOS transistor 2 is in the cut-off state and the regenerative current flows in the direction A in FIG. 5 and the second power MOS transistor 2 is switched from the cut-off to the conductive state and the drive current flows in the direction B in FIG. Will be described.

  FIG. 6 is a timing chart showing the operation of the gate driving apparatus according to the third embodiment. The case where the regenerative current flows in the direction A in FIG. 5 is the same as in the first embodiment, and the first drive signal C1 and the second drive signal C2 are both set to L, and the first power MOS transistor 1 and the second power MOS transistor. By setting 2 to the cut-off state, the potential of the connection point 8 rises to the power supply VCC (11) + the conduction voltage VD1 of the diode D1. Here, the comparator 37 outputs L because the voltage at the node 8 is higher than the power supply VCC (11). Therefore, since the second drive signal C2 is L and the output 38 of the comparator 37 is L, the cutoff circuit 24 puts the first power MOS transistor 1 into the cutoff state by the second current source 26.

  Next, the second drive signal C2 is changed from L to H (time T15), so that the gate voltage of the second power MOS transistor 2 is increased by the second gate drive circuit 6 and becomes conductive. When the second power MOS transistor 2 becomes conductive, the source voltage of the first power MOS transistor 1, that is, the voltage at the connection point 8 rapidly decreases toward the ground GND (14), and the voltage at the connection point 8 immediately becomes the power supply. VCC (11) is reached and the output 38 of the comparator 37 is switched from L to H. Therefore, the output of the cutoff circuit 24 is switched by the selector circuit 27 from the second current source 26 to the first current source 25 having a large discharge current.

  Here, in the conventional example, the operation timing of the shut-off circuit 19 corresponding to the first current source 25 changes before and after the timing when the second power MOS transistor 2 is turned on, and thus the dv / dt penetration. And the power loss was caused by the overcurrent by the interruption circuit.

  In contrast, according to the present embodiment, since the comparator 37 detects the timing at which the second power MOS transistor 2 is turned on from the cutoff state, the second current source 26 to the first current source by the selector circuit 27 is detected. The timing of switching to 25 and the timing when the second power MOS transistor 2 is turned on are not changed, and power loss due to the dv / dt through current and overcurrent that has occurred conventionally can be suppressed. it can.

  The gate driving device of the present invention can suppress the power loss due to the dv / dt through current and overcurrent that have been generated conventionally, and the motor driving that employs the PWM driving method to drive the gate of the power MOS transistor. Useful for devices and the like.

1 is a circuit block diagram showing a configuration example of a gate drive device according to a first embodiment of the present invention. Timing chart showing the operation of the gate driving apparatus of the first embodiment The circuit block diagram which shows one structural example of the gate drive device of Embodiment 2 of this invention Timing chart showing the operation of the gate driving apparatus of the second embodiment The circuit block diagram which shows the example of 1 structure of the gate drive device of Embodiment 3 of this invention Timing chart showing the operation of the gate driving apparatus of the third embodiment A circuit block diagram showing a configuration example of a conventional gate driving device Timing chart showing the operation of the conventional gate drive device Circuit block diagram showing another configuration example of a conventional gate driving device Timing chart showing the operation of the conventional gate drive device Timing chart showing other operations in the conventional gate driving device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st power MOS transistor 2 2nd power MOS transistor 3 Gate (of 1st power MOS transistor) 4 1st gate drive circuit 5 Gate (of 2nd power MOS transistor) 6 2nd gate drive circuit 7 Motor drive load 8 ( Connection point between the first power MOS transistor, the second power MOS transistor and the motor drive load 9 Pch MOS transistor 10 Resistance 11 Power supply VCC
12 Power supply VPUMP
13 Gate drive device 14 Ground GND
15 Parasitic capacitance between drain and gate (of the first power MOS transistor) 16 Parasitic capacitance between gate and source (of the first power MOS transistor) 17 Gate drive device 18 First gate drive circuit 19 Cutoff circuit 20 Nch MOS transistor 21 Gate drive Device 22 First gate drive circuit 23 Conduction circuit 24 Cutoff circuit 25 First current source 26 Second current source 27 Selector circuit 28 Cutoff control circuit 29 Cutoff control circuit output 30 Timing generation circuit 31 Gate drive device 32 Cutoff control circuit 33 Comparator 34 Comparator output 35 Gate drive device 36 Shutdown control circuit 37 Comparator 38 Comparator output C1 1st drive signal C2 2nd drive signal CLK Reference clock D1-D3 Diode

Claims (5)

In a gate drive device for driving the gates of a first power MOS transistor and a second power MOS transistor connected in series between power supplies in order to control power supply to a load,
A first gate driving circuit connected to the gate of the first power MOS transistor to turn on or off the first power MOS transistor based on a first driving signal;
A second gate driving circuit connected to the gate of the second power MOS transistor to turn on or off the second power MOS transistor based on a second driving signal;
A cutoff control circuit for controlling cutoff of the first power MOS transistor by the first gate driving circuit based on the second driving signal;
The first gate driving circuit includes:
A conduction circuit for conducting the first power MOS transistor based on the first drive signal;
A cut-off circuit comprising a first cut-off circuit and a second cut-off circuit and a selector circuit for switching selection of the first cut-off circuit and the second cut-off circuit, and cuts off the first power MOS transistor based on the first drive signal; Have
The cutoff control circuit;
Based on the first drive signal, the first power MOS transistor is turned off and the first power MOS transistor is turned off and turned on for an arbitrary period before and after the second power MOS transistor is turned on by the selector circuit based on the second drive signal. Select the cutoff circuit,
Except for the arbitrary period, the selector circuit selects the second cutoff circuit based on the second drive signal,
The first power MOS transistor is shut off by the selected one shut-off circuit,
A gate driving device characterized by being configured to control. The gate driving apparatus according to claim 1, wherein
The cutoff control circuit;
Selection for the first cutoff circuit and the second cutoff circuit by the selector circuit,
According to the state of the gate potential of the second power MOS transistor based on the second drive signal,
A gate driving device characterized by being configured to control. The gate driving apparatus according to claim 1, wherein
The cutoff control circuit;
Selection for the first cutoff circuit and the second cutoff circuit by the selector circuit,
According to the state of the connection point potential between the first power MOS transistor and the second power MOS transistor based on the second drive signal,
A gate driving device characterized by being configured to control. In the gate drive device according to any one of claims 1 to 3,
A gate driving device characterized in that the first cutoff circuit and the second cutoff circuit are constituted by a current source. In the gate drive device according to any one of claims 1 to 4,
A gate driving device characterized in that a discharge current of a gate charge is larger in the first cutoff circuit than in the second cutoff circuit.

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