JP2007208190A - Semiconductor device - Google Patents

Abstract

A semiconductor device including an MIM element and a fuse formed on a multilayer wiring portion and having a desired performance can be easily manufactured with a high yield.
A semiconductor substrate, circuit elements formed on the semiconductor substrate, a multilayer wiring portion formed on the semiconductor substrate and covering the circuit element, and an outermost interlayer formed on the multilayer wiring portion. In manufacturing the semiconductor device 100 including the insulating film 60, the MIM element 70 formed in the outermost interlayer insulating film, and the fuse 75 formed in the outermost interlayer insulating film, the semiconductor device 100 is provided in the outermost interlayer insulating film. A lower electrode 62 which is embedded in the recessed portion and forms a common surface with the upper surface of the outermost interlayer insulating film, an electric insulating film 64 formed on the lower electrode, and an upper electrode 66 formed on the electric insulating film, The MIM element is constituted by the above, and a fuse is embedded in the outermost interlayer insulating film so as to form a common surface with the upper surface of the outermost interlayer insulating film by being embedded in the recess provided in the outermost interlayer insulating film To do.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device including an outermost interlayer insulating film on a multilayer wiring portion, and an MIM element (Metal Insulator Metal) formed on the outermost interlayer insulating film.

  Nowadays, in order to reduce the size and cost of electronic devices, various integrated circuits are mixedly mounted on one semiconductor chip, and one semiconductor device is configured accordingly. These circuit elements are also being miniaturized and highly integrated. In addition, diversification of circuit element arrangement is also progressing. For example, a fuse for electrically replacing a defective memory cell with a good memory cell on a redundant circuit is formed in the uppermost interlayer insulating film in the multilayer wiring portion. In addition, when a predetermined performance according to consumer needs is handled as an option, an MIM element necessary for realizing the predetermined performance is formed on a multilayer wiring portion.

  For example, when a fuse is formed in the uppermost interlayer insulating film in the multilayer wiring portion and a capacitor element as an MIM element is formed on the multilayer wiring portion, first, the uppermost interlayer insulating film in the multilayer wiring portion is formed. After forming a fuse as a part of wiring in the interlayer insulating film, an outermost interlayer insulating film is formed on the multilayer wiring portion by silicon oxide or the like. The outermost interlayer insulating film provides a field for forming the MIM element.

  Next, a concave portion having a predetermined shape is formed in the outermost interlayer insulating film, and further, a via hole that connects a predetermined wiring formed in the uppermost interlayer insulating film in the multilayer wiring portion and a predetermined portion of the concave portion is formed. . A barrier metal layer is formed on the surface of each of these recesses and via holes using, for example, tantalum or tantalum nitride, and then the recesses and via holes are filled with an electrode material such as tungsten or tungsten-aluminum alloy, and are formed on the outermost interlayer insulating film The excess electrode material and barrier metal deposited are removed by chemical mechanical polishing (CMP). By performing this CMP, the lower electrode of the capacitive element is formed in the recess, and the contact plug is formed in the via hole.

  At this time, if the surface flatness of the outermost interlayer insulating film is low, the amount of polishing when the excess electrode material and the excess barrier metal are removed by CMP increases, resulting in the thinning of the lower electrode of the capacitive element. Since disappearance is caused, CMP is performed on the outermost interlayer insulating film before the formation of the lower electrode, and the surface thereof is flattened.

  Next, a capacitive insulating film is formed from, for example, silicon nitride so as to cover the lower electrode, and an upper electrode of the capacitive element is formed thereon from, for example, titanium nitride. By forming up to the upper electrode, a capacitive element can be obtained.

  Thereafter, a pad is formed of, for example, aluminum on the outermost interlayer insulating film so as to cover the upper electrode of the capacitive element, and silicon nitride or the like is formed so as to cover the pad and the exposed surface of the outermost interlayer insulating film. A passivation film is formed. At this time, the region located on the pad and the region located on the fuse in the film that is the basis of the passivation film are removed by etching, for example. In addition, the region of the outermost interlayer insulating film located on the fuse is thinned by, for example, etching to have a thickness capable of chemically protecting the fuse (protecting from oxidation, corrosion, etc.). When necessary, a protective part having a thickness capable of easily blowing the fuse by laser blow is formed.

  When the MIM element is formed on the multilayer wiring portion, CMP is performed on the outermost interlayer insulating film prior to the formation of the lower electrode as described above, and the upper surface thereof is flattened. At this time, since the upper surface of the multilayer wiring part which is the base is not necessarily flat, the film thickness of the outermost interlayer insulating film with the flat upper surface varies. The formation of the protective portion on the fuse is performed after the thickness of the outermost interlayer insulating film varies. For this reason, in the conventional semiconductor device, it is difficult to control the etching conditions when forming the protective portion on the fuse, and as a result, it is difficult to form a memory element having desired performance or reliability.

  The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device that includes an MIM element and a fuse formed on a multilayer wiring portion and can easily manufacture a desired performance with a high yield. And

  A semiconductor device of the present invention that achieves the above object is formed on a semiconductor substrate, a circuit element formed on the semiconductor substrate, a multilayer wiring portion formed on the semiconductor substrate and covering the circuit element, and a multilayer wiring portion. An outermost interlayer insulating film, an MIM element formed in the outermost interlayer insulating film, and a fuse formed in the outermost interlayer insulating film. The MIM element is a recess provided in the outermost interlayer insulating film. A lower electrode that forms a common surface with the upper surface of the outermost interlayer insulating film, an electric insulating film formed on the lower electrode, and an upper electrode formed on the electric insulating film. A surface common to the upper surface of the outermost interlayer insulating film is formed by being embedded in a recess provided in the outermost interlayer insulating film.

  In the semiconductor device of the present invention, since the lower electrode of the MIM element and the fuse are embedded in the outermost interlayer insulating film so as to form a surface common to the upper surface of the outermost interlayer insulating film, the outermost interlayer insulating film Regardless of whether or not CMP is performed, a film having a substantially constant thickness can be easily formed on the outermost interlayer insulating film. As a result, it becomes easy to form a protective part having a desired thickness on the fuse. Therefore, according to the present invention, it becomes easy to obtain a semiconductor device having desired performance including the MIM element and the fuse formed on the multilayer wiring portion at a high yield.

  Embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the drawings. The present invention is not limited to the embodiments described below.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view schematically showing an example of the semiconductor device of the present invention. A semiconductor device 100 shown in the figure includes a semiconductor substrate 10, circuit elements 20 and 30 formed on the semiconductor substrate 10, a multilayer wiring portion 50 formed on the semiconductor substrate 10 and covering the circuit elements 20 and 30, and a multilayer The outermost interlayer insulating film 60 formed on the wiring portion 50, the MIM element 70 formed on the outermost interlayer insulating film 60, and a plurality of fuses 75 (see FIG. 1) formed on the outermost interlayer insulating film 60. Only one fuse 75 appears).

  The semiconductor device 100 has a memory element and a redundant circuit for the memory element, and a part of the plurality of fuses 75 electrically replaces a defective memory cell with a good memory cell on the redundant circuit. For example, it is melted by laser blow. Further, the MIM element 70 is provided in the semiconductor device 100 in order to realize predetermined performance treated as an option.

The semiconductor substrate 10 may be a substrate made of an elemental semiconductor such as silicon, or may be a substrate made of a compound semiconductor such as gallium arsenide. Furthermore, an SOI (Silicon On Insulator) substrate may be used. A predetermined element region (well) corresponding to the type of circuit element to be formed on the semiconductor substrate 10 and an element isolation region having a predetermined shape are formed at predetermined positions of the semiconductor substrate 10. The illustrated semiconductor substrate 10 has an N-type well 3 and a P-type well 5 formed at predetermined locations on a P ⁻ -type silicon substrate 1, and further element isolation regions so as to partition the element regions 3 and 5 in plan view. 7 is formed.

  Which element is formed as the circuit element is appropriately selected according to the function required for the semiconductor device 100. The circuit elements 20 and 30 shown in FIG. 1 are both field effect transistors (hereinafter referred to as “field effect transistor 20” and “field effect transistor 30”). The field effect transistor 20 has a source region 12 and a drain region 14 formed in the N-type well 3, and a gate electrode 18 disposed on the semiconductor substrate 10 via a gate insulating film 16. The field effect transistor 30 includes a source region 22 and a drain region 24 formed in the P-type well 5, and a gate electrode 28 disposed on the semiconductor substrate 10 via a gate insulating film 26.

  The multilayer wiring unit 50 includes a plurality of interlayer insulating films, contact plugs formed in each of these interlayer insulating films, and a number of wirings that form an integrated circuit by electrically connecting the contact plugs in a predetermined pattern. It has. In the first interlayer insulating film 35 which is the lowest interlayer insulating film, a first layer contact plug and a first layer wiring (not shown in FIG. 1) connected to the field effect transistors 20 and 30 are formed. In the (n−1) th interlayer insulating film 40, an (n−1) th layer contact plug and an (n−1) th layer wiring are formed. An n-th layer contact plug and an n-th layer wiring are formed in the n-th interlayer insulating film 45 which is the uppermost interlayer insulating film. Further, a liner film formed of, for example, silicon nitride or silicon carbonitride is provided on each interlayer insulating film. The liner film prevents, for example, copper wiring from being oxidized or corroded, or copper atoms from diffusing when a copper wiring is formed in the underlying interlayer insulating film. Note that “n” represents an integer of 3 or more, but it is also possible to configure a multilayer wiring portion by setting “n” to 2.

In FIG. 1, among the contact plugs and wirings formed in each interlayer insulating film, four first layer contact plugs 32a to 32d, one (n-1) th layer contact plug 37, and three first layers are provided. (N-1) layer wirings 39a to 39c, one n-th layer contact plug 42, and three n-th layer wirings 44a to 44c appear. Of the liner films formed on each interlayer insulating film, the (n-1) th liner film L _n-1 formed on the (n-1) th interlayer insulating film 40 and the nth interlayer insulating film An n-th liner film L _n formed on the film 45 appears.

  Each contact plug can be formed of a conductive material such as tungsten, a tungsten-aluminum alloy, or copper. Similarly, each wiring can be formed of a conductive material such as aluminum or copper. Usually, a barrier metal layer made of a predetermined inorganic material is provided between the contact plug and the interlayer insulating film, and between the contact plug and the wiring connected to the contact plug, depending on the material of the contact plug. For example, when a contact plug is formed of aluminum, a barrier metal layer made of titanium nitride or the like is provided, and when a contact plug is formed of tungsten or copper, it is made of titanium nitride, tantalum, tantalum nitride, or the like. A barrier metal layer is provided. The same applies to each wiring provided in the interlayer insulating film. However, the barrier metal layer can be omitted depending on the material of the interlayer insulating film.

  Each of the wirings 39a to 39c and 44a to 44c shown in FIG. 1 is a copper embedded wiring formed by the damascene method, and the contact plugs 32a to 32d, 37, and 42 described above are also made of copper formed by the damascene method. However, the illustration of the barrier metal layer is omitted.

  The outermost interlayer insulating film 60 covering the multilayer wiring part 50 is formed of, for example, silicon oxide or the like, and provides a place for forming the MIM element 70. The outermost interlayer insulating film 60 is provided with a lower electrode 62 of the MIM element 70 and a fuse 75. The illustrated MIM element 70 is a capacitive element including a lower electrode 62, an electrical insulating film (capacitive insulating film) 64, and an upper electrode 66.

  The lower electrode 62 is embedded in a recess provided in the outermost interlayer insulating film 60 so as to form a common surface with the upper surface of the outermost interlayer insulating film 60. As a material of the lower electrode 62, for example, tungsten, tungsten-aluminum alloy or the like is used. The lower electrode 62 is connected to a predetermined wiring 44b formed in the nth interlayer insulating film 45 through a contact plug 61. Is done. Between each of the lower electrode 62 and the contact plug 61 and the outermost interlayer insulating film 60, between the contact plug 61 and the nth layer wiring 44b, between a contact plug 86 and an outermost interlayer insulating film 60 described later, A barrier metal layer (not shown) is interposed between the contact plug 86 and the n-th layer wiring 44c.

  An electric insulating film (capacitive insulating film) 64 constituting the MIM element is formed on the outermost interlayer insulating film 60 by silicon nitride or the like and covers the lower electrode 62, and the upper electrode 66 is made of, for example, titanium nitride or the like. Is formed on the electric insulating film 64.

  The fuse 75 is formed in the outermost interlayer insulating film 60 with the same material as the lower electrode 62 described above, and is embedded in a recess provided in the outermost interlayer insulating film 60 in the same manner as the lower electrode 62. A common surface is formed with the upper surface. A first protective film 77 formed on the outermost interlayer insulating film 60 with the same material as the above-described electric insulating film 64 covers the fuse 75 to protect the fuse 75 from oxidation, corrosion, and the like. The film thickness of the first protective film 77 is the same as the film thickness of the electrical insulating film 64 described above, and the film thickness is selected so that the fuse 75 can be easily blown by laser blow, for example, when necessary. Yes.

  A second protective film 79 is formed on the first protective film 77 and partially covers the first protective film 77. The second protective film 79 is formed of the same material as the upper electrode 66 described above, and the film thickness of the second protective film 79 is the same as the film thickness of the upper electrode 66. Therefore, when forming openings on the MIM element 70 and the fuse 75 in forming a passivation film to be described later, the depth of the opening on the MIM element 70 and the depth of the opening on the fuse 75 are determined. Are the same.

  In the semiconductor device 100 having the MIM element 70 and the fuse 75 described above, the upper electrode 66 of the MIM element 70 is covered with, for example, an aluminum pad 82, and the upper surface of the pad 82 is a barrier metal made of, for example, titanium nitride. Layer 84 is formed. Further, in FIG. 1, a contact plug 86 for connecting the n-th layer wiring 44c to an external circuit, and one end of the contact plug 86 are formed on the outermost interlayer insulating film 60 by using, for example, aluminum. A pad 88 is also shown, and a barrier metal layer 90 made of, for example, titanium nitride is also formed on the upper surface of the pad 88.

Further, in the semiconductor device 100, a passivation film 92 made of, for example, silicon nitride or silicon oxynitride is formed so as to cover the upper surface of the outermost interlayer insulating film 60. However, openings OP _{1 to} OP ₃ are formed in the regions of the passivation film 92 located on the pads 82 and 88 and the region located on the first protective film 77. The opening OP ₁ formed on the pad 82 reaches the upper surface of the pad 82, and the opening OP ₂ formed on the pad 88 reaches the upper surface of the pad 88. The opening OP ₃ formed on the first protective film 77 reaches the upper surface of the first protective film 77. The second protective layer 79 is located around the opening OP _3.

From the viewpoint of facilitating to leave first protective film 77 of the desired thickness to the fuse 75 on the formation of substantially the same in to the opening OP ₃ the depth of each opening OP ₁ ~OP ₃ is It is preferable that the barrier metal layers 84 and 90 and the second protective film 79 are made of the same material and have the same film thickness.

In the semiconductor device 100 having such a configuration, a film having a substantially constant film thickness on the outermost interlayer insulating film 60, that is, a film having a film thickness, regardless of whether or not the outermost interlayer insulating film 60 is subjected to CMP. It is possible to easily form a film having only variations in which variations occur during film formation. For this reason, when forming the inorganic film which becomes the basis of the passivation film 92, the film thickness of the inorganic film above the pads 82 and 88 and the film thickness of the inorganic film above the fuse 75 are substantially equal. It will be easy to make it the same. As a result, it is easy to leave the first protective film 77 having a desired thickness on the fuse 75 as a protective portion even if the formation conditions of the openings OP _{1 to} OP ₃ are constant.

Therefore, in the semiconductor device 100, it is easy to form the MIM element 70 and the fuse 75 on the multilayer wiring portion 50, and the yield is easily increased. Once a semiconductor device serving as a base of the semiconductor device 100, that is, a semiconductor device formed up to the multilayer wiring portion 50 on the semiconductor substrate 10 (hereinafter referred to as a “base semiconductor device”) is once developed, It becomes easy to obtain the semiconductor device 100 to which optional functions meeting the needs of consumers are appropriately added at a high yield. If the barrier metal layers 84 and 90 and the second protective film 79 are formed of the same material and have the same film thickness, a desired film thickness is formed on the fuse 75 when the opening OP ₃ is formed. Since it becomes easier to leave the first protective film 77, it becomes easier to obtain the desired semiconductor device 100.

Note that the first protective film 77 and the second protective film 79 are not essential constituent members, and may be omitted as necessary. When the first protective film 77 and the second protective film 79 are omitted, a predetermined region located on the fuse 75 in the passivation film 92 is thinned when the opening OP ₃ is formed, and remains as a protective portion. Further, the passivation film 92 is not an essential constituent member, and may be omitted as necessary. When the passivation film 92 is omitted, a protective part having a desired film thickness is formed on the fuse 75 with an organic material or an inorganic material.

  The semiconductor device 100 having the above-described technical effect performs, for example, an outermost interlayer insulating film forming process, a fuse forming process, an upper electrode forming process, a pad forming process, and a passivation film forming process described below in this order. Can be obtained by: Hereinafter, these steps will be described in detail with reference to the reference numerals used in FIG.

(Outermost interlayer insulation film formation process)
In the outermost interlayer insulating film forming step, after obtaining the base semiconductor device formed up to the multilayer wiring portion on the semiconductor substrate, the outermost interlayer insulating film is formed on the multilayer wiring portion in the base semiconductor device. The base semiconductor device can be manufactured by a conventional method.

  The outermost interlayer insulating film 60 (see FIG. 1) is formed by forming an insulating film having a predetermined film thickness as a base, for example, a silicon oxide film by, for example, chemical vapor deposition (CVD). Can be obtained by patterning into a predetermined shape. The patterning of the insulating film includes, for example, a first sub-process for forming a recess for forming the lower electrode 62 (see FIG. 1) for the MIM element and a recess for forming the fuse 75 (see FIG. 1), respectively. The process is divided into two steps including a second sub-step of forming a via hole for forming a contact plug. In these first sub-step and second sub-step, for example, the insulating film is patterned by etching using an etching mask having a predetermined shape.

FIG. 2A is a cross-sectional view schematically showing an example of a recess formed in the first sub-process in the insulating film that is the base of the outermost interlayer insulating film. As shown in the figure, in the first sub-process, a first recess C ₁ is formed at a position where the lower electrode 62 (see FIG. 1) is to be formed in the insulating film 60A that is the source of the outermost interlayer insulating film, and the fuse 75 A second recessed portion C ₂ is formed at a planned formation location (see FIG. 1). Among the components shown in FIG. 2A, the components already described with reference to FIG. 1 are denoted by the same reference symbols as those used in FIG. 1 and the description thereof is omitted. The same applies to FIGS. 2-2 and 3 to 6 described later.

FIG. 2B is a cross-sectional view schematically showing an example of a via hole formed in the second sub-process in the insulating film that is the source of the outermost interlayer insulating film. As shown in the figure, in the second sub-process, a predetermined n-th layer wiring 44b penetrates through the insulating film 60A that is the source of the outermost interlayer insulating film and the liner film L (see FIG. 2-1) therebelow. , 44c, via holes VH ₁ and VH ₂ are formed. The above inorganic film 60A by forming to these via holes VH _1, VH _2, the n-th liner film L _n obtained with the outermost insulating film 60 is obtained.

(Fuse formation process)
In the fuse forming step, a contact plug is formed in each via hole formed in the outermost interlayer insulating film, and a lower electrode and a fuse for the MIM element are formed. These contact plugs, lower electrodes, and fuses are formed by, for example, tungsten, tungsten-aluminum alloy by CVD in each recess and each via hole provided in the outermost interlayer insulating film formed in the outermost interlayer insulating film forming step. After depositing a conductive material such as the conductive material, the conductive material deposited on the outermost interlayer insulating film and the conductive material overflowing from each recess and via hole are removed by CMP.

FIG. 3 is a sectional view schematically showing an example of each of the contact plug, the lower electrode for the MIM element, and the fuse formed in the outermost interlayer insulating film in the fuse formation step. As shown in the figure, the lower electrode 62 and the fuse 75 for the MIM element are embedded in the recesses C ₁ and C ₂ (see FIGS. 2-1 and 2-2) provided in the outermost interlayer insulating film 60. Thus, a surface common to the upper surface of the outermost interlayer insulating film 60 is formed. The contact plug 86 also forms a common surface with the upper surface of the outermost interlayer insulating film 60. It is provided as follows. A contact plug 61 is connected to the lower surface of the lower electrode 62, and one end of the contact plug 61 is connected to the n-th layer wiring 44b. One end of the contact plug 86 is connected to the n-th layer wiring 44c.

(Upper electrode formation process)
In the upper electrode forming step, first, an insulating film that is a source of each of the MIM element electric insulating film and the fuse first protective film is formed on the outermost interlayer insulating film by using, for example, silicon nitride, and then the MIM is formed thereon. For example, titanium nitride is used to form a conductive film as a base for the upper electrode for the element and the second protective film for the fuse. These insulating film and conductive film can be formed by, for example, a CVD method. Thereafter, the insulating film and the conductive film are patterned to form an electrical insulating film for the MIM element, an upper electrode, and a first protective film for the fuse. Further, a third protective film serving as a source of the second protective film for the fuse is formed. The patterning of each of the insulating film and the conductive film is performed by etching using an etching mask having a predetermined shape.

  FIG. 4 is a cross-sectional view schematically showing an example of each of the electrical insulating film and upper electrode for the MIM element formed in the upper electrode forming step, and the first protective film and the third protective film for the fuse. As shown in the figure, an electrical insulating film 64 for the MIM element is formed on the outermost interlayer insulating film 60 to cover the lower electrode 62, and an upper electrode 66 for the MIM element is disposed thereon. The first protective film 77 for the fuse 75 is formed on the outermost interlayer insulating film 60 to cover the fuse 75, and the third protective film 79A is disposed thereon. By performing the process up to the upper electrode formation step, the MIM element 70 is formed on the multilayer wiring portion 50 (see FIG. 1).

(Pad formation process)
In the pad forming step, a pad made of a conductive material such as aluminum is formed at a predetermined position on the outermost interlayer insulating film, and a barrier metal layer is further formed on each pad. For example, pads are formed so as to cover the upper electrode 66 of the MIM element 70 shown in FIG. 4, and pads are formed so as to cover the upper surface of the contact plug 86 shown in FIG. A barrier metal layer is formed.

  The pad is formed by, for example, forming a conductive layer that is a source of the pad on the outermost interlayer insulating film by physical vapor deposition (PVD) or CVD and then patterning the conductive layer. The In addition, the barrier metal layer is formed by patterning the film that is the base metal film by the PVD method or the CVD method. When a pad is formed by patterning the conductive layer, a pad and a barrier metal layer on the pad are formed by laminating a film that forms a barrier metal layer on the conductive layer and then patterning the film into a predetermined shape. It can be formed by patterning once. The barrier metal layer is formed of the same material as each of the upper electrode of the MIM element and the third protective film for the fuse element, and the thickness of the barrier metal layer is the same as that of the upper electrode of the MIM element and the fuse element for the fuse element. It is preferable that the thickness of each of the three protective films is the same.

  FIG. 5 is a cross-sectional view schematically showing an example of each of the pad and the barrier metal layer formed in the pad forming process. As shown in the figure, a pad 82 is formed so as to cover the upper electrode 66 of the MIM element 70, and a barrier metal layer 84A is formed thereon. A pad 88 is formed so as to cover the upper surface of the contact plug 86, and a barrier metal layer 90A is formed thereon.

(Passivation film formation process)
In the passivation film forming step, first, silicon nitride, silicon oxynitride, or the like is deposited on the outermost interlayer insulating film by the PVD method or the CVD method to form an inorganic film that is the basis of the passivation film. FIG. 6 is a cross-sectional view schematically showing an example of an inorganic film formed in the passivation film forming step. The inorganic film 92A shown in the figure is formed on the outermost interlayer insulating film 60 to cover the exposed surface of the outermost interlayer insulating film 60, and for the pads 82 and 88, the barrier metal layers 84 and 90A, and the fuse 75. The third protective film 79A is covered.

  Thereafter, a predetermined region located on the pads 82 and 88 and a predetermined region located on the third protective film 79A in the inorganic film 92A are removed, for example, by etching. At this time, the barrier metal layer 84A formed on the pad 82, the third protective film 79A for the fuse 75, and the barrier metal layer 90A formed on the pad 88 are also locally removed.

Thus, on the pad 82 opening OP ₁ to reach the top surface of the pad 82 (see FIG. 1) is formed, the openings OP ₂ on the first protective film 77 to reach the upper surface of the first protective film 77 1 (see FIG. 1) is formed, and an opening OP ₃ (see FIG. 1) reaching the upper surface of the pad 88 is formed on the pad 88 to obtain the passivation film 92 shown in FIG. The barrier metal layer 84, the second protective film 79, and the barrier metal layer 90 shown in FIG. That is, the semiconductor device 100 shown in FIG.

Note that, in the outermost interlayer insulating film forming step, CMP may be applied to the insulating film that is the source of the outermost interlayer insulating film as necessary to planarize the upper surface of the insulating film. The planarization by CMP is performed by, for example, a recess C ₁ (see FIG. 2-1) for forming a lower electrode for an MIM element in the insulating film and a recess C ₂ (see FIG. 2-1) for forming a fuse. ) Before each is formed. In the manufacturing method described above, the upper electrode 66 for the MIM element and the third protective film 79A (see FIG. 4) for the fuse 75 are formed in the upper electrode formation step. In addition, the barrier metal layers 84A and 90A can be formed on the pads 82 and 88, and the third protective film 79A for the fuse 75 can be formed. The material and film thickness of the third protective film 79A thus formed are the same as the material or film thickness of the barrier metal layers 84A and 90A.

Embodiment 2. FIG.
In the semiconductor device of the present invention, the reinforcing portion can be formed on the uppermost interlayer insulating film in the multilayer wiring portion so as to overlap the fuse in plan view. By providing this reinforcing part, even if the interlayer insulating film in the multilayer wiring part is formed of a material with low mechanical strength, the multilayer wiring part is locally deformed when the fuse is blown, and the wiring and the contact plug are damaged. It becomes easy to suppress it.

  FIG. 7 is a cross-sectional view schematically showing an example of a semiconductor device having the above-described reinforcing portion. In the semiconductor device 200 shown in the figure, a reinforcing portion 144 is formed on the n-th interlayer insulating film 45 that is the uppermost interlayer insulating film in the multilayer wiring portion 50 so as to overlap the fuse 75 in plan view. The semiconductor device 100 has the same structure as that of the semiconductor device 100 shown in FIG. Among the constituent elements shown in FIG. 7, the same constituent elements as those shown in FIG. 1 are denoted by the same reference numerals as those used in FIG.

  The thickness of the reinforcing portion 144 is such that the interlayer insulating film constituting the multilayer wiring portion 50 is locally formed even when the interlayer insulating film is formed of a material having low mechanical strength such as a low dielectric constant dielectric. In particular, local deformation of the multilayer wiring portion 50 when the fuse 75 is blown can be suppressed, and damage to the wiring and contact plug formed in the multilayer wiring portion 50 can be prevented. Is selected as follows. The reinforcing portion 144 can be formed of a material different from the material of the n-th layer wirings 44a to 44c. However, from the viewpoint of suppressing an increase in man-hours, these wirings are formed when the n-th layer wirings 44a to 44c are formed. It is preferable to form together by the same material as 44a-44c. When the reinforcing portion 144 is formed of the same material as that of the n-th layer wirings 44a to 44c, the reinforcing portion 144 may be a wiring that constitutes the integrated circuit or is electrically isolated from the integrated circuit. May be.

  Although the semiconductor device of the present invention has been specifically described with reference to two embodiments, the present invention is not limited to the above-described embodiment, and various MIM elements and fuses are formed on the multilayer wiring portion. And can be applied to semiconductor devices having various configurations. Various modifications, modifications, combinations, and the like can be made according to functions required for the semiconductor device and uses of the semiconductor device.

It is sectional drawing which shows roughly an example of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the recessed part formed at the 1st sub process in the outermost interlayer insulation film formation process performed when manufacturing the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the via hole formed at the 2nd sub process in the outermost interlayer insulation film formation process performed when manufacturing the semiconductor device of this invention. It is sectional drawing which shows roughly an example of each of the contact plug formed in the outermost interlayer insulation film in the fuse formation process performed when manufacturing the semiconductor device of this invention, the lower electrode for MIM elements, and a fuse. An example of each of the electrical insulating film, the upper electrode for the MIM element, the first protective film for the fuse, and the third protective film for the fuse formed in the upper electrode forming step performed when manufacturing the semiconductor device of the present invention FIG. It is sectional drawing which shows roughly an example of each of the pad formed in the pad formation process performed when manufacturing the semiconductor device of this invention, and a barrier metal layer. It is sectional drawing which shows roughly an example of the inorganic film | membrane formed in the passivation film formation process performed when manufacturing the semiconductor device of this invention, and becomes the origin of a passivation film. It is sectional drawing which shows schematically the other example of the semiconductor device of this invention.

Explanation of symbols

10 Semiconductor substrate 20, 30 Circuit element (field effect transistor)
35 first interlayer insulating film 40th (n-1) interlayer insulating film 45 nth interlayer insulating film 50 multilayer wiring part 60 outermost interlayer insulating film 62 lower electrode 64 electric insulating film 66 upper electrode 70 MIM element 75 fuse 77 first Protective film 79 Second protective film 82,88 Pad 84,90 Barrier metal layer 100,200 Semiconductor device 144 Reinforcing part

Claims (4)

A semiconductor substrate; a circuit element formed on the semiconductor substrate; a multilayer wiring portion formed on the semiconductor substrate and covering the circuit element; an outermost interlayer insulating film formed on the multilayer wiring portion; An MIM element formed in the outermost interlayer insulating film, and a fuse formed in the outermost interlayer insulating film,
The MIM element includes a lower electrode that is embedded in a recess provided in the outermost interlayer insulating film and forms a common surface with the upper surface of the outermost interlayer insulating film, and an electric insulating film formed on the lower electrode And an upper electrode formed on the electrical insulating film,
The fuse is embedded in a recess provided in the outermost interlayer insulating film to form a common surface with the upper surface of the outermost interlayer insulating film;
A semiconductor device.   A first protective film formed on the fuse and covering the fuse, wherein the material of the first protective film is the same as the material of the electrical insulating film, and the film thickness of the first protective film is The semiconductor device according to claim 1, wherein the semiconductor device has the same thickness as the electrical insulating film. A pad covering the upper electrode;
A barrier metal layer formed on the pad;
A second protective film formed on the first protective film and partially covering the first protective film, wherein the material of the second protective film is the same as the material of the barrier metal layer, and The semiconductor device according to claim 2, wherein the thickness of the second protective film is the same as the thickness of the barrier metal layer.   A reinforcing portion that is formed on the uppermost interlayer insulating film in the multilayer wiring portion and suppresses local deformation of the multilayer wiring portion is further provided, and the reinforcing portion is disposed at a position overlapping the fuse in plan view. The semiconductor device according to claim 1, wherein the semiconductor device is formed.

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