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JP2007208159A - Semiconductor device - Google Patents

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Publication number
JP2007208159A
JP2007208159A JP2006027849A JP2006027849A JP2007208159A JP 2007208159 A JP2007208159 A JP 2007208159A JP 2006027849 A JP2006027849 A JP 2006027849A JP 2006027849 A JP2006027849 A JP 2006027849A JP 2007208159 A JP2007208159 A JP 2007208159A
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interposer
semiconductor device
semiconductor
semiconductor element
lead frame
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Isamu Yoshida
勇 吉田
Shosaku Ishihara
昌作 石原
Shinichi Fujiwara
伸一 藤原
Shiro Yamashita
志郎 山下
Ukyo Ikeda
宇亨 池田
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Hitachi Ltd
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Hitachi Ltd
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    • H10W72/884
    • H10W90/724
    • H10W90/732

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Abstract

【課題】リードフレームとインターポーザを使用した高放熱半導体装置とリードフレームの両面に半導体素子を搭載したマルチチップ型半導体装置の両方の機能を兼ね備えた半導体装置を得る。
【解決手段】リードフレームの上下に接着層を介して第一半導体素子と第二半導体素子とを搭載し、第一半導体素子と第二半導体素子とをインターポーザと電気的に接続させ、インターポーザ上面をモールドした半導体装置であって、リードフレームには複数の孔を設け、第一半導体装置とインターポーザの接続にワイヤを用い、第二半導体装置とインターポーザの接続にバンプを用い、第一半導体装置とインターポーザの接続に用いるワイヤは、リードフレームに設けられた孔を通って接続されているものである。
【選択図】図2
A semiconductor device having both functions of a high heat dissipation semiconductor device using a lead frame and an interposer and a multichip semiconductor device having semiconductor elements mounted on both sides of the lead frame is obtained.
A first semiconductor element and a second semiconductor element are mounted above and below a lead frame via an adhesive layer, the first semiconductor element and the second semiconductor element are electrically connected to an interposer, and an upper surface of the interposer is A molded semiconductor device, wherein a lead frame is provided with a plurality of holes, wires are used for connection between the first semiconductor device and the interposer, bumps are used for connection between the second semiconductor device and the interposer, and the first semiconductor device and the interposer The wire used for connection is connected through a hole provided in the lead frame.
[Selection] Figure 2

Description

本発明は、半導体装置に係り、特にリードフレームの両面に半導体素子を搭載するマルチチップ型半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a multichip semiconductor device in which semiconductor elements are mounted on both sides of a lead frame.

近年、半導体装置の高密度化、小型化への要求に対して、1つの方法として二つの半導体素子をリードフレームの表裏に搭載し各インナリードと半導体素子をワイヤボンディングにより接続する特許文献1のような構造が提案されている。   In recent years, in response to the demand for higher density and smaller size of a semiconductor device, as one method, two semiconductor elements are mounted on the front and back of a lead frame, and each inner lead and the semiconductor element are connected by wire bonding. Such a structure has been proposed.

また、半導体素子は、年々発熱量が増加する傾向にあり放熱性向上の要求も高まってきた。そこで高密度化、小型化、高放熱性化の要求に対して特許文献2のような構造が提案されている。特許文献2によると、リードフレームに張り合わされた金属板の片面に第一の半導体素子を設けインナリードとワイヤにより接続する。そして、金属板の一方にも第二の半導体素子を搭載し、その第二の半導体素子の回路形成面に配線テープを設けワイヤにより接続し、外部基板と配線テープの接続にバンプを設けている構造となっている。特許文献2の構造とすることにより、高密度化、高放熱化が図れることが記載されている。   In addition, semiconductor elements tend to increase in calorific value year by year, and the demand for improving heat dissipation has increased. Therefore, a structure as in Patent Document 2 has been proposed in response to demands for higher density, smaller size, and higher heat dissipation. According to Patent Document 2, a first semiconductor element is provided on one side of a metal plate bonded to a lead frame and connected to an inner lead by a wire. A second semiconductor element is also mounted on one of the metal plates, a wiring tape is provided on the circuit forming surface of the second semiconductor element and connected by a wire, and a bump is provided to connect the external substrate and the wiring tape. It has a structure. It is described that the structure of Patent Document 2 can achieve high density and high heat dissipation.

特開平8−191129号公報JP-A-8-191129 特開2002−124623号公報JP 2002-124623 A

しかし、特許文献1の方法では、金属に比べて熱伝導率が低いモールド樹脂からの放熱とワイヤ、インナリード、アウタリードと伝わる熱伝導率は高いが放熱経路が狭い経路しかなく高発熱の半導体素子の搭載には不向きな構造であった。   However, in the method of Patent Document 1, the heat dissipation from the mold resin, which has a lower thermal conductivity than that of metal, and the thermal conductivity transmitted to the wire, the inner lead, and the outer lead are high, but the heat dissipation semiconductor device has only a narrow path and a high heat generation. The structure was unsuitable for mounting.

また、特許文献2の方法では、金属板で熱を広げているが信号線であるインナリード、アウタリードからの放熱経路は狭く、且つ第二の半導体素子の回路形成面に金属に比べて熱伝導率の低い配線テープを介してバンプがあるために放熱性に限界があった。   Further, in the method of Patent Document 2, heat is spread by a metal plate, but the heat radiation path from the inner lead and outer lead that are signal lines is narrow, and the circuit formation surface of the second semiconductor element is more thermally conductive than metal. There was a limit to heat dissipation due to bumps through low-rate wiring tape.

本発明の目的は、上記した従来技術の欠点を解消し、半導体素子を搭載している放熱リードを外部基板に直接接続することにより、高放熱性な高密度の半導体装置を提供することにある。   An object of the present invention is to provide a high-heat-dissipating and high-density semiconductor device by eliminating the above-mentioned drawbacks of the prior art and directly connecting a heat-dissipation lead mounting a semiconductor element to an external substrate. .

本発明の半導体装置は、リードフレームの上下に接着層を介して第一半導体素子と第二半導体素子とを搭載し、前記第一半導体素子と第二半導体素子とをインターポーザと電気的に接続させ、インターポーザ上面をモールドした半導体装置であって、前記リードフレームには一つもしくは複数の孔を設け、前記第一半導体装置とインターポーザの接続にワイヤを用い、前記第二半導体装置とインターポーザの接続にバンプを用い、前記第一半導体装置とインターポーザの接続に用いるワイヤは、前記リードフレームに設けられた孔を通って接続されているものである。   The semiconductor device of the present invention has a first semiconductor element and a second semiconductor element mounted on the top and bottom of a lead frame via an adhesive layer, and the first semiconductor element and the second semiconductor element are electrically connected to an interposer. A semiconductor device in which the upper surface of the interposer is molded, wherein the lead frame is provided with one or a plurality of holes, wires are used to connect the first semiconductor device and the interposer, and the second semiconductor device and the interposer are connected. The wires used for connecting the first semiconductor device and the interposer using bumps are connected through holes provided in the lead frame.

本発明では複数の半導体素子を搭載した構造にすることにより高密度化、リードフレームを用いて直接外部基板に放熱することができるので高放熱化が図ることができる。   In the present invention, a structure in which a plurality of semiconductor elements are mounted can increase the density, and heat can be radiated directly to an external substrate using a lead frame, so that high heat dissipation can be achieved.

以下、本発明の実施の形態を説明する。   Embodiments of the present invention will be described below.

図1は本発明の第一の実施例の断面模式図である。リードフレーム1の上面には第一半導体素子2が回路形成面を上にして接着剤層(図示せず)を介して搭載され、リードフレーム1の下面には第二半導体素子3が回路形成面を下にして接着剤層(図示せず)を介して搭載されている。また、第一半導体素子2はワイヤ4を介してインターポーザ5と電気的に接続されており、第二半導体素子3はバンプ6を介してインターポーザ5と電気的に接続されている。さらに、インターポーザ5の上面はモールド樹脂7で保護されており、インターポーザ5の下面には外部基板(図示せず)との接続用に外部接続用バンプ8が設けられている。リードフレーム1は、第一半導体素子2と第二半導体素子3で発生する熱を外部基板に逃がすために外部基板と接着部材を介して接続しやすいように通常の半導体装置のアウタリードのように曲折した構造になっている。なお、バンプ6、外部接続用バンプ8の材料にははんだや導電性接着剤などを用いる。   FIG. 1 is a schematic sectional view of a first embodiment of the present invention. A first semiconductor element 2 is mounted on the upper surface of the lead frame 1 with a circuit forming surface facing upward via an adhesive layer (not shown), and a second semiconductor element 3 is mounted on the lower surface of the lead frame 1 on the circuit forming surface. It is mounted with an adhesive layer (not shown) facing down. The first semiconductor element 2 is electrically connected to the interposer 5 via the wires 4, and the second semiconductor element 3 is electrically connected to the interposer 5 via the bumps 6. Further, the upper surface of the interposer 5 is protected by a mold resin 7, and external connection bumps 8 are provided on the lower surface of the interposer 5 for connection to an external substrate (not shown). The lead frame 1 is bent like an outer lead of a normal semiconductor device so that the heat generated in the first semiconductor element 2 and the second semiconductor element 3 can be easily connected to the external board via an adhesive member in order to release the heat to the external board. It has a structure. Note that solder, conductive adhesive, or the like is used as the material for the bumps 6 and the external connection bumps 8.

図2は本発明の第一の実施例の平面模式図である。モールド樹脂7は内部構造を見やすくするために図示せず、その代わり封止するエリアを点線で表している。リードフレーム1には孔9が設けられており、ワイヤ4は孔9の中を通って第一半導体素子2とインターポーザ5を接続している。孔9は、大きくすると熱の逃げる経路が少なくなり放熱性が低下するためワイヤ9を通す必要最低限の大きさにすることが重要である。   FIG. 2 is a schematic plan view of the first embodiment of the present invention. The mold resin 7 is not shown in order to make the internal structure easy to see, and instead the area to be sealed is represented by a dotted line. A hole 9 is provided in the lead frame 1, and the wire 4 passes through the hole 9 to connect the first semiconductor element 2 and the interposer 5. If the hole 9 is made large, the path through which heat escapes is reduced and the heat dissipation performance is lowered. Therefore, it is important to make the hole 9 the minimum size through which the wire 9 can pass.

図3は本発明の第一の実施例の外部基板に搭載された時の断面模式図である。リードフレーム1ははんだ10を介して外部基板11に接続されている。リードフレーム1が接続される外部基板11の箇所には、基板内でさらに熱を拡散、放熱するために対策を採ることは言うまでもない。また、本発明ははんだによりリードフレーム1と外部基板11とを接続する方法で説明したが、導電性接着剤を用いても良いことは言うまでもない。   FIG. 3 is a schematic cross-sectional view when mounted on the external substrate of the first embodiment of the present invention. The lead frame 1 is connected to an external substrate 11 via solder 10. It goes without saying that measures are taken to further diffuse and dissipate heat within the substrate at the location of the external substrate 11 to which the lead frame 1 is connected. Further, although the present invention has been described by the method of connecting the lead frame 1 and the external substrate 11 with solder, it goes without saying that a conductive adhesive may be used.

上記のように構成することにより、2つの半導体素子を1つの半導体装置に内蔵することにより高密度化が図れ、また半導体素子の熱はリードフレームを用いて直接基板に放熱させることができるので放熱性の向上を図ることができる。さらに、孔を通してリードフレーム上下のモールド樹脂が密着するのでリードフレーム上下の樹脂間の密着性が向上し信頼性を向上させることができる。   By configuring as described above, it is possible to increase the density by incorporating two semiconductor elements in one semiconductor device, and the heat of the semiconductor elements can be directly radiated to the substrate using a lead frame, so that heat is dissipated. It is possible to improve the performance. Furthermore, since the mold resin above and below the lead frame adheres through the hole, the adhesion between the resin above and below the lead frame is improved and the reliability can be improved.

図4は本発明の第二の実施例の断面模式図である。インターポーザ5には第二半導体素子3とほぼ同等な大きさで開口部12があり、その開口部12から第二半導体素子3の回路形成面が露出しており、外部接続用バンプ8はインターポーザ5の下面と第二半導体素子3の回路形成面上に接続されている構造になっている。   FIG. 4 is a schematic cross-sectional view of the second embodiment of the present invention. The interposer 5 has an opening 12 that is substantially the same size as the second semiconductor element 3, and the circuit forming surface of the second semiconductor element 3 is exposed from the opening 12, and the external connection bump 8 is formed by the interposer 5. And a circuit forming surface of the second semiconductor element 3 are connected to each other.

上記のように構成することにより、第二半導体素子の熱を外部基板に直接逃がすことができるので第一の実施例に比べて放熱性が向上することができる。   By configuring as described above, the heat of the second semiconductor element can be directly released to the external substrate, so that the heat dissipation can be improved as compared with the first embodiment.

本発明の第一の実施例の半導体装置の断面模式図である。1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 本発明の第一の実施例の半導体装置の平面模式図である。1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention. 本発明の第一の実施例の外部基板に搭載されて時の半導体装置の断面模式図である。It is a cross-sectional schematic diagram of the semiconductor device when mounted on the external substrate of the first embodiment of the present invention. 本発明の第二の実施例の半導体装置の断面模式図である。It is a cross-sectional schematic diagram of the semiconductor device of the 2nd Example of this invention.

符号の説明Explanation of symbols

1…リードフレーム、2…第一半導体素子、3…第二半導体素子、4…ワイヤ、5…インターポーザ、6…一層目薄膜、9…孔、12…開口部。
DESCRIPTION OF SYMBOLS 1 ... Lead frame, 2 ... 1st semiconductor element, 3 ... 2nd semiconductor element, 4 ... Wire, 5 ... Interposer, 6 ... Single layer thin film, 9 ... Hole, 12 ... Opening part.

Claims (5)

リードフレームの上下に接着層を介して第一半導体素子と第二半導体素子とを搭載し、前記第一半導体素子と第二半導体素子とをインターポーザと電気的に接続させ、インターポーザ上面をモールドした半導体装置において、
前記第一半導体素子と第二半導体素子の電気信号をインターポーザ下面に設置された接続部材によって外部基板に電気的に接続されていることを特徴とする半導体装置。
A semiconductor in which a first semiconductor element and a second semiconductor element are mounted on the top and bottom of a lead frame via an adhesive layer, the first semiconductor element and the second semiconductor element are electrically connected to an interposer, and the upper surface of the interposer is molded In the device
A semiconductor device, wherein electrical signals of the first semiconductor element and the second semiconductor element are electrically connected to an external substrate by a connecting member provided on a lower surface of the interposer.
請求項1記載の半導体装置において、
前記第一半導体装置とインターポーザの接続にワイヤを用い、前記第二半導体装置とインターポーザの接続にバンプを用いたことを特徴とする半導体装置。
The semiconductor device according to claim 1,
A semiconductor device using a wire for connecting the first semiconductor device and the interposer and using a bump for connecting the second semiconductor device and the interposer.
請求項1記載の半導体モジュールにおいて、
前記リードフレームに一つもしくは複数の孔を有することを特徴とする半導体装置。
The semiconductor module according to claim 1,
A semiconductor device, wherein the lead frame has one or a plurality of holes.
請求項2記載の半導体モジュールにおいて、
前記第一半導体装置とインターポーザの接続に用いるワイヤは、前記リードフレームに設けられた孔を通って接続されていることを特徴とする半導体装置。
The semiconductor module according to claim 2,
A wire used for connecting the first semiconductor device and the interposer is connected through a hole provided in the lead frame.
請求項1記載の半導体モジュールにおいて、
インターポーザに第二半導体素子と同等な大きさの開口部を有し、外部基板と電気的に接続する接続部材をインターポーザ下面と第二半導体素子の回路形成面に設けたことを特徴とする半導体装置。
The semiconductor module according to claim 1,
A semiconductor device characterized in that an opening having a size equivalent to that of the second semiconductor element is provided in the interposer, and a connection member electrically connected to the external substrate is provided on the lower surface of the interposer and the circuit forming surface of the second semiconductor element. .
JP2006027849A 2006-02-06 2006-02-06 Semiconductor device Pending JP2007208159A (en)

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