JP2007206012A - Load current detecting circuit, and abnormality determination device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide "a load current detecting circuit and an abnormality determination device using the same" which determine precisely the presence of the generation of abnormality in a load, without providing an AD-converter additionally. <P>SOLUTION: The first resistance R<SB>1</SB>(resistance for generating a voltage drop) is connected to in a prestage of the first transistor Tr<SB>1</SB>for switching, and an output voltage V<SB>o</SB>is taken out between the first resistance R<SB>1</SB>and the first transistor Tr<SB>1</SB>, the first voltage value V<SB>o1</SB>when a load R<SB>L</SB>is disconnected and the second voltage value V<SB>o2</SB>when the load R<SB>L</SB>is connected, are detected thereby to find a difference between the voltage values V<SB>o1</SB>, V<SB>o2</SB>, the generation of the abnormality in the load R<SB>L</SB>is determined, based on a difference value to absorb a dispersion of an electric power voltage V<SB>cc</SB>, and the presence of the abnormality is thereby determined precisely irrespective of the dispersion of an electric power voltage V<SB>cc</SB>. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a load current detection circuit and an abnormality determination device using the same, and more particularly, a circuit for detecting a current value (or a voltage value corresponding to the current) flowing through the load and whether or not an abnormality has occurred in the load based on the detected value. It is suitable for use in an apparatus for diagnosing the above.

  In general, many parts and circuits are used in electronic devices. In order to draw out the required performance of electronic equipment, high reliability is required for individual components. In addition, when an abnormality occurs due to some cause, it is desired to quickly detect it. For this reason, a circuit for detecting the presence or absence of an open abnormality due to wiring disconnection or poor connection in a component or the like, or a short abnormality due to a short circuit between wirings is often incorporated in an electronic device. .

A technique has been proposed that can automatically check for an open abnormality of the antenna line and a short-circuit abnormality with respect to the ground (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 5-90818

  Whether there is an open abnormality or a short abnormality can be determined by detecting a load current flowing in a component or the like and comparing the detected value with a reference value. There are various methods for detecting the load current. The most typical example is the load current detection circuit shown in FIG.

In FIG. 4, _RL is a load such as a component, and _VCC is a power supply or its output voltage value. Tr ₁ is a first transistor connected between the power supply _VCC and the load _RL , its emitter is connected to the power supply _VCC side, and its collector is connected to the load _RL side. Between the first transistor collectors of Tr ₁ and the load R _L is connected to the first resistor R ₁ is. The first end of the resistor R ₁ is connected to a first collector of the transistor Tr _1, the other end is connected to the output terminal OUT of the load current detection circuit. An AD converter (not shown) is connected to the output terminal OUT.

Tr ₂ is a second transistor, its emitter is grounded, and its collector is connected to the base of the first transistor Tr ₁ via a _second resistor R ₂ . Second base of the transistor Tr ₂ is connected to the control terminal CTL via a third resistor R _3. Further, the second transistor Tr ₂ of the base and emitter are connected to each other via a fourth resistor R _4.

In the conventional load current detection circuit shown in FIG. 4, the load current I _L can be determined by the following equation (1). Here, for the sake of simplicity, the saturation voltage of the first transistor Tr ₁ is set to 0 [V] for the sake of convenience.
I _L = (V _CC −V _o ) / R ₁ (Formula 1)
In practice, the load current detection circuit of Figure 4 is supplied to the AD converter of the first voltage drop level V _o of the resistor R ₁ generated by the load current I _L flowing through the load R _L from the output terminal OUT.

Transforming the equation (1), the output voltage V _o of the load current detecting circuit is given by the following equation (2).
_{V o = V CC -R 1 I} L ··· ( Equation 2)
Therefore, when excessive current flows through the load R _L, the value of the output voltage V _o becomes smaller. Therefore, a digital value to output the output voltage V _o, as described above in the AD converter, and compares the digital value and the first threshold value. When the output voltage V _o falls below the first threshold value, the load R _L is considered to be damaged by the short mode.

Conversely, if too little current flows through the load R _L, the value of the output voltage V _o increases. Therefore, the output voltage V _o is compared with the second threshold value, and when the output voltage V _o exceeds the second threshold value, it is considered that the load _RL is damaged in the open mode.

In the circuit shown in FIG. 4, when a short abnormality or an open abnormality is detected, the second transistor Tr is switched by switching the control signal input from the control terminal CTL to the base of the second transistor Tr ₂ from Hi to Lo. ₂ is turned off, thereby making it possible to first turn off the transistor Tr ₁ drives out this. Thereby, when an abnormality occurs, the power supply to the load _RL can be cut off.

However, in general, the power supply circuit has variations in the output voltage _VCC even in the power supply circuit using the same type of parts due to the influence of individual differences of parts used in the power supply circuit and the surrounding atmosphere. Usually there is a tolerance of about 2-5%. When using the power supply _{V CC} of 5 V, the tolerance becomes ± 0.25 [V] at 5%. This is a problem that should be called bottle neck in order to detect the output voltage V _o. That is, in the circuit of Figure 4 detects when the variation of the voltage V _o is within 0.50 [V] is a variation range of the power supply V _CC, variation due to its variation of the load current I _L or due to variations of the power supply V _CC I cannot identify it.

Therefore, for example, when the value of the detected voltage V _o is a value closer to the first threshold value, or determines that the original is short abnormal to normal, conversely, the short originally abnormality has occurred In some cases, it was judged to be normal. Further, when the value of the detection voltage V _o is close to the second threshold value, it is determined that an open abnormality has occurred although it is normally normal, or conversely, an open abnormality has occurred originally. Sometimes it was determined to be normal.

As a method for measuring the power V _CC accurate load current I _L to the exclusion of variation of the circuit of FIG. 4, the potential of the first subsequent transistor Tr ₁ (first preceding resistor R ₁₎ Are measured simultaneously (that is, the potential across the _first resistor R1 is measured). However, in this case, there is a problem that an extra AD converter must be used as compared with a normal circuit.

  The present invention has been made to solve such a problem, and is capable of accurately determining whether or not an abnormality has occurred in a load without providing an additional AD converter. Objective.

  In order to solve the above-described problem, in the load current detection circuit of the present invention, a voltage drop generation resistor is connected between the power supply and the load closer to the power supply than the switching transistor. The voltage stepped down at is taken out as an output voltage.

  Further, in the abnormality determination device of the present invention, a difference value between the output voltage when the switching transistor of the load current detection circuit is turned off and the output voltage when the switching transistor is turned on is obtained, and based on the difference value, The occurrence of abnormality is determined.

  According to the present invention configured as described above, the output voltage when the switching transistor is off and the load is disconnected, and the output voltage when the switching transistor is on and the load is connected And the presence / absence of a load abnormality is determined based on the difference value. As a result, even if the power supply voltage varies due to the influence of individual differences of parts, ambient atmosphere, etc., the variation is substantially eliminated by taking the difference in output voltage as described above. That is, the obtained difference value does not include the fluctuation due to the variation in the characteristics of the power supply voltage. Since the load abnormality determination is performed based on such a difference value, it is possible to suppress erroneous determination due to variations in power supply voltage and perform determination with high accuracy. In addition, since the voltage across the voltage drop generating resistor is not measured, there is no need to provide an additional AD converter.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating a configuration example of a load current detection circuit according to the present embodiment. In FIG. 1, _RL is a load, and _VCC is a power supply or its output voltage value. Tr ₁ is a first transistor (corresponding to a switching transistor of the present invention), R ₁ is a first resistor (corresponding to a voltage drop generating resistor of the present invention), and these are a power supply _VCC and a load _RL . Are connected in series.

In the present embodiment, the first resistor R ₁ is connected to the previous stage of the first transistor Tr ₁ , that is, to the side closer to the power supply _VCC . That is, the emitter of the first transistor Tr ₁ is connected to the subsequent stage of the first resistor R ₁ and the collector is connected to the load _RL . Further, by connecting the subsequent stage of the first resistor R ₁ (the emitter side of the first transistor Tr ₁ ) to the output terminal OUT, the voltage stepped down by the first resistor R ₁ is taken out as the output voltage. Yes. An AD converter (not shown) is connected to the output terminal OUT.

Tr ₂ is a second transistor, its emitter is grounded, and its collector is connected to the base of the first transistor Tr ₁ via a _second resistor R ₂ . Second base of the transistor Tr ₂ is connected to the control terminal CTL via a third resistor R _3. Further, the second transistor Tr ₂ of the base and emitter are connected to each other via a fourth resistor R _4.

  FIG. 2 is a diagram illustrating a configuration example of an abnormality determination device using the load current detection circuit of the present embodiment configured as described above. As shown in FIG. 2, the abnormality determination device according to the present embodiment includes a load current detection circuit 11, an AD converter 12, and a DSP (Digital Signal Processor) 13. The DSP 13 includes a control unit 13a, a difference calculation unit 13b, and an abnormality determination unit 13c as functional configurations.

The load current detection circuit 11 has the configuration shown in FIG. The AD converter 12 A / D converts the analog voltage value output from the output terminal OUT of the load current detection circuit 11 into a digital value. The control unit 13 a of the DSP 13 generates a control signal for controlling on / off of the first transistor Tr _{1 in} the load current detection circuit 11.

Control signals generated by the control unit 13a is input from the control terminal CTL of the load current detecting circuit 11 to the second base of the transistor Tr _2. By the logic of the control signal Hi, the second transistor Tr ₂ is turned on, which can be turned on the first transistor Tr ₁ I or more. On the other hand, the logic of the control signal by a Lo, the second transistor Tr ₂ is turned off, which can be off the first transistor Tr ₁ I or more.

Difference calculation unit 13b, a first voltage by the first transistor Tr ₁ is the control obtained by the A / D conversion by the load current detection circuit 11 AD converter 12 are output from when it is turned off in the control section 13a values and, with a second voltage value obtained by a / D conversion by the load current detection circuit 11 AD converter 12 are output from when the control of the control unit 13a first transistor Tr ₁ is turned on Find the difference value.

Specifically, at a certain timing, the control unit 13a sets the logic of the control signal to Lo, and at this time, the first voltage value output from the load current detection circuit 11 and A / D converted by the AD converter 12 is obtained. The result is stored in the register of the difference calculation unit 13b. The first voltage value is obtained by (Equation 2) described above. Here, the first voltage value _{V o1} obtained when the control signal is off the first transistor Tr ₁ in the Lo, when the load current is _{I L1, V o1} by the following (Equation 3) Given.
V _o1 = V _CC -R ₁ I _L1 (Formula 3)

Next, the control unit 13a sets the logic of the control signal to Hi, and at this time, the second voltage value output from the load current detection circuit 11 and A / D-converted by the AD converter 12 is used as the difference calculation unit 13b. Save to register. Here, assuming that the second voltage value obtained when the control signal is Hi and the first transistor Tr ₁ is turned off is V _o2 and the load current is I _L2 , V _o2 is expressed by the following (Equation 4). Given.
V _o2 = V _CC -R ₁ I _L2 (Formula 4)
Then, the difference calculation unit 13b calculates a difference between the first voltage value V _o1 and the second voltage value V _o2 stored in the register.

The abnormality determination unit 13c determines the occurrence of an abnormality in the load _RL based on the difference value obtained by the difference calculation unit 13b. For example, the difference value obtained by the difference calculation unit 13b is compared with the first threshold value Th1, and when the difference value exceeds the first threshold value Th1, it is considered that the load _RL is damaged in the short mode. . Further, the difference value obtained by the difference calculation unit 13b is compared with the second threshold value Th2 (Th1> Th2), and when the difference value falls below the second threshold value Th2, the load _RL is damaged in the open mode. It is assumed that

When there is no abnormality, the control unit 13a maintains the first transistor Tr1 in the ON state by keeping the logic of the control signal as Hi. Thereafter, the same abnormality determination is performed, and when a short abnormality or an open abnormality is detected, the logic of the control signal is switched from Hi to Lo, thereby turning off the first transistor Tr ₁ and supplying power to the load _RL . Try to cut off the supply.

Incidentally, determine the load current I _L from the difference value and the first resistance value of the resistor R ₁ obtained by the difference calculation unit 13b, determines the short abnormality in comparison with the threshold value Th3 in the load current I _L and the third and it may be determined open fault in comparison with the load current _{I L} and the fourth threshold value Th4 (Th3> Th4). The load current I _L can be determined by the following equation (5).
I _L = I _L2 −I _L1
= (V _CC -V _o2 ) / R _1- (V _CC -V _o1 ) / R ₁
= (V _o1 −V _o2 ) / R ₁ (Formula 5)

FIG. 3 is a flowchart illustrating an operation example of the abnormality determination device according to the present embodiment. This flowchart starts when, for example, the abnormality determination device is turned on. First, the control unit 13a of the DSP 13 turns off the first transistor Tr1 by setting the logic of the control signal supplied to the control terminal CTL of the load current detection circuit 11 to Lo (step S1). The AD converter 12 obtains a first voltage value V _o1 by A / D converting the voltage output from the output terminal OUT of the load current detection circuit 11 at this time (step S2). The difference calculation unit 13b stores the first voltage value V _o1 in a register (not shown) (step S3).

Next, the control unit 13a turns on the first transistor Tr1 by setting the logic of the control signal supplied to the control terminal CTL of the load current detection circuit 11 to Hi (step S4). At this time, the AD converter 12 A / D converts the voltage output from the output terminal OUT of the load current detection circuit 11 to obtain the second voltage value V _o2 (step S5). The difference calculation unit 13b stores the second voltage value V _o2 in a register (not shown) (step S6).

Then, the difference calculation unit 13b calculates the difference between the first voltage value V _o1 and the second voltage value V _o2 stored in the register (step S7). The abnormality determination unit 13c determines whether or not the difference value is equal to or greater than the first threshold Th1 (step S8). When the difference value is not equal to or greater than the first threshold value Th1, the abnormality determination unit 13c determines whether or not the difference value is equal to or less than the second threshold value Th2 (step S9).

  Here, when the difference value is not equal to or greater than the first threshold value Th1 or equal to or less than the second threshold value Th2, the abnormality determination unit 13c determines that the normal mode (no abnormality) (step S10). In this case, the process returns to step S5 and monitoring is continued.

Further, when the difference value is equal to or smaller than the second threshold Th2, the abnormality determining unit 13c determines that the open mode (open abnormality exists) (step S11). In this case, the control unit 13a sets the logic of the control signal to Lo to once cut off the power supply to the load _RL (step S12), and then returns to step S2 to continue monitoring.

If the difference value is equal to or greater than the first threshold value Th1, the abnormality determination unit 13c determines that the short mode (there is a short abnormality) (step S13). In this case, the control unit 13a sets the logic of the control signal to Lo, cuts off the power supply to the load _RL (step S14), and ends the process.

As described above in detail, in the present embodiment, in the load current detection circuit 11, the first resistor R ₁ (voltage drop generating resistor) is connected to the previous stage of the first transistor Tr ₁ for switching, and the first are the resistances R ₁ and from between the first transistor Tr ₁ to take out the output voltage V _o. Thus, the first transistor Tr ₁ is the first voltage value V _o1 when the load R _L off is disconnected, the first transistor Tr ₁ is turned on the load R _L is connected It is possible to detect the second voltage value V _o2 when That is, the voltage (potential difference) can be detected while detecting the potential at the same point.

Then, in the abnormality determination device using such a load current detection circuit 11, a difference between the first voltage value V _o1 and the second voltage value V _o2 is obtained, and an abnormality in the load _RL is determined based on the difference value. Is determined to occur. As can be seen from the above-described (Equation 5), the power supply voltage V _CC in the equation for the load current I _L in the present embodiment is not entered, it is able to absorb a variation in power supply voltage V _CC . As a result, even if the power supply voltage _VCC varies due to the influence of individual differences of parts, the ambient atmosphere, etc., it is possible to suppress erroneous determination caused by this and to determine whether there is an abnormality with high accuracy. . Moreover, this can be realized by one AD converter 12.

  In addition, although the said embodiment demonstrated the example which implement | achieves the function of the control part 13a, the difference calculating part 13b, and the abnormality determination part 13c by DSP13, it is not limited to this. These functions may be configured by hardware logic, or may be realized by software. For example, when realized by software, the functions of the control unit 13a, the difference calculation unit 13b, and the abnormality determination unit 13c are configured to include a computer CPU or MPU, RAM, ROM, etc., and a program stored in the RAM or ROM operates. It can be realized by doing.

In the above embodiment, when it is determined that the open mode although the first temporarily turn off the transistor Tr _1, was described for an example in which monitoring is continued. In contrast, as in the case it is determined that the short mode, the first transistor Tr ₁ turned down the power supply to clear the load R _L, it may be the process ends.

  Further, in the above embodiment, when it is determined that the normal mode, the open mode, or the short mode is selected, the determined mode may be displayed on the display device to notify the user.

  In addition, each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. In other words, the present invention can be implemented in various forms without departing from the spirit or main features thereof.

  The present invention is useful for an abnormality determination device for determining an open abnormality and a short abnormality and a load current detection circuit used therefor.

It is a figure which shows the structural example of the load current detection circuit by this embodiment. It is a figure which shows the structural example of the abnormality determination apparatus by this embodiment. It is a flowchart which shows the operation example of the abnormality determination apparatus by this embodiment. It is a figure which shows the conventional load current detection circuit.

Explanation of symbols

11 Load Current Detection Circuit 12 AD Converter 13 DSP
13a Control unit 13b Difference calculation unit 13c Abnormality determination unit Tr ₁ First transistor (switching transistor)
R ₁ first resistor (resistance for voltage drop generation)
_RL load V _CC power supply

Claims (4)

A voltage drop generating resistor and a switching transistor connected in series between the power source and the load are provided.
A load current characterized in that the voltage drop generating resistor is connected to a side closer to the power supply than the switching transistor, and a voltage stepped down by the voltage drop generating resistor is taken out as an output voltage. Detection circuit. A load current detection circuit according to claim 1;
An AD converter for A / D converting the output voltage into a digital value;
Control means for generating a control signal for controlling on / off of the switching transistor;
A first voltage value output from the load current detection circuit and A / D-converted by the AD converter when the switching transistor is turned off by the control means; and the switching transistor by the control means. Difference calculating means for obtaining a difference value from the second voltage value that is output from the load current detection circuit and A / D converted by the AD converter when is turned on;
An abnormality determination device comprising: an abnormality determination unit that determines occurrence of abnormality in the load based on a difference value obtained by the difference calculation unit. The abnormality determination device according to claim 2, wherein the abnormality determination unit determines that a short abnormality has occurred when the difference value is equal to or greater than a first threshold value. The abnormality determination device according to claim 2, wherein the abnormality determination unit determines that an open abnormality has occurred when the difference value is equal to or less than a second threshold value.

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